1/* SPDX-License-Identifier: GPL-2.0 */
2/* Marvell Octeon EP (EndPoint) Ethernet Driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8#ifndef _OCTEP_CONFIG_H_
9#define _OCTEP_CONFIG_H_
10
11/* Tx instruction types by length */
12#define OCTEP_32BYTE_INSTR 32
13#define OCTEP_64BYTE_INSTR 64
14
15/* Tx Queue: maximum descriptors per ring */
16/* This needs to be a power of 2 */
17#define OCTEP_IQ_MAX_DESCRIPTORS 1024
18/* Minimum input (Tx) requests to be enqueued to ring doorbell */
19#define OCTEP_DB_MIN 8
20/* Packet threshold for Tx queue interrupt */
21#define OCTEP_IQ_INTR_THRESHOLD 0x0
22
23/* Minimum watermark for backpressure */
24#define OCTEP_OQ_WMARK_MIN 256
25
26/* Rx Queue: maximum descriptors per ring */
27#define OCTEP_OQ_MAX_DESCRIPTORS 1024
28
29/* Rx buffer size: Use page size buffers.
30 * Build skb from allocated page buffer once the packet is received.
31 * When a gathered packet is received, make head page as skb head and
32 * page buffers in consecutive Rx descriptors as fragments.
33 */
34#define OCTEP_OQ_BUF_SIZE (SKB_WITH_OVERHEAD(PAGE_SIZE))
35#define OCTEP_OQ_PKTS_PER_INTR 128
36#define OCTEP_OQ_REFILL_THRESHOLD (OCTEP_OQ_MAX_DESCRIPTORS / 4)
37
38#define OCTEP_OQ_INTR_PKT_THRESHOLD 1
39#define OCTEP_OQ_INTR_TIME_THRESHOLD 10
40
41#define OCTEP_MSIX_NAME_SIZE (IFNAMSIZ + 32)
42
43/* Tx Queue wake threshold
44 * wakeup a stopped Tx queue if minimum 2 descriptors are available.
45 * Even a skb with fragments consume only one Tx queue descriptor entry.
46 */
47#define OCTEP_WAKE_QUEUE_THRESHOLD 2
48
49/* Minimum MTU supported by Octeon network interface */
50#define OCTEP_MIN_MTU ETH_MIN_MTU
51/* Default MTU */
52#define OCTEP_DEFAULT_MTU 1500
53
54/* pf heartbeat interval in milliseconds */
55#define OCTEP_DEFAULT_FW_HB_INTERVAL 1000
56/* pf heartbeat miss count */
57#define OCTEP_DEFAULT_FW_HB_MISS_COUNT 20
58
59/* Macros to get octeon config params */
60#define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
61#define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
62#define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
63#define CFG_GET_IQ_INSTR_SIZE(cfg) (64)
64#define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
65#define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold)
66
67#define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs)
68#define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size)
69#define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold)
70#define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt)
71#define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time)
72#define CFG_GET_OQ_WMARK(cfg) ((cfg)->oq.wmark)
73
74#define CFG_GET_PORTS_MAX_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.max_io_rings)
75#define CFG_GET_PORTS_ACTIVE_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.active_io_rings)
76#define CFG_GET_PORTS_PF_SRN(cfg) ((cfg)->pf_ring_cfg.srn)
77
78#define CFG_GET_CORE_TICS_PER_US(cfg) ((cfg)->core_cfg.core_tics_per_us)
79#define CFG_GET_COPROC_TICS_PER_US(cfg) ((cfg)->core_cfg.coproc_tics_per_us)
80
81#define CFG_GET_MAX_VFS(cfg) ((cfg)->sriov_cfg.max_vfs)
82#define CFG_GET_ACTIVE_VFS(cfg) ((cfg)->sriov_cfg.active_vfs)
83#define CFG_GET_MAX_RPVF(cfg) ((cfg)->sriov_cfg.max_rings_per_vf)
84#define CFG_GET_ACTIVE_RPVF(cfg) ((cfg)->sriov_cfg.active_rings_per_vf)
85#define CFG_GET_VF_SRN(cfg) ((cfg)->sriov_cfg.vf_srn)
86
87#define CFG_GET_IOQ_MSIX(cfg) ((cfg)->msix_cfg.ioq_msix)
88#define CFG_GET_NON_IOQ_MSIX(cfg) ((cfg)->msix_cfg.non_ioq_msix)
89#define CFG_GET_NON_IOQ_MSIX_NAMES(cfg) ((cfg)->msix_cfg.non_ioq_msix_names)
90
91#define CFG_GET_CTRL_MBOX_MEM_ADDR(cfg) ((cfg)->ctrl_mbox_cfg.barmem_addr)
92
93/* Hardware Tx Queue configuration. */
94struct octep_iq_config {
95 /* Size of the Input queue (number of commands) */
96 u16 num_descs;
97
98 /* Command size - 32 or 64 bytes */
99 u16 instr_type;
100
101 /* Minimum number of commands pending to be posted to Octeon before driver
102 * hits the Input queue doorbell.
103 */
104 u16 db_min;
105
106 /* Trigger the IQ interrupt when processed cmd count reaches
107 * this level.
108 */
109 u32 intr_threshold;
110};
111
112/* Hardware Rx Queue configuration. */
113struct octep_oq_config {
114 /* Size of Output queue (number of descriptors) */
115 u16 num_descs;
116
117 /* Size of buffer in this Output queue. */
118 u16 buf_size;
119
120 /* The number of buffers that were consumed during packet processing
121 * by the driver on this Output queue before the driver attempts to
122 * replenish the descriptor ring with new buffers.
123 */
124 u16 refill_threshold;
125
126 /* Interrupt Coalescing (Packet Count). Octeon will interrupt the host
127 * only if it sent as many packets as specified by this field.
128 * The driver usually does not use packet count interrupt coalescing.
129 */
130 u32 oq_intr_pkt;
131
132 /* Interrupt Coalescing (Time Interval). Octeon will interrupt the host
133 * if at least one packet was sent in the time interval specified by
134 * this field. The driver uses time interval interrupt coalescing by
135 * default. The time is specified in microseconds.
136 */
137 u32 oq_intr_time;
138
139 /* Water mark for backpressure.
140 * Output queue sends backpressure signal to source when
141 * free buffer count falls below wmark.
142 */
143 u32 wmark;
144};
145
146/* Tx/Rx configuration */
147struct octep_pf_ring_config {
148 /* Max number of IOQs */
149 u16 max_io_rings;
150
151 /* Number of active IOQs */
152 u16 active_io_rings;
153
154 /* Starting IOQ number: this changes based on which PEM is used */
155 u16 srn;
156};
157
158/* Octeon Hardware SRIOV config */
159struct octep_sriov_config {
160 /* Max number of VF devices supported */
161 u16 max_vfs;
162
163 /* Number of VF devices enabled */
164 u16 active_vfs;
165
166 /* Max number of rings assigned to VF */
167 u8 max_rings_per_vf;
168
169 /* Number of rings enabled per VF */
170 u8 active_rings_per_vf;
171
172 /* starting ring number of VF's: ring-0 of VF-0 of the PF */
173 u16 vf_srn;
174};
175
176/* Octeon MSI-x config. */
177struct octep_msix_config {
178 /* Number of IOQ interrupts */
179 u16 ioq_msix;
180
181 /* Number of Non IOQ interrupts */
182 u16 non_ioq_msix;
183
184 /* Names of Non IOQ interrupts */
185 char **non_ioq_msix_names;
186};
187
188struct octep_ctrl_mbox_config {
189 /* Barmem address for control mbox */
190 void __iomem *barmem_addr;
191};
192
193/* Info from firmware */
194struct octep_fw_info {
195 /* interface pkind */
196 u8 pkind;
197
198 /* front size data */
199 u8 fsz;
200
201 /* heartbeat interval in milliseconds */
202 u16 hb_interval;
203
204 /* heartbeat miss count */
205 u16 hb_miss_count;
206
207 /* reserved */
208 u16 reserved1;
209
210 /* supported rx offloads OCTEP_ETH_RX_OFFLOAD_* */
211 u16 rx_ol_flags;
212
213 /* supported tx offloads OCTEP_ETH_TX_OFFLOAD_* */
214 u16 tx_ol_flags;
215
216 /* reserved */
217 u32 reserved_offloads;
218
219 /* extra offload flags */
220 u64 ext_ol_flags;
221
222 /* supported features */
223 u64 features[2];
224
225 /* reserved */
226 u64 reserved2[3];
227};
228
229/* Data Structure to hold configuration limits and active config */
230struct octep_config {
231 /* Input Queue attributes. */
232 struct octep_iq_config iq;
233
234 /* Output Queue attributes. */
235 struct octep_oq_config oq;
236
237 /* NIC Port Configuration */
238 struct octep_pf_ring_config pf_ring_cfg;
239
240 /* SRIOV configuration of the PF */
241 struct octep_sriov_config sriov_cfg;
242
243 /* MSI-X interrupt config */
244 struct octep_msix_config msix_cfg;
245
246 /* ctrl mbox config */
247 struct octep_ctrl_mbox_config ctrl_mbox_cfg;
248
249 /* fw info */
250 struct octep_fw_info fw_info;
251};
252#endif /* _OCTEP_CONFIG_H_ */
253

source code of linux/drivers/net/ethernet/marvell/octeon_ep/octep_config.h