| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Marvell Octeon EP (EndPoint) Ethernet Driver |
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| 3 | * |
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| 4 | * Copyright (C) 2020 Marvell. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _OCTEP_REGS_CN9K_PF_H_ |
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| 9 | #define _OCTEP_REGS_CN9K_PF_H_ |
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| 10 | |
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| 11 | /* ############################ RST ######################### */ |
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| 12 | #define CN93_RST_BOOT 0x000087E006001600ULL |
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| 13 | #define CN93_RST_CORE_DOMAIN_W1S 0x000087E006001820ULL |
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| 14 | #define CN93_RST_CORE_DOMAIN_W1C 0x000087E006001828ULL |
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| 15 | |
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| 16 | #define CN93_CONFIG_XPANSION_BAR 0x38 |
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| 17 | #define CN93_CONFIG_PCIE_CAP 0x70 |
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| 18 | #define CN93_CONFIG_PCIE_DEVCAP 0x74 |
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| 19 | #define CN93_CONFIG_PCIE_DEVCTL 0x78 |
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| 20 | #define CN93_CONFIG_PCIE_LINKCAP 0x7C |
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| 21 | #define CN93_CONFIG_PCIE_LINKCTL 0x80 |
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| 22 | #define CN93_CONFIG_PCIE_SLOTCAP 0x84 |
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| 23 | #define CN93_CONFIG_PCIE_SLOTCTL 0x88 |
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| 24 | |
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| 25 | #define CN93_PCIE_SRIOV_FDL 0x188 /* 0x98 */ |
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| 26 | #define CN93_PCIE_SRIOV_FDL_BIT_POS 0x10 |
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| 27 | #define CN93_PCIE_SRIOV_FDL_MASK 0xFF |
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| 28 | |
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| 29 | #define CN93_CONFIG_PCIE_FLTMSK 0x720 |
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| 30 | |
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| 31 | /* ################# Offsets of RING, EPF, MAC ######################### */ |
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| 32 | #define CN93_RING_OFFSET (0x1ULL << 17) |
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| 33 | #define CN93_EPF_OFFSET (0x1ULL << 25) |
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| 34 | #define CN93_MAC_OFFSET (0x1ULL << 4) |
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| 35 | #define CN93_BIT_ARRAY_OFFSET (0x1ULL << 4) |
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| 36 | #define CN93_EPVF_RING_OFFSET (0x1ULL << 4) |
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| 37 | |
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| 38 | /* ################# Scratch Registers ######################### */ |
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| 39 | #define CN93_SDP_EPF_SCRATCH 0x205E0 |
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| 40 | |
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| 41 | /* ################# Window Registers ######################### */ |
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| 42 | #define CN93_SDP_WIN_WR_ADDR64 0x20000 |
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| 43 | #define CN93_SDP_WIN_RD_ADDR64 0x20010 |
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| 44 | #define CN93_SDP_WIN_WR_DATA64 0x20020 |
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| 45 | #define CN93_SDP_WIN_WR_MASK_REG 0x20030 |
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| 46 | #define CN93_SDP_WIN_RD_DATA64 0x20040 |
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| 47 | |
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| 48 | #define CN93_SDP_MAC_NUMBER 0x2C100 |
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| 49 | |
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| 50 | /* ################# Global Previliged registers ######################### */ |
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| 51 | #define CN93_SDP_EPF_RINFO 0x205F0 |
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| 52 | |
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| 53 | #define CN93_SDP_EPF_RINFO_SRN(val) ((val) & 0xFF) |
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| 54 | #define CN93_SDP_EPF_RINFO_RPVF(val) (((val) >> 32) & 0xF) |
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| 55 | #define CN93_SDP_EPF_RINFO_NVFS(val) (((val) >> 48) & 0xFF) |
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| 56 | |
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| 57 | /* SDP Function select */ |
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| 58 | #define CN93_SDP_FUNC_SEL_EPF_BIT_POS 8 |
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| 59 | #define CN93_SDP_FUNC_SEL_FUNC_BIT_POS 0 |
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| 60 | |
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| 61 | /* ##### RING IN (Into device from PCI: Tx Ring) REGISTERS #### */ |
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| 62 | #define CN93_SDP_R_IN_CONTROL_START 0x10000 |
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| 63 | #define CN93_SDP_R_IN_ENABLE_START 0x10010 |
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| 64 | #define CN93_SDP_R_IN_INSTR_BADDR_START 0x10020 |
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| 65 | #define CN93_SDP_R_IN_INSTR_RSIZE_START 0x10030 |
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| 66 | #define CN93_SDP_R_IN_INSTR_DBELL_START 0x10040 |
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| 67 | #define CN93_SDP_R_IN_CNTS_START 0x10050 |
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| 68 | #define CN93_SDP_R_IN_INT_LEVELS_START 0x10060 |
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| 69 | #define CN93_SDP_R_IN_PKT_CNT_START 0x10080 |
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| 70 | #define CN93_SDP_R_IN_BYTE_CNT_START 0x10090 |
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| 71 | |
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| 72 | #define CN93_SDP_R_IN_CONTROL(ring) \ |
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| 73 | (CN93_SDP_R_IN_CONTROL_START + ((ring) * CN93_RING_OFFSET)) |
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| 74 | |
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| 75 | #define CN93_SDP_R_IN_ENABLE(ring) \ |
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| 76 | (CN93_SDP_R_IN_ENABLE_START + ((ring) * CN93_RING_OFFSET)) |
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| 77 | |
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| 78 | #define CN93_SDP_R_IN_INSTR_BADDR(ring) \ |
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| 79 | (CN93_SDP_R_IN_INSTR_BADDR_START + ((ring) * CN93_RING_OFFSET)) |
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| 80 | |
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| 81 | #define CN93_SDP_R_IN_INSTR_RSIZE(ring) \ |
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| 82 | (CN93_SDP_R_IN_INSTR_RSIZE_START + ((ring) * CN93_RING_OFFSET)) |
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| 83 | |
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| 84 | #define CN93_SDP_R_IN_INSTR_DBELL(ring) \ |
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| 85 | (CN93_SDP_R_IN_INSTR_DBELL_START + ((ring) * CN93_RING_OFFSET)) |
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| 86 | |
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| 87 | #define CN93_SDP_R_IN_CNTS(ring) \ |
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| 88 | (CN93_SDP_R_IN_CNTS_START + ((ring) * CN93_RING_OFFSET)) |
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| 89 | |
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| 90 | #define CN93_SDP_R_IN_INT_LEVELS(ring) \ |
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| 91 | (CN93_SDP_R_IN_INT_LEVELS_START + ((ring) * CN93_RING_OFFSET)) |
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| 92 | |
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| 93 | #define CN93_SDP_R_IN_PKT_CNT(ring) \ |
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| 94 | (CN93_SDP_R_IN_PKT_CNT_START + ((ring) * CN93_RING_OFFSET)) |
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| 95 | |
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| 96 | #define CN93_SDP_R_IN_BYTE_CNT(ring) \ |
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| 97 | (CN93_SDP_R_IN_BYTE_CNT_START + ((ring) * CN93_RING_OFFSET)) |
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| 98 | |
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| 99 | /* Rings per Virtual Function */ |
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| 100 | #define CN93_R_IN_CTL_RPVF_MASK (0xF) |
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| 101 | #define CN93_R_IN_CTL_RPVF_POS (48) |
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| 102 | |
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| 103 | /* Number of instructions to be read in one MAC read request. |
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| 104 | * setting to Max value(4) |
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| 105 | */ |
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| 106 | #define CN93_R_IN_CTL_IDLE (0x1ULL << 28) |
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| 107 | #define CN93_R_IN_CTL_RDSIZE (0x3ULL << 25) |
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| 108 | #define CN93_R_IN_CTL_IS_64B (0x1ULL << 24) |
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| 109 | #define CN93_R_IN_CTL_D_NSR (0x1ULL << 8) |
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| 110 | #define CN93_R_IN_CTL_D_ESR (0x1ULL << 6) |
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| 111 | #define CN93_R_IN_CTL_D_ROR (0x1ULL << 5) |
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| 112 | #define CN93_R_IN_CTL_NSR (0x1ULL << 3) |
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| 113 | #define CN93_R_IN_CTL_ESR (0x1ULL << 1) |
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| 114 | #define CN93_R_IN_CTL_ROR (0x1ULL << 0) |
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| 115 | |
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| 116 | #define CN93_R_IN_CTL_MASK (CN93_R_IN_CTL_RDSIZE | CN93_R_IN_CTL_IS_64B) |
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| 117 | |
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| 118 | /* ##### RING OUT (out from device to PCI host: Rx Ring) REGISTERS #### */ |
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| 119 | #define CN93_SDP_R_OUT_CNTS_START 0x10100 |
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| 120 | #define CN93_SDP_R_OUT_INT_LEVELS_START 0x10110 |
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| 121 | #define CN93_SDP_R_OUT_SLIST_BADDR_START 0x10120 |
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| 122 | #define CN93_SDP_R_OUT_SLIST_RSIZE_START 0x10130 |
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| 123 | #define CN93_SDP_R_OUT_SLIST_DBELL_START 0x10140 |
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| 124 | #define CN93_SDP_R_OUT_CONTROL_START 0x10150 |
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| 125 | #define CN93_SDP_R_OUT_ENABLE_START 0x10160 |
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| 126 | #define CN93_SDP_R_OUT_PKT_CNT_START 0x10180 |
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| 127 | #define CN93_SDP_R_OUT_BYTE_CNT_START 0x10190 |
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| 128 | |
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| 129 | #define CN93_SDP_R_OUT_CONTROL(ring) \ |
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| 130 | (CN93_SDP_R_OUT_CONTROL_START + ((ring) * CN93_RING_OFFSET)) |
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| 131 | |
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| 132 | #define CN93_SDP_R_OUT_ENABLE(ring) \ |
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| 133 | (CN93_SDP_R_OUT_ENABLE_START + ((ring) * CN93_RING_OFFSET)) |
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| 134 | |
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| 135 | #define CN93_SDP_R_OUT_SLIST_BADDR(ring) \ |
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| 136 | (CN93_SDP_R_OUT_SLIST_BADDR_START + ((ring) * CN93_RING_OFFSET)) |
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| 137 | |
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| 138 | #define CN93_SDP_R_OUT_SLIST_RSIZE(ring) \ |
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| 139 | (CN93_SDP_R_OUT_SLIST_RSIZE_START + ((ring) * CN93_RING_OFFSET)) |
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| 140 | |
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| 141 | #define CN93_SDP_R_OUT_SLIST_DBELL(ring) \ |
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| 142 | (CN93_SDP_R_OUT_SLIST_DBELL_START + ((ring) * CN93_RING_OFFSET)) |
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| 143 | |
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| 144 | #define CN93_SDP_R_OUT_CNTS(ring) \ |
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| 145 | (CN93_SDP_R_OUT_CNTS_START + ((ring) * CN93_RING_OFFSET)) |
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| 146 | |
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| 147 | #define CN93_SDP_R_OUT_INT_LEVELS(ring) \ |
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| 148 | (CN93_SDP_R_OUT_INT_LEVELS_START + ((ring) * CN93_RING_OFFSET)) |
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| 149 | |
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| 150 | #define CN93_SDP_R_OUT_PKT_CNT(ring) \ |
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| 151 | (CN93_SDP_R_OUT_PKT_CNT_START + ((ring) * CN93_RING_OFFSET)) |
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| 152 | |
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| 153 | #define CN93_SDP_R_OUT_BYTE_CNT(ring) \ |
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| 154 | (CN93_SDP_R_OUT_BYTE_CNT_START + ((ring) * CN93_RING_OFFSET)) |
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| 155 | |
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| 156 | /*------------------ R_OUT Masks ----------------*/ |
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| 157 | #define CN93_R_OUT_INT_LEVELS_BMODE BIT_ULL(63) |
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| 158 | #define CN93_R_OUT_INT_LEVELS_TIMET (32) |
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| 159 | |
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| 160 | #define CN93_R_OUT_CTL_IDLE BIT_ULL(40) |
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| 161 | #define CN93_R_OUT_CTL_ES_I BIT_ULL(34) |
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| 162 | #define CN93_R_OUT_CTL_NSR_I BIT_ULL(33) |
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| 163 | #define CN93_R_OUT_CTL_ROR_I BIT_ULL(32) |
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| 164 | #define CN93_R_OUT_CTL_ES_D BIT_ULL(30) |
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| 165 | #define CN93_R_OUT_CTL_NSR_D BIT_ULL(29) |
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| 166 | #define CN93_R_OUT_CTL_ROR_D BIT_ULL(28) |
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| 167 | #define CN93_R_OUT_CTL_ES_P BIT_ULL(26) |
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| 168 | #define CN93_R_OUT_CTL_NSR_P BIT_ULL(25) |
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| 169 | #define CN93_R_OUT_CTL_ROR_P BIT_ULL(24) |
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| 170 | #define CN93_R_OUT_CTL_IMODE BIT_ULL(23) |
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| 171 | |
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| 172 | /* ############### Interrupt Moderation Registers ############### */ |
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| 173 | #define CN93_SDP_R_IN_INT_MDRT_CTL0_START 0x10280 |
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| 174 | #define CN93_SDP_R_IN_INT_MDRT_CTL1_START 0x102A0 |
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| 175 | #define CN93_SDP_R_IN_INT_MDRT_DBG_START 0x102C0 |
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| 176 | |
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| 177 | #define CN93_SDP_R_OUT_INT_MDRT_CTL0_START 0x10380 |
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| 178 | #define CN93_SDP_R_OUT_INT_MDRT_CTL1_START 0x103A0 |
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| 179 | #define CN93_SDP_R_OUT_INT_MDRT_DBG_START 0x103C0 |
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| 180 | |
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| 181 | #define CN93_SDP_R_IN_INT_MDRT_CTL0(ring) \ |
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| 182 | (CN93_SDP_R_IN_INT_MDRT_CTL0_START + ((ring) * CN93_RING_OFFSET)) |
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| 183 | |
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| 184 | #define CN93_SDP_R_IN_INT_MDRT_CTL1(ring) \ |
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| 185 | (CN93_SDP_R_IN_INT_MDRT_CTL1_START + ((ring) * CN93_RING_OFFSET)) |
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| 186 | |
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| 187 | #define CN93_SDP_R_IN_INT_MDRT_DBG(ring) \ |
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| 188 | (CN93_SDP_R_IN_INT_MDRT_DBG_START + ((ring) * CN93_RING_OFFSET)) |
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| 189 | |
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| 190 | #define CN93_SDP_R_OUT_INT_MDRT_CTL0(ring) \ |
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| 191 | (CN93_SDP_R_OUT_INT_MDRT_CTL0_START + ((ring) * CN93_RING_OFFSET)) |
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| 192 | |
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| 193 | #define CN93_SDP_R_OUT_INT_MDRT_CTL1(ring) \ |
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| 194 | (CN93_SDP_R_OUT_INT_MDRT_CTL1_START + ((ring) * CN93_RING_OFFSET)) |
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| 195 | |
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| 196 | #define CN93_SDP_R_OUT_INT_MDRT_DBG(ring) \ |
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| 197 | (CN93_SDP_R_OUT_INT_MDRT_DBG_START + ((ring) * CN93_RING_OFFSET)) |
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| 198 | |
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| 199 | /* ##################### Mail Box Registers ########################## */ |
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| 200 | /* INT register for VF. when a MBOX write from PF happed to a VF, |
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| 201 | * corresponding bit will be set in this register as well as in |
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| 202 | * PF_VF_INT register. |
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| 203 | * |
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| 204 | * This is a RO register, the int can be cleared by writing 1 to PF_VF_INT |
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| 205 | */ |
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| 206 | /* Basically first 3 are from PF to VF. The last one is data from VF to PF */ |
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| 207 | #define CN93_SDP_R_MBOX_PF_VF_DATA_START 0x10210 |
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| 208 | #define CN93_SDP_R_MBOX_PF_VF_INT_START 0x10220 |
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| 209 | #define CN93_SDP_R_MBOX_VF_PF_DATA_START 0x10230 |
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| 210 | |
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| 211 | #define CN93_SDP_MBOX_VF_PF_DATA_START 0x24000 |
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| 212 | #define CN93_SDP_MBOX_PF_VF_DATA_START 0x22000 |
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| 213 | |
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| 214 | #define CN93_SDP_R_MBOX_PF_VF_DATA(ring) \ |
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| 215 | (CN93_SDP_R_MBOX_PF_VF_DATA_START + ((ring) * CN93_RING_OFFSET)) |
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| 216 | |
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| 217 | #define CN93_SDP_R_MBOX_PF_VF_INT(ring) \ |
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| 218 | (CN93_SDP_R_MBOX_PF_VF_INT_START + ((ring) * CN93_RING_OFFSET)) |
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| 219 | |
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| 220 | #define CN93_SDP_R_MBOX_VF_PF_DATA(ring) \ |
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| 221 | (CN93_SDP_R_MBOX_VF_PF_DATA_START + ((ring) * CN93_RING_OFFSET)) |
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| 222 | |
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| 223 | #define CN93_SDP_MBOX_VF_PF_DATA(ring) \ |
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| 224 | (CN93_SDP_MBOX_VF_PF_DATA_START + ((ring) * CN93_EPVF_RING_OFFSET)) |
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| 225 | |
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| 226 | #define CN93_SDP_MBOX_PF_VF_DATA(ring) \ |
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| 227 | (CN93_SDP_MBOX_PF_VF_DATA_START + ((ring) * CN93_EPVF_RING_OFFSET)) |
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| 228 | |
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| 229 | /* ##################### Interrupt Registers ########################## */ |
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| 230 | #define CN93_SDP_R_ERR_TYPE_START 0x10400 |
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| 231 | |
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| 232 | #define CN93_SDP_R_ERR_TYPE(ring) \ |
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| 233 | (CN93_SDP_R_ERR_TYPE_START + ((ring) * CN93_RING_OFFSET)) |
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| 234 | |
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| 235 | #define CN93_SDP_R_MBOX_ISM_START 0x10500 |
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| 236 | #define CN93_SDP_R_OUT_CNTS_ISM_START 0x10510 |
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| 237 | #define CN93_SDP_R_IN_CNTS_ISM_START 0x10520 |
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| 238 | |
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| 239 | #define CN93_SDP_R_MBOX_ISM(ring) \ |
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| 240 | (CN93_SDP_R_MBOX_ISM_START + ((ring) * CN93_RING_OFFSET)) |
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| 241 | |
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| 242 | #define CN93_SDP_R_OUT_CNTS_ISM(ring) \ |
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| 243 | (CN93_SDP_R_OUT_CNTS_ISM_START + ((ring) * CN93_RING_OFFSET)) |
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| 244 | |
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| 245 | #define CN93_SDP_R_IN_CNTS_ISM(ring) \ |
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| 246 | (CN93_SDP_R_IN_CNTS_ISM_START + ((ring) * CN93_RING_OFFSET)) |
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| 247 | |
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| 248 | #define CN93_SDP_EPF_MBOX_RINT_START 0x20100 |
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| 249 | #define CN93_SDP_EPF_MBOX_RINT_W1S_START 0x20120 |
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| 250 | #define CN93_SDP_EPF_MBOX_RINT_ENA_W1C_START 0x20140 |
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| 251 | #define CN93_SDP_EPF_MBOX_RINT_ENA_W1S_START 0x20160 |
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| 252 | |
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| 253 | #define CN93_SDP_EPF_VFIRE_RINT_START 0x20180 |
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| 254 | #define CN93_SDP_EPF_VFIRE_RINT_W1S_START 0x201A0 |
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| 255 | #define CN93_SDP_EPF_VFIRE_RINT_ENA_W1C_START 0x201C0 |
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| 256 | #define CN93_SDP_EPF_VFIRE_RINT_ENA_W1S_START 0x201E0 |
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| 257 | |
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| 258 | #define CN93_SDP_EPF_IRERR_RINT 0x20200 |
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| 259 | #define CN93_SDP_EPF_IRERR_RINT_W1S 0x20210 |
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| 260 | #define CN93_SDP_EPF_IRERR_RINT_ENA_W1C 0x20220 |
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| 261 | #define CN93_SDP_EPF_IRERR_RINT_ENA_W1S 0x20230 |
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| 262 | |
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| 263 | #define CN93_SDP_EPF_VFORE_RINT_START 0x20240 |
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| 264 | #define CN93_SDP_EPF_VFORE_RINT_W1S_START 0x20260 |
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| 265 | #define CN93_SDP_EPF_VFORE_RINT_ENA_W1C_START 0x20280 |
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| 266 | #define CN93_SDP_EPF_VFORE_RINT_ENA_W1S_START 0x202A0 |
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| 267 | |
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| 268 | #define CN93_SDP_EPF_ORERR_RINT 0x20320 |
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| 269 | #define CN93_SDP_EPF_ORERR_RINT_W1S 0x20330 |
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| 270 | #define CN93_SDP_EPF_ORERR_RINT_ENA_W1C 0x20340 |
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| 271 | #define CN93_SDP_EPF_ORERR_RINT_ENA_W1S 0x20350 |
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| 272 | |
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| 273 | #define CN93_SDP_EPF_OEI_RINT 0x20360 |
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| 274 | #define CN93_SDP_EPF_OEI_RINT_W1S 0x20370 |
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| 275 | #define CN93_SDP_EPF_OEI_RINT_ENA_W1C 0x20380 |
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| 276 | #define CN93_SDP_EPF_OEI_RINT_ENA_W1S 0x20390 |
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| 277 | |
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| 278 | #define CN93_SDP_EPF_DMA_RINT 0x20400 |
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| 279 | #define CN93_SDP_EPF_DMA_RINT_W1S 0x20410 |
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| 280 | #define CN93_SDP_EPF_DMA_RINT_ENA_W1C 0x20420 |
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| 281 | #define CN93_SDP_EPF_DMA_RINT_ENA_W1S 0x20430 |
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| 282 | |
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| 283 | #define CN93_SDP_EPF_DMA_INT_LEVEL_START 0x20440 |
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| 284 | #define CN93_SDP_EPF_DMA_CNT_START 0x20460 |
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| 285 | #define CN93_SDP_EPF_DMA_TIM_START 0x20480 |
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| 286 | |
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| 287 | #define CN93_SDP_EPF_MISC_RINT 0x204A0 |
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| 288 | #define CN93_SDP_EPF_MISC_RINT_W1S 0x204B0 |
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| 289 | #define CN93_SDP_EPF_MISC_RINT_ENA_W1C 0x204C0 |
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| 290 | #define CN93_SDP_EPF_MISC_RINT_ENA_W1S 0x204D0 |
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| 291 | |
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| 292 | #define CN93_SDP_EPF_DMA_VF_RINT_START 0x204E0 |
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| 293 | #define CN93_SDP_EPF_DMA_VF_RINT_W1S_START 0x20500 |
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| 294 | #define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C_START 0x20520 |
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| 295 | #define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S_START 0x20540 |
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| 296 | |
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| 297 | #define CN93_SDP_EPF_PP_VF_RINT_START 0x20560 |
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| 298 | #define CN93_SDP_EPF_PP_VF_RINT_W1S_START 0x20580 |
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| 299 | #define CN93_SDP_EPF_PP_VF_RINT_ENA_W1C_START 0x205A0 |
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| 300 | #define CN93_SDP_EPF_PP_VF_RINT_ENA_W1S_START 0x205C0 |
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| 301 | |
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| 302 | #define CN93_SDP_EPF_MBOX_RINT(index) \ |
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| 303 | (CN93_SDP_EPF_MBOX_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 304 | #define CN93_SDP_EPF_MBOX_RINT_W1S(index) \ |
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| 305 | (CN93_SDP_EPF_MBOX_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 306 | #define CN93_SDP_EPF_MBOX_RINT_ENA_W1C(index) \ |
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| 307 | (CN93_SDP_EPF_MBOX_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 308 | #define CN93_SDP_EPF_MBOX_RINT_ENA_W1S(index) \ |
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| 309 | (CN93_SDP_EPF_MBOX_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 310 | |
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| 311 | #define CN93_SDP_EPF_VFIRE_RINT(index) \ |
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| 312 | (CN93_SDP_EPF_VFIRE_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 313 | #define CN93_SDP_EPF_VFIRE_RINT_W1S(index) \ |
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| 314 | (CN93_SDP_EPF_VFIRE_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 315 | #define CN93_SDP_EPF_VFIRE_RINT_ENA_W1C(index) \ |
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| 316 | (CN93_SDP_EPF_VFIRE_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 317 | #define CN93_SDP_EPF_VFIRE_RINT_ENA_W1S(index) \ |
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| 318 | (CN93_SDP_EPF_VFIRE_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 319 | |
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| 320 | #define CN93_SDP_EPF_VFORE_RINT(index) \ |
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| 321 | (CN93_SDP_EPF_VFORE_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 322 | #define CN93_SDP_EPF_VFORE_RINT_W1S(index) \ |
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| 323 | (CN93_SDP_EPF_VFORE_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 324 | #define CN93_SDP_EPF_VFORE_RINT_ENA_W1C(index) \ |
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| 325 | (CN93_SDP_EPF_VFORE_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 326 | #define CN93_SDP_EPF_VFORE_RINT_ENA_W1S(index) \ |
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| 327 | (CN93_SDP_EPF_VFORE_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) |
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| 328 | |
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| 329 | #define CN93_SDP_EPF_DMA_VF_RINT(index) \ |
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| 330 | (CN93_SDP_EPF_DMA_VF_RINT_START + ((index) + CN93_BIT_ARRAY_OFFSET)) |
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| 331 | #define CN93_SDP_EPF_DMA_VF_RINT_W1S(index) \ |
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| 332 | (CN93_SDP_EPF_DMA_VF_RINT_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) |
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| 333 | #define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C(index) \ |
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| 334 | (CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C_START + ((index) + CN93_BIT_ARRAY_OFFSET)) |
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| 335 | #define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S(index) \ |
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| 336 | (CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) |
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| 337 | |
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| 338 | #define CN93_SDP_EPF_PP_VF_RINT(index) \ |
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| 339 | (CN93_SDP_EPF_PP_VF_RINT_START + ((index) + CN93_BIT_ARRAY_OFFSET)) |
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| 340 | #define CN93_SDP_EPF_PP_VF_RINT_W1S(index) \ |
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| 341 | (CN93_SDP_EPF_PP_VF_RINT_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) |
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| 342 | #define CN93_SDP_EPF_PP_VF_RINT_ENA_W1C(index) \ |
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| 343 | (CN93_SDP_EPF_PP_VF_RINT_ENA_W1C_START + ((index) + CN93_BIT_ARRAY_OFFSET)) |
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| 344 | #define CN93_SDP_EPF_PP_VF_RINT_ENA_W1S(index) \ |
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| 345 | (CN93_SDP_EPF_PP_VF_RINT_ENA_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) |
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| 346 | |
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| 347 | /*------------------ Interrupt Masks ----------------*/ |
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| 348 | #define CN93_INTR_R_SEND_ISM BIT_ULL(63) |
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| 349 | #define CN93_INTR_R_OUT_INT BIT_ULL(62) |
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| 350 | #define CN93_INTR_R_IN_INT BIT_ULL(61) |
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| 351 | #define CN93_INTR_R_MBOX_INT BIT_ULL(60) |
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| 352 | #define CN93_INTR_R_RESEND BIT_ULL(59) |
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| 353 | #define CN93_INTR_R_CLR_TIM BIT_ULL(58) |
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| 354 | |
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| 355 | /* ####################### Ring Mapping Registers ################################## */ |
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| 356 | #define CN93_SDP_EPVF_RING_START 0x26000 |
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| 357 | #define CN93_SDP_IN_RING_TB_MAP_START 0x28000 |
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| 358 | #define CN93_SDP_IN_RATE_LIMIT_START 0x2A000 |
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| 359 | #define CN93_SDP_MAC_PF_RING_CTL_START 0x2C000 |
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| 360 | |
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| 361 | #define CN93_SDP_EPVF_RING(ring) \ |
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| 362 | (CN93_SDP_EPVF_RING_START + ((ring) * CN93_EPVF_RING_OFFSET)) |
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| 363 | #define CN93_SDP_IN_RING_TB_MAP(ring) \ |
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| 364 | (CN93_SDP_N_RING_TB_MAP_START + ((ring) * CN93_EPVF_RING_OFFSET)) |
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| 365 | #define CN93_SDP_IN_RATE_LIMIT(ring) \ |
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| 366 | (CN93_SDP_IN_RATE_LIMIT_START + ((ring) * CN93_EPVF_RING_OFFSET)) |
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| 367 | #define CN93_SDP_MAC_PF_RING_CTL(mac) \ |
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| 368 | (CN93_SDP_MAC_PF_RING_CTL_START + ((mac) * CN93_MAC_OFFSET)) |
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| 369 | |
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| 370 | #define CN93_SDP_MAC_PF_RING_CTL_NPFS(val) ((val) & 0xF) |
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| 371 | #define CN93_SDP_MAC_PF_RING_CTL_SRN(val) (((val) >> 8) & 0xFF) |
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| 372 | #define CN93_SDP_MAC_PF_RING_CTL_RPPF(val) (((val) >> 16) & 0x3F) |
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| 373 | |
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| 374 | #define CN98_SDP_MAC_PF_RING_CTL_NPFS(val) (((val) >> 48) & 0xF) |
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| 375 | #define CN98_SDP_MAC_PF_RING_CTL_SRN(val) ((val) & 0xFF) |
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| 376 | #define CN98_SDP_MAC_PF_RING_CTL_RPPF(val) (((val) >> 32) & 0x3F) |
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| 377 | |
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| 378 | /* Number of non-queue interrupts in CN93xx */ |
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| 379 | #define CN93_NUM_NON_IOQ_INTR 16 |
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| 380 | |
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| 381 | /* bit 0 for control mbox interrupt */ |
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| 382 | #define CN93_SDP_EPF_OEI_RINT_DATA_BIT_MBOX BIT_ULL(0) |
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| 383 | /* bit 1 for firmware heartbeat interrupt */ |
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| 384 | #define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1) |
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| 385 | |
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| 386 | #define CN93_PEM_BAR4_INDEX 7 |
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| 387 | #define CN93_PEM_BAR4_INDEX_SIZE 0x400000ULL |
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| 388 | #define CN93_PEM_BAR4_INDEX_OFFSET (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR4_INDEX_SIZE) |
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| 389 | |
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| 390 | #endif /* _OCTEP_REGS_CN9K_PF_H_ */ |
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| 391 | |
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