| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Marvell RVU Admin Function driver |
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| 3 | * |
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| 4 | * Copyright (C) 2018 Marvell. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef RVU_REG_H |
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| 9 | #define RVU_REG_H |
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| 10 | |
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| 11 | /* Admin function registers */ |
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| 12 | #define RVU_AF_MSIXTR_BASE (0x10) |
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| 13 | #define RVU_AF_ECO (0x20) |
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| 14 | #define RVU_AF_BLK_RST (0x30) |
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| 15 | #define RVU_AF_PF_BAR4_ADDR (0x40) |
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| 16 | #define RVU_AF_RAS (0x100) |
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| 17 | #define RVU_AF_RAS_W1S (0x108) |
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| 18 | #define RVU_AF_RAS_ENA_W1S (0x110) |
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| 19 | #define RVU_AF_RAS_ENA_W1C (0x118) |
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| 20 | #define RVU_AF_GEN_INT (0x120) |
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| 21 | #define RVU_AF_GEN_INT_W1S (0x128) |
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| 22 | #define RVU_AF_GEN_INT_ENA_W1S (0x130) |
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| 23 | #define RVU_AF_GEN_INT_ENA_W1C (0x138) |
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| 24 | #define RVU_AF_AFPF_MBOX0 (0x02000) |
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| 25 | #define RVU_AF_AFPF_MBOX1 (0x02008) |
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| 26 | #define RVU_AF_AFPFX_MBOXX(a, b) (0x2000 | (a) << 4 | (b) << 3) |
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| 27 | #define RVU_AF_PFME_STATUS (0x2800) |
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| 28 | #define RVU_AF_PFTRPEND (0x2810) |
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| 29 | #define RVU_AF_PFTRPEND_W1S (0x2820) |
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| 30 | #define RVU_AF_PF_RST (0x2840) |
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| 31 | #define RVU_AF_HWVF_RST (0x2850) |
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| 32 | #define RVU_AF_PFAF_MBOX_INT (0x2880) |
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| 33 | #define RVU_AF_PFAF_MBOX_INT_W1S (0x2888) |
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| 34 | #define RVU_AF_PFAF_MBOX_INT_ENA_W1S (0x2890) |
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| 35 | #define RVU_AF_PFAF_MBOX_INT_ENA_W1C (0x2898) |
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| 36 | #define RVU_AF_PFFLR_INT (0x28a0) |
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| 37 | #define RVU_AF_PFFLR_INT_W1S (0x28a8) |
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| 38 | #define RVU_AF_PFFLR_INT_ENA_W1S (0x28b0) |
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| 39 | #define RVU_AF_PFFLR_INT_ENA_W1C (0x28b8) |
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| 40 | #define RVU_AF_PFME_INT (0x28c0) |
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| 41 | #define RVU_AF_PFME_INT_W1S (0x28c8) |
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| 42 | #define RVU_AF_PFME_INT_ENA_W1S (0x28d0) |
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| 43 | #define RVU_AF_PFME_INT_ENA_W1C (0x28d8) |
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| 44 | #define RVU_AF_PFX_BAR4_ADDR(a) (0x5000 | (a) << 4) |
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| 45 | #define RVU_AF_PFX_BAR4_CFG (0x5200 | (a) << 4) |
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| 46 | #define RVU_AF_PFX_VF_BAR4_ADDR (0x5400 | (a) << 4) |
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| 47 | #define RVU_AF_PFX_VF_BAR4_CFG (0x5600 | (a) << 4) |
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| 48 | #define RVU_AF_PFX_LMTLINE_ADDR (0x5800 | (a) << 4) |
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| 49 | #define RVU_AF_SMMU_ADDR_REQ (0x6000) |
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| 50 | #define RVU_AF_SMMU_TXN_REQ (0x6008) |
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| 51 | #define RVU_AF_SMMU_ADDR_RSP_STS (0x6010) |
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| 52 | #define RVU_AF_SMMU_ADDR_TLN (0x6018) |
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| 53 | #define RVU_AF_SMMU_TLN_FLIT0 (0x6020) |
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| 54 | |
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| 55 | /* Admin function's privileged PF/VF registers */ |
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| 56 | #define RVU_PRIV_CONST (0x8000000) |
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| 57 | #define RVU_PRIV_GEN_CFG (0x8000010) |
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| 58 | #define RVU_PRIV_CLK_CFG (0x8000020) |
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| 59 | #define RVU_PRIV_ACTIVE_PC (0x8000030) |
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| 60 | #define RVU_PRIV_PFX_CFG(a) (0x8000100 | (a) << 16) |
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| 61 | #define RVU_PRIV_PFX_MSIX_CFG(a) (0x8000110 | (a) << 16) |
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| 62 | #define RVU_PRIV_PFX_ID_CFG(a) (0x8000120 | (a) << 16) |
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| 63 | #define RVU_PRIV_PFX_INT_CFG(a) (0x8000200 | (a) << 16) |
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| 64 | #define RVU_PRIV_PFX_NIXX_CFG(a) (0x8000300 | (a) << 3) |
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| 65 | #define RVU_PRIV_PFX_NPA_CFG (0x8000310) |
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| 66 | #define RVU_PRIV_PFX_SSO_CFG (0x8000320) |
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| 67 | #define RVU_PRIV_PFX_SSOW_CFG (0x8000330) |
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| 68 | #define RVU_PRIV_PFX_TIM_CFG (0x8000340) |
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| 69 | #define RVU_PRIV_PFX_CPTX_CFG(a) (0x8000350 | (a) << 3) |
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| 70 | #define RVU_PRIV_BLOCK_TYPEX_REV(a) (0x8000400 | (a) << 3) |
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| 71 | #define RVU_PRIV_HWVFX_INT_CFG(a) (0x8001280 | (a) << 16) |
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| 72 | #define RVU_PRIV_HWVFX_NIXX_CFG(a) (0x8001300 | (a) << 3) |
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| 73 | #define RVU_PRIV_HWVFX_NPA_CFG (0x8001310) |
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| 74 | #define RVU_PRIV_HWVFX_SSO_CFG (0x8001320) |
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| 75 | #define RVU_PRIV_HWVFX_SSOW_CFG (0x8001330) |
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| 76 | #define RVU_PRIV_HWVFX_TIM_CFG (0x8001340) |
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| 77 | #define RVU_PRIV_HWVFX_CPTX_CFG(a) (0x8001350 | (a) << 3) |
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| 78 | |
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| 79 | /* RVU PF registers */ |
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| 80 | #define RVU_PF_VFX_PFVF_MBOX0 (0x00000) |
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| 81 | #define RVU_PF_VFX_PFVF_MBOX1 (0x00008) |
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| 82 | #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3) |
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| 83 | #define RVU_PF_VF_BAR4_ADDR (0x10) |
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| 84 | #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) |
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| 85 | #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3) |
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| 86 | #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3) |
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| 87 | #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3) |
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| 88 | #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3) |
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| 89 | #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3) |
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| 90 | #define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8C0 | (a) << 3) |
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| 91 | #define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8E0 | (a) << 3) |
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| 92 | #define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3) |
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| 93 | #define RVU_PF_VFFLR_INT_W1SX(a) (0x920 | (a) << 3) |
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| 94 | #define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3) |
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| 95 | #define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960 | (a) << 3) |
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| 96 | #define RVU_PF_VFME_INTX(a) (0x980 | (a) << 3) |
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| 97 | #define RVU_PF_VFME_INT_W1SX(a) (0x9A0 | (a) << 3) |
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| 98 | #define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3) |
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| 99 | #define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9E0 | (a) << 3) |
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| 100 | #define RVU_PF_PFAF_MBOX0 (0xC00) |
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| 101 | #define RVU_PF_PFAF_MBOX1 (0xC08) |
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| 102 | #define RVU_PF_PFAF_MBOXX(a) (0xC00 | (a) << 3) |
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| 103 | #define RVU_PF_INT (0xc20) |
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| 104 | #define RVU_PF_INT_W1S (0xc28) |
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| 105 | #define RVU_PF_INT_ENA_W1S (0xc30) |
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| 106 | #define RVU_PF_INT_ENA_W1C (0xc38) |
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| 107 | #define RVU_PF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4) |
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| 108 | #define RVU_PF_MSIX_VECX_CTL(a) (0x008 | (a) << 4) |
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| 109 | #define RVU_PF_MSIX_PBAX(a) (0xF0000 | (a) << 3) |
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| 110 | #define RVU_PF_VF_MBOX_ADDR (0xC40) |
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| 111 | #define RVU_PF_LMTLINE_ADDR (0xC48) |
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| 112 | |
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| 113 | /* RVU VF registers */ |
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| 114 | #define RVU_VF_VFPF_MBOX0 (0x00000) |
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| 115 | #define RVU_VF_VFPF_MBOX1 (0x00008) |
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| 116 | |
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| 117 | /* NPA block's admin function registers */ |
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| 118 | #define NPA_AF_BLK_RST (0x0000) |
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| 119 | #define NPA_AF_CONST (0x0010) |
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| 120 | #define NPA_AF_CONST1 (0x0018) |
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| 121 | #define NPA_AF_LF_RST (0x0020) |
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| 122 | #define NPA_AF_GEN_CFG (0x0030) |
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| 123 | #define NPA_AF_NDC_CFG (0x0040) |
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| 124 | #define NPA_AF_INP_CTL (0x00D0) |
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| 125 | #define NPA_AF_ACTIVE_CYCLES_PC (0x00F0) |
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| 126 | #define NPA_AF_AVG_DELAY (0x0100) |
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| 127 | #define NPA_AF_GEN_INT (0x0140) |
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| 128 | #define NPA_AF_GEN_INT_W1S (0x0148) |
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| 129 | #define NPA_AF_GEN_INT_ENA_W1S (0x0150) |
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| 130 | #define NPA_AF_GEN_INT_ENA_W1C (0x0158) |
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| 131 | #define NPA_AF_RVU_INT (0x0160) |
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| 132 | #define NPA_AF_RVU_INT_W1S (0x0168) |
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| 133 | #define NPA_AF_RVU_INT_ENA_W1S (0x0170) |
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| 134 | #define NPA_AF_RVU_INT_ENA_W1C (0x0178) |
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| 135 | #define NPA_AF_ERR_INT (0x0180) |
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| 136 | #define NPA_AF_ERR_INT_W1S (0x0188) |
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| 137 | #define NPA_AF_ERR_INT_ENA_W1S (0x0190) |
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| 138 | #define NPA_AF_ERR_INT_ENA_W1C (0x0198) |
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| 139 | #define NPA_AF_RAS (0x01A0) |
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| 140 | #define NPA_AF_RAS_W1S (0x01A8) |
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| 141 | #define NPA_AF_RAS_ENA_W1S (0x01B0) |
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| 142 | #define NPA_AF_RAS_ENA_W1C (0x01B8) |
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| 143 | #define NPA_AF_BP_TEST (0x0200) |
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| 144 | #define NPA_AF_ECO (0x0300) |
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| 145 | #define NPA_AF_AQ_CFG (0x0600) |
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| 146 | #define NPA_AF_AQ_BASE (0x0610) |
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| 147 | #define NPA_AF_AQ_STATUS (0x0620) |
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| 148 | #define NPA_AF_AQ_DOOR (0x0630) |
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| 149 | #define NPA_AF_AQ_DONE_WAIT (0x0640) |
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| 150 | #define NPA_AF_AQ_DONE (0x0650) |
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| 151 | #define NPA_AF_AQ_DONE_ACK (0x0660) |
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| 152 | #define NPA_AF_AQ_DONE_INT (0x0680) |
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| 153 | #define NPA_AF_AQ_DONE_INT_W1S (0x0688) |
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| 154 | #define NPA_AF_AQ_DONE_ENA_W1S (0x0690) |
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| 155 | #define NPA_AF_AQ_DONE_ENA_W1C (0x0698) |
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| 156 | #define NPA_AF_BATCH_CTL (0x06a0) |
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| 157 | #define NPA_AF_LFX_AURAS_CFG(a) (0x4000 | (a) << 18) |
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| 158 | #define NPA_AF_LFX_LOC_AURAS_BASE(a) (0x4010 | (a) << 18) |
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| 159 | #define NPA_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 18) |
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| 160 | #define NPA_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 18) |
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| 161 | #define NPA_PRIV_AF_INT_CFG (0x10000) |
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| 162 | #define NPA_PRIV_LFX_CFG (0x10010) |
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| 163 | #define NPA_PRIV_LFX_INT_CFG (0x10020) |
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| 164 | #define NPA_AF_RVU_LF_CFG_DEBUG (0x10030) |
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| 165 | |
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| 166 | /* NIX block's admin function registers */ |
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| 167 | #define NIX_AF_CFG (0x0000) |
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| 168 | #define NIX_AF_STATUS (0x0010) |
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| 169 | #define NIX_AF_NDC_CFG (0x0018) |
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| 170 | #define NIX_AF_CONST (0x0020) |
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| 171 | #define NIX_AF_CONST1 (0x0028) |
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| 172 | #define NIX_AF_CONST2 (0x0030) |
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| 173 | #define NIX_AF_CONST3 (0x0038) |
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| 174 | #define NIX_AF_SQ_CONST (0x0040) |
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| 175 | #define NIX_AF_CQ_CONST (0x0048) |
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| 176 | #define NIX_AF_RQ_CONST (0x0050) |
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| 177 | #define NIX_AF_PL_CONST (0x0058) |
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| 178 | #define NIX_AF_PSE_CONST (0x0060) |
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| 179 | #define NIX_AF_TL1_CONST (0x0070) |
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| 180 | #define NIX_AF_TL2_CONST (0x0078) |
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| 181 | #define NIX_AF_TL3_CONST (0x0080) |
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| 182 | #define NIX_AF_TL4_CONST (0x0088) |
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| 183 | #define NIX_AF_MDQ_CONST (0x0090) |
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| 184 | #define NIX_AF_MC_MIRROR_CONST (0x0098) |
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| 185 | #define NIX_AF_LSO_CFG (0x00A8) |
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| 186 | #define NIX_AF_BLK_RST (0x00B0) |
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| 187 | #define NIX_AF_TX_TSTMP_CFG (0x00C0) |
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| 188 | #define NIX_AF_PL_TS (0x00C8) |
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| 189 | #define NIX_AF_RX_CFG (0x00D0) |
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| 190 | #define NIX_AF_AVG_DELAY (0x00E0) |
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| 191 | #define NIX_AF_CINT_DELAY (0x00F0) |
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| 192 | #define NIX_AF_VWQE_TIMER (0x00F8) |
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| 193 | #define NIX_AF_RX_MCAST_BASE (0x0100) |
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| 194 | #define NIX_AF_RX_MCAST_CFG (0x0110) |
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| 195 | #define NIX_AF_RX_MCAST_BUF_BASE (0x0120) |
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| 196 | #define NIX_AF_RX_MCAST_BUF_CFG (0x0130) |
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| 197 | #define NIX_AF_RX_MIRROR_BUF_BASE (0x0140) |
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| 198 | #define NIX_AF_RX_MIRROR_BUF_CFG (0x0148) |
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| 199 | #define NIX_AF_LF_RST (0x0150) |
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| 200 | #define NIX_AF_GEN_INT (0x0160) |
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| 201 | #define NIX_AF_GEN_INT_W1S (0x0168) |
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| 202 | #define NIX_AF_GEN_INT_ENA_W1S (0x0170) |
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| 203 | #define NIX_AF_GEN_INT_ENA_W1C (0x0178) |
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| 204 | #define NIX_AF_ERR_INT (0x0180) |
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| 205 | #define NIX_AF_ERR_INT_W1S (0x0188) |
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| 206 | #define NIX_AF_ERR_INT_ENA_W1S (0x0190) |
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| 207 | #define NIX_AF_ERR_INT_ENA_W1C (0x0198) |
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| 208 | #define NIX_AF_RAS (0x01A0) |
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| 209 | #define NIX_AF_RAS_W1S (0x01A8) |
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| 210 | #define NIX_AF_RAS_ENA_W1S (0x01B0) |
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| 211 | #define NIX_AF_RAS_ENA_W1C (0x01B8) |
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| 212 | #define NIX_AF_RVU_INT (0x01C0) |
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| 213 | #define NIX_AF_RVU_INT_W1S (0x01C8) |
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| 214 | #define NIX_AF_RVU_INT_ENA_W1S (0x01D0) |
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| 215 | #define NIX_AF_RVU_INT_ENA_W1C (0x01D8) |
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| 216 | #define NIX_AF_TCP_TIMER (0x01E0) |
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| 217 | #define NIX_AF_RX_DEF_ET(a) (0x01F0ull | (uint64_t)(a) << 3) |
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| 218 | #define NIX_AF_RX_DEF_OL2 (0x0200) |
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| 219 | #define NIX_AF_RX_DEF_OIP4 (0x0210) |
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| 220 | #define NIX_AF_RX_DEF_IIP4 (0x0220) |
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| 221 | #define NIX_AF_RX_DEF_VLAN0_PCP_DEI (0x0228) |
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| 222 | #define NIX_AF_RX_DEF_OIP6 (0x0230) |
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| 223 | #define NIX_AF_RX_DEF_VLAN1_PCP_DEI (0x0238) |
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| 224 | #define NIX_AF_RX_DEF_IIP6 (0x0240) |
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| 225 | #define NIX_AF_RX_DEF_OTCP (0x0250) |
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| 226 | #define NIX_AF_RX_DEF_ITCP (0x0260) |
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| 227 | #define NIX_AF_RX_DEF_OUDP (0x0270) |
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| 228 | #define NIX_AF_RX_DEF_IUDP (0x0280) |
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| 229 | #define NIX_AF_RX_DEF_OSCTP (0x0290) |
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| 230 | #define NIX_AF_RX_DEF_CST_APAD0 (0x0298) |
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| 231 | #define NIX_AF_RX_DEF_ISCTP (0x02A0) |
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| 232 | #define NIX_AF_RX_DEF_IPSECX (0x02B0) |
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| 233 | #define NIX_AF_RX_DEF_CST_APAD1 (0x02A8) |
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| 234 | #define NIX_AF_RX_DEF_IIP4_DSCP (0x02E0) |
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| 235 | #define NIX_AF_RX_DEF_OIP4_DSCP (0x02E8) |
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| 236 | #define NIX_AF_RX_DEF_IIP6_DSCP (0x02F0) |
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| 237 | #define NIX_AF_RX_DEF_OIP6_DSCP (0x02F8) |
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| 238 | #define NIX_AF_RX_IPSEC_GEN_CFG (0x0300) |
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| 239 | #define NIX_AF_RX_CPTX_INST_ADDR (0x0310) |
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| 240 | #define NIX_AF_RX_CPTX_INST_QSEL(a) (0x0320ull | (uint64_t)(a) << 3) |
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| 241 | #define NIX_AF_RX_CPTX_CREDIT(a) (0x0360ull | (uint64_t)(a) << 3) |
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| 242 | #define NIX_AF_NDC_TX_SYNC (0x03F0) |
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| 243 | #define NIX_AF_AQ_CFG (0x0400) |
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| 244 | #define NIX_AF_AQ_BASE (0x0410) |
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| 245 | #define NIX_AF_AQ_STATUS (0x0420) |
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| 246 | #define NIX_AF_AQ_DOOR (0x0430) |
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| 247 | #define NIX_AF_AQ_DONE_WAIT (0x0440) |
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| 248 | #define NIX_AF_AQ_DONE (0x0450) |
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| 249 | #define NIX_AF_AQ_DONE_ACK (0x0460) |
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| 250 | #define NIX_AF_AQ_DONE_TIMER (0x0470) |
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| 251 | #define NIX_AF_AQ_DONE_INT (0x0480) |
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| 252 | #define NIX_AF_AQ_DONE_INT_W1S (0x0488) |
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| 253 | #define NIX_AF_AQ_DONE_ENA_W1S (0x0490) |
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| 254 | #define NIX_AF_AQ_DONE_ENA_W1C (0x0498) |
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| 255 | #define NIX_AF_RX_LINKX_SLX_SPKT_CNT (0x0500) |
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| 256 | #define NIX_AF_RX_LINKX_SLX_SXQE_CNT (0x0510) |
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| 257 | #define NIX_AF_RX_MCAST_JOBSX_SW_CNT (0x0520) |
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| 258 | #define NIX_AF_RX_MIRROR_JOBSX_SW_CNT (0x0530) |
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| 259 | #define NIX_AF_RX_LINKX_CFG(a) (0x0540 | (a) << 16) |
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| 260 | #define NIX_AF_RX_SW_SYNC (0x0550) |
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| 261 | #define NIX_AF_RX_SW_SYNC_DONE (0x0560) |
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| 262 | #define NIX_AF_SEB_ECO (0x0600) |
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| 263 | #define NIX_AF_SEB_TEST_BP (0x0610) |
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| 264 | #define NIX_AF_NORM_TX_FIFO_STATUS (0x0620) |
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| 265 | #define NIX_AF_EXPR_TX_FIFO_STATUS (0x0630) |
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| 266 | #define NIX_AF_SDP_TX_FIFO_STATUS (0x0640) |
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| 267 | #define NIX_AF_TX_NPC_CAPTURE_CONFIG (0x0660) |
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| 268 | #define NIX_AF_TX_NPC_CAPTURE_INFO (0x0670) |
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| 269 | #define NIX_AF_SEB_CFG (0x05F0) |
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| 270 | #define NIX_PTP_1STEP_EN BIT_ULL(2) |
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| 271 | |
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| 272 | #define NIX_AF_DEBUG_NPC_RESP_DATAX(a) (0x680 | (a) << 3) |
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| 273 | #define NIX_AF_SMQX_CFG(a) (0x700 | (a) << 16) |
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| 274 | #define NIX_AF_SQM_DBG_CTL_STATUS (0x750) |
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| 275 | #define NIX_AF_DWRR_SDP_MTU (0x790) /* All CN10K except CN10KB */ |
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| 276 | #define NIX_AF_DWRR_MTUX(a) (0x790 | (a) << 16) /* Only for CN10KB */ |
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| 277 | #define NIX_AF_DWRR_RPM_MTU (0x7A0) |
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| 278 | #define NIX_AF_PSE_CHANNEL_LEVEL (0x800) |
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| 279 | #define NIX_AF_PSE_SHAPER_CFG (0x810) |
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| 280 | #define NIX_AF_TX_EXPR_CREDIT (0x830) |
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| 281 | #define NIX_AF_MARK_FORMATX_CTL(a) (0x900 | (a) << 18) |
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| 282 | #define NIX_AF_TX_LINKX_NORM_CREDIT(a) (0xA00 | (a) << 16) |
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| 283 | #define NIX_AF_TX_LINKX_EXPR_CREDIT(a) (0xA10 | (a) << 16) |
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| 284 | #define NIX_AF_TX_LINKX_SW_XOFF(a) (0xA20 | (a) << 16) |
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| 285 | #define NIX_AF_TX_LINKX_HW_XOFF(a) (0xA30 | (a) << 16) |
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| 286 | #define NIX_AF_SDP_LINK_CREDIT (0xa40) |
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| 287 | #define NIX_AF_SDP_SW_XOFFX(a) (0xA60 | (a) << 3) |
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| 288 | #define NIX_AF_SDP_HW_XOFFX(a) (0xAC0 | (a) << 3) |
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| 289 | #define NIX_AF_TL4X_BP_STATUS(a) (0xB00 | (a) << 16) |
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| 290 | #define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xB10 | (a) << 16) |
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| 291 | #define NIX_AF_TL1X_SCHEDULE(a) (0xC00 | (a) << 16) |
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| 292 | #define NIX_AF_TL1X_SHAPE(a) (0xC10 | (a) << 16) |
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| 293 | #define NIX_AF_TL1X_CIR(a) (0xC20 | (a) << 16) |
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| 294 | #define NIX_AF_TL1X_SHAPE_STATE(a) (0xC50 | (a) << 16) |
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| 295 | #define NIX_AF_TL1X_SW_XOFF(a) (0xC70 | (a) << 16) |
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| 296 | #define NIX_AF_TL1X_TOPOLOGY(a) (0xC80 | (a) << 16) |
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| 297 | #define NIX_AF_TL1X_GREEN(a) (0xC90 | (a) << 16) |
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| 298 | #define NIX_AF_TL1X_YELLOW(a) (0xCA0 | (a) << 16) |
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| 299 | #define NIX_AF_TL1X_RED(a) (0xCB0 | (a) << 16) |
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| 300 | #define NIX_AF_TL1X_MD_DEBUG0(a) (0xCC0 | (a) << 16) |
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| 301 | #define NIX_AF_TL1X_MD_DEBUG1(a) (0xCC8 | (a) << 16) |
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| 302 | #define NIX_AF_TL1X_MD_DEBUG2(a) (0xCD0 | (a) << 16) |
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| 303 | #define NIX_AF_TL1X_MD_DEBUG3(a) (0xCD8 | (a) << 16) |
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| 304 | #define NIX_AF_TL1A_DEBUG (0xce0) |
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| 305 | #define NIX_AF_TL1B_DEBUG (0xcf0) |
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| 306 | #define NIX_AF_TL1_DEBUG_GREEN (0xd00) |
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| 307 | #define NIX_AF_TL1_DEBUG_NODE (0xd10) |
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| 308 | #define NIX_AF_TL1X_DROPPED_PACKETS(a) (0xD20 | (a) << 16) |
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| 309 | #define NIX_AF_TL1X_DROPPED_BYTES(a) (0xD30 | (a) << 16) |
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| 310 | #define NIX_AF_TL1X_RED_PACKETS(a) (0xD40 | (a) << 16) |
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| 311 | #define NIX_AF_TL1X_RED_BYTES(a) (0xD50 | (a) << 16) |
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| 312 | #define NIX_AF_TL1X_YELLOW_PACKETS(a) (0xD60 | (a) << 16) |
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| 313 | #define NIX_AF_TL1X_YELLOW_BYTES(a) (0xD70 | (a) << 16) |
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| 314 | #define NIX_AF_TL1X_GREEN_PACKETS(a) (0xD80 | (a) << 16) |
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| 315 | #define NIX_AF_TL1X_GREEN_BYTES(a) (0xD90 | (a) << 16) |
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| 316 | #define NIX_AF_TL2X_SCHEDULE(a) (0xE00 | (a) << 16) |
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| 317 | #define NIX_AF_TL2X_SHAPE(a) (0xE10 | (a) << 16) |
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| 318 | #define NIX_AF_TL2X_CIR(a) (0xE20 | (a) << 16) |
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| 319 | #define NIX_AF_TL2X_PIR(a) (0xE30 | (a) << 16) |
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| 320 | #define NIX_AF_TL2X_SCHED_STATE(a) (0xE40 | (a) << 16) |
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| 321 | #define NIX_AF_TL2X_SHAPE_STATE(a) (0xE50 | (a) << 16) |
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| 322 | #define NIX_AF_TL2X_POINTERS(a) (0xE60 | (a) << 16) |
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| 323 | #define NIX_AF_TL2X_SW_XOFF(a) (0xE70 | (a) << 16) |
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| 324 | #define NIX_AF_TL2X_TOPOLOGY(a) (0xE80 | (a) << 16) |
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| 325 | #define NIX_AF_TL2X_PARENT(a) (0xE88 | (a) << 16) |
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| 326 | #define NIX_AF_TL2X_GREEN(a) (0xE90 | (a) << 16) |
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| 327 | #define NIX_AF_TL2X_YELLOW(a) (0xEA0 | (a) << 16) |
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| 328 | #define NIX_AF_TL2X_RED(a) (0xEB0 | (a) << 16) |
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| 329 | #define NIX_AF_TL2X_MD_DEBUG0(a) (0xEC0 | (a) << 16) |
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| 330 | #define NIX_AF_TL2X_MD_DEBUG1(a) (0xEC8 | (a) << 16) |
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| 331 | #define NIX_AF_TL2X_MD_DEBUG2(a) (0xED0 | (a) << 16) |
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| 332 | #define NIX_AF_TL2X_MD_DEBUG3(a) (0xED8 | (a) << 16) |
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| 333 | #define NIX_AF_TL2A_DEBUG (0xee0) |
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| 334 | #define NIX_AF_TL2B_DEBUG (0xef0) |
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| 335 | #define NIX_AF_TL3X_SCHEDULE(a) (0x1000 | (a) << 16) |
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| 336 | #define NIX_AF_TL3X_SHAPE(a) (0x1010 | (a) << 16) |
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| 337 | #define NIX_AF_TL3X_CIR(a) (0x1020 | (a) << 16) |
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| 338 | #define NIX_AF_TL3X_PIR(a) (0x1030 | (a) << 16) |
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| 339 | #define NIX_AF_TL3X_SCHED_STATE(a) (0x1040 | (a) << 16) |
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| 340 | #define NIX_AF_TL3X_SHAPE_STATE(a) (0x1050 | (a) << 16) |
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| 341 | #define NIX_AF_TL3X_POINTERS(a) (0x1060 | (a) << 16) |
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| 342 | #define NIX_AF_TL3X_SW_XOFF(a) (0x1070 | (a) << 16) |
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| 343 | #define NIX_AF_TL3X_TOPOLOGY(a) (0x1080 | (a) << 16) |
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| 344 | #define NIX_AF_TL3X_PARENT(a) (0x1088 | (a) << 16) |
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| 345 | #define NIX_AF_TL3X_GREEN(a) (0x1090 | (a) << 16) |
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| 346 | #define NIX_AF_TL3X_YELLOW(a) (0x10A0 | (a) << 16) |
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| 347 | #define NIX_AF_TL3X_RED(a) (0x10B0 | (a) << 16) |
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| 348 | #define NIX_AF_TL3X_MD_DEBUG0(a) (0x10C0 | (a) << 16) |
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| 349 | #define NIX_AF_TL3X_MD_DEBUG1(a) (0x10C8 | (a) << 16) |
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| 350 | #define NIX_AF_TL3X_MD_DEBUG2(a) (0x10D0 | (a) << 16) |
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| 351 | #define NIX_AF_TL3X_MD_DEBUG3(a) (0x10D8 | (a) << 16) |
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| 352 | #define NIX_AF_TL3A_DEBUG (0x10e0) |
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| 353 | #define NIX_AF_TL3B_DEBUG (0x10f0) |
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| 354 | #define NIX_AF_TL4X_SCHEDULE(a) (0x1200 | (a) << 16) |
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| 355 | #define NIX_AF_TL4X_SHAPE(a) (0x1210 | (a) << 16) |
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| 356 | #define NIX_AF_TL4X_CIR(a) (0x1220 | (a) << 16) |
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| 357 | #define NIX_AF_TL4X_PIR(a) (0x1230 | (a) << 16) |
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| 358 | #define NIX_AF_TL4X_SCHED_STATE(a) (0x1240 | (a) << 16) |
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| 359 | #define NIX_AF_TL4X_SHAPE_STATE(a) (0x1250 | (a) << 16) |
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| 360 | #define NIX_AF_TL4X_POINTERS(a) (0x1260 | (a) << 16) |
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| 361 | #define NIX_AF_TL4X_SW_XOFF(a) (0x1270 | (a) << 16) |
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| 362 | #define NIX_AF_TL4X_TOPOLOGY(a) (0x1280 | (a) << 16) |
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| 363 | #define NIX_AF_TL4X_PARENT(a) (0x1288 | (a) << 16) |
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| 364 | #define NIX_AF_TL4X_GREEN(a) (0x1290 | (a) << 16) |
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| 365 | #define NIX_AF_TL4X_YELLOW(a) (0x12A0 | (a) << 16) |
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| 366 | #define NIX_AF_TL4X_RED(a) (0x12B0 | (a) << 16) |
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| 367 | #define NIX_AF_TL4X_MD_DEBUG0(a) (0x12C0 | (a) << 16) |
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| 368 | #define NIX_AF_TL4X_MD_DEBUG1(a) (0x12C8 | (a) << 16) |
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| 369 | #define NIX_AF_TL4X_MD_DEBUG2(a) (0x12D0 | (a) << 16) |
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| 370 | #define NIX_AF_TL4X_MD_DEBUG3(a) (0x12D8 | (a) << 16) |
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| 371 | #define NIX_AF_TL4A_DEBUG (0x12e0) |
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| 372 | #define NIX_AF_TL4B_DEBUG (0x12f0) |
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| 373 | #define NIX_AF_MDQX_SCHEDULE(a) (0x1400 | (a) << 16) |
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| 374 | #define NIX_AF_MDQX_SHAPE(a) (0x1410 | (a) << 16) |
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| 375 | #define NIX_AF_MDQX_CIR(a) (0x1420 | (a) << 16) |
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| 376 | #define NIX_AF_MDQX_PIR(a) (0x1430 | (a) << 16) |
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| 377 | #define NIX_AF_MDQX_SCHED_STATE(a) (0x1440 | (a) << 16) |
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| 378 | #define NIX_AF_MDQX_SHAPE_STATE(a) (0x1450 | (a) << 16) |
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| 379 | #define NIX_AF_MDQX_POINTERS(a) (0x1460 | (a) << 16) |
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| 380 | #define NIX_AF_MDQX_SW_XOFF(a) (0x1470 | (a) << 16) |
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| 381 | #define NIX_AF_MDQX_PARENT(a) (0x1480 | (a) << 16) |
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| 382 | #define NIX_AF_MDQX_MD_DEBUG(a) (0x14C0 | (a) << 16) |
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| 383 | #define NIX_AF_MDQX_PTR_FIFO(a) (0x14D0 | (a) << 16) |
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| 384 | #define NIX_AF_MDQA_DEBUG (0x14e0) |
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| 385 | #define NIX_AF_MDQB_DEBUG (0x14f0) |
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| 386 | #define NIX_AF_TL3_TL2X_CFG(a) (0x1600 | (a) << 18) |
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| 387 | #define NIX_AF_TL3_TL2X_BP_STATUS(a) (0x1610 | (a) << 16) |
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| 388 | #define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (a) << 16 | (b) << 3) |
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| 389 | #define NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(a, b) (0x1800 | (a) << 18 | (b) << 3) |
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| 390 | #define NIX_AF_TX_MCASTX(a) (0x1900 | (a) << 15) |
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| 391 | #define NIX_AF_TX_VTAG_DEFX_CTL(a) (0x1A00 | (a) << 16) |
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| 392 | #define NIX_AF_TX_VTAG_DEFX_DATA(a) (0x1A10 | (a) << 16) |
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| 393 | #define NIX_AF_RX_BPIDX_STATUS(a) (0x1A20 | (a) << 17) |
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| 394 | #define NIX_AF_RX_CHANX_CFG(a) (0x1A30 | (a) << 15) |
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| 395 | #define NIX_AF_CINT_TIMERX(a) (0x1A40 | (a) << 18) |
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| 396 | #define NIX_AF_LSO_FORMATX_FIELDX(a, b) (0x1B00 | (a) << 16 | (b) << 3) |
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| 397 | #define NIX_AF_LFX_CFG(a) (0x4000 | (a) << 17) |
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| 398 | #define NIX_AF_LFX_SQS_CFG(a) (0x4020 | (a) << 17) |
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| 399 | #define NIX_AF_LFX_TX_CFG2(a) (0x4028 | (a) << 17) |
|---|
| 400 | #define NIX_AF_LFX_SQS_BASE(a) (0x4030 | (a) << 17) |
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| 401 | #define NIX_AF_LFX_RQS_CFG(a) (0x4040 | (a) << 17) |
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| 402 | #define NIX_AF_LFX_RQS_BASE(a) (0x4050 | (a) << 17) |
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| 403 | #define NIX_AF_LFX_CQS_CFG(a) (0x4060 | (a) << 17) |
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| 404 | #define NIX_AF_LFX_CQS_BASE(a) (0x4070 | (a) << 17) |
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| 405 | #define NIX_AF_LFX_TX_CFG(a) (0x4080 | (a) << 17) |
|---|
| 406 | #define NIX_AF_LFX_TX_PARSE_CFG(a) (0x4090 | (a) << 17) |
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| 407 | #define NIX_AF_LFX_RX_CFG(a) (0x40A0 | (a) << 17) |
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| 408 | #define (a) (0x40C0 | (a) << 17) |
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| 409 | #define (a) (0x40D0 | (a) << 17) |
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| 410 | #define NIX_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 17) |
|---|
| 411 | #define NIX_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 17) |
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| 412 | #define NIX_AF_LFX_CINTS_CFG(a) (0x4120 | (a) << 17) |
|---|
| 413 | #define NIX_AF_LFX_CINTS_BASE(a) (0x4130 | (a) << 17) |
|---|
| 414 | #define NIX_AF_LFX_RX_IPSEC_CFG0(a) (0x4140 | (a) << 17) |
|---|
| 415 | #define NIX_AF_LFX_RX_IPSEC_CFG1(a) (0x4148 | (a) << 17) |
|---|
| 416 | #define NIX_AF_LFX_RX_IPSEC_DYNO_CFG(a) (0x4150 | (a) << 17) |
|---|
| 417 | #define NIX_AF_LFX_RX_IPSEC_DYNO_BASE(a) (0x4158 | (a) << 17) |
|---|
| 418 | #define NIX_AF_LFX_RX_IPSEC_SA_BASE(a) (0x4170 | (a) << 17) |
|---|
| 419 | #define NIX_AF_LFX_TX_STATUS(a) (0x4180 | (a) << 17) |
|---|
| 420 | #define NIX_AF_LFX_RX_VTAG_TYPEX(a, b) (0x4200 | (a) << 17 | (b) << 3) |
|---|
| 421 | #define NIX_AF_LFX_LOCKX(a, b) (0x4300 | (a) << 17 | (b) << 3) |
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| 422 | #define NIX_AF_LFX_TX_STATX(a, b) (0x4400 | (a) << 17 | (b) << 3) |
|---|
| 423 | #define NIX_AF_LFX_RX_STATX(a, b) (0x4500 | (a) << 17 | (b) << 3) |
|---|
| 424 | #define (a, b) (0x4600 | (a) << 17 | (b) << 3) |
|---|
| 425 | #define NIX_AF_RX_NPC_MC_RCV (0x4700) |
|---|
| 426 | #define NIX_AF_RX_NPC_MC_DROP (0x4710) |
|---|
| 427 | #define NIX_AF_RX_NPC_MIRROR_RCV (0x4720) |
|---|
| 428 | #define NIX_AF_RX_NPC_MIRROR_DROP (0x4730) |
|---|
| 429 | #define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) (0x4800 | (a) << 16) |
|---|
| 430 | #define NIX_AF_LINKX_CFG(a) (0x4010 | (a) << 17) |
|---|
| 431 | #define NIX_AF_MDQX_IN_MD_COUNT(a) (0x14e0 | (a) << 16) |
|---|
| 432 | |
|---|
| 433 | #define NIX_PRIV_AF_INT_CFG (0x8000000) |
|---|
| 434 | #define NIX_PRIV_LFX_CFG (0x8000010) |
|---|
| 435 | #define NIX_PRIV_LFX_INT_CFG (0x8000020) |
|---|
| 436 | #define NIX_AF_RVU_LF_CFG_DEBUG (0x8000030) |
|---|
| 437 | |
|---|
| 438 | #define NIX_AF_LINKX_BASE_MASK GENMASK_ULL(11, 0) |
|---|
| 439 | #define NIX_AF_LINKX_RANGE_MASK GENMASK_ULL(19, 16) |
|---|
| 440 | #define NIX_AF_LINKX_MCS_CNT_MASK GENMASK_ULL(33, 32) |
|---|
| 441 | |
|---|
| 442 | #define NIX_CONST_MAX_BPIDS GENMASK_ULL(23, 12) |
|---|
| 443 | #define NIX_CONST_SDP_CHANS GENMASK_ULL(11, 0) |
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| 444 | |
|---|
| 445 | /* SSO */ |
|---|
| 446 | #define SSO_AF_CONST (0x1000) |
|---|
| 447 | #define SSO_AF_CONST1 (0x1008) |
|---|
| 448 | #define SSO_AF_BLK_RST (0x10f8) |
|---|
| 449 | #define SSO_AF_LF_HWGRP_RST (0x10e0) |
|---|
| 450 | #define SSO_AF_RVU_LF_CFG_DEBUG (0x3800) |
|---|
| 451 | #define SSO_PRIV_LFX_HWGRP_CFG (0x10000) |
|---|
| 452 | #define SSO_PRIV_LFX_HWGRP_INT_CFG (0x20000) |
|---|
| 453 | |
|---|
| 454 | /* SSOW */ |
|---|
| 455 | #define SSOW_AF_RVU_LF_HWS_CFG_DEBUG (0x0010) |
|---|
| 456 | #define SSOW_AF_LF_HWS_RST (0x0030) |
|---|
| 457 | #define SSOW_PRIV_LFX_HWS_CFG (0x1000) |
|---|
| 458 | #define SSOW_PRIV_LFX_HWS_INT_CFG (0x2000) |
|---|
| 459 | |
|---|
| 460 | /* TIM */ |
|---|
| 461 | #define TIM_AF_CONST (0x90) |
|---|
| 462 | #define TIM_PRIV_LFX_CFG (0x20000) |
|---|
| 463 | #define TIM_PRIV_LFX_INT_CFG (0x24000) |
|---|
| 464 | #define TIM_AF_RVU_LF_CFG_DEBUG (0x30000) |
|---|
| 465 | #define TIM_AF_BLK_RST (0x10) |
|---|
| 466 | #define TIM_AF_LF_RST (0x20) |
|---|
| 467 | |
|---|
| 468 | /* CPT */ |
|---|
| 469 | #define CPT_AF_CONSTANTS0 (0x0000) |
|---|
| 470 | #define CPT_AF_CONSTANTS1 (0x1000) |
|---|
| 471 | #define CPT_AF_DIAG (0x3000) |
|---|
| 472 | #define CPT_AF_ECO (0x4000) |
|---|
| 473 | #define CPT_AF_FLTX_INT(a) (0xa000ull | (u64)(a) << 3) |
|---|
| 474 | #define CPT_AF_FLTX_INT_W1S(a) (0xb000ull | (u64)(a) << 3) |
|---|
| 475 | #define CPT_AF_FLTX_INT_ENA_W1C(a) (0xc000ull | (u64)(a) << 3) |
|---|
| 476 | #define CPT_AF_FLTX_INT_ENA_W1S(a) (0xd000ull | (u64)(a) << 3) |
|---|
| 477 | #define CPT_AF_PSNX_EXE(a) (0xe000ull | (u64)(a) << 3) |
|---|
| 478 | #define CPT_AF_PSNX_EXE_W1S(a) (0xf000ull | (u64)(a) << 3) |
|---|
| 479 | #define CPT_AF_PSNX_LF(a) (0x10000ull | (u64)(a) << 3) |
|---|
| 480 | #define CPT_AF_PSNX_LF_W1S(a) (0x11000ull | (u64)(a) << 3) |
|---|
| 481 | #define CPT_AF_EXEX_CTL2(a) (0x12000ull | (u64)(a) << 3) |
|---|
| 482 | #define CPT_AF_EXEX_STS(a) (0x13000ull | (u64)(a) << 3) |
|---|
| 483 | #define CPT_AF_EXE_ERR_INFO (0x14000) |
|---|
| 484 | #define CPT_AF_EXEX_ACTIVE(a) (0x16000ull | (u64)(a) << 3) |
|---|
| 485 | #define CPT_AF_INST_REQ_PC (0x17000) |
|---|
| 486 | #define CPT_AF_INST_LATENCY_PC (0x18000) |
|---|
| 487 | #define CPT_AF_RD_REQ_PC (0x19000) |
|---|
| 488 | #define CPT_AF_RD_LATENCY_PC (0x1a000) |
|---|
| 489 | #define CPT_AF_RD_UC_PC (0x1b000) |
|---|
| 490 | #define CPT_AF_ACTIVE_CYCLES_PC (0x1c000) |
|---|
| 491 | #define CPT_AF_EXE_DBG_CTL (0x1d000) |
|---|
| 492 | #define CPT_AF_EXE_DBG_DATA (0x1e000) |
|---|
| 493 | #define CPT_AF_EXE_REQ_TIMER (0x1f000) |
|---|
| 494 | #define CPT_AF_EXEX_CTL(a) (0x20000ull | (u64)(a) << 3) |
|---|
| 495 | #define CPT_AF_EXE_PERF_CTL (0x21000) |
|---|
| 496 | #define CPT_AF_EXE_DBG_CNTX(a) (0x22000ull | (u64)(a) << 3) |
|---|
| 497 | #define CPT_AF_EXE_PERF_EVENT_CNT (0x23000) |
|---|
| 498 | #define CPT_AF_EXE_EPCI_INBX_CNT(a) (0x24000ull | (u64)(a) << 3) |
|---|
| 499 | #define CPT_AF_EXE_EPCI_OUTBX_CNT(a) (0x25000ull | (u64)(a) << 3) |
|---|
| 500 | #define CPT_AF_EXEX_UCODE_BASE(a) (0x26000ull | (u64)(a) << 3) |
|---|
| 501 | #define CPT_AF_LFX_CTL(a) (0x27000ull | (u64)(a) << 3) |
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| 502 | #define CPT_AF_LFX_CTL2(a) (0x29000ull | (u64)(a) << 3) |
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| 503 | #define CPT_AF_CPTCLK_CNT (0x2a000) |
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| 504 | #define CPT_AF_PF_FUNC (0x2b000) |
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| 505 | #define CPT_AF_LFX_PTR_CTL(a) (0x2c000ull | (u64)(a) << 3) |
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| 506 | #define CPT_AF_GRPX_THR(a) (0x2d000ull | (u64)(a) << 3) |
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| 507 | #define CPT_AF_CTL (0x2e000ull) |
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| 508 | #define CPT_AF_XEX_THR(a) (0x2f000ull | (u64)(a) << 3) |
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| 509 | #define CPT_PRIV_LFX_CFG (0x41000) |
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| 510 | #define CPT_PRIV_AF_INT_CFG (0x42000) |
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| 511 | #define CPT_PRIV_LFX_INT_CFG (0x43000) |
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| 512 | #define CPT_AF_LF_RST (0x44000) |
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| 513 | #define CPT_AF_RVU_LF_CFG_DEBUG (0x45000) |
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| 514 | #define CPT_AF_BLK_RST (0x46000) |
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| 515 | #define CPT_AF_RVU_INT (0x47000) |
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| 516 | #define CPT_AF_RVU_INT_W1S (0x47008) |
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| 517 | #define CPT_AF_RVU_INT_ENA_W1S (0x47010) |
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| 518 | #define CPT_AF_RVU_INT_ENA_W1C (0x47018) |
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| 519 | #define CPT_AF_RAS_INT (0x47020) |
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| 520 | #define CPT_AF_RAS_INT_W1S (0x47028) |
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| 521 | #define CPT_AF_RAS_INT_ENA_W1S (0x47030) |
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| 522 | #define CPT_AF_RAS_INT_ENA_W1C (0x47038) |
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| 523 | #define CPT_AF_CTX_FLUSH_TIMER (0x48000ull) |
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| 524 | #define CPT_AF_CTX_ERR (0x48008ull) |
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| 525 | #define CPT_AF_CTX_ENC_ID (0x48010ull) |
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| 526 | #define CPT_AF_CTX_MIS_PC (0x49400ull) |
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| 527 | #define CPT_AF_CTX_HIT_PC (0x49408ull) |
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| 528 | #define CPT_AF_CTX_AOP_PC (0x49410ull) |
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| 529 | #define CPT_AF_CTX_AOP_LATENCY_PC (0x49418ull) |
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| 530 | #define CPT_AF_CTX_IFETCH_PC (0x49420ull) |
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| 531 | #define CPT_AF_CTX_IFETCH_LATENCY_PC (0x49428ull) |
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| 532 | #define CPT_AF_CTX_FFETCH_PC (0x49430ull) |
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| 533 | #define CPT_AF_CTX_FFETCH_LATENCY_PC (0x49438ull) |
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| 534 | #define CPT_AF_CTX_WBACK_PC (0x49440ull) |
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| 535 | #define CPT_AF_CTX_WBACK_LATENCY_PC (0x49448ull) |
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| 536 | #define CPT_AF_CTX_PSH_PC (0x49450ull) |
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| 537 | #define CPT_AF_CTX_PSH_LATENCY_PC (0x49458ull) |
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| 538 | #define CPT_AF_CTX_CAM_DATA(a) (0x49800ull | (u64)(a) << 3) |
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| 539 | #define CPT_AF_RXC_TIME (0x50010ull) |
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| 540 | #define CPT_AF_RXC_TIME_CFG (0x50018ull) |
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| 541 | #define CPT_AF_RXC_DFRG (0x50020ull) |
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| 542 | #define CPT_AF_RXC_ACTIVE_STS (0x50028ull) |
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| 543 | #define CPT_AF_RXC_ZOMBIE_STS (0x50030ull) |
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| 544 | #define CPT_AF_X2PX_LINK_CFG(a) (0x51000ull | (u64)(a) << 3) |
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| 545 | |
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| 546 | #define AF_BAR2_ALIASX(a, b) (0x9100000ull | (a) << 12 | (b)) |
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| 547 | #define CPT_AF_BAR2_SEL 0x9000000 |
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| 548 | #define CPT_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b) |
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| 549 | |
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| 550 | #define CPT_AF_LF_CTL2_SHIFT 3 |
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| 551 | #define CPT_AF_LF_SSO_PF_FUNC_SHIFT 32 |
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| 552 | |
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| 553 | #define CPT_LF_CTL 0x10 |
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| 554 | #define CPT_LF_INPROG 0x40 |
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| 555 | #define CPT_LF_Q_SIZE 0x100 |
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| 556 | #define CPT_LF_Q_INST_PTR 0x110 |
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| 557 | #define CPT_LF_Q_GRP_PTR 0x120 |
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| 558 | #define CPT_LF_CTX_FLUSH 0x510 |
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| 559 | |
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| 560 | #define NPC_AF_BLK_RST (0x00040) |
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| 561 | |
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| 562 | /* NPC */ |
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| 563 | #define NPC_AF_CFG (0x00000) |
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| 564 | #define NPC_AF_ACTIVE_PC (0x00010) |
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| 565 | #define NPC_AF_CONST (0x00020) |
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| 566 | #define NPC_AF_CONST1 (0x00030) |
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| 567 | #define NPC_AF_BLK_RST (0x00040) |
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| 568 | #define NPC_AF_MCAM_SCRUB_CTL (0x000a0) |
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| 569 | #define NPC_AF_KCAM_SCRUB_CTL (0x000b0) |
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| 570 | #define NPC_AF_CONST2 (0x00100) |
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| 571 | #define NPC_AF_CONST3 (0x00110) |
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| 572 | #define NPC_AF_KPUX_CFG(a) (0x00500 | (a) << 3) |
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| 573 | #define NPC_AF_PCK_CFG (0x00600) |
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| 574 | #define NPC_AF_PCK_DEF_OL2 (0x00610) |
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| 575 | #define NPC_AF_PCK_DEF_OIP4 (0x00620) |
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| 576 | #define NPC_AF_PCK_DEF_OIP6 (0x00630) |
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| 577 | #define NPC_AF_PCK_DEF_IIP4 (0x00640) |
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| 578 | #define NPC_AF_INTFX_HASHX_RESULT_CTRL(a, b) (0x006c0 | (a) << 4 | (b) << 3) |
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| 579 | #define NPC_AF_INTFX_HASHX_MASKX(a, b, c) (0x00700 | (a) << 5 | (b) << 4 | (c) << 3) |
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| 580 | #define NPC_AF_KEX_LDATAX_FLAGS_CFG(a) (0x00800 | (a) << 3) |
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| 581 | #define NPC_AF_INTFX_HASHX_CFG(a, b) (0x00b00 | (a) << 6 | (b) << 4) |
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| 582 | #define NPC_AF_INTFX_SECRET_KEY0(a) (0x00e00 | (a) << 3) |
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| 583 | #define NPC_AF_INTFX_SECRET_KEY1(a) (0x00e20 | (a) << 3) |
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| 584 | #define NPC_AF_INTFX_SECRET_KEY2(a) (0x00e40 | (a) << 3) |
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| 585 | #define NPC_AF_INTFX_KEX_CFG(a) (0x01010 | (a) << 8) |
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| 586 | #define NPC_AF_PKINDX_ACTION0(a) (0x80000ull | (a) << 6) |
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| 587 | #define NPC_AF_PKINDX_ACTION1(a) (0x80008ull | (a) << 6) |
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| 588 | #define NPC_AF_PKINDX_CPI_DEFX(a, b) (0x80020ull | (a) << 6 | (b) << 3) |
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| 589 | #define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \ |
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| 590 | (0x100000 | (a) << 14 | (b) << 6 | (c) << 3) |
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| 591 | #define NPC_AF_KPUX_ENTRYX_ACTION0(a, b) \ |
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| 592 | (0x100020 | (a) << 14 | (b) << 6) |
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| 593 | #define NPC_AF_KPUX_ENTRYX_ACTION1(a, b) \ |
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| 594 | (0x100028 | (a) << 14 | (b) << 6) |
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| 595 | #define NPC_AF_KPUX_ENTRY_DISX(a, b) (0x180000 | (a) << 6 | (b) << 3) |
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| 596 | #define NPC_AF_CPIX_CFG(a) (0x200000 | (a) << 3) |
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| 597 | #define NPC_AF_INTFX_LIDX_LTX_LDX_CFG(a, b, c, d) \ |
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| 598 | (0x900000 | (a) << 16 | (b) << 12 | (c) << 5 | (d) << 3) |
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| 599 | #define NPC_AF_INTFX_LDATAX_FLAGSX_CFG(a, b, c) \ |
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| 600 | (0x980000 | (a) << 16 | (b) << 12 | (c) << 3) |
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| 601 | #define NPC_AF_INTFX_MISS_STAT_ACT(a) (0x1880040 + (a) * 0x8) |
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| 602 | #define NPC_AF_INTFX_MISS_ACT(a) (0x1a00000 | (a) << 4) |
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| 603 | #define NPC_AF_INTFX_MISS_TAG_ACT(a) (0x1b00008 | (a) << 4) |
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| 604 | #define NPC_AF_MCAM_BANKX_HITX(a, b) (0x1c80000 | (a) << 8 | (b) << 4) |
|---|
| 605 | #define NPC_AF_LKUP_CTL (0x2000000) |
|---|
| 606 | #define NPC_AF_LKUP_DATAX(a) (0x2000200 | (a) << 4) |
|---|
| 607 | #define NPC_AF_LKUP_RESULTX(a) (0x2000400 | (a) << 4) |
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| 608 | #define NPC_AF_INTFX_STAT(a) (0x2000800 | (a) << 4) |
|---|
| 609 | #define NPC_AF_DBG_CTL (0x3000000) |
|---|
| 610 | #define NPC_AF_DBG_STATUS (0x3000010) |
|---|
| 611 | #define NPC_AF_KPUX_DBG(a) (0x3000020 | (a) << 8) |
|---|
| 612 | #define NPC_AF_IKPU_ERR_CTL (0x3000080) |
|---|
| 613 | #define NPC_AF_KPUX_ERR_CTL(a) (0x30000a0 | (a) << 8) |
|---|
| 614 | #define NPC_AF_MCAM_DBG (0x3001000) |
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| 615 | #define NPC_AF_DBG_DATAX(a) (0x3001400 | (a) << 4) |
|---|
| 616 | #define NPC_AF_DBG_RESULTX(a) (0x3001800 | (a) << 4) |
|---|
| 617 | |
|---|
| 618 | #define NPC_AF_EXACT_MEM_ENTRY(a, b) (0x300000 | (a) << 15 | (b) << 3) |
|---|
| 619 | #define NPC_AF_EXACT_CAM_ENTRY(a) (0xC00 | (a) << 3) |
|---|
| 620 | #define NPC_AF_INTFX_EXACT_MASK(a) (0x660 | (a) << 3) |
|---|
| 621 | #define NPC_AF_INTFX_EXACT_RESULT_CTL(a)(0x680 | (a) << 3) |
|---|
| 622 | #define NPC_AF_INTFX_EXACT_CFG(a) (0xA00 | (a) << 3) |
|---|
| 623 | #define NPC_AF_INTFX_EXACT_SECRET0(a) (0xE00 | (a) << 3) |
|---|
| 624 | #define NPC_AF_INTFX_EXACT_SECRET1(a) (0xE20 | (a) << 3) |
|---|
| 625 | #define NPC_AF_INTFX_EXACT_SECRET2(a) (0xE40 | (a) << 3) |
|---|
| 626 | |
|---|
| 627 | #define NPC_AF_MCAMEX_BANKX_CAMX_INTF(a, b, c) ({ \ |
|---|
| 628 | u64 offset; \ |
|---|
| 629 | \ |
|---|
| 630 | offset = (0x1000000ull | (a) << 10 | (b) << 6 | (c) << 3); \ |
|---|
| 631 | if (rvu->hw->npc_ext_set) \ |
|---|
| 632 | offset = (0x8000000ull | (a) << 8 | (b) << 22 | (c) << 3); \ |
|---|
| 633 | offset; }) |
|---|
| 634 | |
|---|
| 635 | #define NPC_AF_MCAMEX_BANKX_CAMX_W0(a, b, c) ({ \ |
|---|
| 636 | u64 offset; \ |
|---|
| 637 | \ |
|---|
| 638 | offset = (0x1000010ull | (a) << 10 | (b) << 6 | (c) << 3); \ |
|---|
| 639 | if (rvu->hw->npc_ext_set) \ |
|---|
| 640 | offset = (0x8000010ull | (a) << 8 | (b) << 22 | (c) << 3); \ |
|---|
| 641 | offset; }) |
|---|
| 642 | |
|---|
| 643 | #define NPC_AF_MCAMEX_BANKX_CAMX_W1(a, b, c) ({ \ |
|---|
| 644 | u64 offset; \ |
|---|
| 645 | \ |
|---|
| 646 | offset = (0x1000020ull | (a) << 10 | (b) << 6 | (c) << 3); \ |
|---|
| 647 | if (rvu->hw->npc_ext_set) \ |
|---|
| 648 | offset = (0x8000020ull | (a) << 8 | (b) << 22 | (c) << 3); \ |
|---|
| 649 | offset; }) |
|---|
| 650 | |
|---|
| 651 | #define NPC_AF_MCAMEX_BANKX_CFG(a, b) ({ \ |
|---|
| 652 | u64 offset; \ |
|---|
| 653 | \ |
|---|
| 654 | offset = (0x1800000ull | (a) << 8 | (b) << 4); \ |
|---|
| 655 | if (rvu->hw->npc_ext_set) \ |
|---|
| 656 | offset = (0x8000038ull | (a) << 8 | (b) << 22); \ |
|---|
| 657 | offset; }) |
|---|
| 658 | |
|---|
| 659 | #define NPC_AF_MCAMEX_BANKX_ACTION(a, b) ({ \ |
|---|
| 660 | u64 offset; \ |
|---|
| 661 | \ |
|---|
| 662 | offset = (0x1900000ull | (a) << 8 | (b) << 4); \ |
|---|
| 663 | if (rvu->hw->npc_ext_set) \ |
|---|
| 664 | offset = (0x8000040ull | (a) << 8 | (b) << 22); \ |
|---|
| 665 | offset; }) \ |
|---|
| 666 | |
|---|
| 667 | #define NPC_AF_MCAMEX_BANKX_TAG_ACT(a, b) ({ \ |
|---|
| 668 | u64 offset; \ |
|---|
| 669 | \ |
|---|
| 670 | offset = (0x1900008ull | (a) << 8 | (b) << 4); \ |
|---|
| 671 | if (rvu->hw->npc_ext_set) \ |
|---|
| 672 | offset = (0x8000048ull | (a) << 8 | (b) << 22); \ |
|---|
| 673 | offset; }) \ |
|---|
| 674 | |
|---|
| 675 | #define NPC_AF_MCAMEX_BANKX_STAT_ACT(a, b) ({ \ |
|---|
| 676 | u64 offset; \ |
|---|
| 677 | \ |
|---|
| 678 | offset = (0x1880000ull | (a) << 8 | (b) << 4); \ |
|---|
| 679 | if (rvu->hw->npc_ext_set) \ |
|---|
| 680 | offset = (0x8000050ull | (a) << 8 | (b) << 22); \ |
|---|
| 681 | offset; }) \ |
|---|
| 682 | |
|---|
| 683 | #define NPC_AF_MATCH_STATX(a) ({ \ |
|---|
| 684 | u64 offset; \ |
|---|
| 685 | \ |
|---|
| 686 | offset = (0x1880008ull | (a) << 8); \ |
|---|
| 687 | if (rvu->hw->npc_ext_set) \ |
|---|
| 688 | offset = (0x8000078ull | (a) << 8); \ |
|---|
| 689 | offset; }) \ |
|---|
| 690 | |
|---|
| 691 | /* NDC */ |
|---|
| 692 | #define NDC_AF_CONST (0x00000) |
|---|
| 693 | #define NDC_AF_CLK_EN (0x00020) |
|---|
| 694 | #define NDC_AF_CTL (0x00030) |
|---|
| 695 | #define NDC_AF_BANK_CTL (0x00040) |
|---|
| 696 | #define NDC_AF_BANK_CTL_DONE (0x00048) |
|---|
| 697 | #define NDC_AF_INTR (0x00058) |
|---|
| 698 | #define NDC_AF_INTR_W1S (0x00060) |
|---|
| 699 | #define NDC_AF_INTR_ENA_W1S (0x00068) |
|---|
| 700 | #define NDC_AF_INTR_ENA_W1C (0x00070) |
|---|
| 701 | #define NDC_AF_ACTIVE_PC (0x00078) |
|---|
| 702 | #define NDC_AF_CAMS_RD_INTERVAL (0x00080) |
|---|
| 703 | #define NDC_AF_BP_TEST_ENABLE (0x001F8) |
|---|
| 704 | #define NDC_AF_BP_TEST(a) (0x00200 | (a) << 3) |
|---|
| 705 | #define NDC_AF_BLK_RST (0x002F0) |
|---|
| 706 | #define NDC_PRIV_AF_INT_CFG (0x002F8) |
|---|
| 707 | #define NDC_AF_HASHX(a) (0x00300 | (a) << 3) |
|---|
| 708 | #define NDC_AF_PORTX_RTX_RWX_REQ_PC(a, b, c) \ |
|---|
| 709 | (0x00C00 | (a) << 5 | (b) << 4 | (c) << 3) |
|---|
| 710 | #define NDC_AF_PORTX_RTX_RWX_OSTDN_PC(a, b, c) \ |
|---|
| 711 | (0x00D00 | (a) << 5 | (b) << 4 | (c) << 3) |
|---|
| 712 | #define NDC_AF_PORTX_RTX_RWX_LAT_PC(a, b, c) \ |
|---|
| 713 | (0x00E00 | (a) << 5 | (b) << 4 | (c) << 3) |
|---|
| 714 | #define NDC_AF_PORTX_RTX_CANT_ALLOC_PC(a, b) \ |
|---|
| 715 | (0x00F00 | (a) << 5 | (b) << 4) |
|---|
| 716 | #define NDC_AF_BANKX_HIT_PC(a) (0x01000 | (a) << 3) |
|---|
| 717 | #define NDC_AF_BANKX_MISS_PC(a) (0x01100 | (a) << 3) |
|---|
| 718 | #define NDC_AF_BANKX_LINEX_METADATA(a, b) \ |
|---|
| 719 | (0x10000 | (a) << 12 | (b) << 3) |
|---|
| 720 | |
|---|
| 721 | /* LBK */ |
|---|
| 722 | #define LBK_CONST (0x10ull) |
|---|
| 723 | #define LBK_LINK_CFG_P2X (0x400ull) |
|---|
| 724 | #define LBK_LINK_CFG_X2P (0x408ull) |
|---|
| 725 | #define LBK_CONST_CHANS GENMASK_ULL(47, 32) |
|---|
| 726 | #define LBK_CONST_DST GENMASK_ULL(31, 28) |
|---|
| 727 | #define LBK_CONST_SRC GENMASK_ULL(27, 24) |
|---|
| 728 | #define LBK_CONST_BUF_SIZE GENMASK_ULL(23, 0) |
|---|
| 729 | #define LBK_LINK_CFG_RANGE_MASK GENMASK_ULL(19, 16) |
|---|
| 730 | #define LBK_LINK_CFG_ID_MASK GENMASK_ULL(11, 6) |
|---|
| 731 | #define LBK_LINK_CFG_BASE_MASK GENMASK_ULL(5, 0) |
|---|
| 732 | |
|---|
| 733 | /* APR */ |
|---|
| 734 | #define APR_AF_LMT_CFG (0x000ull) |
|---|
| 735 | #define APR_AF_LMT_MAP_BASE (0x008ull) |
|---|
| 736 | #define APR_AF_LMT_CTL (0x010ull) |
|---|
| 737 | #define APR_LMT_MAP_ENT_DIS_SCH_CMP_SHIFT 23 |
|---|
| 738 | #define APR_LMT_MAP_ENT_SCH_ENA_SHIFT 22 |
|---|
| 739 | #define APR_LMT_MAP_ENT_DIS_LINE_PREF_SHIFT 21 |
|---|
| 740 | #define LMTST_THROTTLE_MASK GENMASK_ULL(38, 35) |
|---|
| 741 | #define LMTST_WR_PEND_MAX 15 |
|---|
| 742 | |
|---|
| 743 | #endif /* RVU_REG_H */ |
|---|
| 744 | |
|---|
