| 1 | /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ |
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| 2 | /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */ |
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| 3 | |
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| 4 | #ifndef __MLX5_ESW_QOS_H__ |
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| 5 | #define __MLX5_ESW_QOS_H__ |
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| 6 | |
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| 7 | #ifdef CONFIG_MLX5_ESWITCH |
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| 8 | |
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| 9 | int mlx5_esw_qos_set_vport_rate(struct mlx5_eswitch *esw, struct mlx5_vport *evport, |
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| 10 | u32 max_rate, u32 min_rate); |
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| 11 | void mlx5_esw_qos_vport_disable(struct mlx5_eswitch *esw, struct mlx5_vport *vport); |
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| 12 | |
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| 13 | int mlx5_esw_devlink_rate_leaf_tx_share_set(struct devlink_rate *rate_leaf, void *priv, |
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| 14 | u64 tx_share, struct netlink_ext_ack *extack); |
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| 15 | int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devlink_rate *rate_leaf, void *priv, |
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| 16 | u64 tx_max, struct netlink_ext_ack *extack); |
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| 17 | int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node, void *priv, |
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| 18 | u64 tx_share, struct netlink_ext_ack *extack); |
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| 19 | int mlx5_esw_devlink_rate_node_tx_max_set(struct devlink_rate *rate_node, void *priv, |
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| 20 | u64 tx_max, struct netlink_ext_ack *extack); |
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| 21 | int mlx5_esw_devlink_rate_node_new(struct devlink_rate *rate_node, void **priv, |
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| 22 | struct netlink_ext_ack *extack); |
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| 23 | int mlx5_esw_devlink_rate_node_del(struct devlink_rate *rate_node, void *priv, |
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| 24 | struct netlink_ext_ack *extack); |
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| 25 | int mlx5_esw_devlink_rate_parent_set(struct devlink_rate *devlink_rate, |
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| 26 | struct devlink_rate *parent, |
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| 27 | void *priv, void *parent_priv, |
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| 28 | struct netlink_ext_ack *extack); |
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| 29 | #endif |
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| 30 | |
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| 31 | #endif |
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| 32 | |
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