| 1 | /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ |
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| 2 | /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */ |
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| 3 | |
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| 4 | #ifndef MLX5_TIMEOUTS_H |
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| 5 | #define MLX5_TIMEOUTS_H |
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| 6 | |
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| 7 | enum mlx5_timeouts_types { |
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| 8 | /* pre init timeouts (not read from FW) */ |
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| 9 | MLX5_TO_FW_PRE_INIT_TIMEOUT_MS, |
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| 10 | MLX5_TO_FW_PRE_INIT_ON_RECOVERY_TIMEOUT_MS, |
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| 11 | MLX5_TO_FW_PRE_INIT_WARN_MESSAGE_INTERVAL_MS, |
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| 12 | MLX5_TO_FW_PRE_INIT_WAIT_MS, |
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| 13 | |
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| 14 | /* init segment timeouts */ |
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| 15 | MLX5_TO_FW_INIT_MS, |
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| 16 | MLX5_TO_CMD_MS, |
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| 17 | |
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| 18 | /* DTOR timeouts */ |
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| 19 | MLX5_TO_PCI_TOGGLE_MS, |
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| 20 | MLX5_TO_HEALTH_POLL_INTERVAL_MS, |
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| 21 | MLX5_TO_FULL_CRDUMP_MS, |
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| 22 | MLX5_TO_FW_RESET_MS, |
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| 23 | MLX5_TO_FLUSH_ON_ERROR_MS, |
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| 24 | MLX5_TO_PCI_SYNC_UPDATE_MS, |
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| 25 | MLX5_TO_TEARDOWN_MS, |
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| 26 | MLX5_TO_FSM_REACTIVATE_MS, |
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| 27 | MLX5_TO_RECLAIM_PAGES_MS, |
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| 28 | MLX5_TO_RECLAIM_VFS_PAGES_MS, |
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| 29 | MLX5_TO_RESET_UNLOAD_MS, |
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| 30 | |
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| 31 | MAX_TIMEOUT_TYPES |
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| 32 | }; |
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| 33 | |
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| 34 | struct mlx5_core_dev; |
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| 35 | int mlx5_tout_init(struct mlx5_core_dev *dev); |
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| 36 | void mlx5_tout_cleanup(struct mlx5_core_dev *dev); |
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| 37 | void mlx5_tout_query_iseg(struct mlx5_core_dev *dev); |
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| 38 | int mlx5_tout_query_dtor(struct mlx5_core_dev *dev); |
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| 39 | u64 _mlx5_tout_ms(struct mlx5_core_dev *dev, enum mlx5_timeouts_types type); |
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| 40 | |
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| 41 | #define mlx5_tout_ms(dev, type) _mlx5_tout_ms(dev, MLX5_TO_##type##_MS) |
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| 42 | |
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| 43 | # endif /* MLX5_TIMEOUTS_H */ |
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| 44 | |
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