1 | /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ |
2 | /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ |
3 | |
4 | #ifndef _MLXSW_CMD_H |
5 | #define _MLXSW_CMD_H |
6 | |
7 | #include "item.h" |
8 | |
9 | #define MLXSW_CMD_MBOX_SIZE 4096 |
10 | |
11 | static inline char *mlxsw_cmd_mbox_alloc(void) |
12 | { |
13 | return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL); |
14 | } |
15 | |
16 | static inline void mlxsw_cmd_mbox_free(char *mbox) |
17 | { |
18 | kfree(objp: mbox); |
19 | } |
20 | |
21 | static inline void mlxsw_cmd_mbox_zero(char *mbox) |
22 | { |
23 | memset(mbox, 0, MLXSW_CMD_MBOX_SIZE); |
24 | } |
25 | |
26 | struct mlxsw_core; |
27 | |
28 | int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, |
29 | u32 in_mod, bool out_mbox_direct, bool reset_ok, |
30 | char *in_mbox, size_t in_mbox_size, |
31 | char *out_mbox, size_t out_mbox_size); |
32 | |
33 | static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode, |
34 | u8 opcode_mod, u32 in_mod, char *in_mbox, |
35 | size_t in_mbox_size) |
36 | { |
37 | return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, out_mbox_direct: false, |
38 | reset_ok: false, in_mbox, in_mbox_size, NULL, out_mbox_size: 0); |
39 | } |
40 | |
41 | static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode, |
42 | u8 opcode_mod, u32 in_mod, |
43 | bool out_mbox_direct, |
44 | char *out_mbox, size_t out_mbox_size) |
45 | { |
46 | return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, |
47 | out_mbox_direct, reset_ok: false, NULL, in_mbox_size: 0, |
48 | out_mbox, out_mbox_size); |
49 | } |
50 | |
51 | static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode, |
52 | u8 opcode_mod, u32 in_mod) |
53 | { |
54 | return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, out_mbox_direct: false, |
55 | reset_ok: false, NULL, in_mbox_size: 0, NULL, out_mbox_size: 0); |
56 | } |
57 | |
58 | enum mlxsw_cmd_opcode { |
59 | MLXSW_CMD_OPCODE_QUERY_FW = 0x004, |
60 | MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006, |
61 | MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003, |
62 | MLXSW_CMD_OPCODE_MAP_FA = 0xFFF, |
63 | MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE, |
64 | MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100, |
65 | MLXSW_CMD_OPCODE_ACCESS_REG = 0x040, |
66 | MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201, |
67 | MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202, |
68 | MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E, |
69 | MLXSW_CMD_OPCODE_QUERY_DQ = 0x022, |
70 | MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016, |
71 | MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017, |
72 | MLXSW_CMD_OPCODE_QUERY_CQ = 0x018, |
73 | MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013, |
74 | MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014, |
75 | MLXSW_CMD_OPCODE_QUERY_EQ = 0x015, |
76 | MLXSW_CMD_OPCODE_QUERY_RESOURCES = 0x101, |
77 | }; |
78 | |
79 | static inline const char *mlxsw_cmd_opcode_str(u16 opcode) |
80 | { |
81 | switch (opcode) { |
82 | case MLXSW_CMD_OPCODE_QUERY_FW: |
83 | return "QUERY_FW" ; |
84 | case MLXSW_CMD_OPCODE_QUERY_BOARDINFO: |
85 | return "QUERY_BOARDINFO" ; |
86 | case MLXSW_CMD_OPCODE_QUERY_AQ_CAP: |
87 | return "QUERY_AQ_CAP" ; |
88 | case MLXSW_CMD_OPCODE_MAP_FA: |
89 | return "MAP_FA" ; |
90 | case MLXSW_CMD_OPCODE_UNMAP_FA: |
91 | return "UNMAP_FA" ; |
92 | case MLXSW_CMD_OPCODE_CONFIG_PROFILE: |
93 | return "CONFIG_PROFILE" ; |
94 | case MLXSW_CMD_OPCODE_ACCESS_REG: |
95 | return "ACCESS_REG" ; |
96 | case MLXSW_CMD_OPCODE_SW2HW_DQ: |
97 | return "SW2HW_DQ" ; |
98 | case MLXSW_CMD_OPCODE_HW2SW_DQ: |
99 | return "HW2SW_DQ" ; |
100 | case MLXSW_CMD_OPCODE_2ERR_DQ: |
101 | return "2ERR_DQ" ; |
102 | case MLXSW_CMD_OPCODE_QUERY_DQ: |
103 | return "QUERY_DQ" ; |
104 | case MLXSW_CMD_OPCODE_SW2HW_CQ: |
105 | return "SW2HW_CQ" ; |
106 | case MLXSW_CMD_OPCODE_HW2SW_CQ: |
107 | return "HW2SW_CQ" ; |
108 | case MLXSW_CMD_OPCODE_QUERY_CQ: |
109 | return "QUERY_CQ" ; |
110 | case MLXSW_CMD_OPCODE_SW2HW_EQ: |
111 | return "SW2HW_EQ" ; |
112 | case MLXSW_CMD_OPCODE_HW2SW_EQ: |
113 | return "HW2SW_EQ" ; |
114 | case MLXSW_CMD_OPCODE_QUERY_EQ: |
115 | return "QUERY_EQ" ; |
116 | case MLXSW_CMD_OPCODE_QUERY_RESOURCES: |
117 | return "QUERY_RESOURCES" ; |
118 | default: |
119 | return "*UNKNOWN*" ; |
120 | } |
121 | } |
122 | |
123 | enum mlxsw_cmd_status { |
124 | /* Command execution succeeded. */ |
125 | MLXSW_CMD_STATUS_OK = 0x00, |
126 | /* Internal error (e.g. bus error) occurred while processing command. */ |
127 | MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01, |
128 | /* Operation/command not supported or opcode modifier not supported. */ |
129 | MLXSW_CMD_STATUS_BAD_OP = 0x02, |
130 | /* Parameter not supported, parameter out of range. */ |
131 | MLXSW_CMD_STATUS_BAD_PARAM = 0x03, |
132 | /* System was not enabled or bad system state. */ |
133 | MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04, |
134 | /* Attempt to access reserved or unallocated resource, or resource in |
135 | * inappropriate ownership. |
136 | */ |
137 | MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05, |
138 | /* Requested resource is currently executing a command. */ |
139 | MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06, |
140 | /* Required capability exceeds device limits. */ |
141 | MLXSW_CMD_STATUS_EXCEED_LIM = 0x08, |
142 | /* Resource is not in the appropriate state or ownership. */ |
143 | MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09, |
144 | /* Index out of range (might be beyond table size or attempt to |
145 | * access a reserved resource). |
146 | */ |
147 | MLXSW_CMD_STATUS_BAD_INDEX = 0x0A, |
148 | /* NVMEM checksum/CRC failed. */ |
149 | MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B, |
150 | /* Device is currently running reset */ |
151 | MLXSW_CMD_STATUS_RUNNING_RESET = 0x26, |
152 | /* Bad management packet (silently discarded). */ |
153 | MLXSW_CMD_STATUS_BAD_PKT = 0x30, |
154 | }; |
155 | |
156 | static inline const char *mlxsw_cmd_status_str(u8 status) |
157 | { |
158 | switch (status) { |
159 | case MLXSW_CMD_STATUS_OK: |
160 | return "OK" ; |
161 | case MLXSW_CMD_STATUS_INTERNAL_ERR: |
162 | return "INTERNAL_ERR" ; |
163 | case MLXSW_CMD_STATUS_BAD_OP: |
164 | return "BAD_OP" ; |
165 | case MLXSW_CMD_STATUS_BAD_PARAM: |
166 | return "BAD_PARAM" ; |
167 | case MLXSW_CMD_STATUS_BAD_SYS_STATE: |
168 | return "BAD_SYS_STATE" ; |
169 | case MLXSW_CMD_STATUS_BAD_RESOURCE: |
170 | return "BAD_RESOURCE" ; |
171 | case MLXSW_CMD_STATUS_RESOURCE_BUSY: |
172 | return "RESOURCE_BUSY" ; |
173 | case MLXSW_CMD_STATUS_EXCEED_LIM: |
174 | return "EXCEED_LIM" ; |
175 | case MLXSW_CMD_STATUS_BAD_RES_STATE: |
176 | return "BAD_RES_STATE" ; |
177 | case MLXSW_CMD_STATUS_BAD_INDEX: |
178 | return "BAD_INDEX" ; |
179 | case MLXSW_CMD_STATUS_BAD_NVMEM: |
180 | return "BAD_NVMEM" ; |
181 | case MLXSW_CMD_STATUS_RUNNING_RESET: |
182 | return "RUNNING_RESET" ; |
183 | case MLXSW_CMD_STATUS_BAD_PKT: |
184 | return "BAD_PKT" ; |
185 | default: |
186 | return "*UNKNOWN*" ; |
187 | } |
188 | } |
189 | |
190 | /* QUERY_FW - Query Firmware |
191 | * ------------------------- |
192 | * OpMod == 0, INMmod == 0 |
193 | * ----------------------- |
194 | * The QUERY_FW command retrieves information related to firmware, command |
195 | * interface version and the amount of resources that should be allocated to |
196 | * the firmware. |
197 | */ |
198 | |
199 | static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core, |
200 | char *out_mbox) |
201 | { |
202 | return mlxsw_cmd_exec_out(mlxsw_core, opcode: MLXSW_CMD_OPCODE_QUERY_FW, |
203 | opcode_mod: 0, in_mod: 0, out_mbox_direct: false, out_mbox, MLXSW_CMD_MBOX_SIZE); |
204 | } |
205 | |
206 | /* cmd_mbox_query_fw_fw_pages |
207 | * Amount of physical memory to be allocatedfor firmware usage in 4KB pages. |
208 | */ |
209 | MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16); |
210 | |
211 | /* cmd_mbox_query_fw_fw_rev_major |
212 | * Firmware Revision - Major |
213 | */ |
214 | MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16); |
215 | |
216 | /* cmd_mbox_query_fw_fw_rev_subminor |
217 | * Firmware Sub-minor version (Patch level) |
218 | */ |
219 | MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16); |
220 | |
221 | /* cmd_mbox_query_fw_fw_rev_minor |
222 | * Firmware Revision - Minor |
223 | */ |
224 | MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16); |
225 | |
226 | /* cmd_mbox_query_fw_core_clk |
227 | * Internal Clock Frequency (in MHz) |
228 | */ |
229 | MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16); |
230 | |
231 | /* cmd_mbox_query_fw_cmd_interface_rev |
232 | * Command Interface Interpreter Revision ID. This number is bumped up |
233 | * every time a non-backward-compatible change is done for the command |
234 | * interface. The current cmd_interface_rev is 1. |
235 | */ |
236 | MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16); |
237 | |
238 | /* cmd_mbox_query_fw_dt |
239 | * If set, Debug Trace is supported |
240 | */ |
241 | MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1); |
242 | |
243 | /* cmd_mbox_query_fw_api_version |
244 | * Indicates the version of the API, to enable software querying |
245 | * for compatibility. The current api_version is 1. |
246 | */ |
247 | MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16); |
248 | |
249 | /* cmd_mbox_query_fw_fw_hour |
250 | * Firmware timestamp - hour |
251 | */ |
252 | MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8); |
253 | |
254 | /* cmd_mbox_query_fw_fw_minutes |
255 | * Firmware timestamp - minutes |
256 | */ |
257 | MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8); |
258 | |
259 | /* cmd_mbox_query_fw_fw_seconds |
260 | * Firmware timestamp - seconds |
261 | */ |
262 | MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8); |
263 | |
264 | /* cmd_mbox_query_fw_fw_year |
265 | * Firmware timestamp - year |
266 | */ |
267 | MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16); |
268 | |
269 | /* cmd_mbox_query_fw_fw_month |
270 | * Firmware timestamp - month |
271 | */ |
272 | MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8); |
273 | |
274 | /* cmd_mbox_query_fw_fw_day |
275 | * Firmware timestamp - day |
276 | */ |
277 | MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8); |
278 | |
279 | /* cmd_mbox_query_fw_lag_mode_support |
280 | * 0: CONFIG_PROFILE.lag_mode is not supported by FW |
281 | * 1: CONFIG_PROFILE.lag_mode is supported by FW |
282 | */ |
283 | MLXSW_ITEM32(cmd_mbox, query_fw, lag_mode_support, 0x18, 1, 1); |
284 | |
285 | /* cmd_mbox_query_fw_clr_int_base_offset |
286 | * Clear Interrupt register's offset from clr_int_bar register |
287 | * in PCI address space. |
288 | */ |
289 | MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64); |
290 | |
291 | /* cmd_mbox_query_fw_clr_int_bar |
292 | * PCI base address register (BAR) where clr_int register is located. |
293 | * 00 - BAR 0-1 (64 bit BAR) |
294 | */ |
295 | MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2); |
296 | |
297 | /* cmd_mbox_query_fw_error_buf_offset |
298 | * Read Only buffer for internal error reports of offset |
299 | * from error_buf_bar register in PCI address space). |
300 | */ |
301 | MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64); |
302 | |
303 | /* cmd_mbox_query_fw_error_buf_size |
304 | * Internal error buffer size in DWORDs |
305 | */ |
306 | MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32); |
307 | |
308 | /* cmd_mbox_query_fw_error_int_bar |
309 | * PCI base address register (BAR) where error buffer |
310 | * register is located. |
311 | * 00 - BAR 0-1 (64 bit BAR) |
312 | */ |
313 | MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2); |
314 | |
315 | /* cmd_mbox_query_fw_doorbell_page_offset |
316 | * Offset of the doorbell page |
317 | */ |
318 | MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64); |
319 | |
320 | /* cmd_mbox_query_fw_doorbell_page_bar |
321 | * PCI base address register (BAR) of the doorbell page |
322 | * 00 - BAR 0-1 (64 bit BAR) |
323 | */ |
324 | MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2); |
325 | |
326 | /* cmd_mbox_query_fw_free_running_clock_offset |
327 | * The offset of the free running clock page |
328 | */ |
329 | MLXSW_ITEM64(cmd_mbox, query_fw, free_running_clock_offset, 0x50, 0, 64); |
330 | |
331 | /* cmd_mbox_query_fw_fr_rn_clk_bar |
332 | * PCI base address register (BAR) of the free running clock page |
333 | * 0: BAR 0 |
334 | * 1: 64 bit BAR |
335 | */ |
336 | MLXSW_ITEM32(cmd_mbox, query_fw, fr_rn_clk_bar, 0x58, 30, 2); |
337 | |
338 | /* cmd_mbox_query_fw_utc_sec_offset |
339 | * The offset of the UTC_Sec page |
340 | */ |
341 | MLXSW_ITEM64(cmd_mbox, query_fw, utc_sec_offset, 0x70, 0, 64); |
342 | |
343 | /* cmd_mbox_query_fw_utc_sec_bar |
344 | * PCI base address register (BAR) of the UTC_Sec page |
345 | * 0: BAR 0 |
346 | * 1: 64 bit BAR |
347 | * Reserved on SwitchX/-2, Switch-IB/2, Spectrum-1 |
348 | */ |
349 | MLXSW_ITEM32(cmd_mbox, query_fw, utc_sec_bar, 0x78, 30, 2); |
350 | |
351 | /* cmd_mbox_query_fw_utc_nsec_offset |
352 | * The offset of the UTC_nSec page |
353 | */ |
354 | MLXSW_ITEM64(cmd_mbox, query_fw, utc_nsec_offset, 0x80, 0, 64); |
355 | |
356 | /* cmd_mbox_query_fw_utc_nsec_bar |
357 | * PCI base address register (BAR) of the UTC_nSec page |
358 | * 0: BAR 0 |
359 | * 1: 64 bit BAR |
360 | * Reserved on SwitchX/-2, Switch-IB/2, Spectrum-1 |
361 | */ |
362 | MLXSW_ITEM32(cmd_mbox, query_fw, utc_nsec_bar, 0x88, 30, 2); |
363 | |
364 | /* QUERY_BOARDINFO - Query Board Information |
365 | * ----------------------------------------- |
366 | * OpMod == 0 (N/A), INMmod == 0 (N/A) |
367 | * ----------------------------------- |
368 | * The QUERY_BOARDINFO command retrieves adapter specific parameters. |
369 | */ |
370 | |
371 | static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core, |
372 | char *out_mbox) |
373 | { |
374 | return mlxsw_cmd_exec_out(mlxsw_core, opcode: MLXSW_CMD_OPCODE_QUERY_BOARDINFO, |
375 | opcode_mod: 0, in_mod: 0, out_mbox_direct: false, out_mbox, MLXSW_CMD_MBOX_SIZE); |
376 | } |
377 | |
378 | /* cmd_mbox_boardinfo_intapin |
379 | * When PCIe interrupt messages are being used, this value is used for clearing |
380 | * an interrupt. When using MSI-X, this register is not used. |
381 | */ |
382 | MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8); |
383 | |
384 | /* cmd_mbox_boardinfo_vsd_vendor_id |
385 | * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor |
386 | * specifying/formatting the VSD. The vsd_vendor_id identifies the management |
387 | * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID |
388 | * format and encoding as long as they use their assigned vsd_vendor_id. |
389 | */ |
390 | MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16); |
391 | |
392 | /* cmd_mbox_boardinfo_vsd |
393 | * Vendor Specific Data. The VSD string that is burnt to the Flash |
394 | * with the firmware. |
395 | */ |
396 | #define MLXSW_CMD_BOARDINFO_VSD_LEN 208 |
397 | MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN); |
398 | |
399 | /* cmd_mbox_boardinfo_psid |
400 | * The PSID field is a 16-ascii (byte) character string which acts as |
401 | * the board ID. The PSID format is used in conjunction with |
402 | * Mellanox vsd_vendor_id (15B3h). |
403 | */ |
404 | #define MLXSW_CMD_BOARDINFO_PSID_LEN 16 |
405 | MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN); |
406 | |
407 | /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities |
408 | * ----------------------------------------------------- |
409 | * OpMod == 0 (N/A), INMmod == 0 (N/A) |
410 | * ----------------------------------- |
411 | * The QUERY_AQ_CAP command returns the device asynchronous queues |
412 | * capabilities supported. |
413 | */ |
414 | |
415 | static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core, |
416 | char *out_mbox) |
417 | { |
418 | return mlxsw_cmd_exec_out(mlxsw_core, opcode: MLXSW_CMD_OPCODE_QUERY_AQ_CAP, |
419 | opcode_mod: 0, in_mod: 0, out_mbox_direct: false, out_mbox, MLXSW_CMD_MBOX_SIZE); |
420 | } |
421 | |
422 | /* cmd_mbox_query_aq_cap_log_max_sdq_sz |
423 | * Log (base 2) of max WQEs allowed on SDQ. |
424 | */ |
425 | MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8); |
426 | |
427 | /* cmd_mbox_query_aq_cap_max_num_sdqs |
428 | * Maximum number of SDQs. |
429 | */ |
430 | MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8); |
431 | |
432 | /* cmd_mbox_query_aq_cap_log_max_rdq_sz |
433 | * Log (base 2) of max WQEs allowed on RDQ. |
434 | */ |
435 | MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8); |
436 | |
437 | /* cmd_mbox_query_aq_cap_max_num_rdqs |
438 | * Maximum number of RDQs. |
439 | */ |
440 | MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8); |
441 | |
442 | /* cmd_mbox_query_aq_cap_log_max_cq_sz |
443 | * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv0 and CQEv1. |
444 | */ |
445 | MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8); |
446 | |
447 | /* cmd_mbox_query_aq_cap_log_max_cqv2_sz |
448 | * Log (base 2) of the Maximum CQEs allowed in a CQ for CQEv2. |
449 | */ |
450 | MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cqv2_sz, 0x08, 16, 8); |
451 | |
452 | /* cmd_mbox_query_aq_cap_max_num_cqs |
453 | * Maximum number of CQs. |
454 | */ |
455 | MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8); |
456 | |
457 | /* cmd_mbox_query_aq_cap_log_max_eq_sz |
458 | * Log (base 2) of max EQEs allowed on EQ. |
459 | */ |
460 | MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8); |
461 | |
462 | /* cmd_mbox_query_aq_cap_max_num_eqs |
463 | * Maximum number of EQs. |
464 | */ |
465 | MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8); |
466 | |
467 | /* cmd_mbox_query_aq_cap_max_sg_sq |
468 | * The maximum S/G list elements in an DSQ. DSQ must not contain |
469 | * more S/G entries than indicated here. |
470 | */ |
471 | MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8); |
472 | |
473 | /* cmd_mbox_query_aq_cap_ |
474 | * The maximum S/G list elements in an DRQ. DRQ must not contain |
475 | * more S/G entries than indicated here. |
476 | */ |
477 | MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8); |
478 | |
479 | /* MAP_FA - Map Firmware Area |
480 | * -------------------------- |
481 | * OpMod == 0 (N/A), INMmod == Number of VPM entries |
482 | * ------------------------------------------------- |
483 | * The MAP_FA command passes physical pages to the switch. These pages |
484 | * are used to store the device firmware. MAP_FA can be executed multiple |
485 | * times until all the firmware area is mapped (the size that should be |
486 | * mapped is retrieved through the QUERY_FW command). All required pages |
487 | * must be mapped to finish the initialization phase. Physical memory |
488 | * passed in this command must be pinned. |
489 | */ |
490 | |
491 | #define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32 |
492 | |
493 | static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core, |
494 | char *in_mbox, u32 vpm_entries_count) |
495 | { |
496 | return mlxsw_cmd_exec_in(mlxsw_core, opcode: MLXSW_CMD_OPCODE_MAP_FA, |
497 | opcode_mod: 0, in_mod: vpm_entries_count, |
498 | in_mbox, MLXSW_CMD_MBOX_SIZE); |
499 | } |
500 | |
501 | /* cmd_mbox_map_fa_pa |
502 | * Physical Address. |
503 | */ |
504 | MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true); |
505 | |
506 | /* cmd_mbox_map_fa_log2size |
507 | * Log (base 2) of the size in 4KB pages of the physical and contiguous memory |
508 | * that starts at PA_L/H. |
509 | */ |
510 | MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false); |
511 | |
512 | /* UNMAP_FA - Unmap Firmware Area |
513 | * ------------------------------ |
514 | * OpMod == 0 (N/A), INMmod == 0 (N/A) |
515 | * ----------------------------------- |
516 | * The UNMAP_FA command unload the firmware and unmaps all the |
517 | * firmware area. After this command is completed the device will not access |
518 | * the pages that were mapped to the firmware area. After executing UNMAP_FA |
519 | * command, software reset must be done prior to execution of MAP_FW command. |
520 | */ |
521 | |
522 | static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core) |
523 | { |
524 | return mlxsw_cmd_exec_none(mlxsw_core, opcode: MLXSW_CMD_OPCODE_UNMAP_FA, opcode_mod: 0, in_mod: 0); |
525 | } |
526 | |
527 | /* QUERY_RESOURCES - Query chip resources |
528 | * -------------------------------------- |
529 | * OpMod == 0 (N/A) , INMmod is index |
530 | * ---------------------------------- |
531 | * The QUERY_RESOURCES command retrieves information related to chip resources |
532 | * by resource ID. Every command returns 32 entries. INmod is being use as base. |
533 | * for example, index 1 will return entries 32-63. When the tables end and there |
534 | * are no more sources in the table, will return resource id 0xFFF to indicate |
535 | * it. |
536 | */ |
537 | |
538 | #define MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID 0xffff |
539 | #define MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES 100 |
540 | #define MLXSW_CMD_QUERY_RESOURCES_PER_QUERY 32 |
541 | |
542 | static inline int mlxsw_cmd_query_resources(struct mlxsw_core *mlxsw_core, |
543 | char *out_mbox, int index) |
544 | { |
545 | return mlxsw_cmd_exec_out(mlxsw_core, opcode: MLXSW_CMD_OPCODE_QUERY_RESOURCES, |
546 | opcode_mod: 0, in_mod: index, out_mbox_direct: false, out_mbox, |
547 | MLXSW_CMD_MBOX_SIZE); |
548 | } |
549 | |
550 | /* cmd_mbox_query_resource_id |
551 | * The resource id. 0xFFFF indicates table's end. |
552 | */ |
553 | MLXSW_ITEM32_INDEXED(cmd_mbox, query_resource, id, 0x00, 16, 16, 0x8, 0, false); |
554 | |
555 | /* cmd_mbox_query_resource_data |
556 | * The resource |
557 | */ |
558 | MLXSW_ITEM64_INDEXED(cmd_mbox, query_resource, data, |
559 | 0x00, 0, 40, 0x8, 0, false); |
560 | |
561 | /* CONFIG_PROFILE (Set) - Configure Switch Profile |
562 | * ------------------------------ |
563 | * OpMod == 1 (Set), INMmod == 0 (N/A) |
564 | * ----------------------------------- |
565 | * The CONFIG_PROFILE command sets the switch profile. The command can be |
566 | * executed on the device only once at startup in order to allocate and |
567 | * configure all switch resources and prepare it for operational mode. |
568 | * It is not possible to change the device profile after the chip is |
569 | * in operational mode. |
570 | * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate |
571 | * state therefore it is required to perform software reset to the device |
572 | * following an unsuccessful completion of the command. It is required |
573 | * to perform software reset to the device to change an existing profile. |
574 | */ |
575 | |
576 | static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core, |
577 | char *in_mbox) |
578 | { |
579 | return mlxsw_cmd_exec_in(mlxsw_core, opcode: MLXSW_CMD_OPCODE_CONFIG_PROFILE, |
580 | opcode_mod: 1, in_mod: 0, in_mbox, MLXSW_CMD_MBOX_SIZE); |
581 | } |
582 | |
583 | /* cmd_mbox_config_profile_set_max_vepa_channels |
584 | * Capability bit. Setting a bit to 1 configures the profile |
585 | * according to the mailbox contents. |
586 | */ |
587 | MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1); |
588 | |
589 | /* cmd_mbox_config_profile_set_max_lag |
590 | * Capability bit. Setting a bit to 1 configures the profile |
591 | * according to the mailbox contents. |
592 | */ |
593 | MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1); |
594 | |
595 | /* cmd_mbox_config_profile_set_max_port_per_lag |
596 | * Capability bit. Setting a bit to 1 configures the profile |
597 | * according to the mailbox contents. |
598 | */ |
599 | MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1); |
600 | |
601 | /* cmd_mbox_config_profile_set_max_mid |
602 | * Capability bit. Setting a bit to 1 configures the profile |
603 | * according to the mailbox contents. |
604 | */ |
605 | MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1); |
606 | |
607 | /* cmd_mbox_config_profile_set_max_pgt |
608 | * Capability bit. Setting a bit to 1 configures the profile |
609 | * according to the mailbox contents. |
610 | */ |
611 | MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1); |
612 | |
613 | /* cmd_mbox_config_profile_set_max_system_port |
614 | * Capability bit. Setting a bit to 1 configures the profile |
615 | * according to the mailbox contents. |
616 | */ |
617 | MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1); |
618 | |
619 | /* cmd_mbox_config_profile_set_max_vlan_groups |
620 | * Capability bit. Setting a bit to 1 configures the profile |
621 | * according to the mailbox contents. |
622 | */ |
623 | MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1); |
624 | |
625 | /* cmd_mbox_config_profile_set_max_regions |
626 | * Capability bit. Setting a bit to 1 configures the profile |
627 | * according to the mailbox contents. |
628 | */ |
629 | MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1); |
630 | |
631 | /* cmd_mbox_config_profile_set_flood_mode |
632 | * Capability bit. Setting a bit to 1 configures the profile |
633 | * according to the mailbox contents. |
634 | */ |
635 | MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1); |
636 | |
637 | /* cmd_mbox_config_profile_set_max_flood_tables |
638 | * Capability bit. Setting a bit to 1 configures the profile |
639 | * according to the mailbox contents. |
640 | */ |
641 | MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1); |
642 | |
643 | /* cmd_mbox_config_profile_set_max_ib_mc |
644 | * Capability bit. Setting a bit to 1 configures the profile |
645 | * according to the mailbox contents. |
646 | */ |
647 | MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1); |
648 | |
649 | /* cmd_mbox_config_profile_set_max_pkey |
650 | * Capability bit. Setting a bit to 1 configures the profile |
651 | * according to the mailbox contents. |
652 | */ |
653 | MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1); |
654 | |
655 | /* cmd_mbox_config_profile_set_adaptive_routing_group_cap |
656 | * Capability bit. Setting a bit to 1 configures the profile |
657 | * according to the mailbox contents. |
658 | */ |
659 | MLXSW_ITEM32(cmd_mbox, config_profile, |
660 | set_adaptive_routing_group_cap, 0x0C, 14, 1); |
661 | |
662 | /* cmd_mbox_config_profile_set_ar_sec |
663 | * Capability bit. Setting a bit to 1 configures the profile |
664 | * according to the mailbox contents. |
665 | */ |
666 | MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1); |
667 | |
668 | /* cmd_mbox_config_profile_set_ubridge |
669 | * Capability bit. Setting a bit to 1 configures the profile |
670 | * according to the mailbox contents. |
671 | */ |
672 | MLXSW_ITEM32(cmd_mbox, config_profile, set_ubridge, 0x0C, 22, 1); |
673 | |
674 | /* cmd_mbox_config_profile_set_kvd_linear_size |
675 | * Capability bit. Setting a bit to 1 configures the profile |
676 | * according to the mailbox contents. |
677 | */ |
678 | MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_linear_size, 0x0C, 24, 1); |
679 | |
680 | /* cmd_mbox_config_profile_set_kvd_hash_single_size |
681 | * Capability bit. Setting a bit to 1 configures the profile |
682 | * according to the mailbox contents. |
683 | */ |
684 | MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1); |
685 | |
686 | /* cmd_mbox_config_profile_set_kvd_hash_double_size |
687 | * Capability bit. Setting a bit to 1 configures the profile |
688 | * according to the mailbox contents. |
689 | */ |
690 | MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1); |
691 | |
692 | /* cmd_mbox_config_profile_set_cqe_version |
693 | * Capability bit. Setting a bit to 1 configures the profile |
694 | * according to the mailbox contents. |
695 | */ |
696 | MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1); |
697 | |
698 | /* cmd_mbox_config_profile_set_cqe_time_stamp_type |
699 | * Capability bit. Setting a bit to 1 configures the profile |
700 | * according to the mailbox contents. |
701 | */ |
702 | MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_time_stamp_type, 0x08, 2, 1); |
703 | |
704 | /* cmd_mbox_config_profile_set_lag_mode |
705 | * Capability bit. Setting a bit to 1 configures the lag_mode |
706 | * according to the mailbox contents. |
707 | */ |
708 | MLXSW_ITEM32(cmd_mbox, config_profile, set_lag_mode, 0x08, 7, 1); |
709 | |
710 | /* cmd_mbox_config_profile_max_vepa_channels |
711 | * Maximum number of VEPA channels per port (0 through 16) |
712 | * 0 - multi-channel VEPA is disabled |
713 | */ |
714 | MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8); |
715 | |
716 | /* cmd_mbox_config_profile_max_lag |
717 | * Maximum number of LAG IDs requested. |
718 | * Reserved when Spectrum-1/2/3, supported from Spectrum-4 and above. |
719 | * For Spectrum-4, firmware sets 128 for values between 1-128 and 256 for values |
720 | * between 129-256. |
721 | */ |
722 | MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16); |
723 | |
724 | /* cmd_mbox_config_profile_max_port_per_lag |
725 | * Maximum number of ports per LAG requested. |
726 | */ |
727 | MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16); |
728 | |
729 | /* cmd_mbox_config_profile_max_mid |
730 | * Maximum Multicast IDs. |
731 | * Multicast IDs are allocated from 0 to max_mid-1 |
732 | */ |
733 | MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16); |
734 | |
735 | /* cmd_mbox_config_profile_max_pgt |
736 | * Maximum records in the Port Group Table per Switch Partition. |
737 | * Port Group Table indexes are from 0 to max_pgt-1 |
738 | */ |
739 | MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16); |
740 | |
741 | /* cmd_mbox_config_profile_max_system_port |
742 | * The maximum number of system ports that can be allocated. |
743 | */ |
744 | MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16); |
745 | |
746 | /* cmd_mbox_config_profile_max_vlan_groups |
747 | * Maximum number VLAN Groups for VLAN binding. |
748 | */ |
749 | MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12); |
750 | |
751 | /* cmd_mbox_config_profile_max_regions |
752 | * Maximum number of TCAM Regions. |
753 | */ |
754 | MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16); |
755 | |
756 | /* cmd_mbox_config_profile_max_flood_tables |
757 | * Maximum number of single-entry flooding tables. Different flooding tables |
758 | * can be associated with different packet types. |
759 | */ |
760 | MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4); |
761 | |
762 | /* cmd_mbox_config_profile_max_vid_flood_tables |
763 | * Maximum number of per-vid flooding tables. Flooding tables are associated |
764 | * to the different packet types for the different switch partitions. |
765 | * Table size is 4K entries covering all VID space. |
766 | */ |
767 | MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4); |
768 | |
769 | enum mlxsw_cmd_mbox_config_profile_flood_mode { |
770 | /* Mixed mode, where: |
771 | * max_flood_tables indicates the number of single-entry tables. |
772 | * max_vid_flood_tables indicates the number of per-VID tables. |
773 | * max_fid_offset_flood_tables indicates the number of FID-offset |
774 | * tables. max_fid_flood_tables indicates the number of per-FID tables. |
775 | * Reserved when unified bridge model is used. |
776 | */ |
777 | MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_MIXED = 3, |
778 | /* Controlled flood tables. Reserved when legacy bridge model is |
779 | * used. |
780 | */ |
781 | MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED = 4, |
782 | }; |
783 | |
784 | /* cmd_mbox_config_profile_flood_mode |
785 | * Flooding mode to use. |
786 | */ |
787 | MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 3); |
788 | |
789 | /* cmd_mbox_config_profile_max_fid_offset_flood_tables |
790 | * Maximum number of FID-offset flooding tables. |
791 | */ |
792 | MLXSW_ITEM32(cmd_mbox, config_profile, |
793 | max_fid_offset_flood_tables, 0x34, 24, 4); |
794 | |
795 | /* cmd_mbox_config_profile_fid_offset_flood_table_size |
796 | * The size (number of entries) of each FID-offset flood table. |
797 | */ |
798 | MLXSW_ITEM32(cmd_mbox, config_profile, |
799 | fid_offset_flood_table_size, 0x34, 0, 16); |
800 | |
801 | /* cmd_mbox_config_profile_max_fid_flood_tables |
802 | * Maximum number of per-FID flooding tables. |
803 | * |
804 | * Note: This flooding tables cover special FIDs only (vFIDs), starting at |
805 | * FID value 4K and higher. |
806 | */ |
807 | MLXSW_ITEM32(cmd_mbox, config_profile, max_fid_flood_tables, 0x38, 24, 4); |
808 | |
809 | /* cmd_mbox_config_profile_fid_flood_table_size |
810 | * The size (number of entries) of each per-FID table. |
811 | */ |
812 | MLXSW_ITEM32(cmd_mbox, config_profile, fid_flood_table_size, 0x38, 0, 16); |
813 | |
814 | /* cmd_mbox_config_profile_max_ib_mc |
815 | * Maximum number of multicast FDB records for InfiniBand |
816 | * FDB (in 512 chunks) per InfiniBand switch partition. |
817 | */ |
818 | MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15); |
819 | |
820 | /* cmd_mbox_config_profile_max_pkey |
821 | * Maximum per port PKEY table size (for PKEY enforcement) |
822 | */ |
823 | MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15); |
824 | |
825 | /* cmd_mbox_config_profile_ar_sec |
826 | * Primary/secondary capability |
827 | * Describes the number of adaptive routing sub-groups |
828 | * 0 - disable primary/secondary (single group) |
829 | * 1 - enable primary/secondary (2 sub-groups) |
830 | * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2 |
831 | * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2 |
832 | */ |
833 | MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2); |
834 | |
835 | /* cmd_mbox_config_profile_adaptive_routing_group_cap |
836 | * Adaptive Routing Group Capability. Indicates the number of AR groups |
837 | * supported. Note that when Primary/secondary is enabled, each |
838 | * primary/secondary couple consumes 2 adaptive routing entries. |
839 | */ |
840 | MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16); |
841 | |
842 | /* cmd_mbox_config_profile_arn |
843 | * Adaptive Routing Notification Enable |
844 | * Not supported in SwitchX, SwitchX-2 |
845 | */ |
846 | MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1); |
847 | |
848 | /* cmd_mbox_config_profile_ubridge |
849 | * Unified Bridge |
850 | * 0 - non unified bridge |
851 | * 1 - unified bridge |
852 | */ |
853 | MLXSW_ITEM32(cmd_mbox, config_profile, ubridge, 0x50, 4, 1); |
854 | |
855 | enum mlxsw_cmd_mbox_config_profile_lag_mode { |
856 | /* FW manages PGT LAG table */ |
857 | MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_FW, |
858 | /* SW manages PGT LAG table */ |
859 | MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW, |
860 | }; |
861 | |
862 | /* cmd_mbox_config_profile_lag_mode |
863 | * LAG mode |
864 | * Configured if set_lag_mode is set |
865 | * Supported from Spectrum-2 and above. |
866 | * Supported only when ubridge = 1 |
867 | */ |
868 | MLXSW_ITEM32(cmd_mbox, config_profile, lag_mode, 0x50, 3, 1); |
869 | |
870 | /* cmd_mbox_config_kvd_linear_size |
871 | * KVD Linear Size |
872 | * Valid for Spectrum only |
873 | * Allowed values are 128*N where N=0 or higher |
874 | */ |
875 | MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24); |
876 | |
877 | /* cmd_mbox_config_profile_kvd_hash_single_size |
878 | * KVD Hash single-entries size |
879 | * Valid for Spectrum only |
880 | * Allowed values are 128*N where N=0 or higher |
881 | * Must be greater or equal to cap_min_kvd_hash_single_size |
882 | * Must be smaller or equal to cap_kvd_size - kvd_linear_size |
883 | */ |
884 | MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_single_size, 0x58, 0, 24); |
885 | |
886 | /* cmd_mbox_config_profile_kvd_hash_double_size |
887 | * KVD Hash double-entries size (units of single-size entries) |
888 | * Valid for Spectrum only |
889 | * Allowed values are 128*N where N=0 or higher |
890 | * Must be either 0 or greater or equal to cap_min_kvd_hash_double_size |
891 | * Must be smaller or equal to cap_kvd_size - kvd_linear_size |
892 | */ |
893 | MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_double_size, 0x5C, 0, 24); |
894 | |
895 | /* cmd_mbox_config_profile_swid_config_mask |
896 | * Modify Switch Partition Configuration mask. When set, the configu- |
897 | * ration value for the Switch Partition are taken from the mailbox. |
898 | * When clear, the current configuration values are used. |
899 | * Bit 0 - set type |
900 | * Bit 1 - properties |
901 | * Other - reserved |
902 | */ |
903 | MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask, |
904 | 0x60, 24, 8, 0x08, 0x00, false); |
905 | |
906 | /* cmd_mbox_config_profile_swid_config_type |
907 | * Switch Partition type. |
908 | * 0000 - disabled (Switch Partition does not exist) |
909 | * 0001 - InfiniBand |
910 | * 0010 - Ethernet |
911 | * 1000 - router port (SwitchX-2 only) |
912 | * Other - reserved |
913 | */ |
914 | MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type, |
915 | 0x60, 20, 4, 0x08, 0x00, false); |
916 | |
917 | /* cmd_mbox_config_profile_swid_config_properties |
918 | * Switch Partition properties. |
919 | */ |
920 | MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties, |
921 | 0x60, 0, 8, 0x08, 0x00, false); |
922 | |
923 | enum mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type { |
924 | /* uSec - 1.024uSec (default). Only bits 15:0 are valid. */ |
925 | MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_USEC, |
926 | /* FRC - Free Running Clock, units of 1nSec. |
927 | * Reserved when SwitchX/-2, Switch-IB/2 and Spectrum-1. |
928 | */ |
929 | MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_FRC, |
930 | /* UTC. time_stamp[37:30] = Sec, time_stamp[29:0] = nSec. |
931 | * Reserved when SwitchX/2, Switch-IB/2 and Spectrum-1. |
932 | */ |
933 | MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, |
934 | }; |
935 | |
936 | /* cmd_mbox_config_profile_cqe_time_stamp_type |
937 | * CQE time_stamp_type for non-mirror-packets. |
938 | * Configured if set_cqe_time_stamp_type is set. |
939 | * Reserved when SwitchX/-2, Switch-IB/2 and Spectrum-1. |
940 | */ |
941 | MLXSW_ITEM32(cmd_mbox, config_profile, cqe_time_stamp_type, 0xB0, 8, 2); |
942 | |
943 | /* cmd_mbox_config_profile_cqe_version |
944 | * CQE version: |
945 | * 0: CQE version is 0 |
946 | * 1: CQE version is either 1 or 2 |
947 | * CQE ver 1 or 2 is configured by Completion Queue Context field cqe_ver. |
948 | */ |
949 | MLXSW_ITEM32(cmd_mbox, config_profile, cqe_version, 0xB0, 0, 8); |
950 | |
951 | /* ACCESS_REG - Access EMAD Supported Register |
952 | * ---------------------------------- |
953 | * OpMod == 0 (N/A), INMmod == 0 (N/A) |
954 | * ------------------------------------- |
955 | * The ACCESS_REG command supports accessing device registers. This access |
956 | * is mainly used for bootstrapping. |
957 | */ |
958 | |
959 | static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core, |
960 | bool reset_ok, |
961 | char *in_mbox, char *out_mbox) |
962 | { |
963 | return mlxsw_cmd_exec(mlxsw_core, opcode: MLXSW_CMD_OPCODE_ACCESS_REG, |
964 | opcode_mod: 0, in_mod: 0, out_mbox_direct: false, reset_ok, |
965 | in_mbox, MLXSW_CMD_MBOX_SIZE, |
966 | out_mbox, MLXSW_CMD_MBOX_SIZE); |
967 | } |
968 | |
969 | /* SW2HW_DQ - Software to Hardware DQ |
970 | * ---------------------------------- |
971 | * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) |
972 | * INMmod == DQ number |
973 | * ---------------------------------------------- |
974 | * The SW2HW_DQ command transitions a descriptor queue from software to |
975 | * hardware ownership. The command enables posting WQEs and ringing DoorBells |
976 | * on the descriptor queue. |
977 | */ |
978 | |
979 | static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core, |
980 | char *in_mbox, u32 dq_number, |
981 | u8 opcode_mod) |
982 | { |
983 | return mlxsw_cmd_exec_in(mlxsw_core, opcode: MLXSW_CMD_OPCODE_SW2HW_DQ, |
984 | opcode_mod, in_mod: dq_number, |
985 | in_mbox, MLXSW_CMD_MBOX_SIZE); |
986 | } |
987 | |
988 | enum { |
989 | MLXSW_CMD_OPCODE_MOD_SDQ = 0, |
990 | MLXSW_CMD_OPCODE_MOD_RDQ = 1, |
991 | }; |
992 | |
993 | static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core, |
994 | char *in_mbox, u32 dq_number) |
995 | { |
996 | return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, |
997 | opcode_mod: MLXSW_CMD_OPCODE_MOD_SDQ); |
998 | } |
999 | |
1000 | static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core, |
1001 | char *in_mbox, u32 dq_number) |
1002 | { |
1003 | return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, |
1004 | opcode_mod: MLXSW_CMD_OPCODE_MOD_RDQ); |
1005 | } |
1006 | |
1007 | /* cmd_mbox_sw2hw_dq_cq |
1008 | * Number of the CQ that this Descriptor Queue reports completions to. |
1009 | */ |
1010 | MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8); |
1011 | |
1012 | enum mlxsw_cmd_mbox_sw2hw_dq_sdq_lp { |
1013 | MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_WQE, |
1014 | MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_IGNORE_WQE, |
1015 | }; |
1016 | |
1017 | /* cmd_mbox_sw2hw_dq_sdq_lp |
1018 | * SDQ local Processing |
1019 | * 0: local processing by wqe.lp |
1020 | * 1: local processing (ignoring wqe.lp) |
1021 | */ |
1022 | MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_lp, 0x00, 23, 1); |
1023 | |
1024 | /* cmd_mbox_sw2hw_dq_sdq_tclass |
1025 | * SDQ: CPU Egress TClass |
1026 | * RDQ: Reserved |
1027 | */ |
1028 | MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6); |
1029 | |
1030 | /* cmd_mbox_sw2hw_dq_log2_dq_sz |
1031 | * Log (base 2) of the Descriptor Queue size in 4KB pages. |
1032 | */ |
1033 | MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6); |
1034 | |
1035 | /* cmd_mbox_sw2hw_dq_pa |
1036 | * Physical Address. |
1037 | */ |
1038 | MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true); |
1039 | |
1040 | /* HW2SW_DQ - Hardware to Software DQ |
1041 | * ---------------------------------- |
1042 | * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) |
1043 | * INMmod == DQ number |
1044 | * ---------------------------------------------- |
1045 | * The HW2SW_DQ command transitions a descriptor queue from hardware to |
1046 | * software ownership. Incoming packets on the DQ are silently discarded, |
1047 | * SW should not post descriptors on nonoperational DQs. |
1048 | */ |
1049 | |
1050 | static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core, |
1051 | u32 dq_number, u8 opcode_mod) |
1052 | { |
1053 | return mlxsw_cmd_exec_none(mlxsw_core, opcode: MLXSW_CMD_OPCODE_HW2SW_DQ, |
1054 | opcode_mod, in_mod: dq_number); |
1055 | } |
1056 | |
1057 | static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core, |
1058 | u32 dq_number) |
1059 | { |
1060 | return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, |
1061 | opcode_mod: MLXSW_CMD_OPCODE_MOD_SDQ); |
1062 | } |
1063 | |
1064 | static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core, |
1065 | u32 dq_number) |
1066 | { |
1067 | return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, |
1068 | opcode_mod: MLXSW_CMD_OPCODE_MOD_RDQ); |
1069 | } |
1070 | |
1071 | /* 2ERR_DQ - To Error DQ |
1072 | * --------------------- |
1073 | * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) |
1074 | * INMmod == DQ number |
1075 | * ---------------------------------------------- |
1076 | * The 2ERR_DQ command transitions the DQ into the error state from the state |
1077 | * in which it has been. While the command is executed, some in-process |
1078 | * descriptors may complete. Once the DQ transitions into the error state, |
1079 | * if there are posted descriptors on the RDQ/SDQ, the hardware writes |
1080 | * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ. |
1081 | * When the command is completed successfully, the DQ is already in |
1082 | * the error state. |
1083 | */ |
1084 | |
1085 | static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core, |
1086 | u32 dq_number, u8 opcode_mod) |
1087 | { |
1088 | return mlxsw_cmd_exec_none(mlxsw_core, opcode: MLXSW_CMD_OPCODE_2ERR_DQ, |
1089 | opcode_mod, in_mod: dq_number); |
1090 | } |
1091 | |
1092 | static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core, |
1093 | u32 dq_number) |
1094 | { |
1095 | return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, |
1096 | opcode_mod: MLXSW_CMD_OPCODE_MOD_SDQ); |
1097 | } |
1098 | |
1099 | static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core, |
1100 | u32 dq_number) |
1101 | { |
1102 | return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, |
1103 | opcode_mod: MLXSW_CMD_OPCODE_MOD_RDQ); |
1104 | } |
1105 | |
1106 | /* QUERY_DQ - Query DQ |
1107 | * --------------------- |
1108 | * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) |
1109 | * INMmod == DQ number |
1110 | * ---------------------------------------------- |
1111 | * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware. |
1112 | * |
1113 | * Note: Output mailbox has the same format as SW2HW_DQ. |
1114 | */ |
1115 | |
1116 | static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core, |
1117 | char *out_mbox, u32 dq_number, |
1118 | u8 opcode_mod) |
1119 | { |
1120 | return mlxsw_cmd_exec_out(mlxsw_core, opcode: MLXSW_CMD_OPCODE_2ERR_DQ, |
1121 | opcode_mod, in_mod: dq_number, out_mbox_direct: false, |
1122 | out_mbox, MLXSW_CMD_MBOX_SIZE); |
1123 | } |
1124 | |
1125 | static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core, |
1126 | char *out_mbox, u32 dq_number) |
1127 | { |
1128 | return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, |
1129 | opcode_mod: MLXSW_CMD_OPCODE_MOD_SDQ); |
1130 | } |
1131 | |
1132 | static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core, |
1133 | char *out_mbox, u32 dq_number) |
1134 | { |
1135 | return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, |
1136 | opcode_mod: MLXSW_CMD_OPCODE_MOD_RDQ); |
1137 | } |
1138 | |
1139 | /* SW2HW_CQ - Software to Hardware CQ |
1140 | * ---------------------------------- |
1141 | * OpMod == 0 (N/A), INMmod == CQ number |
1142 | * ------------------------------------- |
1143 | * The SW2HW_CQ command transfers ownership of a CQ context entry from software |
1144 | * to hardware. The command takes the CQ context entry from the input mailbox |
1145 | * and stores it in the CQC in the ownership of the hardware. The command fails |
1146 | * if the requested CQC entry is already in the ownership of the hardware. |
1147 | */ |
1148 | |
1149 | static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core, |
1150 | char *in_mbox, u32 cq_number) |
1151 | { |
1152 | return mlxsw_cmd_exec_in(mlxsw_core, opcode: MLXSW_CMD_OPCODE_SW2HW_CQ, |
1153 | opcode_mod: 0, in_mod: cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); |
1154 | } |
1155 | |
1156 | enum mlxsw_cmd_mbox_sw2hw_cq_cqe_ver { |
1157 | MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1, |
1158 | MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2, |
1159 | }; |
1160 | |
1161 | /* cmd_mbox_sw2hw_cq_cqe_ver |
1162 | * CQE Version. |
1163 | */ |
1164 | MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cqe_ver, 0x00, 28, 4); |
1165 | |
1166 | /* cmd_mbox_sw2hw_cq_c_eqn |
1167 | * Event Queue this CQ reports completion events to. |
1168 | */ |
1169 | MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1); |
1170 | |
1171 | /* cmd_mbox_sw2hw_cq_st |
1172 | * Event delivery state machine |
1173 | * 0x0 - FIRED |
1174 | * 0x1 - ARMED (Request for Notification) |
1175 | */ |
1176 | MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1); |
1177 | |
1178 | /* cmd_mbox_sw2hw_cq_log_cq_size |
1179 | * Log (base 2) of the CQ size (in entries). |
1180 | */ |
1181 | MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4); |
1182 | |
1183 | /* cmd_mbox_sw2hw_cq_producer_counter |
1184 | * Producer Counter. The counter is incremented for each CQE that is |
1185 | * written by the HW to the CQ. |
1186 | * Maintained by HW (valid for the QUERY_CQ command only) |
1187 | */ |
1188 | MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16); |
1189 | |
1190 | /* cmd_mbox_sw2hw_cq_pa |
1191 | * Physical Address. |
1192 | */ |
1193 | MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true); |
1194 | |
1195 | /* HW2SW_CQ - Hardware to Software CQ |
1196 | * ---------------------------------- |
1197 | * OpMod == 0 (N/A), INMmod == CQ number |
1198 | * ------------------------------------- |
1199 | * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware |
1200 | * to software. The CQC entry is invalidated as a result of this command. |
1201 | */ |
1202 | |
1203 | static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core, |
1204 | u32 cq_number) |
1205 | { |
1206 | return mlxsw_cmd_exec_none(mlxsw_core, opcode: MLXSW_CMD_OPCODE_HW2SW_CQ, |
1207 | opcode_mod: 0, in_mod: cq_number); |
1208 | } |
1209 | |
1210 | /* QUERY_CQ - Query CQ |
1211 | * ---------------------------------- |
1212 | * OpMod == 0 (N/A), INMmod == CQ number |
1213 | * ------------------------------------- |
1214 | * The QUERY_CQ command retrieves a snapshot of the current CQ context entry. |
1215 | * The command stores the snapshot in the output mailbox in the software format. |
1216 | * Note that the CQ context state and values are not affected by the QUERY_CQ |
1217 | * command. The QUERY_CQ command is for debug purposes only. |
1218 | * |
1219 | * Note: Output mailbox has the same format as SW2HW_CQ. |
1220 | */ |
1221 | |
1222 | static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core, |
1223 | char *out_mbox, u32 cq_number) |
1224 | { |
1225 | return mlxsw_cmd_exec_out(mlxsw_core, opcode: MLXSW_CMD_OPCODE_QUERY_CQ, |
1226 | opcode_mod: 0, in_mod: cq_number, out_mbox_direct: false, |
1227 | out_mbox, MLXSW_CMD_MBOX_SIZE); |
1228 | } |
1229 | |
1230 | /* SW2HW_EQ - Software to Hardware EQ |
1231 | * ---------------------------------- |
1232 | * OpMod == 0 (N/A), INMmod == EQ number |
1233 | * ------------------------------------- |
1234 | * The SW2HW_EQ command transfers ownership of an EQ context entry from software |
1235 | * to hardware. The command takes the EQ context entry from the input mailbox |
1236 | * and stores it in the EQC in the ownership of the hardware. The command fails |
1237 | * if the requested EQC entry is already in the ownership of the hardware. |
1238 | */ |
1239 | |
1240 | static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core, |
1241 | char *in_mbox, u32 eq_number) |
1242 | { |
1243 | return mlxsw_cmd_exec_in(mlxsw_core, opcode: MLXSW_CMD_OPCODE_SW2HW_EQ, |
1244 | opcode_mod: 0, in_mod: eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); |
1245 | } |
1246 | |
1247 | /* cmd_mbox_sw2hw_eq_int_msix |
1248 | * When set, MSI-X cycles will be generated by this EQ. |
1249 | * When cleared, an interrupt will be generated by this EQ. |
1250 | */ |
1251 | MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1); |
1252 | |
1253 | /* cmd_mbox_sw2hw_eq_st |
1254 | * Event delivery state machine |
1255 | * 0x0 - FIRED |
1256 | * 0x1 - ARMED (Request for Notification) |
1257 | * 0x11 - Always ARMED |
1258 | * other - reserved |
1259 | */ |
1260 | MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2); |
1261 | |
1262 | /* cmd_mbox_sw2hw_eq_log_eq_size |
1263 | * Log (base 2) of the EQ size (in entries). |
1264 | */ |
1265 | MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4); |
1266 | |
1267 | /* cmd_mbox_sw2hw_eq_producer_counter |
1268 | * Producer Counter. The counter is incremented for each EQE that is written |
1269 | * by the HW to the EQ. |
1270 | * Maintained by HW (valid for the QUERY_EQ command only) |
1271 | */ |
1272 | MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16); |
1273 | |
1274 | /* cmd_mbox_sw2hw_eq_pa |
1275 | * Physical Address. |
1276 | */ |
1277 | MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true); |
1278 | |
1279 | /* HW2SW_EQ - Hardware to Software EQ |
1280 | * ---------------------------------- |
1281 | * OpMod == 0 (N/A), INMmod == EQ number |
1282 | * ------------------------------------- |
1283 | */ |
1284 | |
1285 | static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core, |
1286 | u32 eq_number) |
1287 | { |
1288 | return mlxsw_cmd_exec_none(mlxsw_core, opcode: MLXSW_CMD_OPCODE_HW2SW_EQ, |
1289 | opcode_mod: 0, in_mod: eq_number); |
1290 | } |
1291 | |
1292 | /* QUERY_EQ - Query EQ |
1293 | * ---------------------------------- |
1294 | * OpMod == 0 (N/A), INMmod == EQ number |
1295 | * ------------------------------------- |
1296 | * |
1297 | * Note: Output mailbox has the same format as SW2HW_EQ. |
1298 | */ |
1299 | |
1300 | static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core, |
1301 | char *out_mbox, u32 eq_number) |
1302 | { |
1303 | return mlxsw_cmd_exec_out(mlxsw_core, opcode: MLXSW_CMD_OPCODE_QUERY_EQ, |
1304 | opcode_mod: 0, in_mod: eq_number, out_mbox_direct: false, |
1305 | out_mbox, MLXSW_CMD_MBOX_SIZE); |
1306 | } |
1307 | |
1308 | #endif |
1309 | |