1/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3
4#ifndef _MLXSW_REG_H
5#define _MLXSW_REG_H
6
7#include <linux/kernel.h>
8#include <linux/string.h>
9#include <linux/bitops.h>
10#include <linux/if_vlan.h>
11
12#include "item.h"
13#include "port.h"
14
15struct mlxsw_reg_info {
16 u16 id;
17 u16 len; /* In u8 */
18 const char *name;
19};
20
21#define MLXSW_REG_DEFINE(_name, _id, _len) \
22static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
23 .id = _id, \
24 .len = _len, \
25 .name = #_name, \
26}
27
28#define MLXSW_REG(type) (&mlxsw_reg_##type)
29#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31
32/* SGCR - Switch General Configuration Register
33 * --------------------------------------------
34 * This register is used for configuration of the switch capabilities.
35 */
36#define MLXSW_REG_SGCR_ID 0x2000
37#define MLXSW_REG_SGCR_LEN 0x10
38
39MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40
41/* reg_sgcr_lag_lookup_pgt_base
42 * Base address used for lookup in PGT table
43 * Supported when CONFIG_PROFILE.lag_mode = 1
44 * Note: when IGCR.ddd_lag_mode=0, the address shall be aligned to 8 entries.
45 * Access: RW
46 */
47MLXSW_ITEM32(reg, sgcr, lag_lookup_pgt_base, 0x0C, 0, 16);
48
49static inline void mlxsw_reg_sgcr_pack(char *payload, u16 lag_lookup_pgt_base)
50{
51 MLXSW_REG_ZERO(sgcr, payload);
52 mlxsw_reg_sgcr_lag_lookup_pgt_base_set(buf: payload, val: lag_lookup_pgt_base);
53}
54
55/* SPAD - Switch Physical Address Register
56 * ---------------------------------------
57 * The SPAD register configures the switch physical MAC address.
58 */
59#define MLXSW_REG_SPAD_ID 0x2002
60#define MLXSW_REG_SPAD_LEN 0x10
61
62MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63
64/* reg_spad_base_mac
65 * Base MAC address for the switch partitions.
66 * Per switch partition MAC address is equal to:
67 * base_mac + swid
68 * Access: RW
69 */
70MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71
72/* SSPR - Switch System Port Record Register
73 * -----------------------------------------
74 * Configures the system port to local port mapping.
75 */
76#define MLXSW_REG_SSPR_ID 0x2008
77#define MLXSW_REG_SSPR_LEN 0x8
78
79MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
80
81/* reg_sspr_m
82 * Master - if set, then the record describes the master system port.
83 * This is needed in case a local port is mapped into several system ports
84 * (for multipathing). That number will be reported as the source system
85 * port when packets are forwarded to the CPU. Only one master port is allowed
86 * per local port.
87 *
88 * Note: Must be set for Spectrum.
89 * Access: RW
90 */
91MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
92
93/* reg_sspr_local_port
94 * Local port number.
95 *
96 * Access: RW
97 */
98MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12);
99
100/* reg_sspr_system_port
101 * Unique identifier within the stacking domain that represents all the ports
102 * that are available in the system (external ports).
103 *
104 * Currently, only single-ASIC configurations are supported, so we default to
105 * 1:1 mapping between system ports and local ports.
106 * Access: Index
107 */
108MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
109
110static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port)
111{
112 MLXSW_REG_ZERO(sspr, payload);
113 mlxsw_reg_sspr_m_set(buf: payload, val: 1);
114 mlxsw_reg_sspr_local_port_set(buf: payload, val: local_port);
115 mlxsw_reg_sspr_system_port_set(buf: payload, val: local_port);
116}
117
118/* SFDAT - Switch Filtering Database Aging Time
119 * --------------------------------------------
120 * Controls the Switch aging time. Aging time is able to be set per Switch
121 * Partition.
122 */
123#define MLXSW_REG_SFDAT_ID 0x2009
124#define MLXSW_REG_SFDAT_LEN 0x8
125
126MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
127
128/* reg_sfdat_swid
129 * Switch partition ID.
130 * Access: Index
131 */
132MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
133
134/* reg_sfdat_age_time
135 * Aging time in seconds
136 * Min - 10 seconds
137 * Max - 1,000,000 seconds
138 * Default is 300 seconds.
139 * Access: RW
140 */
141MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
142
143static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
144{
145 MLXSW_REG_ZERO(sfdat, payload);
146 mlxsw_reg_sfdat_swid_set(buf: payload, val: 0);
147 mlxsw_reg_sfdat_age_time_set(buf: payload, val: age_time);
148}
149
150/* SFD - Switch Filtering Database
151 * -------------------------------
152 * The following register defines the access to the filtering database.
153 * The register supports querying, adding, removing and modifying the database.
154 * The access is optimized for bulk updates in which case more than one
155 * FDB record is present in the same command.
156 */
157#define MLXSW_REG_SFD_ID 0x200A
158#define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
159#define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
160#define MLXSW_REG_SFD_REC_MAX_COUNT 64
161#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
162 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
163
164MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
165
166/* reg_sfd_swid
167 * Switch partition ID for queries. Reserved on Write.
168 * Access: Index
169 */
170MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
171
172enum mlxsw_reg_sfd_op {
173 /* Dump entire FDB a (process according to record_locator) */
174 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
175 /* Query records by {MAC, VID/FID} value */
176 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
177 /* Query and clear activity. Query records by {MAC, VID/FID} value */
178 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
179 /* Test. Response indicates if each of the records could be
180 * added to the FDB.
181 */
182 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
183 /* Add/modify. Aged-out records cannot be added. This command removes
184 * the learning notification of the {MAC, VID/FID}. Response includes
185 * the entries that were added to the FDB.
186 */
187 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
188 /* Remove record by {MAC, VID/FID}. This command also removes
189 * the learning notification and aged-out notifications
190 * of the {MAC, VID/FID}. The response provides current (pre-removal)
191 * entries as non-aged-out.
192 */
193 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
194 /* Remove learned notification by {MAC, VID/FID}. The response provides
195 * the removed learning notification.
196 */
197 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
198};
199
200/* reg_sfd_op
201 * Operation.
202 * Access: OP
203 */
204MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
205
206/* reg_sfd_record_locator
207 * Used for querying the FDB. Use record_locator=0 to initiate the
208 * query. When a record is returned, a new record_locator is
209 * returned to be used in the subsequent query.
210 * Reserved for database update.
211 * Access: Index
212 */
213MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
214
215/* reg_sfd_num_rec
216 * Request: Number of records to read/add/modify/remove
217 * Response: Number of records read/added/replaced/removed
218 * See above description for more details.
219 * Ranges 0..64
220 * Access: RW
221 */
222MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
223
224static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
225 u32 record_locator)
226{
227 MLXSW_REG_ZERO(sfd, payload);
228 mlxsw_reg_sfd_op_set(buf: payload, val: op);
229 mlxsw_reg_sfd_record_locator_set(buf: payload, val: record_locator);
230}
231
232/* reg_sfd_rec_swid
233 * Switch partition ID.
234 * Access: Index
235 */
236MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
237 MLXSW_REG_SFD_REC_LEN, 0x00, false);
238
239enum mlxsw_reg_sfd_rec_type {
240 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
241 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
242 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
243 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
244};
245
246/* reg_sfd_rec_type
247 * FDB record type.
248 * Access: RW
249 */
250MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
251 MLXSW_REG_SFD_REC_LEN, 0x00, false);
252
253enum mlxsw_reg_sfd_rec_policy {
254 /* Replacement disabled, aging disabled. */
255 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
256 /* (mlag remote): Replacement enabled, aging disabled,
257 * learning notification enabled on this port.
258 */
259 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
260 /* (ingress device): Replacement enabled, aging enabled. */
261 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
262};
263
264/* reg_sfd_rec_policy
265 * Policy.
266 * Access: RW
267 */
268MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
269 MLXSW_REG_SFD_REC_LEN, 0x00, false);
270
271/* reg_sfd_rec_a
272 * Activity. Set for new static entries. Set for static entries if a frame SMAC
273 * lookup hits on the entry.
274 * To clear the a bit, use "query and clear activity" op.
275 * Access: RO
276 */
277MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
278 MLXSW_REG_SFD_REC_LEN, 0x00, false);
279
280/* reg_sfd_rec_mac
281 * MAC address.
282 * Access: Index
283 */
284MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
285 MLXSW_REG_SFD_REC_LEN, 0x02);
286
287enum mlxsw_reg_sfd_rec_action {
288 /* forward */
289 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
290 /* forward and trap, trap_id is FDB_TRAP */
291 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
292 /* trap and do not forward, trap_id is FDB_TRAP */
293 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
294 /* forward to IP router */
295 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
296 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
297};
298
299/* reg_sfd_rec_action
300 * Action to apply on the packet.
301 * Note: Dynamic entries can only be configured with NOP action.
302 * Access: RW
303 */
304MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
305 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
306
307/* reg_sfd_uc_sub_port
308 * VEPA channel on local port.
309 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
310 * VEPA is not enabled.
311 * Access: RW
312 */
313MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
314 MLXSW_REG_SFD_REC_LEN, 0x08, false);
315
316/* reg_sfd_uc_set_vid
317 * Set VID.
318 * 0 - Do not update VID.
319 * 1 - Set VID.
320 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid.
321 * Access: RW
322 *
323 * Note: Reserved when legacy bridge model is used.
324 */
325MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
326 MLXSW_REG_SFD_REC_LEN, 0x08, false);
327
328/* reg_sfd_uc_fid_vid
329 * Filtering ID or VLAN ID
330 * For SwitchX and SwitchX-2:
331 * - Dynamic entries (policy 2,3) use FID
332 * - Static entries (policy 0) use VID
333 * - When independent learning is configured, VID=FID
334 * For Spectrum: use FID for both Dynamic and Static entries.
335 * VID should not be used.
336 * Access: Index
337 */
338MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
339 MLXSW_REG_SFD_REC_LEN, 0x08, false);
340
341/* reg_sfd_uc_vid
342 * New VID when set_vid=1.
343 * Access: RW
344 *
345 * Note: Reserved when legacy bridge model is used and when set_vid=0.
346 */
347MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
348 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
349
350/* reg_sfd_uc_system_port
351 * Unique port identifier for the final destination of the packet.
352 * Access: RW
353 */
354MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
355 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
356
357static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
358 enum mlxsw_reg_sfd_rec_type rec_type,
359 const char *mac,
360 enum mlxsw_reg_sfd_rec_action action)
361{
362 u8 num_rec = mlxsw_reg_sfd_num_rec_get(buf: payload);
363
364 if (rec_index >= num_rec)
365 mlxsw_reg_sfd_num_rec_set(buf: payload, val: rec_index + 1);
366 mlxsw_reg_sfd_rec_swid_set(buf: payload, index: rec_index, val: 0);
367 mlxsw_reg_sfd_rec_type_set(buf: payload, index: rec_index, val: rec_type);
368 mlxsw_reg_sfd_rec_mac_memcpy_to(buf: payload, index: rec_index, src: mac);
369 mlxsw_reg_sfd_rec_action_set(buf: payload, index: rec_index, val: action);
370}
371
372static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
373 enum mlxsw_reg_sfd_rec_policy policy,
374 const char *mac, u16 fid_vid, u16 vid,
375 enum mlxsw_reg_sfd_rec_action action,
376 u16 local_port)
377{
378 mlxsw_reg_sfd_rec_pack(payload, rec_index,
379 rec_type: MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
380 mlxsw_reg_sfd_rec_policy_set(buf: payload, index: rec_index, val: policy);
381 mlxsw_reg_sfd_uc_sub_port_set(buf: payload, index: rec_index, val: 0);
382 mlxsw_reg_sfd_uc_fid_vid_set(buf: payload, index: rec_index, val: fid_vid);
383 mlxsw_reg_sfd_uc_set_vid_set(buf: payload, index: rec_index, val: vid ? true : false);
384 mlxsw_reg_sfd_uc_vid_set(buf: payload, index: rec_index, val: vid);
385 mlxsw_reg_sfd_uc_system_port_set(buf: payload, index: rec_index, val: local_port);
386}
387
388/* reg_sfd_uc_lag_sub_port
389 * LAG sub port.
390 * Must be 0 if multichannel VEPA is not enabled.
391 * Access: RW
392 */
393MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
394 MLXSW_REG_SFD_REC_LEN, 0x08, false);
395
396/* reg_sfd_uc_lag_set_vid
397 * Set VID.
398 * 0 - Do not update VID.
399 * 1 - Set VID.
400 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid.
401 * Access: RW
402 *
403 * Note: Reserved when legacy bridge model is used.
404 */
405MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1,
406 MLXSW_REG_SFD_REC_LEN, 0x08, false);
407
408/* reg_sfd_uc_lag_fid_vid
409 * Filtering ID or VLAN ID
410 * For SwitchX and SwitchX-2:
411 * - Dynamic entries (policy 2,3) use FID
412 * - Static entries (policy 0) use VID
413 * - When independent learning is configured, VID=FID
414 * For Spectrum: use FID for both Dynamic and Static entries.
415 * VID should not be used.
416 * Access: Index
417 */
418MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
419 MLXSW_REG_SFD_REC_LEN, 0x08, false);
420
421/* reg_sfd_uc_lag_lag_vid
422 * New vlan ID.
423 * Access: RW
424 *
425 * Note: Reserved when legacy bridge model is used and set_vid=0.
426 */
427MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
428 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
429
430/* reg_sfd_uc_lag_lag_id
431 * LAG Identifier - pointer into the LAG descriptor table.
432 * Access: RW
433 */
434MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
435 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
436
437static inline void
438mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
439 enum mlxsw_reg_sfd_rec_policy policy,
440 const char *mac, u16 fid_vid,
441 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
442 u16 lag_id)
443{
444 mlxsw_reg_sfd_rec_pack(payload, rec_index,
445 rec_type: MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
446 mac, action);
447 mlxsw_reg_sfd_rec_policy_set(buf: payload, index: rec_index, val: policy);
448 mlxsw_reg_sfd_uc_lag_sub_port_set(buf: payload, index: rec_index, val: 0);
449 mlxsw_reg_sfd_uc_lag_fid_vid_set(buf: payload, index: rec_index, val: fid_vid);
450 mlxsw_reg_sfd_uc_lag_set_vid_set(buf: payload, index: rec_index, val: true);
451 mlxsw_reg_sfd_uc_lag_lag_vid_set(buf: payload, index: rec_index, val: lag_vid);
452 mlxsw_reg_sfd_uc_lag_lag_id_set(buf: payload, index: rec_index, val: lag_id);
453}
454
455/* reg_sfd_mc_pgi
456 *
457 * Multicast port group index - index into the port group table.
458 * Value 0x1FFF indicates the pgi should point to the MID entry.
459 * For Spectrum this value must be set to 0x1FFF
460 * Access: RW
461 */
462MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
463 MLXSW_REG_SFD_REC_LEN, 0x08, false);
464
465/* reg_sfd_mc_fid_vid
466 *
467 * Filtering ID or VLAN ID
468 * Access: Index
469 */
470MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
471 MLXSW_REG_SFD_REC_LEN, 0x08, false);
472
473/* reg_sfd_mc_mid
474 *
475 * Multicast identifier - global identifier that represents the multicast
476 * group across all devices.
477 * Access: RW
478 */
479MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
480 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
481
482static inline void
483mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
484 const char *mac, u16 fid_vid,
485 enum mlxsw_reg_sfd_rec_action action, u16 mid)
486{
487 mlxsw_reg_sfd_rec_pack(payload, rec_index,
488 rec_type: MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
489 mlxsw_reg_sfd_mc_pgi_set(buf: payload, index: rec_index, val: 0x1FFF);
490 mlxsw_reg_sfd_mc_fid_vid_set(buf: payload, index: rec_index, val: fid_vid);
491 mlxsw_reg_sfd_mc_mid_set(buf: payload, index: rec_index, val: mid);
492}
493
494/* reg_sfd_uc_tunnel_uip_msb
495 * When protocol is IPv4, the most significant byte of the underlay IPv4
496 * destination IP.
497 * When protocol is IPv6, reserved.
498 * Access: RW
499 */
500MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
501 8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
502
503/* reg_sfd_uc_tunnel_fid
504 * Filtering ID.
505 * Access: Index
506 */
507MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
508 MLXSW_REG_SFD_REC_LEN, 0x08, false);
509
510enum mlxsw_reg_sfd_uc_tunnel_protocol {
511 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
512 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
513};
514
515/* reg_sfd_uc_tunnel_protocol
516 * IP protocol.
517 * Access: RW
518 */
519MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
520 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
521
522/* reg_sfd_uc_tunnel_uip_lsb
523 * When protocol is IPv4, the least significant bytes of the underlay
524 * IPv4 destination IP.
525 * When protocol is IPv6, pointer to the underlay IPv6 destination IP
526 * which is configured by RIPS.
527 * Access: RW
528 */
529MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
530 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
531
532static inline void
533mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
534 enum mlxsw_reg_sfd_rec_policy policy,
535 const char *mac, u16 fid,
536 enum mlxsw_reg_sfd_rec_action action,
537 enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
538{
539 mlxsw_reg_sfd_rec_pack(payload, rec_index,
540 rec_type: MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
541 action);
542 mlxsw_reg_sfd_rec_policy_set(buf: payload, index: rec_index, val: policy);
543 mlxsw_reg_sfd_uc_tunnel_fid_set(buf: payload, index: rec_index, val: fid);
544 mlxsw_reg_sfd_uc_tunnel_protocol_set(buf: payload, index: rec_index, val: proto);
545}
546
547static inline void
548mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index,
549 enum mlxsw_reg_sfd_rec_policy policy,
550 const char *mac, u16 fid,
551 enum mlxsw_reg_sfd_rec_action action, u32 uip)
552{
553 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(buf: payload, index: rec_index, val: uip >> 24);
554 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(buf: payload, index: rec_index, val: uip);
555 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid,
556 action,
557 proto: MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4);
558}
559
560static inline void
561mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac,
562 u16 fid, enum mlxsw_reg_sfd_rec_action action,
563 u32 uip_ptr)
564{
565 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(buf: payload, index: rec_index, val: uip_ptr);
566 /* Only static policy is supported for IPv6 unicast tunnel entry. */
567 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index,
568 policy: MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY,
569 mac, fid, action,
570 proto: MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6);
571}
572
573enum mlxsw_reg_tunnel_port {
574 MLXSW_REG_TUNNEL_PORT_NVE,
575 MLXSW_REG_TUNNEL_PORT_VPLS,
576 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0,
577 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1,
578};
579
580/* SFN - Switch FDB Notification Register
581 * -------------------------------------------
582 * The switch provides notifications on newly learned FDB entries and
583 * aged out entries. The notifications can be polled by software.
584 */
585#define MLXSW_REG_SFN_ID 0x200B
586#define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
587#define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
588#define MLXSW_REG_SFN_REC_MAX_COUNT 64
589#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
590 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
591
592MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
593
594/* reg_sfn_swid
595 * Switch partition ID.
596 * Access: Index
597 */
598MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
599
600/* reg_sfn_end
601 * Forces the current session to end.
602 * Access: OP
603 */
604MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
605
606/* reg_sfn_num_rec
607 * Request: Number of learned notifications and aged-out notification
608 * records requested.
609 * Response: Number of notification records returned (must be smaller
610 * than or equal to the value requested)
611 * Ranges 0..64
612 * Access: OP
613 */
614MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
615
616static inline void mlxsw_reg_sfn_pack(char *payload)
617{
618 MLXSW_REG_ZERO(sfn, payload);
619 mlxsw_reg_sfn_swid_set(buf: payload, val: 0);
620 mlxsw_reg_sfn_end_set(buf: payload, val: 0);
621 mlxsw_reg_sfn_num_rec_set(buf: payload, MLXSW_REG_SFN_REC_MAX_COUNT);
622}
623
624/* reg_sfn_rec_swid
625 * Switch partition ID.
626 * Access: RO
627 */
628MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
629 MLXSW_REG_SFN_REC_LEN, 0x00, false);
630
631enum mlxsw_reg_sfn_rec_type {
632 /* MAC addresses learned on a regular port. */
633 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
634 /* MAC addresses learned on a LAG port. */
635 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
636 /* Aged-out MAC address on a regular port. */
637 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
638 /* Aged-out MAC address on a LAG port. */
639 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
640 /* Learned unicast tunnel record. */
641 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
642 /* Aged-out unicast tunnel record. */
643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
644};
645
646/* reg_sfn_rec_type
647 * Notification record type.
648 * Access: RO
649 */
650MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
651 MLXSW_REG_SFN_REC_LEN, 0x00, false);
652
653/* reg_sfn_rec_mac
654 * MAC address.
655 * Access: RO
656 */
657MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
658 MLXSW_REG_SFN_REC_LEN, 0x02);
659
660/* reg_sfn_mac_sub_port
661 * VEPA channel on the local port.
662 * 0 if multichannel VEPA is not enabled.
663 * Access: RO
664 */
665MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
666 MLXSW_REG_SFN_REC_LEN, 0x08, false);
667
668/* reg_sfn_mac_fid
669 * Filtering identifier.
670 * Access: RO
671 */
672MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
673 MLXSW_REG_SFN_REC_LEN, 0x08, false);
674
675/* reg_sfn_mac_system_port
676 * Unique port identifier for the final destination of the packet.
677 * Access: RO
678 */
679MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
680 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
681
682static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
683 char *mac, u16 *p_vid,
684 u16 *p_local_port)
685{
686 mlxsw_reg_sfn_rec_mac_memcpy_from(buf: payload, index: rec_index, dst: mac);
687 *p_vid = mlxsw_reg_sfn_mac_fid_get(buf: payload, index: rec_index);
688 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(buf: payload, index: rec_index);
689}
690
691/* reg_sfn_mac_lag_lag_id
692 * LAG ID (pointer into the LAG descriptor table).
693 * Access: RO
694 */
695MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
696 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
697
698static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
699 char *mac, u16 *p_vid,
700 u16 *p_lag_id)
701{
702 mlxsw_reg_sfn_rec_mac_memcpy_from(buf: payload, index: rec_index, dst: mac);
703 *p_vid = mlxsw_reg_sfn_mac_fid_get(buf: payload, index: rec_index);
704 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(buf: payload, index: rec_index);
705}
706
707/* reg_sfn_uc_tunnel_uip_msb
708 * When protocol is IPv4, the most significant byte of the underlay IPv4
709 * address of the remote VTEP.
710 * When protocol is IPv6, reserved.
711 * Access: RO
712 */
713MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
714 8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
715
716enum mlxsw_reg_sfn_uc_tunnel_protocol {
717 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
718 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
719};
720
721/* reg_sfn_uc_tunnel_protocol
722 * IP protocol.
723 * Access: RO
724 */
725MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
726 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
727
728/* reg_sfn_uc_tunnel_uip_lsb
729 * When protocol is IPv4, the least significant bytes of the underlay
730 * IPv4 address of the remote VTEP.
731 * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
732 * Access: RO
733 */
734MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
735 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
736
737/* reg_sfn_uc_tunnel_port
738 * Tunnel port.
739 * Reserved on Spectrum.
740 * Access: RO
741 */
742MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
743 MLXSW_REG_SFN_REC_LEN, 0x10, false);
744
745static inline void
746mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
747 u16 *p_fid, u32 *p_uip,
748 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
749{
750 u32 uip_msb, uip_lsb;
751
752 mlxsw_reg_sfn_rec_mac_memcpy_from(buf: payload, index: rec_index, dst: mac);
753 *p_fid = mlxsw_reg_sfn_mac_fid_get(buf: payload, index: rec_index);
754 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(buf: payload, index: rec_index);
755 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(buf: payload, index: rec_index);
756 *p_uip = uip_msb << 24 | uip_lsb;
757 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(buf: payload, index: rec_index);
758}
759
760/* SPMS - Switch Port MSTP/RSTP State Register
761 * -------------------------------------------
762 * Configures the spanning tree state of a physical port.
763 */
764#define MLXSW_REG_SPMS_ID 0x200D
765#define MLXSW_REG_SPMS_LEN 0x404
766
767MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
768
769/* reg_spms_local_port
770 * Local port number.
771 * Access: Index
772 */
773MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12);
774
775enum mlxsw_reg_spms_state {
776 MLXSW_REG_SPMS_STATE_NO_CHANGE,
777 MLXSW_REG_SPMS_STATE_DISCARDING,
778 MLXSW_REG_SPMS_STATE_LEARNING,
779 MLXSW_REG_SPMS_STATE_FORWARDING,
780};
781
782/* reg_spms_state
783 * Spanning tree state of each VLAN ID (VID) of the local port.
784 * 0 - Do not change spanning tree state (used only when writing).
785 * 1 - Discarding. No learning or forwarding to/from this port (default).
786 * 2 - Learning. Port is learning, but not forwarding.
787 * 3 - Forwarding. Port is learning and forwarding.
788 * Access: RW
789 */
790MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
791
792static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port)
793{
794 MLXSW_REG_ZERO(spms, payload);
795 mlxsw_reg_spms_local_port_set(buf: payload, val: local_port);
796}
797
798static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
799 enum mlxsw_reg_spms_state state)
800{
801 mlxsw_reg_spms_state_set(buf: payload, index: vid, val: state);
802}
803
804/* SPVID - Switch Port VID
805 * -----------------------
806 * The switch port VID configures the default VID for a port.
807 */
808#define MLXSW_REG_SPVID_ID 0x200E
809#define MLXSW_REG_SPVID_LEN 0x08
810
811MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
812
813/* reg_spvid_tport
814 * Port is tunnel port.
815 * Reserved when SwitchX/-2 or Spectrum-1.
816 * Access: Index
817 */
818MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1);
819
820/* reg_spvid_local_port
821 * When tport = 0: Local port number. Not supported for CPU port.
822 * When tport = 1: Tunnel port.
823 * Access: Index
824 */
825MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12);
826
827/* reg_spvid_sub_port
828 * Virtual port within the physical port.
829 * Should be set to 0 when virtual ports are not enabled on the port.
830 * Access: Index
831 */
832MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
833
834/* reg_spvid_egr_et_set
835 * When VLAN is pushed at ingress (for untagged packets or for
836 * QinQ push mode) then the EtherType is decided at the egress port.
837 * Reserved when Spectrum-1.
838 * Access: RW
839 */
840MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1);
841
842/* reg_spvid_et_vlan
843 * EtherType used for when VLAN is pushed at ingress (for untagged
844 * packets or for QinQ push mode).
845 * 0: ether_type0 - (default)
846 * 1: ether_type1
847 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2
848 * Ethertype IDs are configured by SVER.
849 * Reserved when egr_et_set = 1.
850 * Access: RW
851 */
852MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2);
853
854/* reg_spvid_pvid
855 * Port default VID
856 * Access: RW
857 */
858MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
859
860static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid,
861 u8 et_vlan)
862{
863 MLXSW_REG_ZERO(spvid, payload);
864 mlxsw_reg_spvid_local_port_set(buf: payload, val: local_port);
865 mlxsw_reg_spvid_pvid_set(buf: payload, val: pvid);
866 mlxsw_reg_spvid_et_vlan_set(buf: payload, val: et_vlan);
867}
868
869/* SPVM - Switch Port VLAN Membership
870 * ----------------------------------
871 * The Switch Port VLAN Membership register configures the VLAN membership
872 * of a port in a VLAN denoted by VID. VLAN membership is managed per
873 * virtual port. The register can be used to add and remove VID(s) from a port.
874 */
875#define MLXSW_REG_SPVM_ID 0x200F
876#define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
877#define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
878#define MLXSW_REG_SPVM_REC_MAX_COUNT 255
879#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
880 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
881
882MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
883
884/* reg_spvm_pt
885 * Priority tagged. If this bit is set, packets forwarded to the port with
886 * untagged VLAN membership (u bit is set) will be tagged with priority tag
887 * (VID=0)
888 * Access: RW
889 */
890MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
891
892/* reg_spvm_pte
893 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
894 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
895 * Access: WO
896 */
897MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
898
899/* reg_spvm_local_port
900 * Local port number.
901 * Access: Index
902 */
903MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12);
904
905/* reg_spvm_sub_port
906 * Virtual port within the physical port.
907 * Should be set to 0 when virtual ports are not enabled on the port.
908 * Access: Index
909 */
910MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
911
912/* reg_spvm_num_rec
913 * Number of records to update. Each record contains: i, e, u, vid.
914 * Access: OP
915 */
916MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
917
918/* reg_spvm_rec_i
919 * Ingress membership in VLAN ID.
920 * Access: Index
921 */
922MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
923 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
924 MLXSW_REG_SPVM_REC_LEN, 0, false);
925
926/* reg_spvm_rec_e
927 * Egress membership in VLAN ID.
928 * Access: Index
929 */
930MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
931 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
932 MLXSW_REG_SPVM_REC_LEN, 0, false);
933
934/* reg_spvm_rec_u
935 * Untagged - port is an untagged member - egress transmission uses untagged
936 * frames on VID<n>
937 * Access: Index
938 */
939MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
940 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
941 MLXSW_REG_SPVM_REC_LEN, 0, false);
942
943/* reg_spvm_rec_vid
944 * Egress membership in VLAN ID.
945 * Access: Index
946 */
947MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
948 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
949 MLXSW_REG_SPVM_REC_LEN, 0, false);
950
951static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port,
952 u16 vid_begin, u16 vid_end,
953 bool is_member, bool untagged)
954{
955 int size = vid_end - vid_begin + 1;
956 int i;
957
958 MLXSW_REG_ZERO(spvm, payload);
959 mlxsw_reg_spvm_local_port_set(buf: payload, val: local_port);
960 mlxsw_reg_spvm_num_rec_set(buf: payload, val: size);
961
962 for (i = 0; i < size; i++) {
963 mlxsw_reg_spvm_rec_i_set(buf: payload, index: i, val: is_member);
964 mlxsw_reg_spvm_rec_e_set(buf: payload, index: i, val: is_member);
965 mlxsw_reg_spvm_rec_u_set(buf: payload, index: i, val: untagged);
966 mlxsw_reg_spvm_rec_vid_set(buf: payload, index: i, val: vid_begin + i);
967 }
968}
969
970/* SPAFT - Switch Port Acceptable Frame Types
971 * ------------------------------------------
972 * The Switch Port Acceptable Frame Types register configures the frame
973 * admittance of the port.
974 */
975#define MLXSW_REG_SPAFT_ID 0x2010
976#define MLXSW_REG_SPAFT_LEN 0x08
977
978MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
979
980/* reg_spaft_local_port
981 * Local port number.
982 * Access: Index
983 *
984 * Note: CPU port is not supported (all tag types are allowed).
985 */
986MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12);
987
988/* reg_spaft_sub_port
989 * Virtual port within the physical port.
990 * Should be set to 0 when virtual ports are not enabled on the port.
991 * Access: RW
992 */
993MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
994
995/* reg_spaft_allow_untagged
996 * When set, untagged frames on the ingress are allowed (default).
997 * Access: RW
998 */
999MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
1000
1001/* reg_spaft_allow_prio_tagged
1002 * When set, priority tagged frames on the ingress are allowed (default).
1003 * Access: RW
1004 */
1005MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
1006
1007/* reg_spaft_allow_tagged
1008 * When set, tagged frames on the ingress are allowed (default).
1009 * Access: RW
1010 */
1011MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
1012
1013static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port,
1014 bool allow_untagged)
1015{
1016 MLXSW_REG_ZERO(spaft, payload);
1017 mlxsw_reg_spaft_local_port_set(buf: payload, val: local_port);
1018 mlxsw_reg_spaft_allow_untagged_set(buf: payload, val: allow_untagged);
1019 mlxsw_reg_spaft_allow_prio_tagged_set(buf: payload, val: allow_untagged);
1020 mlxsw_reg_spaft_allow_tagged_set(buf: payload, val: true);
1021}
1022
1023/* SFGC - Switch Flooding Group Configuration
1024 * ------------------------------------------
1025 * The following register controls the association of flooding tables and MIDs
1026 * to packet types used for flooding.
1027 *
1028 * Reserved when CONFIG_PROFILE.flood_mode = CFF.
1029 */
1030#define MLXSW_REG_SFGC_ID 0x2011
1031#define MLXSW_REG_SFGC_LEN 0x14
1032
1033MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1034
1035enum mlxsw_reg_sfgc_type {
1036 MLXSW_REG_SFGC_TYPE_BROADCAST,
1037 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1038 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1039 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1040 MLXSW_REG_SFGC_TYPE_RESERVED,
1041 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1042 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1043 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1044 MLXSW_REG_SFGC_TYPE_MAX,
1045};
1046
1047/* reg_sfgc_type
1048 * The traffic type to reach the flooding table.
1049 * Access: Index
1050 */
1051MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1052
1053/* bridge_type is used in SFGC and SFMR. */
1054enum mlxsw_reg_bridge_type {
1055 MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */
1056 MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */
1057};
1058
1059/* reg_sfgc_bridge_type
1060 * Access: Index
1061 *
1062 * Note: SwitchX-2 only supports 802.1Q mode.
1063 */
1064MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1065
1066enum mlxsw_flood_table_type {
1067 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1068 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1069 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1070 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1071 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1072};
1073
1074/* reg_sfgc_table_type
1075 * See mlxsw_flood_table_type
1076 * Access: RW
1077 *
1078 * Note: FID offset and FID types are not supported in SwitchX-2.
1079 */
1080MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1081
1082/* reg_sfgc_flood_table
1083 * Flooding table index to associate with the specific type on the specific
1084 * switch partition.
1085 * Access: RW
1086 */
1087MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1088
1089/* reg_sfgc_counter_set_type
1090 * Counter Set Type for flow counters.
1091 * Access: RW
1092 */
1093MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1094
1095/* reg_sfgc_counter_index
1096 * Counter Index for flow counters.
1097 * Access: RW
1098 */
1099MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1100
1101/* reg_sfgc_mid_base
1102 * MID Base.
1103 * Access: RW
1104 *
1105 * Note: Reserved when legacy bridge model is used.
1106 */
1107MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16);
1108
1109static inline void
1110mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1111 enum mlxsw_reg_bridge_type bridge_type,
1112 enum mlxsw_flood_table_type table_type,
1113 unsigned int flood_table, u16 mid_base)
1114{
1115 MLXSW_REG_ZERO(sfgc, payload);
1116 mlxsw_reg_sfgc_type_set(buf: payload, val: type);
1117 mlxsw_reg_sfgc_bridge_type_set(buf: payload, val: bridge_type);
1118 mlxsw_reg_sfgc_table_type_set(buf: payload, val: table_type);
1119 mlxsw_reg_sfgc_flood_table_set(buf: payload, val: flood_table);
1120 mlxsw_reg_sfgc_mid_base_set(buf: payload, val: mid_base);
1121}
1122
1123/* SFDF - Switch Filtering DB Flush
1124 * --------------------------------
1125 * The switch filtering DB flush register is used to flush the FDB.
1126 * Note that FDB notifications are flushed as well.
1127 */
1128#define MLXSW_REG_SFDF_ID 0x2013
1129#define MLXSW_REG_SFDF_LEN 0x14
1130
1131MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1132
1133/* reg_sfdf_swid
1134 * Switch partition ID.
1135 * Access: Index
1136 */
1137MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1138
1139enum mlxsw_reg_sfdf_flush_type {
1140 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1141 MLXSW_REG_SFDF_FLUSH_PER_FID,
1142 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1143 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1144 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1145 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1146 MLXSW_REG_SFDF_FLUSH_PER_NVE,
1147 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1148};
1149
1150/* reg_sfdf_flush_type
1151 * Flush type.
1152 * 0 - All SWID dynamic entries are flushed.
1153 * 1 - All FID dynamic entries are flushed.
1154 * 2 - All dynamic entries pointing to port are flushed.
1155 * 3 - All FID dynamic entries pointing to port are flushed.
1156 * 4 - All dynamic entries pointing to LAG are flushed.
1157 * 5 - All FID dynamic entries pointing to LAG are flushed.
1158 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1159 * flushed.
1160 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1161 * flushed, per FID.
1162 * Access: RW
1163 */
1164MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1165
1166/* reg_sfdf_flush_static
1167 * Static.
1168 * 0 - Flush only dynamic entries.
1169 * 1 - Flush both dynamic and static entries.
1170 * Access: RW
1171 */
1172MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1173
1174static inline void mlxsw_reg_sfdf_pack(char *payload,
1175 enum mlxsw_reg_sfdf_flush_type type)
1176{
1177 MLXSW_REG_ZERO(sfdf, payload);
1178 mlxsw_reg_sfdf_flush_type_set(buf: payload, val: type);
1179 mlxsw_reg_sfdf_flush_static_set(buf: payload, val: true);
1180}
1181
1182/* reg_sfdf_fid
1183 * FID to flush.
1184 * Access: RW
1185 */
1186MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1187
1188/* reg_sfdf_system_port
1189 * Port to flush.
1190 * Access: RW
1191 */
1192MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1193
1194/* reg_sfdf_port_fid_system_port
1195 * Port to flush, pointed to by FID.
1196 * Access: RW
1197 */
1198MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1199
1200/* reg_sfdf_lag_id
1201 * LAG ID to flush.
1202 * Access: RW
1203 */
1204MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1205
1206/* reg_sfdf_lag_fid_lag_id
1207 * LAG ID to flush, pointed to by FID.
1208 * Access: RW
1209 */
1210MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1211
1212/* SLDR - Switch LAG Descriptor Register
1213 * -----------------------------------------
1214 * The switch LAG descriptor register is populated by LAG descriptors.
1215 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1216 * max_lag-1.
1217 */
1218#define MLXSW_REG_SLDR_ID 0x2014
1219#define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1220
1221MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1222
1223enum mlxsw_reg_sldr_op {
1224 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1225 MLXSW_REG_SLDR_OP_LAG_CREATE,
1226 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1227 /* Ports that appear in the list have the Distributor enabled */
1228 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1229 /* Removes ports from the disributor list */
1230 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1231};
1232
1233/* reg_sldr_op
1234 * Operation.
1235 * Access: RW
1236 */
1237MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1238
1239/* reg_sldr_lag_id
1240 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1241 * Access: Index
1242 */
1243MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1244
1245static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1246{
1247 MLXSW_REG_ZERO(sldr, payload);
1248 mlxsw_reg_sldr_op_set(buf: payload, val: MLXSW_REG_SLDR_OP_LAG_CREATE);
1249 mlxsw_reg_sldr_lag_id_set(buf: payload, val: lag_id);
1250}
1251
1252static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1253{
1254 MLXSW_REG_ZERO(sldr, payload);
1255 mlxsw_reg_sldr_op_set(buf: payload, val: MLXSW_REG_SLDR_OP_LAG_DESTROY);
1256 mlxsw_reg_sldr_lag_id_set(buf: payload, val: lag_id);
1257}
1258
1259/* reg_sldr_num_ports
1260 * The number of member ports of the LAG.
1261 * Reserved for Create / Destroy operations
1262 * For Add / Remove operations - indicates the number of ports in the list.
1263 * Access: RW
1264 */
1265MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1266
1267/* reg_sldr_system_port
1268 * System port.
1269 * Access: RW
1270 */
1271MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1272
1273static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1274 u16 local_port)
1275{
1276 MLXSW_REG_ZERO(sldr, payload);
1277 mlxsw_reg_sldr_op_set(buf: payload, val: MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1278 mlxsw_reg_sldr_lag_id_set(buf: payload, val: lag_id);
1279 mlxsw_reg_sldr_num_ports_set(buf: payload, val: 1);
1280 mlxsw_reg_sldr_system_port_set(buf: payload, index: 0, val: local_port);
1281}
1282
1283static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1284 u16 local_port)
1285{
1286 MLXSW_REG_ZERO(sldr, payload);
1287 mlxsw_reg_sldr_op_set(buf: payload, val: MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1288 mlxsw_reg_sldr_lag_id_set(buf: payload, val: lag_id);
1289 mlxsw_reg_sldr_num_ports_set(buf: payload, val: 1);
1290 mlxsw_reg_sldr_system_port_set(buf: payload, index: 0, val: local_port);
1291}
1292
1293/* SLCR - Switch LAG Configuration 2 Register
1294 * -------------------------------------------
1295 * The Switch LAG Configuration register is used for configuring the
1296 * LAG properties of the switch.
1297 */
1298#define MLXSW_REG_SLCR_ID 0x2015
1299#define MLXSW_REG_SLCR_LEN 0x10
1300
1301MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1302
1303enum mlxsw_reg_slcr_pp {
1304 /* Global Configuration (for all ports) */
1305 MLXSW_REG_SLCR_PP_GLOBAL,
1306 /* Per port configuration, based on local_port field */
1307 MLXSW_REG_SLCR_PP_PER_PORT,
1308};
1309
1310/* reg_slcr_pp
1311 * Per Port Configuration
1312 * Note: Reading at Global mode results in reading port 1 configuration.
1313 * Access: Index
1314 */
1315MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1316
1317/* reg_slcr_local_port
1318 * Local port number
1319 * Supported from CPU port
1320 * Not supported from router port
1321 * Reserved when pp = Global Configuration
1322 * Access: Index
1323 */
1324MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12);
1325
1326enum mlxsw_reg_slcr_type {
1327 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1328 MLXSW_REG_SLCR_TYPE_XOR,
1329 MLXSW_REG_SLCR_TYPE_RANDOM,
1330};
1331
1332/* reg_slcr_type
1333 * Hash type
1334 * Access: RW
1335 */
1336MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1337
1338/* Ingress port */
1339#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1340/* SMAC - for IPv4 and IPv6 packets */
1341#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1342/* SMAC - for non-IP packets */
1343#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1344#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1345 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1346 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1347/* DMAC - for IPv4 and IPv6 packets */
1348#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1349/* DMAC - for non-IP packets */
1350#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1351#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1352 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1353 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1354/* Ethertype - for IPv4 and IPv6 packets */
1355#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1356/* Ethertype - for non-IP packets */
1357#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1358#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1359 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1360 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1361/* VLAN ID - for IPv4 and IPv6 packets */
1362#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1363/* VLAN ID - for non-IP packets */
1364#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1365#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1366 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1367 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1368/* Source IP address (can be IPv4 or IPv6) */
1369#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1370/* Destination IP address (can be IPv4 or IPv6) */
1371#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1372/* TCP/UDP source port */
1373#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1374/* TCP/UDP destination port*/
1375#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1376/* IPv4 Protocol/IPv6 Next Header */
1377#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1378/* IPv6 Flow label */
1379#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1380/* SID - FCoE source ID */
1381#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1382/* DID - FCoE destination ID */
1383#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1384/* OXID - FCoE originator exchange ID */
1385#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1386/* Destination QP number - for RoCE packets */
1387#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1388
1389/* reg_slcr_lag_hash
1390 * LAG hashing configuration. This is a bitmask, in which each set
1391 * bit includes the corresponding item in the LAG hash calculation.
1392 * The default lag_hash contains SMAC, DMAC, VLANID and
1393 * Ethertype (for all packet types).
1394 * Access: RW
1395 */
1396MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1397
1398/* reg_slcr_seed
1399 * LAG seed value. The seed is the same for all ports.
1400 * Access: RW
1401 */
1402MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1403
1404static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1405{
1406 MLXSW_REG_ZERO(slcr, payload);
1407 mlxsw_reg_slcr_pp_set(buf: payload, val: MLXSW_REG_SLCR_PP_GLOBAL);
1408 mlxsw_reg_slcr_type_set(buf: payload, val: MLXSW_REG_SLCR_TYPE_CRC);
1409 mlxsw_reg_slcr_lag_hash_set(buf: payload, val: lag_hash);
1410 mlxsw_reg_slcr_seed_set(buf: payload, val: seed);
1411}
1412
1413/* SLCOR - Switch LAG Collector Register
1414 * -------------------------------------
1415 * The Switch LAG Collector register controls the Local Port membership
1416 * in a LAG and enablement of the collector.
1417 */
1418#define MLXSW_REG_SLCOR_ID 0x2016
1419#define MLXSW_REG_SLCOR_LEN 0x10
1420
1421MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1422
1423enum mlxsw_reg_slcor_col {
1424 /* Port is added with collector disabled */
1425 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1426 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1427 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1428 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1429};
1430
1431/* reg_slcor_col
1432 * Collector configuration
1433 * Access: RW
1434 */
1435MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1436
1437/* reg_slcor_local_port
1438 * Local port number
1439 * Not supported for CPU port
1440 * Access: Index
1441 */
1442MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12);
1443
1444/* reg_slcor_lag_id
1445 * LAG Identifier. Index into the LAG descriptor table.
1446 * Access: Index
1447 */
1448MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1449
1450/* reg_slcor_port_index
1451 * Port index in the LAG list. Only valid on Add Port to LAG col.
1452 * Valid range is from 0 to cap_max_lag_members-1
1453 * Access: RW
1454 */
1455MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1456
1457static inline void mlxsw_reg_slcor_pack(char *payload,
1458 u16 local_port, u16 lag_id,
1459 enum mlxsw_reg_slcor_col col)
1460{
1461 MLXSW_REG_ZERO(slcor, payload);
1462 mlxsw_reg_slcor_col_set(buf: payload, val: col);
1463 mlxsw_reg_slcor_local_port_set(buf: payload, val: local_port);
1464 mlxsw_reg_slcor_lag_id_set(buf: payload, val: lag_id);
1465}
1466
1467static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1468 u16 local_port, u16 lag_id,
1469 u8 port_index)
1470{
1471 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1472 col: MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1473 mlxsw_reg_slcor_port_index_set(buf: payload, val: port_index);
1474}
1475
1476static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1477 u16 local_port, u16 lag_id)
1478{
1479 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1480 col: MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1481}
1482
1483static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1484 u16 local_port, u16 lag_id)
1485{
1486 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1487 col: MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1488}
1489
1490static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1491 u16 local_port, u16 lag_id)
1492{
1493 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1494 col: MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1495}
1496
1497/* SPMLR - Switch Port MAC Learning Register
1498 * -----------------------------------------
1499 * Controls the Switch MAC learning policy per port.
1500 */
1501#define MLXSW_REG_SPMLR_ID 0x2018
1502#define MLXSW_REG_SPMLR_LEN 0x8
1503
1504MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1505
1506/* reg_spmlr_local_port
1507 * Local port number.
1508 * Access: Index
1509 */
1510MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12);
1511
1512/* reg_spmlr_sub_port
1513 * Virtual port within the physical port.
1514 * Should be set to 0 when virtual ports are not enabled on the port.
1515 * Access: Index
1516 */
1517MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1518
1519enum mlxsw_reg_spmlr_learn_mode {
1520 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1521 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1522 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1523};
1524
1525/* reg_spmlr_learn_mode
1526 * Learning mode on the port.
1527 * 0 - Learning disabled.
1528 * 2 - Learning enabled.
1529 * 3 - Security mode.
1530 *
1531 * In security mode the switch does not learn MACs on the port, but uses the
1532 * SMAC to see if it exists on another ingress port. If so, the packet is
1533 * classified as a bad packet and is discarded unless the software registers
1534 * to receive port security error packets usign HPKT.
1535 */
1536MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1537
1538static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port,
1539 enum mlxsw_reg_spmlr_learn_mode mode)
1540{
1541 MLXSW_REG_ZERO(spmlr, payload);
1542 mlxsw_reg_spmlr_local_port_set(buf: payload, val: local_port);
1543 mlxsw_reg_spmlr_sub_port_set(buf: payload, val: 0);
1544 mlxsw_reg_spmlr_learn_mode_set(buf: payload, val: mode);
1545}
1546
1547/* SVFA - Switch VID to FID Allocation Register
1548 * --------------------------------------------
1549 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1550 * virtualized ports.
1551 */
1552#define MLXSW_REG_SVFA_ID 0x201C
1553#define MLXSW_REG_SVFA_LEN 0x18
1554
1555MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1556
1557/* reg_svfa_swid
1558 * Switch partition ID.
1559 * Access: Index
1560 */
1561MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1562
1563/* reg_svfa_local_port
1564 * Local port number.
1565 * Access: Index
1566 *
1567 * Note: Reserved for 802.1Q FIDs.
1568 */
1569MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12);
1570
1571enum mlxsw_reg_svfa_mt {
1572 MLXSW_REG_SVFA_MT_VID_TO_FID,
1573 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1574 MLXSW_REG_SVFA_MT_VNI_TO_FID,
1575};
1576
1577/* reg_svfa_mapping_table
1578 * Mapping table:
1579 * 0 - VID to FID
1580 * 1 - {Port, VID} to FID
1581 * Access: Index
1582 *
1583 * Note: Reserved for SwitchX-2.
1584 */
1585MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1586
1587/* reg_svfa_v
1588 * Valid.
1589 * Valid if set.
1590 * Access: RW
1591 *
1592 * Note: Reserved for SwitchX-2.
1593 */
1594MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1595
1596/* reg_svfa_fid
1597 * Filtering ID.
1598 * Access: RW
1599 */
1600MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1601
1602/* reg_svfa_vid
1603 * VLAN ID.
1604 * Access: Index
1605 */
1606MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1607
1608/* reg_svfa_counter_set_type
1609 * Counter set type for flow counters.
1610 * Access: RW
1611 *
1612 * Note: Reserved for SwitchX-2.
1613 */
1614MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1615
1616/* reg_svfa_counter_index
1617 * Counter index for flow counters.
1618 * Access: RW
1619 *
1620 * Note: Reserved for SwitchX-2.
1621 */
1622MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1623
1624/* reg_svfa_vni
1625 * Virtual Network Identifier.
1626 * Access: Index
1627 *
1628 * Note: Reserved when mapping_table is not 2 (VNI mapping table).
1629 */
1630MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24);
1631
1632/* reg_svfa_irif_v
1633 * Ingress RIF valid.
1634 * 0 - Ingress RIF is not valid, no ingress RIF assigned.
1635 * 1 - Ingress RIF valid.
1636 * Must not be set for a non enabled RIF.
1637 * Access: RW
1638 *
1639 * Note: Reserved when legacy bridge model is used.
1640 */
1641MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1);
1642
1643/* reg_svfa_irif
1644 * Ingress RIF (Router Interface).
1645 * Range is 0..cap_max_router_interfaces-1.
1646 * Access: RW
1647 *
1648 * Note: Reserved when legacy bridge model is used and when irif_v=0.
1649 */
1650MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16);
1651
1652static inline void __mlxsw_reg_svfa_pack(char *payload,
1653 enum mlxsw_reg_svfa_mt mt, bool valid,
1654 u16 fid, bool irif_v, u16 irif)
1655{
1656 MLXSW_REG_ZERO(svfa, payload);
1657 mlxsw_reg_svfa_swid_set(buf: payload, val: 0);
1658 mlxsw_reg_svfa_mapping_table_set(buf: payload, val: mt);
1659 mlxsw_reg_svfa_v_set(buf: payload, val: valid);
1660 mlxsw_reg_svfa_fid_set(buf: payload, val: fid);
1661 mlxsw_reg_svfa_irif_v_set(buf: payload, val: irif_v);
1662 mlxsw_reg_svfa_irif_set(buf: payload, val: irif_v ? irif : 0);
1663}
1664
1665static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port,
1666 bool valid, u16 fid, u16 vid,
1667 bool irif_v, u16 irif)
1668{
1669 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1670
1671 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);
1672 mlxsw_reg_svfa_local_port_set(buf: payload, val: local_port);
1673 mlxsw_reg_svfa_vid_set(buf: payload, val: vid);
1674}
1675
1676static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid,
1677 u16 vid, bool irif_v, u16 irif)
1678{
1679 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID;
1680
1681 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);
1682 mlxsw_reg_svfa_vid_set(buf: payload, val: vid);
1683}
1684
1685static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid,
1686 u32 vni, bool irif_v, u16 irif)
1687{
1688 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID;
1689
1690 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif);
1691 mlxsw_reg_svfa_vni_set(buf: payload, val: vni);
1692}
1693
1694/* SPVTR - Switch Port VLAN Stacking Register
1695 * ------------------------------------------
1696 * The Switch Port VLAN Stacking register configures the VLAN mode of the port
1697 * to enable VLAN stacking.
1698 */
1699#define MLXSW_REG_SPVTR_ID 0x201D
1700#define MLXSW_REG_SPVTR_LEN 0x10
1701
1702MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN);
1703
1704/* reg_spvtr_tport
1705 * Port is tunnel port.
1706 * Access: Index
1707 *
1708 * Note: Reserved when SwitchX/-2 or Spectrum-1.
1709 */
1710MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1);
1711
1712/* reg_spvtr_local_port
1713 * When tport = 0: local port number (Not supported from/to CPU).
1714 * When tport = 1: tunnel port.
1715 * Access: Index
1716 */
1717MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12);
1718
1719/* reg_spvtr_ippe
1720 * Ingress Port Prio Mode Update Enable.
1721 * When set, the Port Prio Mode is updated with the provided ipprio_mode field.
1722 * Reserved on Get operations.
1723 * Access: OP
1724 */
1725MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1);
1726
1727/* reg_spvtr_ipve
1728 * Ingress Port VID Mode Update Enable.
1729 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode
1730 * field.
1731 * Reserved on Get operations.
1732 * Access: OP
1733 */
1734MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1);
1735
1736/* reg_spvtr_epve
1737 * Egress Port VID Mode Update Enable.
1738 * When set, the Egress Port VID Mode is updated with the provided epvid_mode
1739 * field.
1740 * Access: OP
1741 */
1742MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1);
1743
1744/* reg_spvtr_ipprio_mode
1745 * Ingress Port Priority Mode.
1746 * This controls the PCP and DEI of the new outer VLAN
1747 * Note: for SwitchX/-2 the DEI is not affected.
1748 * 0: use port default PCP and DEI (configured by QPDPC).
1749 * 1: use C-VLAN PCP and DEI.
1750 * Has no effect when ipvid_mode = 0.
1751 * Reserved when tport = 1.
1752 * Access: RW
1753 */
1754MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4);
1755
1756enum mlxsw_reg_spvtr_ipvid_mode {
1757 /* IEEE Compliant PVID (default) */
1758 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID,
1759 /* Push VLAN (for VLAN stacking, except prio tagged packets) */
1760 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET,
1761 /* Always push VLAN (also for prio tagged packets) */
1762 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN,
1763};
1764
1765/* reg_spvtr_ipvid_mode
1766 * Ingress Port VLAN-ID Mode.
1767 * For Spectrum family, this affects the values of SPVM.i
1768 * Access: RW
1769 */
1770MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4);
1771
1772enum mlxsw_reg_spvtr_epvid_mode {
1773 /* IEEE Compliant VLAN membership */
1774 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP,
1775 /* Pop VLAN (for VLAN stacking) */
1776 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN,
1777};
1778
1779/* reg_spvtr_epvid_mode
1780 * Egress Port VLAN-ID Mode.
1781 * For Spectrum family, this affects the values of SPVM.e,u,pt.
1782 * Access: WO
1783 */
1784MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4);
1785
1786static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport,
1787 u16 local_port,
1788 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode)
1789{
1790 MLXSW_REG_ZERO(spvtr, payload);
1791 mlxsw_reg_spvtr_tport_set(buf: payload, val: tport);
1792 mlxsw_reg_spvtr_local_port_set(buf: payload, val: local_port);
1793 mlxsw_reg_spvtr_ipvid_mode_set(buf: payload, val: ipvid_mode);
1794 mlxsw_reg_spvtr_ipve_set(buf: payload, val: true);
1795}
1796
1797/* SVPE - Switch Virtual-Port Enabling Register
1798 * --------------------------------------------
1799 * Enables port virtualization.
1800 */
1801#define MLXSW_REG_SVPE_ID 0x201E
1802#define MLXSW_REG_SVPE_LEN 0x4
1803
1804MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1805
1806/* reg_svpe_local_port
1807 * Local port number
1808 * Access: Index
1809 *
1810 * Note: CPU port is not supported (uses VLAN mode only).
1811 */
1812MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12);
1813
1814/* reg_svpe_vp_en
1815 * Virtual port enable.
1816 * 0 - Disable, VLAN mode (VID to FID).
1817 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1818 * Access: RW
1819 */
1820MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1821
1822static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port,
1823 bool enable)
1824{
1825 MLXSW_REG_ZERO(svpe, payload);
1826 mlxsw_reg_svpe_local_port_set(buf: payload, val: local_port);
1827 mlxsw_reg_svpe_vp_en_set(buf: payload, val: enable);
1828}
1829
1830/* SFMR - Switch FID Management Register
1831 * -------------------------------------
1832 * Creates and configures FIDs.
1833 */
1834#define MLXSW_REG_SFMR_ID 0x201F
1835#define MLXSW_REG_SFMR_LEN 0x30
1836
1837MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1838
1839enum mlxsw_reg_sfmr_op {
1840 MLXSW_REG_SFMR_OP_CREATE_FID,
1841 MLXSW_REG_SFMR_OP_DESTROY_FID,
1842};
1843
1844/* reg_sfmr_op
1845 * Operation.
1846 * 0 - Create or edit FID.
1847 * 1 - Destroy FID.
1848 * Access: WO
1849 */
1850MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1851
1852/* reg_sfmr_fid
1853 * Filtering ID.
1854 * Access: Index
1855 */
1856MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1857
1858/* reg_sfmr_flood_rsp
1859 * Router sub-port flooding table.
1860 * 0 - Regular flooding table.
1861 * 1 - Router sub-port flooding table. For this FID the flooding is per
1862 * router-sub-port local_port. Must not be set for a FID which is not a
1863 * router-sub-port and must be set prior to enabling the relevant RIF.
1864 * Access: RW
1865 *
1866 * Note: Reserved when legacy bridge model is used.
1867 * Reserved when CONFIG_PROFILE.flood_mode = CFF.
1868 */
1869MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1);
1870
1871/* reg_sfmr_flood_bridge_type
1872 * Flood bridge type (see SFGC.bridge_type).
1873 * 0 - type_0.
1874 * 1 - type_1.
1875 * Access: RW
1876 *
1877 * Note: Reserved when legacy bridge model is used and when flood_rsp=1.
1878 * Reserved when CONFIG_PROFILE.flood_mode = CFF
1879 */
1880MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1);
1881
1882/* reg_sfmr_fid_offset
1883 * FID offset.
1884 * Used to point into the flooding table selected by SFGC register if
1885 * the table is of type FID-Offset. Otherwise, this field is reserved.
1886 * Access: RW
1887 *
1888 * Note: Reserved when CONFIG_PROFILE.flood_mode = CFF
1889 */
1890MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1891
1892/* reg_sfmr_vtfp
1893 * Valid Tunnel Flood Pointer.
1894 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1895 * Access: RW
1896 *
1897 * Note: Reserved for 802.1Q FIDs.
1898 */
1899MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1900
1901/* reg_sfmr_nve_tunnel_flood_ptr
1902 * Underlay Flooding and BC Pointer.
1903 * Used as a pointer to the first entry of the group based link lists of
1904 * flooding or BC entries (for NVE tunnels).
1905 * Access: RW
1906 */
1907MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1908
1909/* reg_sfmr_vv
1910 * VNI Valid.
1911 * If not set, then vni is reserved.
1912 * Access: RW
1913 *
1914 * Note: Reserved for 802.1Q FIDs.
1915 */
1916MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1917
1918/* reg_sfmr_vni
1919 * Virtual Network Identifier.
1920 * When legacy bridge model is used, a given VNI can only be assigned to one
1921 * FID. When unified bridge model is used, it configures only the FID->VNI,
1922 * the VNI->FID is done by SVFA.
1923 * Access: RW
1924 */
1925MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1926
1927/* reg_sfmr_irif_v
1928 * Ingress RIF valid.
1929 * 0 - Ingress RIF is not valid, no ingress RIF assigned.
1930 * 1 - Ingress RIF valid.
1931 * Must not be set for a non valid RIF.
1932 * Access: RW
1933 *
1934 * Note: Reserved when legacy bridge model is used.
1935 */
1936MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1);
1937
1938/* reg_sfmr_irif
1939 * Ingress RIF (Router Interface).
1940 * Range is 0..cap_max_router_interfaces-1.
1941 * Access: RW
1942 *
1943 * Note: Reserved when legacy bridge model is used and when irif_v=0.
1944 */
1945MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16);
1946
1947/* reg_sfmr_cff_mid_base
1948 * Pointer to PGT table.
1949 * Range: 0..(cap_max_pgt-1)
1950 * Access: RW
1951 *
1952 * Note: Reserved when SwitchX/-2 and Spectrum-1.
1953 * Supported when CONFIG_PROFILE.flood_mode = CFF.
1954 */
1955MLXSW_ITEM32(reg, sfmr, cff_mid_base, 0x20, 0, 16);
1956
1957/* reg_sfmr_nve_flood_prf_id
1958 * FID flooding profile_id for NVE Encap
1959 * Range 0..(max_cap_nve_flood_prf-1)
1960 * Access: RW
1961 *
1962 * Note: Reserved when SwitchX/-2 and Spectrum-1
1963 */
1964MLXSW_ITEM32(reg, sfmr, nve_flood_prf_id, 0x24, 8, 2);
1965
1966/* reg_sfmr_cff_prf_id
1967 * Compressed Fid Flooding profile_id
1968 * Range 0..(max_cap_nve_flood_prf-1)
1969 * Access: RW
1970 *
1971 * Note: Reserved when SwitchX/-2 and Spectrum-1
1972 * Supported only when CONFIG_PROFLE.flood_mode = CFF.
1973 */
1974MLXSW_ITEM32(reg, sfmr, cff_prf_id, 0x24, 0, 2);
1975
1976/* reg_sfmr_smpe_valid
1977 * SMPE is valid.
1978 * Access: RW
1979 *
1980 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on
1981 * Spectrum-1.
1982 */
1983MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1);
1984
1985/* reg_sfmr_smpe
1986 * Switch multicast port to egress VID.
1987 * Range is 0..cap_max_rmpe-1
1988 * Access: RW
1989 *
1990 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on
1991 * Spectrum-1.
1992 */
1993MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16);
1994
1995static inline void mlxsw_reg_sfmr_pack(char *payload,
1996 enum mlxsw_reg_sfmr_op op, u16 fid,
1997 bool smpe_valid, u16 smpe)
1998{
1999 MLXSW_REG_ZERO(sfmr, payload);
2000 mlxsw_reg_sfmr_op_set(buf: payload, val: op);
2001 mlxsw_reg_sfmr_fid_set(buf: payload, val: fid);
2002 mlxsw_reg_sfmr_smpe_valid_set(buf: payload, val: smpe_valid);
2003 mlxsw_reg_sfmr_smpe_set(buf: payload, val: smpe);
2004}
2005
2006/* SPVMLR - Switch Port VLAN MAC Learning Register
2007 * -----------------------------------------------
2008 * Controls the switch MAC learning policy per {Port, VID}.
2009 */
2010#define MLXSW_REG_SPVMLR_ID 0x2020
2011#define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
2012#define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
2013#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
2014#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
2015 MLXSW_REG_SPVMLR_REC_LEN * \
2016 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
2017
2018MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
2019
2020/* reg_spvmlr_local_port
2021 * Local ingress port.
2022 * Access: Index
2023 *
2024 * Note: CPU port is not supported.
2025 */
2026MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12);
2027
2028/* reg_spvmlr_num_rec
2029 * Number of records to update.
2030 * Access: OP
2031 */
2032MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
2033
2034/* reg_spvmlr_rec_learn_enable
2035 * 0 - Disable learning for {Port, VID}.
2036 * 1 - Enable learning for {Port, VID}.
2037 * Access: RW
2038 */
2039MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
2040 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
2041
2042/* reg_spvmlr_rec_vid
2043 * VLAN ID to be added/removed from port or for querying.
2044 * Access: Index
2045 */
2046MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
2047 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
2048
2049static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port,
2050 u16 vid_begin, u16 vid_end,
2051 bool learn_enable)
2052{
2053 int num_rec = vid_end - vid_begin + 1;
2054 int i;
2055
2056 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
2057
2058 MLXSW_REG_ZERO(spvmlr, payload);
2059 mlxsw_reg_spvmlr_local_port_set(buf: payload, val: local_port);
2060 mlxsw_reg_spvmlr_num_rec_set(buf: payload, val: num_rec);
2061
2062 for (i = 0; i < num_rec; i++) {
2063 mlxsw_reg_spvmlr_rec_learn_enable_set(buf: payload, index: i, val: learn_enable);
2064 mlxsw_reg_spvmlr_rec_vid_set(buf: payload, index: i, val: vid_begin + i);
2065 }
2066}
2067
2068/* SPFSR - Switch Port FDB Security Register
2069 * -----------------------------------------
2070 * Configures the security mode per port.
2071 */
2072#define MLXSW_REG_SPFSR_ID 0x2023
2073#define MLXSW_REG_SPFSR_LEN 0x08
2074
2075MLXSW_REG_DEFINE(spfsr, MLXSW_REG_SPFSR_ID, MLXSW_REG_SPFSR_LEN);
2076
2077/* reg_spfsr_local_port
2078 * Local port.
2079 * Access: Index
2080 *
2081 * Note: not supported for CPU port.
2082 */
2083MLXSW_ITEM32_LP(reg, spfsr, 0x00, 16, 0x00, 12);
2084
2085/* reg_spfsr_security
2086 * Security checks.
2087 * 0: disabled (default)
2088 * 1: enabled
2089 * Access: RW
2090 */
2091MLXSW_ITEM32(reg, spfsr, security, 0x04, 31, 1);
2092
2093static inline void mlxsw_reg_spfsr_pack(char *payload, u16 local_port,
2094 bool security)
2095{
2096 MLXSW_REG_ZERO(spfsr, payload);
2097 mlxsw_reg_spfsr_local_port_set(buf: payload, val: local_port);
2098 mlxsw_reg_spfsr_security_set(buf: payload, val: security);
2099}
2100
2101/* SPVC - Switch Port VLAN Classification Register
2102 * -----------------------------------------------
2103 * Configures the port to identify packets as untagged / single tagged /
2104 * double packets based on the packet EtherTypes.
2105 * Ethertype IDs are configured by SVER.
2106 */
2107#define MLXSW_REG_SPVC_ID 0x2026
2108#define MLXSW_REG_SPVC_LEN 0x0C
2109
2110MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN);
2111
2112/* reg_spvc_local_port
2113 * Local port.
2114 * Access: Index
2115 *
2116 * Note: applies both to Rx port and Tx port, so if a packet traverses
2117 * through Rx port i and a Tx port j then port i and port j must have the
2118 * same configuration.
2119 */
2120MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12);
2121
2122/* reg_spvc_inner_et2
2123 * Vlan Tag1 EtherType2 enable.
2124 * Packet is initially classified as double VLAN Tag if in addition to
2125 * being classified with a tag0 VLAN Tag its tag1 EtherType value is
2126 * equal to ether_type2.
2127 * 0: disable (default)
2128 * 1: enable
2129 * Access: RW
2130 */
2131MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1);
2132
2133/* reg_spvc_et2
2134 * Vlan Tag0 EtherType2 enable.
2135 * Packet is initially classified as VLAN Tag if its tag0 EtherType is
2136 * equal to ether_type2.
2137 * 0: disable (default)
2138 * 1: enable
2139 * Access: RW
2140 */
2141MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1);
2142
2143/* reg_spvc_inner_et1
2144 * Vlan Tag1 EtherType1 enable.
2145 * Packet is initially classified as double VLAN Tag if in addition to
2146 * being classified with a tag0 VLAN Tag its tag1 EtherType value is
2147 * equal to ether_type1.
2148 * 0: disable
2149 * 1: enable (default)
2150 * Access: RW
2151 */
2152MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1);
2153
2154/* reg_spvc_et1
2155 * Vlan Tag0 EtherType1 enable.
2156 * Packet is initially classified as VLAN Tag if its tag0 EtherType is
2157 * equal to ether_type1.
2158 * 0: disable
2159 * 1: enable (default)
2160 * Access: RW
2161 */
2162MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1);
2163
2164/* reg_inner_et0
2165 * Vlan Tag1 EtherType0 enable.
2166 * Packet is initially classified as double VLAN Tag if in addition to
2167 * being classified with a tag0 VLAN Tag its tag1 EtherType value is
2168 * equal to ether_type0.
2169 * 0: disable
2170 * 1: enable (default)
2171 * Access: RW
2172 */
2173MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1);
2174
2175/* reg_et0
2176 * Vlan Tag0 EtherType0 enable.
2177 * Packet is initially classified as VLAN Tag if its tag0 EtherType is
2178 * equal to ether_type0.
2179 * 0: disable
2180 * 1: enable (default)
2181 * Access: RW
2182 */
2183MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);
2184
2185static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1,
2186 bool et0)
2187{
2188 MLXSW_REG_ZERO(spvc, payload);
2189 mlxsw_reg_spvc_local_port_set(buf: payload, val: local_port);
2190 /* Enable inner_et1 and inner_et0 to enable identification of double
2191 * tagged packets.
2192 */
2193 mlxsw_reg_spvc_inner_et1_set(buf: payload, val: 1);
2194 mlxsw_reg_spvc_inner_et0_set(buf: payload, val: 1);
2195 mlxsw_reg_spvc_et1_set(buf: payload, val: et1);
2196 mlxsw_reg_spvc_et0_set(buf: payload, val: et0);
2197}
2198
2199/* SFFP - Switch FID Flooding Profiles Register
2200 * --------------------------------------------
2201 * The SFFP register populates the fid flooding profile tables used for the NVE
2202 * flooding and Compressed-FID Flooding (CFF).
2203 *
2204 * Reserved on Spectrum-1.
2205 */
2206#define MLXSW_REG_SFFP_ID 0x2029
2207#define MLXSW_REG_SFFP_LEN 0x0C
2208
2209MLXSW_REG_DEFINE(sffp, MLXSW_REG_SFFP_ID, MLXSW_REG_SFFP_LEN);
2210
2211/* reg_sffp_profile_id
2212 * Profile ID a.k.a. SFMR.nve_flood_prf_id or SFMR.cff_prf_id
2213 * Range 0..max_cap_nve_flood_prf-1
2214 * Access: Index
2215 */
2216MLXSW_ITEM32(reg, sffp, profile_id, 0x00, 16, 2);
2217
2218/* reg_sffp_type
2219 * The traffic type to reach the flooding table.
2220 * Same as SFGC.type
2221 * Access: Index
2222 */
2223MLXSW_ITEM32(reg, sffp, type, 0x00, 0, 4);
2224
2225/* reg_sffp_flood_offset
2226 * Flood offset. Offset to add to SFMR.cff_mid_base to get the final PGT address
2227 * for FID flood; or offset to add to SFMR.nve_tunnel_flood_ptr to get KVD
2228 * pointer for NVE underlay.
2229 * Access: RW
2230 */
2231MLXSW_ITEM32(reg, sffp, flood_offset, 0x04, 0, 3);
2232
2233static inline void mlxsw_reg_sffp_pack(char *payload, u8 profile_id,
2234 enum mlxsw_reg_sfgc_type type,
2235 u8 flood_offset)
2236{
2237 MLXSW_REG_ZERO(sffp, payload);
2238 mlxsw_reg_sffp_profile_id_set(buf: payload, val: profile_id);
2239 mlxsw_reg_sffp_type_set(buf: payload, val: type);
2240 mlxsw_reg_sffp_flood_offset_set(buf: payload, val: flood_offset);
2241}
2242
2243/* SPEVET - Switch Port Egress VLAN EtherType
2244 * ------------------------------------------
2245 * The switch port egress VLAN EtherType configures which EtherType to push at
2246 * egress for packets incoming through a local port for which 'SPVID.egr_et_set'
2247 * is set.
2248 */
2249#define MLXSW_REG_SPEVET_ID 0x202A
2250#define MLXSW_REG_SPEVET_LEN 0x08
2251
2252MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN);
2253
2254/* reg_spevet_local_port
2255 * Egress Local port number.
2256 * Not supported to CPU port.
2257 * Access: Index
2258 */
2259MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12);
2260
2261/* reg_spevet_et_vlan
2262 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet:
2263 * 0: ether_type0 - (default)
2264 * 1: ether_type1
2265 * 2: ether_type2
2266 * Access: RW
2267 */
2268MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2);
2269
2270static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port,
2271 u8 et_vlan)
2272{
2273 MLXSW_REG_ZERO(spevet, payload);
2274 mlxsw_reg_spevet_local_port_set(buf: payload, val: local_port);
2275 mlxsw_reg_spevet_et_vlan_set(buf: payload, val: et_vlan);
2276}
2277
2278/* SMPE - Switch Multicast Port to Egress VID
2279 * ------------------------------------------
2280 * The switch multicast port to egress VID maps
2281 * {egress_port, SMPE index} -> {VID}.
2282 */
2283#define MLXSW_REG_SMPE_ID 0x202B
2284#define MLXSW_REG_SMPE_LEN 0x0C
2285
2286MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN);
2287
2288/* reg_smpe_local_port
2289 * Local port number.
2290 * CPU port is not supported.
2291 * Access: Index
2292 */
2293MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12);
2294
2295/* reg_smpe_smpe_index
2296 * Switch multicast port to egress VID.
2297 * Range is 0..cap_max_rmpe-1.
2298 * Access: Index
2299 */
2300MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16);
2301
2302/* reg_smpe_evid
2303 * Egress VID.
2304 * Access: RW
2305 */
2306MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12);
2307
2308static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port,
2309 u16 smpe_index, u16 evid)
2310{
2311 MLXSW_REG_ZERO(smpe, payload);
2312 mlxsw_reg_smpe_local_port_set(buf: payload, val: local_port);
2313 mlxsw_reg_smpe_smpe_index_set(buf: payload, val: smpe_index);
2314 mlxsw_reg_smpe_evid_set(buf: payload, val: evid);
2315}
2316
2317/* SMID-V2 - Switch Multicast ID Version 2 Register
2318 * ------------------------------------------------
2319 * The MID record maps from a MID (Multicast ID), which is a unique identifier
2320 * of the multicast group within the stacking domain, into a list of local
2321 * ports into which the packet is replicated.
2322 */
2323#define MLXSW_REG_SMID2_ID 0x2034
2324#define MLXSW_REG_SMID2_LEN 0x120
2325
2326MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN);
2327
2328/* reg_smid2_swid
2329 * Switch partition ID.
2330 * Access: Index
2331 */
2332MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8);
2333
2334/* reg_smid2_mid
2335 * Multicast identifier - global identifier that represents the multicast group
2336 * across all devices.
2337 * Access: Index
2338 */
2339MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16);
2340
2341/* reg_smid2_smpe_valid
2342 * SMPE is valid.
2343 * When not valid, the egress VID will not be modified by the SMPE table.
2344 * Access: RW
2345 *
2346 * Note: Reserved when legacy bridge model is used and on Spectrum-2.
2347 */
2348MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1);
2349
2350/* reg_smid2_smpe
2351 * Switch multicast port to egress VID.
2352 * Access: RW
2353 *
2354 * Note: Reserved when legacy bridge model is used and on Spectrum-2.
2355 */
2356MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16);
2357
2358/* reg_smid2_port
2359 * Local port memebership (1 bit per port).
2360 * Access: RW
2361 */
2362MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1);
2363
2364/* reg_smid2_port_mask
2365 * Local port mask (1 bit per port).
2366 * Access: WO
2367 */
2368MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1);
2369
2370static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port,
2371 bool set, bool smpe_valid, u16 smpe)
2372{
2373 MLXSW_REG_ZERO(smid2, payload);
2374 mlxsw_reg_smid2_swid_set(buf: payload, val: 0);
2375 mlxsw_reg_smid2_mid_set(buf: payload, val: mid);
2376 mlxsw_reg_smid2_port_set(buf: payload, index: port, val: set);
2377 mlxsw_reg_smid2_port_mask_set(buf: payload, index: port, val: 1);
2378 mlxsw_reg_smid2_smpe_valid_set(buf: payload, val: smpe_valid);
2379 mlxsw_reg_smid2_smpe_set(buf: payload, val: smpe_valid ? smpe : 0);
2380}
2381
2382/* CWTP - Congetion WRED ECN TClass Profile
2383 * ----------------------------------------
2384 * Configures the profiles for queues of egress port and traffic class
2385 */
2386#define MLXSW_REG_CWTP_ID 0x2802
2387#define MLXSW_REG_CWTP_BASE_LEN 0x28
2388#define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
2389#define MLXSW_REG_CWTP_LEN 0x40
2390
2391MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
2392
2393/* reg_cwtp_local_port
2394 * Local port number
2395 * Not supported for CPU port
2396 * Access: Index
2397 */
2398MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12);
2399
2400/* reg_cwtp_traffic_class
2401 * Traffic Class to configure
2402 * Access: Index
2403 */
2404MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
2405
2406/* reg_cwtp_profile_min
2407 * Minimum Average Queue Size of the profile in cells.
2408 * Access: RW
2409 */
2410MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
2411 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
2412
2413/* reg_cwtp_profile_percent
2414 * Percentage of WRED and ECN marking for maximum Average Queue size
2415 * Range is 0 to 100, units of integer percentage
2416 * Access: RW
2417 */
2418MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
2419 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2420
2421/* reg_cwtp_profile_max
2422 * Maximum Average Queue size of the profile in cells
2423 * Access: RW
2424 */
2425MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
2426 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2427
2428#define MLXSW_REG_CWTP_MIN_VALUE 64
2429#define MLXSW_REG_CWTP_MAX_PROFILE 2
2430#define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
2431
2432static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port,
2433 u8 traffic_class)
2434{
2435 int i;
2436
2437 MLXSW_REG_ZERO(cwtp, payload);
2438 mlxsw_reg_cwtp_local_port_set(buf: payload, val: local_port);
2439 mlxsw_reg_cwtp_traffic_class_set(buf: payload, val: traffic_class);
2440
2441 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
2442 mlxsw_reg_cwtp_profile_min_set(buf: payload, index: i,
2443 MLXSW_REG_CWTP_MIN_VALUE);
2444 mlxsw_reg_cwtp_profile_max_set(buf: payload, index: i,
2445 MLXSW_REG_CWTP_MIN_VALUE);
2446 }
2447}
2448
2449#define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
2450
2451static inline void
2452mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
2453 u32 probability)
2454{
2455 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
2456
2457 mlxsw_reg_cwtp_profile_min_set(buf: payload, index, val: min);
2458 mlxsw_reg_cwtp_profile_max_set(buf: payload, index, val: max);
2459 mlxsw_reg_cwtp_profile_percent_set(buf: payload, index, val: probability);
2460}
2461
2462/* CWTPM - Congestion WRED ECN TClass and Pool Mapping
2463 * ---------------------------------------------------
2464 * The CWTPM register maps each egress port and traffic class to profile num.
2465 */
2466#define MLXSW_REG_CWTPM_ID 0x2803
2467#define MLXSW_REG_CWTPM_LEN 0x44
2468
2469MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
2470
2471/* reg_cwtpm_local_port
2472 * Local port number
2473 * Not supported for CPU port
2474 * Access: Index
2475 */
2476MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12);
2477
2478/* reg_cwtpm_traffic_class
2479 * Traffic Class to configure
2480 * Access: Index
2481 */
2482MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
2483
2484/* reg_cwtpm_ew
2485 * Control enablement of WRED for traffic class:
2486 * 0 - Disable
2487 * 1 - Enable
2488 * Access: RW
2489 */
2490MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
2491
2492/* reg_cwtpm_ee
2493 * Control enablement of ECN for traffic class:
2494 * 0 - Disable
2495 * 1 - Enable
2496 * Access: RW
2497 */
2498MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
2499
2500/* reg_cwtpm_tcp_g
2501 * TCP Green Profile.
2502 * Index of the profile within {port, traffic class} to use.
2503 * 0 for disabling both WRED and ECN for this type of traffic.
2504 * Access: RW
2505 */
2506MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
2507
2508/* reg_cwtpm_tcp_y
2509 * TCP Yellow Profile.
2510 * Index of the profile within {port, traffic class} to use.
2511 * 0 for disabling both WRED and ECN for this type of traffic.
2512 * Access: RW
2513 */
2514MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
2515
2516/* reg_cwtpm_tcp_r
2517 * TCP Red Profile.
2518 * Index of the profile within {port, traffic class} to use.
2519 * 0 for disabling both WRED and ECN for this type of traffic.
2520 * Access: RW
2521 */
2522MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2523
2524/* reg_cwtpm_ntcp_g
2525 * Non-TCP Green Profile.
2526 * Index of the profile within {port, traffic class} to use.
2527 * 0 for disabling both WRED and ECN for this type of traffic.
2528 * Access: RW
2529 */
2530MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2531
2532/* reg_cwtpm_ntcp_y
2533 * Non-TCP Yellow Profile.
2534 * Index of the profile within {port, traffic class} to use.
2535 * 0 for disabling both WRED and ECN for this type of traffic.
2536 * Access: RW
2537 */
2538MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2539
2540/* reg_cwtpm_ntcp_r
2541 * Non-TCP Red Profile.
2542 * Index of the profile within {port, traffic class} to use.
2543 * 0 for disabling both WRED and ECN for this type of traffic.
2544 * Access: RW
2545 */
2546MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2547
2548#define MLXSW_REG_CWTPM_RESET_PROFILE 0
2549
2550static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port,
2551 u8 traffic_class, u8 profile,
2552 bool wred, bool ecn)
2553{
2554 MLXSW_REG_ZERO(cwtpm, payload);
2555 mlxsw_reg_cwtpm_local_port_set(buf: payload, val: local_port);
2556 mlxsw_reg_cwtpm_traffic_class_set(buf: payload, val: traffic_class);
2557 mlxsw_reg_cwtpm_ew_set(buf: payload, val: wred);
2558 mlxsw_reg_cwtpm_ee_set(buf: payload, val: ecn);
2559 mlxsw_reg_cwtpm_tcp_g_set(buf: payload, val: profile);
2560 mlxsw_reg_cwtpm_tcp_y_set(buf: payload, val: profile);
2561 mlxsw_reg_cwtpm_tcp_r_set(buf: payload, val: profile);
2562 mlxsw_reg_cwtpm_ntcp_g_set(buf: payload, val: profile);
2563 mlxsw_reg_cwtpm_ntcp_y_set(buf: payload, val: profile);
2564 mlxsw_reg_cwtpm_ntcp_r_set(buf: payload, val: profile);
2565}
2566
2567/* PGCR - Policy-Engine General Configuration Register
2568 * ---------------------------------------------------
2569 * This register configures general Policy-Engine settings.
2570 */
2571#define MLXSW_REG_PGCR_ID 0x3001
2572#define MLXSW_REG_PGCR_LEN 0x20
2573
2574MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2575
2576/* reg_pgcr_default_action_pointer_base
2577 * Default action pointer base. Each region has a default action pointer
2578 * which is equal to default_action_pointer_base + region_id.
2579 * Access: RW
2580 */
2581MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2582
2583static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2584{
2585 MLXSW_REG_ZERO(pgcr, payload);
2586 mlxsw_reg_pgcr_default_action_pointer_base_set(buf: payload, val: pointer_base);
2587}
2588
2589/* PPBT - Policy-Engine Port Binding Table
2590 * ---------------------------------------
2591 * This register is used for configuration of the Port Binding Table.
2592 */
2593#define MLXSW_REG_PPBT_ID 0x3002
2594#define MLXSW_REG_PPBT_LEN 0x14
2595
2596MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2597
2598enum mlxsw_reg_pxbt_e {
2599 MLXSW_REG_PXBT_E_IACL,
2600 MLXSW_REG_PXBT_E_EACL,
2601};
2602
2603/* reg_ppbt_e
2604 * Access: Index
2605 */
2606MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2607
2608enum mlxsw_reg_pxbt_op {
2609 MLXSW_REG_PXBT_OP_BIND,
2610 MLXSW_REG_PXBT_OP_UNBIND,
2611};
2612
2613/* reg_ppbt_op
2614 * Access: RW
2615 */
2616MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2617
2618/* reg_ppbt_local_port
2619 * Local port. Not including CPU port.
2620 * Access: Index
2621 */
2622MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12);
2623
2624/* reg_ppbt_g
2625 * group - When set, the binding is of an ACL group. When cleared,
2626 * the binding is of an ACL.
2627 * Must be set to 1 for Spectrum.
2628 * Access: RW
2629 */
2630MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2631
2632/* reg_ppbt_acl_info
2633 * ACL/ACL group identifier. If the g bit is set, this field should hold
2634 * the acl_group_id, else it should hold the acl_id.
2635 * Access: RW
2636 */
2637MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2638
2639static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2640 enum mlxsw_reg_pxbt_op op,
2641 u16 local_port, u16 acl_info)
2642{
2643 MLXSW_REG_ZERO(ppbt, payload);
2644 mlxsw_reg_ppbt_e_set(buf: payload, val: e);
2645 mlxsw_reg_ppbt_op_set(buf: payload, val: op);
2646 mlxsw_reg_ppbt_local_port_set(buf: payload, val: local_port);
2647 mlxsw_reg_ppbt_g_set(buf: payload, val: true);
2648 mlxsw_reg_ppbt_acl_info_set(buf: payload, val: acl_info);
2649}
2650
2651/* PACL - Policy-Engine ACL Register
2652 * ---------------------------------
2653 * This register is used for configuration of the ACL.
2654 */
2655#define MLXSW_REG_PACL_ID 0x3004
2656#define MLXSW_REG_PACL_LEN 0x70
2657
2658MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2659
2660/* reg_pacl_v
2661 * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2662 * while the ACL is bounded to either a port, VLAN or ACL rule.
2663 * Access: RW
2664 */
2665MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2666
2667/* reg_pacl_acl_id
2668 * An identifier representing the ACL (managed by software)
2669 * Range 0 .. cap_max_acl_regions - 1
2670 * Access: Index
2671 */
2672MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2673
2674#define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2675
2676/* reg_pacl_tcam_region_info
2677 * Opaque object that represents a TCAM region.
2678 * Obtained through PTAR register.
2679 * Access: RW
2680 */
2681MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2682 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2683
2684static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2685 bool valid, const char *tcam_region_info)
2686{
2687 MLXSW_REG_ZERO(pacl, payload);
2688 mlxsw_reg_pacl_acl_id_set(buf: payload, val: acl_id);
2689 mlxsw_reg_pacl_v_set(buf: payload, val: valid);
2690 mlxsw_reg_pacl_tcam_region_info_memcpy_to(buf: payload, src: tcam_region_info);
2691}
2692
2693/* PAGT - Policy-Engine ACL Group Table
2694 * ------------------------------------
2695 * This register is used for configuration of the ACL Group Table.
2696 */
2697#define MLXSW_REG_PAGT_ID 0x3005
2698#define MLXSW_REG_PAGT_BASE_LEN 0x30
2699#define MLXSW_REG_PAGT_ACL_LEN 4
2700#define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2701#define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2702 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2703
2704MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2705
2706/* reg_pagt_size
2707 * Number of ACLs in the group.
2708 * Size 0 invalidates a group.
2709 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2710 * Total number of ACLs in all groups must be lower or equal
2711 * to cap_max_acl_tot_groups
2712 * Note: a group which is binded must not be invalidated
2713 * Access: Index
2714 */
2715MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2716
2717/* reg_pagt_acl_group_id
2718 * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2719 * the ACL Group identifier (managed by software).
2720 * Access: Index
2721 */
2722MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2723
2724/* reg_pagt_multi
2725 * Multi-ACL
2726 * 0 - This ACL is the last ACL in the multi-ACL
2727 * 1 - This ACL is part of a multi-ACL
2728 * Access: RW
2729 */
2730MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2731
2732/* reg_pagt_acl_id
2733 * ACL identifier
2734 * Access: RW
2735 */
2736MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2737
2738static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2739{
2740 MLXSW_REG_ZERO(pagt, payload);
2741 mlxsw_reg_pagt_acl_group_id_set(buf: payload, val: acl_group_id);
2742}
2743
2744static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2745 u16 acl_id, bool multi)
2746{
2747 u8 size = mlxsw_reg_pagt_size_get(buf: payload);
2748
2749 if (index >= size)
2750 mlxsw_reg_pagt_size_set(buf: payload, val: index + 1);
2751 mlxsw_reg_pagt_multi_set(buf: payload, index, val: multi);
2752 mlxsw_reg_pagt_acl_id_set(buf: payload, index, val: acl_id);
2753}
2754
2755/* PTAR - Policy-Engine TCAM Allocation Register
2756 * ---------------------------------------------
2757 * This register is used for allocation of regions in the TCAM.
2758 * Note: Query method is not supported on this register.
2759 */
2760#define MLXSW_REG_PTAR_ID 0x3006
2761#define MLXSW_REG_PTAR_BASE_LEN 0x20
2762#define MLXSW_REG_PTAR_KEY_ID_LEN 1
2763#define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2764#define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2765 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2766
2767MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2768
2769enum mlxsw_reg_ptar_op {
2770 /* allocate a TCAM region */
2771 MLXSW_REG_PTAR_OP_ALLOC,
2772 /* resize a TCAM region */
2773 MLXSW_REG_PTAR_OP_RESIZE,
2774 /* deallocate TCAM region */
2775 MLXSW_REG_PTAR_OP_FREE,
2776 /* test allocation */
2777 MLXSW_REG_PTAR_OP_TEST,
2778};
2779
2780/* reg_ptar_op
2781 * Access: OP
2782 */
2783MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2784
2785/* reg_ptar_action_set_type
2786 * Type of action set to be used on this region.
2787 * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2788 * Access: WO
2789 */
2790MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2791
2792enum mlxsw_reg_ptar_key_type {
2793 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2794 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2795};
2796
2797/* reg_ptar_key_type
2798 * TCAM key type for the region.
2799 * Access: WO
2800 */
2801MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2802
2803/* reg_ptar_region_size
2804 * TCAM region size. When allocating/resizing this is the requested size,
2805 * the response is the actual size. Note that actual size may be
2806 * larger than requested.
2807 * Allowed range 1 .. cap_max_rules-1
2808 * Reserved during op deallocate.
2809 * Access: WO
2810 */
2811MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2812
2813/* reg_ptar_region_id
2814 * Region identifier
2815 * Range 0 .. cap_max_regions-1
2816 * Access: Index
2817 */
2818MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2819
2820/* reg_ptar_tcam_region_info
2821 * Opaque object that represents the TCAM region.
2822 * Returned when allocating a region.
2823 * Provided by software for ACL generation and region deallocation and resize.
2824 * Access: RW
2825 */
2826MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2827 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2828
2829/* reg_ptar_flexible_key_id
2830 * Identifier of the Flexible Key.
2831 * Only valid if key_type == "FLEX_KEY"
2832 * The key size will be rounded up to one of the following values:
2833 * 9B, 18B, 36B, 54B.
2834 * This field is reserved for in resize operation.
2835 * Access: WO
2836 */
2837MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2838 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2839
2840static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2841 enum mlxsw_reg_ptar_key_type key_type,
2842 u16 region_size, u16 region_id,
2843 const char *tcam_region_info)
2844{
2845 MLXSW_REG_ZERO(ptar, payload);
2846 mlxsw_reg_ptar_op_set(buf: payload, val: op);
2847 mlxsw_reg_ptar_action_set_type_set(buf: payload, val: 2); /* "flexible" */
2848 mlxsw_reg_ptar_key_type_set(buf: payload, val: key_type);
2849 mlxsw_reg_ptar_region_size_set(buf: payload, val: region_size);
2850 mlxsw_reg_ptar_region_id_set(buf: payload, val: region_id);
2851 mlxsw_reg_ptar_tcam_region_info_memcpy_to(buf: payload, src: tcam_region_info);
2852}
2853
2854static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2855 u16 key_id)
2856{
2857 mlxsw_reg_ptar_flexible_key_id_set(buf: payload, index, val: key_id);
2858}
2859
2860static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2861{
2862 mlxsw_reg_ptar_tcam_region_info_memcpy_from(buf: payload, dst: tcam_region_info);
2863}
2864
2865/* PPRR - Policy-Engine Port Range Register
2866 * ----------------------------------------
2867 * This register is used for configuring port range identification.
2868 */
2869#define MLXSW_REG_PPRR_ID 0x3008
2870#define MLXSW_REG_PPRR_LEN 0x14
2871
2872MLXSW_REG_DEFINE(pprr, MLXSW_REG_PPRR_ID, MLXSW_REG_PPRR_LEN);
2873
2874/* reg_pprr_ipv4
2875 * Apply port range register to IPv4 packets.
2876 * Access: RW
2877 */
2878MLXSW_ITEM32(reg, pprr, ipv4, 0x00, 31, 1);
2879
2880/* reg_pprr_ipv6
2881 * Apply port range register to IPv6 packets.
2882 * Access: RW
2883 */
2884MLXSW_ITEM32(reg, pprr, ipv6, 0x00, 30, 1);
2885
2886/* reg_pprr_src
2887 * Apply port range register to source L4 ports.
2888 * Access: RW
2889 */
2890MLXSW_ITEM32(reg, pprr, src, 0x00, 29, 1);
2891
2892/* reg_pprr_dst
2893 * Apply port range register to destination L4 ports.
2894 * Access: RW
2895 */
2896MLXSW_ITEM32(reg, pprr, dst, 0x00, 28, 1);
2897
2898/* reg_pprr_tcp
2899 * Apply port range register to TCP packets.
2900 * Access: RW
2901 */
2902MLXSW_ITEM32(reg, pprr, tcp, 0x00, 27, 1);
2903
2904/* reg_pprr_udp
2905 * Apply port range register to UDP packets.
2906 * Access: RW
2907 */
2908MLXSW_ITEM32(reg, pprr, udp, 0x00, 26, 1);
2909
2910/* reg_pprr_register_index
2911 * Index of Port Range Register being accessed.
2912 * Range is 0..cap_max_acl_l4_port_range-1.
2913 * Access: Index
2914 */
2915MLXSW_ITEM32(reg, pprr, register_index, 0x00, 0, 8);
2916
2917/* reg_prrr_port_range_min
2918 * Minimum port range for comparison.
2919 * Match is defined as:
2920 * port_range_min <= packet_port <= port_range_max.
2921 * Access: RW
2922 */
2923MLXSW_ITEM32(reg, pprr, port_range_min, 0x04, 16, 16);
2924
2925/* reg_prrr_port_range_max
2926 * Maximum port range for comparison.
2927 * Access: RW
2928 */
2929MLXSW_ITEM32(reg, pprr, port_range_max, 0x04, 0, 16);
2930
2931static inline void mlxsw_reg_pprr_pack(char *payload, u8 register_index)
2932{
2933 MLXSW_REG_ZERO(pprr, payload);
2934 mlxsw_reg_pprr_register_index_set(buf: payload, val: register_index);
2935}
2936
2937/* PPBS - Policy-Engine Policy Based Switching Register
2938 * ----------------------------------------------------
2939 * This register retrieves and sets Policy Based Switching Table entries.
2940 */
2941#define MLXSW_REG_PPBS_ID 0x300C
2942#define MLXSW_REG_PPBS_LEN 0x14
2943
2944MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2945
2946/* reg_ppbs_pbs_ptr
2947 * Index into the PBS table.
2948 * For Spectrum, the index points to the KVD Linear.
2949 * Access: Index
2950 */
2951MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2952
2953/* reg_ppbs_system_port
2954 * Unique port identifier for the final destination of the packet.
2955 * Access: RW
2956 */
2957MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2958
2959static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2960 u16 system_port)
2961{
2962 MLXSW_REG_ZERO(ppbs, payload);
2963 mlxsw_reg_ppbs_pbs_ptr_set(buf: payload, val: pbs_ptr);
2964 mlxsw_reg_ppbs_system_port_set(buf: payload, val: system_port);
2965}
2966
2967/* PRCR - Policy-Engine Rules Copy Register
2968 * ----------------------------------------
2969 * This register is used for accessing rules within a TCAM region.
2970 */
2971#define MLXSW_REG_PRCR_ID 0x300D
2972#define MLXSW_REG_PRCR_LEN 0x40
2973
2974MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2975
2976enum mlxsw_reg_prcr_op {
2977 /* Move rules. Moves the rules from "tcam_region_info" starting
2978 * at offset "offset" to "dest_tcam_region_info"
2979 * at offset "dest_offset."
2980 */
2981 MLXSW_REG_PRCR_OP_MOVE,
2982 /* Copy rules. Copies the rules from "tcam_region_info" starting
2983 * at offset "offset" to "dest_tcam_region_info"
2984 * at offset "dest_offset."
2985 */
2986 MLXSW_REG_PRCR_OP_COPY,
2987};
2988
2989/* reg_prcr_op
2990 * Access: OP
2991 */
2992MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2993
2994/* reg_prcr_offset
2995 * Offset within the source region to copy/move from.
2996 * Access: Index
2997 */
2998MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2999
3000/* reg_prcr_size
3001 * The number of rules to copy/move.
3002 * Access: WO
3003 */
3004MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
3005
3006/* reg_prcr_tcam_region_info
3007 * Opaque object that represents the source TCAM region.
3008 * Access: Index
3009 */
3010MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
3011 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3012
3013/* reg_prcr_dest_offset
3014 * Offset within the source region to copy/move to.
3015 * Access: Index
3016 */
3017MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
3018
3019/* reg_prcr_dest_tcam_region_info
3020 * Opaque object that represents the destination TCAM region.
3021 * Access: Index
3022 */
3023MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
3024 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3025
3026static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
3027 const char *src_tcam_region_info,
3028 u16 src_offset,
3029 const char *dest_tcam_region_info,
3030 u16 dest_offset, u16 size)
3031{
3032 MLXSW_REG_ZERO(prcr, payload);
3033 mlxsw_reg_prcr_op_set(buf: payload, val: op);
3034 mlxsw_reg_prcr_offset_set(buf: payload, val: src_offset);
3035 mlxsw_reg_prcr_size_set(buf: payload, val: size);
3036 mlxsw_reg_prcr_tcam_region_info_memcpy_to(buf: payload,
3037 src: src_tcam_region_info);
3038 mlxsw_reg_prcr_dest_offset_set(buf: payload, val: dest_offset);
3039 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(buf: payload,
3040 src: dest_tcam_region_info);
3041}
3042
3043/* PEFA - Policy-Engine Extended Flexible Action Register
3044 * ------------------------------------------------------
3045 * This register is used for accessing an extended flexible action entry
3046 * in the central KVD Linear Database.
3047 */
3048#define MLXSW_REG_PEFA_ID 0x300F
3049#define MLXSW_REG_PEFA_LEN 0xB0
3050
3051MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
3052
3053/* reg_pefa_index
3054 * Index in the KVD Linear Centralized Database.
3055 * Access: Index
3056 */
3057MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
3058
3059/* reg_pefa_a
3060 * Index in the KVD Linear Centralized Database.
3061 * Activity
3062 * For a new entry: set if ca=0, clear if ca=1
3063 * Set if a packet lookup has hit on the specific entry
3064 * Access: RO
3065 */
3066MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
3067
3068/* reg_pefa_ca
3069 * Clear activity
3070 * When write: activity is according to this field
3071 * When read: after reading the activity is cleared according to ca
3072 * Access: OP
3073 */
3074MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
3075
3076#define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
3077
3078/* reg_pefa_flex_action_set
3079 * Action-set to perform when rule is matched.
3080 * Must be zero padded if action set is shorter.
3081 * Access: RW
3082 */
3083MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
3084
3085static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
3086 const char *flex_action_set)
3087{
3088 MLXSW_REG_ZERO(pefa, payload);
3089 mlxsw_reg_pefa_index_set(buf: payload, val: index);
3090 mlxsw_reg_pefa_ca_set(buf: payload, val: ca);
3091 if (flex_action_set)
3092 mlxsw_reg_pefa_flex_action_set_memcpy_to(buf: payload,
3093 src: flex_action_set);
3094}
3095
3096static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
3097{
3098 *p_a = mlxsw_reg_pefa_a_get(buf: payload);
3099}
3100
3101/* PEMRBT - Policy-Engine Multicast Router Binding Table Register
3102 * --------------------------------------------------------------
3103 * This register is used for binding Multicast router to an ACL group
3104 * that serves the MC router.
3105 * This register is not supported by SwitchX/-2 and Spectrum.
3106 */
3107#define MLXSW_REG_PEMRBT_ID 0x3014
3108#define MLXSW_REG_PEMRBT_LEN 0x14
3109
3110MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
3111
3112enum mlxsw_reg_pemrbt_protocol {
3113 MLXSW_REG_PEMRBT_PROTO_IPV4,
3114 MLXSW_REG_PEMRBT_PROTO_IPV6,
3115};
3116
3117/* reg_pemrbt_protocol
3118 * Access: Index
3119 */
3120MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
3121
3122/* reg_pemrbt_group_id
3123 * ACL group identifier.
3124 * Range 0..cap_max_acl_groups-1
3125 * Access: RW
3126 */
3127MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
3128
3129static inline void
3130mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
3131 u16 group_id)
3132{
3133 MLXSW_REG_ZERO(pemrbt, payload);
3134 mlxsw_reg_pemrbt_protocol_set(buf: payload, val: protocol);
3135 mlxsw_reg_pemrbt_group_id_set(buf: payload, val: group_id);
3136}
3137
3138/* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
3139 * -----------------------------------------------------
3140 * This register is used for accessing rules within a TCAM region.
3141 * It is a new version of PTCE in order to support wider key,
3142 * mask and action within a TCAM region. This register is not supported
3143 * by SwitchX and SwitchX-2.
3144 */
3145#define MLXSW_REG_PTCE2_ID 0x3017
3146#define MLXSW_REG_PTCE2_LEN 0x1D8
3147
3148MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
3149
3150/* reg_ptce2_v
3151 * Valid.
3152 * Access: RW
3153 */
3154MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
3155
3156/* reg_ptce2_a
3157 * Activity. Set if a packet lookup has hit on the specific entry.
3158 * To clear the "a" bit, use "clear activity" op or "clear on read" op.
3159 * Access: RO
3160 */
3161MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
3162
3163enum mlxsw_reg_ptce2_op {
3164 /* Read operation. */
3165 MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
3166 /* clear on read operation. Used to read entry
3167 * and clear Activity bit.
3168 */
3169 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
3170 /* Write operation. Used to write a new entry to the table.
3171 * All R/W fields are relevant for new entry. Activity bit is set
3172 * for new entries - Note write with v = 0 will delete the entry.
3173 */
3174 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
3175 /* Update action. Only action set will be updated. */
3176 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
3177 /* Clear activity. A bit is cleared for the entry. */
3178 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
3179};
3180
3181/* reg_ptce2_op
3182 * Access: OP
3183 */
3184MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
3185
3186/* reg_ptce2_offset
3187 * Access: Index
3188 */
3189MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
3190
3191/* reg_ptce2_priority
3192 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
3193 * Note: priority does not have to be unique per rule.
3194 * Within a region, higher priority should have lower offset (no limitation
3195 * between regions in a multi-region).
3196 * Access: RW
3197 */
3198MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
3199
3200/* reg_ptce2_tcam_region_info
3201 * Opaque object that represents the TCAM region.
3202 * Access: Index
3203 */
3204MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
3205 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3206
3207#define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
3208
3209/* reg_ptce2_flex_key_blocks
3210 * ACL Key.
3211 * Access: RW
3212 */
3213MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
3214 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3215
3216/* reg_ptce2_mask
3217 * mask- in the same size as key. A bit that is set directs the TCAM
3218 * to compare the corresponding bit in key. A bit that is clear directs
3219 * the TCAM to ignore the corresponding bit in key.
3220 * Access: RW
3221 */
3222MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
3223 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3224
3225/* reg_ptce2_flex_action_set
3226 * ACL action set.
3227 * Access: RW
3228 */
3229MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
3230 MLXSW_REG_FLEX_ACTION_SET_LEN);
3231
3232static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
3233 enum mlxsw_reg_ptce2_op op,
3234 const char *tcam_region_info,
3235 u16 offset, u32 priority)
3236{
3237 MLXSW_REG_ZERO(ptce2, payload);
3238 mlxsw_reg_ptce2_v_set(buf: payload, val: valid);
3239 mlxsw_reg_ptce2_op_set(buf: payload, val: op);
3240 mlxsw_reg_ptce2_offset_set(buf: payload, val: offset);
3241 mlxsw_reg_ptce2_priority_set(buf: payload, val: priority);
3242 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(buf: payload, src: tcam_region_info);
3243}
3244
3245/* PERPT - Policy-Engine ERP Table Register
3246 * ----------------------------------------
3247 * This register adds and removes eRPs from the eRP table.
3248 */
3249#define MLXSW_REG_PERPT_ID 0x3021
3250#define MLXSW_REG_PERPT_LEN 0x80
3251
3252MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
3253
3254/* reg_perpt_erpt_bank
3255 * eRP table bank.
3256 * Range 0 .. cap_max_erp_table_banks - 1
3257 * Access: Index
3258 */
3259MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
3260
3261/* reg_perpt_erpt_index
3262 * Index to eRP table within the eRP bank.
3263 * Range is 0 .. cap_max_erp_table_bank_size - 1
3264 * Access: Index
3265 */
3266MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
3267
3268enum mlxsw_reg_perpt_key_size {
3269 MLXSW_REG_PERPT_KEY_SIZE_2KB,
3270 MLXSW_REG_PERPT_KEY_SIZE_4KB,
3271 MLXSW_REG_PERPT_KEY_SIZE_8KB,
3272 MLXSW_REG_PERPT_KEY_SIZE_12KB,
3273};
3274
3275/* reg_perpt_key_size
3276 * Access: OP
3277 */
3278MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
3279
3280/* reg_perpt_bf_bypass
3281 * 0 - The eRP is used only if bloom filter state is set for the given
3282 * rule.
3283 * 1 - The eRP is used regardless of bloom filter state.
3284 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
3285 * Access: RW
3286 */
3287MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
3288
3289/* reg_perpt_erp_id
3290 * eRP ID for use by the rules.
3291 * Access: RW
3292 */
3293MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
3294
3295/* reg_perpt_erpt_base_bank
3296 * Base eRP table bank, points to head of erp_vector
3297 * Range is 0 .. cap_max_erp_table_banks - 1
3298 * Access: OP
3299 */
3300MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
3301
3302/* reg_perpt_erpt_base_index
3303 * Base index to eRP table within the eRP bank
3304 * Range is 0 .. cap_max_erp_table_bank_size - 1
3305 * Access: OP
3306 */
3307MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
3308
3309/* reg_perpt_erp_index_in_vector
3310 * eRP index in the vector.
3311 * Access: OP
3312 */
3313MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
3314
3315/* reg_perpt_erp_vector
3316 * eRP vector.
3317 * Access: OP
3318 */
3319MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
3320
3321/* reg_perpt_mask
3322 * Mask
3323 * 0 - A-TCAM will ignore the bit in key
3324 * 1 - A-TCAM will compare the bit in key
3325 * Access: RW
3326 */
3327MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3328
3329static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
3330 unsigned long *erp_vector,
3331 unsigned long size)
3332{
3333 unsigned long bit;
3334
3335 for_each_set_bit(bit, erp_vector, size)
3336 mlxsw_reg_perpt_erp_vector_set(buf: payload, index: bit, val: true);
3337}
3338
3339static inline void
3340mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
3341 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
3342 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
3343 char *mask)
3344{
3345 MLXSW_REG_ZERO(perpt, payload);
3346 mlxsw_reg_perpt_erpt_bank_set(buf: payload, val: erpt_bank);
3347 mlxsw_reg_perpt_erpt_index_set(buf: payload, val: erpt_index);
3348 mlxsw_reg_perpt_key_size_set(buf: payload, val: key_size);
3349 mlxsw_reg_perpt_bf_bypass_set(buf: payload, val: false);
3350 mlxsw_reg_perpt_erp_id_set(buf: payload, val: erp_id);
3351 mlxsw_reg_perpt_erpt_base_bank_set(buf: payload, val: erpt_base_bank);
3352 mlxsw_reg_perpt_erpt_base_index_set(buf: payload, val: erpt_base_index);
3353 mlxsw_reg_perpt_erp_index_in_vector_set(buf: payload, val: erp_index);
3354 mlxsw_reg_perpt_mask_memcpy_to(buf: payload, src: mask);
3355}
3356
3357/* PERAR - Policy-Engine Region Association Register
3358 * -------------------------------------------------
3359 * This register associates a hw region for region_id's. Changing on the fly
3360 * is supported by the device.
3361 */
3362#define MLXSW_REG_PERAR_ID 0x3026
3363#define MLXSW_REG_PERAR_LEN 0x08
3364
3365MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
3366
3367/* reg_perar_region_id
3368 * Region identifier
3369 * Range 0 .. cap_max_regions-1
3370 * Access: Index
3371 */
3372MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
3373
3374static inline unsigned int
3375mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
3376{
3377 return DIV_ROUND_UP(block_num, 4);
3378}
3379
3380/* reg_perar_hw_region
3381 * HW Region
3382 * Range 0 .. cap_max_regions-1
3383 * Default: hw_region = region_id
3384 * For a 8 key block region, 2 consecutive regions are used
3385 * For a 12 key block region, 3 consecutive regions are used
3386 * Access: RW
3387 */
3388MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
3389
3390static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
3391 u16 hw_region)
3392{
3393 MLXSW_REG_ZERO(perar, payload);
3394 mlxsw_reg_perar_region_id_set(buf: payload, val: region_id);
3395 mlxsw_reg_perar_hw_region_set(buf: payload, val: hw_region);
3396}
3397
3398/* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
3399 * -----------------------------------------------------
3400 * This register is a new version of PTCE-V2 in order to support the
3401 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
3402 */
3403#define MLXSW_REG_PTCE3_ID 0x3027
3404#define MLXSW_REG_PTCE3_LEN 0xF0
3405
3406MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
3407
3408/* reg_ptce3_v
3409 * Valid.
3410 * Access: RW
3411 */
3412MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
3413
3414enum mlxsw_reg_ptce3_op {
3415 /* Write operation. Used to write a new entry to the table.
3416 * All R/W fields are relevant for new entry. Activity bit is set
3417 * for new entries. Write with v = 0 will delete the entry. Must
3418 * not be used if an entry exists.
3419 */
3420 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
3421 /* Update operation */
3422 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
3423 /* Read operation */
3424 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
3425};
3426
3427/* reg_ptce3_op
3428 * Access: OP
3429 */
3430MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
3431
3432/* reg_ptce3_priority
3433 * Priority of the rule. Higher values win.
3434 * For Spectrum-2 range is 1..cap_kvd_size - 1
3435 * Note: Priority does not have to be unique per rule.
3436 * Access: RW
3437 */
3438MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
3439
3440/* reg_ptce3_tcam_region_info
3441 * Opaque object that represents the TCAM region.
3442 * Access: Index
3443 */
3444MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
3445 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3446
3447/* reg_ptce3_flex2_key_blocks
3448 * ACL key. The key must be masked according to eRP (if exists) or
3449 * according to master mask.
3450 * Access: Index
3451 */
3452MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
3453 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3454
3455/* reg_ptce3_erp_id
3456 * eRP ID.
3457 * Access: Index
3458 */
3459MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
3460
3461/* reg_ptce3_delta_start
3462 * Start point of delta_value and delta_mask, in bits. Must not exceed
3463 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
3464 * Access: Index
3465 */
3466MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
3467
3468/* reg_ptce3_delta_mask
3469 * Delta mask.
3470 * 0 - Ignore relevant bit in delta_value
3471 * 1 - Compare relevant bit in delta_value
3472 * Delta mask must not be set for reserved fields in the key blocks.
3473 * Note: No delta when no eRPs. Thus, for regions with
3474 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
3475 * Access: Index
3476 */
3477MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
3478
3479/* reg_ptce3_delta_value
3480 * Delta value.
3481 * Bits which are masked by delta_mask must be 0.
3482 * Access: Index
3483 */
3484MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
3485
3486/* reg_ptce3_prune_vector
3487 * Pruning vector relative to the PERPT.erp_id.
3488 * Used for reducing lookups.
3489 * 0 - NEED: Do a lookup using the eRP.
3490 * 1 - PRUNE: Do not perform a lookup using the eRP.
3491 * Maybe be modified by PEAPBL and PEAPBM.
3492 * Note: In Spectrum-2, a region of 8 key blocks must be set to either
3493 * all 1's or all 0's.
3494 * Access: RW
3495 */
3496MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
3497
3498/* reg_ptce3_prune_ctcam
3499 * Pruning on C-TCAM. Used for reducing lookups.
3500 * 0 - NEED: Do a lookup in the C-TCAM.
3501 * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
3502 * Access: RW
3503 */
3504MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
3505
3506/* reg_ptce3_large_exists
3507 * Large entry key ID exists.
3508 * Within the region:
3509 * 0 - SINGLE: The large_entry_key_id is not currently in use.
3510 * For rule insert: The MSB of the key (blocks 6..11) will be added.
3511 * For rule delete: The MSB of the key will be removed.
3512 * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
3513 * For rule insert: The MSB of the key (blocks 6..11) will not be added.
3514 * For rule delete: The MSB of the key will not be removed.
3515 * Access: WO
3516 */
3517MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
3518
3519/* reg_ptce3_large_entry_key_id
3520 * Large entry key ID.
3521 * A key for 12 key blocks rules. Reserved when region has less than 12 key
3522 * blocks. Must be different for different keys which have the same common
3523 * 6 key blocks (MSB, blocks 6..11) key within a region.
3524 * Range is 0..cap_max_pe_large_key_id - 1
3525 * Access: RW
3526 */
3527MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
3528
3529/* reg_ptce3_action_pointer
3530 * Pointer to action.
3531 * Range is 0..cap_max_kvd_action_sets - 1
3532 * Access: RW
3533 */
3534MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
3535
3536static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
3537 enum mlxsw_reg_ptce3_op op,
3538 u32 priority,
3539 const char *tcam_region_info,
3540 const char *key, u8 erp_id,
3541 u16 delta_start, u8 delta_mask,
3542 u8 delta_value, bool large_exists,
3543 u32 lkey_id, u32 action_pointer)
3544{
3545 MLXSW_REG_ZERO(ptce3, payload);
3546 mlxsw_reg_ptce3_v_set(buf: payload, val: valid);
3547 mlxsw_reg_ptce3_op_set(buf: payload, val: op);
3548 mlxsw_reg_ptce3_priority_set(buf: payload, val: priority);
3549 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(buf: payload, src: tcam_region_info);
3550 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(buf: payload, src: key);
3551 mlxsw_reg_ptce3_erp_id_set(buf: payload, val: erp_id);
3552 mlxsw_reg_ptce3_delta_start_set(buf: payload, val: delta_start);
3553 mlxsw_reg_ptce3_delta_mask_set(buf: payload, val: delta_mask);
3554 mlxsw_reg_ptce3_delta_value_set(buf: payload, val: delta_value);
3555 mlxsw_reg_ptce3_large_exists_set(buf: payload, val: large_exists);
3556 mlxsw_reg_ptce3_large_entry_key_id_set(buf: payload, val: lkey_id);
3557 mlxsw_reg_ptce3_action_pointer_set(buf: payload, val: action_pointer);
3558}
3559
3560/* PERCR - Policy-Engine Region Configuration Register
3561 * ---------------------------------------------------
3562 * This register configures the region parameters. The region_id must be
3563 * allocated.
3564 */
3565#define MLXSW_REG_PERCR_ID 0x302A
3566#define MLXSW_REG_PERCR_LEN 0x80
3567
3568MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
3569
3570/* reg_percr_region_id
3571 * Region identifier.
3572 * Range 0..cap_max_regions-1
3573 * Access: Index
3574 */
3575MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
3576
3577/* reg_percr_atcam_ignore_prune
3578 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
3579 * Access: RW
3580 */
3581MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
3582
3583/* reg_percr_ctcam_ignore_prune
3584 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
3585 * Access: RW
3586 */
3587MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
3588
3589/* reg_percr_bf_bypass
3590 * Bloom filter bypass.
3591 * 0 - Bloom filter is used (default)
3592 * 1 - Bloom filter is bypassed. The bypass is an OR condition of
3593 * region_id or eRP. See PERPT.bf_bypass
3594 * Access: RW
3595 */
3596MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3597
3598/* reg_percr_master_mask
3599 * Master mask. Logical OR mask of all masks of all rules of a region
3600 * (both A-TCAM and C-TCAM). When there are no eRPs
3601 * (erpt_pointer_valid = 0), then this provides the mask.
3602 * Access: RW
3603 */
3604MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3605
3606static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3607{
3608 MLXSW_REG_ZERO(percr, payload);
3609 mlxsw_reg_percr_region_id_set(buf: payload, val: region_id);
3610 mlxsw_reg_percr_atcam_ignore_prune_set(buf: payload, val: false);
3611 mlxsw_reg_percr_ctcam_ignore_prune_set(buf: payload, val: false);
3612 mlxsw_reg_percr_bf_bypass_set(buf: payload, val: false);
3613}
3614
3615/* PERERP - Policy-Engine Region eRP Register
3616 * ------------------------------------------
3617 * This register configures the region eRP. The region_id must be
3618 * allocated.
3619 */
3620#define MLXSW_REG_PERERP_ID 0x302B
3621#define MLXSW_REG_PERERP_LEN 0x1C
3622
3623MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3624
3625/* reg_pererp_region_id
3626 * Region identifier.
3627 * Range 0..cap_max_regions-1
3628 * Access: Index
3629 */
3630MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3631
3632/* reg_pererp_ctcam_le
3633 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
3634 * Access: RW
3635 */
3636MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3637
3638/* reg_pererp_erpt_pointer_valid
3639 * erpt_pointer is valid.
3640 * Access: RW
3641 */
3642MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3643
3644/* reg_pererp_erpt_bank_pointer
3645 * Pointer to eRP table bank. May be modified at any time.
3646 * Range 0..cap_max_erp_table_banks-1
3647 * Reserved when erpt_pointer_valid = 0
3648 */
3649MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3650
3651/* reg_pererp_erpt_pointer
3652 * Pointer to eRP table within the eRP bank. Can be changed for an
3653 * existing region.
3654 * Range 0..cap_max_erp_table_size-1
3655 * Reserved when erpt_pointer_valid = 0
3656 * Access: RW
3657 */
3658MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3659
3660/* reg_pererp_erpt_vector
3661 * Vector of allowed eRP indexes starting from erpt_pointer within the
3662 * erpt_bank_pointer. Next entries will be in next bank.
3663 * Note that eRP index is used and not eRP ID.
3664 * Reserved when erpt_pointer_valid = 0
3665 * Access: RW
3666 */
3667MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3668
3669/* reg_pererp_master_rp_id
3670 * Master RP ID. When there are no eRPs, then this provides the eRP ID
3671 * for the lookup. Can be changed for an existing region.
3672 * Reserved when erpt_pointer_valid = 1
3673 * Access: RW
3674 */
3675MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3676
3677static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3678 unsigned long *erp_vector,
3679 unsigned long size)
3680{
3681 unsigned long bit;
3682
3683 for_each_set_bit(bit, erp_vector, size)
3684 mlxsw_reg_pererp_erpt_vector_set(buf: payload, index: bit, val: true);
3685}
3686
3687static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3688 bool ctcam_le, bool erpt_pointer_valid,
3689 u8 erpt_bank_pointer, u8 erpt_pointer,
3690 u8 master_rp_id)
3691{
3692 MLXSW_REG_ZERO(pererp, payload);
3693 mlxsw_reg_pererp_region_id_set(buf: payload, val: region_id);
3694 mlxsw_reg_pererp_ctcam_le_set(buf: payload, val: ctcam_le);
3695 mlxsw_reg_pererp_erpt_pointer_valid_set(buf: payload, val: erpt_pointer_valid);
3696 mlxsw_reg_pererp_erpt_bank_pointer_set(buf: payload, val: erpt_bank_pointer);
3697 mlxsw_reg_pererp_erpt_pointer_set(buf: payload, val: erpt_pointer);
3698 mlxsw_reg_pererp_master_rp_id_set(buf: payload, val: master_rp_id);
3699}
3700
3701/* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
3702 * ----------------------------------------------------------------
3703 * This register configures the Bloom filter entries.
3704 */
3705#define MLXSW_REG_PEABFE_ID 0x3022
3706#define MLXSW_REG_PEABFE_BASE_LEN 0x10
3707#define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3708#define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3709#define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3710 MLXSW_REG_PEABFE_BF_REC_LEN * \
3711 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3712
3713MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3714
3715/* reg_peabfe_size
3716 * Number of BF entries to be updated.
3717 * Range 1..256
3718 * Access: Op
3719 */
3720MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3721
3722/* reg_peabfe_bf_entry_state
3723 * Bloom filter state
3724 * 0 - Clear
3725 * 1 - Set
3726 * Access: RW
3727 */
3728MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3729 MLXSW_REG_PEABFE_BASE_LEN, 31, 1,
3730 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3731
3732/* reg_peabfe_bf_entry_bank
3733 * Bloom filter bank ID
3734 * Range 0..cap_max_erp_table_banks-1
3735 * Access: Index
3736 */
3737MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3738 MLXSW_REG_PEABFE_BASE_LEN, 24, 4,
3739 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3740
3741/* reg_peabfe_bf_entry_index
3742 * Bloom filter entry index
3743 * Range 0..2^cap_max_bf_log-1
3744 * Access: Index
3745 */
3746MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3747 MLXSW_REG_PEABFE_BASE_LEN, 0, 24,
3748 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3749
3750static inline void mlxsw_reg_peabfe_pack(char *payload)
3751{
3752 MLXSW_REG_ZERO(peabfe, payload);
3753}
3754
3755static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3756 u8 state, u8 bank, u32 bf_index)
3757{
3758 u8 num_rec = mlxsw_reg_peabfe_size_get(buf: payload);
3759
3760 if (rec_index >= num_rec)
3761 mlxsw_reg_peabfe_size_set(buf: payload, val: rec_index + 1);
3762 mlxsw_reg_peabfe_bf_entry_state_set(buf: payload, index: rec_index, val: state);
3763 mlxsw_reg_peabfe_bf_entry_bank_set(buf: payload, index: rec_index, val: bank);
3764 mlxsw_reg_peabfe_bf_entry_index_set(buf: payload, index: rec_index, val: bf_index);
3765}
3766
3767/* IEDR - Infrastructure Entry Delete Register
3768 * ----------------------------------------------------
3769 * This register is used for deleting entries from the entry tables.
3770 * It is legitimate to attempt to delete a nonexisting entry (the device will
3771 * respond as a good flow).
3772 */
3773#define MLXSW_REG_IEDR_ID 0x3804
3774#define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3775#define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3776#define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3777#define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \
3778 MLXSW_REG_IEDR_REC_LEN * \
3779 MLXSW_REG_IEDR_REC_MAX_COUNT)
3780
3781MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3782
3783/* reg_iedr_num_rec
3784 * Number of records.
3785 * Access: OP
3786 */
3787MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3788
3789/* reg_iedr_rec_type
3790 * Resource type.
3791 * Access: OP
3792 */
3793MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3794 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3795
3796/* reg_iedr_rec_size
3797 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3798 * Access: OP
3799 */
3800MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13,
3801 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3802
3803/* reg_iedr_rec_index_start
3804 * Resource index start.
3805 * Access: OP
3806 */
3807MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3808 MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3809
3810static inline void mlxsw_reg_iedr_pack(char *payload)
3811{
3812 MLXSW_REG_ZERO(iedr, payload);
3813}
3814
3815static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3816 u8 rec_type, u16 rec_size,
3817 u32 rec_index_start)
3818{
3819 u8 num_rec = mlxsw_reg_iedr_num_rec_get(buf: payload);
3820
3821 if (rec_index >= num_rec)
3822 mlxsw_reg_iedr_num_rec_set(buf: payload, val: rec_index + 1);
3823 mlxsw_reg_iedr_rec_type_set(buf: payload, index: rec_index, val: rec_type);
3824 mlxsw_reg_iedr_rec_size_set(buf: payload, index: rec_index, val: rec_size);
3825 mlxsw_reg_iedr_rec_index_start_set(buf: payload, index: rec_index, val: rec_index_start);
3826}
3827
3828/* QPTS - QoS Priority Trust State Register
3829 * ----------------------------------------
3830 * This register controls the port policy to calculate the switch priority and
3831 * packet color based on incoming packet fields.
3832 */
3833#define MLXSW_REG_QPTS_ID 0x4002
3834#define MLXSW_REG_QPTS_LEN 0x8
3835
3836MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3837
3838/* reg_qpts_local_port
3839 * Local port number.
3840 * Access: Index
3841 *
3842 * Note: CPU port is supported.
3843 */
3844MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12);
3845
3846enum mlxsw_reg_qpts_trust_state {
3847 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3848 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3849};
3850
3851/* reg_qpts_trust_state
3852 * Trust state for a given port.
3853 * Access: RW
3854 */
3855MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3856
3857static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port,
3858 enum mlxsw_reg_qpts_trust_state ts)
3859{
3860 MLXSW_REG_ZERO(qpts, payload);
3861
3862 mlxsw_reg_qpts_local_port_set(buf: payload, val: local_port);
3863 mlxsw_reg_qpts_trust_state_set(buf: payload, val: ts);
3864}
3865
3866/* QPCR - QoS Policer Configuration Register
3867 * -----------------------------------------
3868 * The QPCR register is used to create policers - that limit
3869 * the rate of bytes or packets via some trap group.
3870 */
3871#define MLXSW_REG_QPCR_ID 0x4004
3872#define MLXSW_REG_QPCR_LEN 0x28
3873
3874MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3875
3876enum mlxsw_reg_qpcr_g {
3877 MLXSW_REG_QPCR_G_GLOBAL = 2,
3878 MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3879};
3880
3881/* reg_qpcr_g
3882 * The policer type.
3883 * Access: Index
3884 */
3885MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3886
3887/* reg_qpcr_pid
3888 * Policer ID.
3889 * Access: Index
3890 */
3891MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3892
3893/* reg_qpcr_clear_counter
3894 * Clear counters.
3895 * Access: OP
3896 */
3897MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1);
3898
3899/* reg_qpcr_color_aware
3900 * Is the policer aware of colors.
3901 * Must be 0 (unaware) for cpu port.
3902 * Access: RW for unbounded policer. RO for bounded policer.
3903 */
3904MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3905
3906/* reg_qpcr_bytes
3907 * Is policer limit is for bytes per sec or packets per sec.
3908 * 0 - packets
3909 * 1 - bytes
3910 * Access: RW for unbounded policer. RO for bounded policer.
3911 */
3912MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3913
3914enum mlxsw_reg_qpcr_ir_units {
3915 MLXSW_REG_QPCR_IR_UNITS_M,
3916 MLXSW_REG_QPCR_IR_UNITS_K,
3917};
3918
3919/* reg_qpcr_ir_units
3920 * Policer's units for cir and eir fields (for bytes limits only)
3921 * 1 - 10^3
3922 * 0 - 10^6
3923 * Access: OP
3924 */
3925MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3926
3927enum mlxsw_reg_qpcr_rate_type {
3928 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3929 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3930};
3931
3932/* reg_qpcr_rate_type
3933 * Policer can have one limit (single rate) or 2 limits with specific operation
3934 * for packets that exceed the lower rate but not the upper one.
3935 * (For cpu port must be single rate)
3936 * Access: RW for unbounded policer. RO for bounded policer.
3937 */
3938MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3939
3940/* reg_qpc_cbs
3941 * Policer's committed burst size.
3942 * The policer is working with time slices of 50 nano sec. By default every
3943 * slice is granted the proportionate share of the committed rate. If we want to
3944 * allow a slice to exceed that share (while still keeping the rate per sec) we
3945 * can allow burst. The burst size is between the default proportionate share
3946 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3947 * committed rate will result in exceeding the rate). The burst size must be a
3948 * log of 2 and will be determined by 2^cbs.
3949 * Access: RW
3950 */
3951MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3952
3953/* reg_qpcr_cir
3954 * Policer's committed rate.
3955 * The rate used for sungle rate, the lower rate for double rate.
3956 * For bytes limits, the rate will be this value * the unit from ir_units.
3957 * (Resolution error is up to 1%).
3958 * Access: RW
3959 */
3960MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3961
3962/* reg_qpcr_eir
3963 * Policer's exceed rate.
3964 * The higher rate for double rate, reserved for single rate.
3965 * Lower rate for double rate policer.
3966 * For bytes limits, the rate will be this value * the unit from ir_units.
3967 * (Resolution error is up to 1%).
3968 * Access: RW
3969 */
3970MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3971
3972#define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3973
3974/* reg_qpcr_exceed_action.
3975 * What to do with packets between the 2 limits for double rate.
3976 * Access: RW for unbounded policer. RO for bounded policer.
3977 */
3978MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3979
3980enum mlxsw_reg_qpcr_action {
3981 /* Discard */
3982 MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3983 /* Forward and set color to red.
3984 * If the packet is intended to cpu port, it will be dropped.
3985 */
3986 MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3987};
3988
3989/* reg_qpcr_violate_action
3990 * What to do with packets that cross the cir limit (for single rate) or the eir
3991 * limit (for double rate).
3992 * Access: RW for unbounded policer. RO for bounded policer.
3993 */
3994MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3995
3996/* reg_qpcr_violate_count
3997 * Counts the number of times violate_action happened on this PID.
3998 * Access: RW
3999 */
4000MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);
4001
4002/* Packets */
4003#define MLXSW_REG_QPCR_LOWEST_CIR 1
4004#define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */
4005#define MLXSW_REG_QPCR_LOWEST_CBS 4
4006#define MLXSW_REG_QPCR_HIGHEST_CBS 24
4007
4008/* Bandwidth */
4009#define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */
4010#define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */
4011#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4
4012#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4
4013#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25
4014#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31
4015
4016static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
4017 enum mlxsw_reg_qpcr_ir_units ir_units,
4018 bool bytes, u32 cir, u16 cbs)
4019{
4020 MLXSW_REG_ZERO(qpcr, payload);
4021 mlxsw_reg_qpcr_pid_set(buf: payload, val: pid);
4022 mlxsw_reg_qpcr_g_set(buf: payload, val: MLXSW_REG_QPCR_G_GLOBAL);
4023 mlxsw_reg_qpcr_rate_type_set(buf: payload, val: MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
4024 mlxsw_reg_qpcr_violate_action_set(buf: payload,
4025 val: MLXSW_REG_QPCR_ACTION_DISCARD);
4026 mlxsw_reg_qpcr_cir_set(buf: payload, val: cir);
4027 mlxsw_reg_qpcr_ir_units_set(buf: payload, val: ir_units);
4028 mlxsw_reg_qpcr_bytes_set(buf: payload, val: bytes);
4029 mlxsw_reg_qpcr_cbs_set(buf: payload, val: cbs);
4030}
4031
4032/* QTCT - QoS Switch Traffic Class Table
4033 * -------------------------------------
4034 * Configures the mapping between the packet switch priority and the
4035 * traffic class on the transmit port.
4036 */
4037#define MLXSW_REG_QTCT_ID 0x400A
4038#define MLXSW_REG_QTCT_LEN 0x08
4039
4040MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
4041
4042/* reg_qtct_local_port
4043 * Local port number.
4044 * Access: Index
4045 *
4046 * Note: CPU port is not supported.
4047 */
4048MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12);
4049
4050/* reg_qtct_sub_port
4051 * Virtual port within the physical port.
4052 * Should be set to 0 when virtual ports are not enabled on the port.
4053 * Access: Index
4054 */
4055MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
4056
4057/* reg_qtct_switch_prio
4058 * Switch priority.
4059 * Access: Index
4060 */
4061MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
4062
4063/* reg_qtct_tclass
4064 * Traffic class.
4065 * Default values:
4066 * switch_prio 0 : tclass 1
4067 * switch_prio 1 : tclass 0
4068 * switch_prio i : tclass i, for i > 1
4069 * Access: RW
4070 */
4071MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
4072
4073static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port,
4074 u8 switch_prio, u8 tclass)
4075{
4076 MLXSW_REG_ZERO(qtct, payload);
4077 mlxsw_reg_qtct_local_port_set(buf: payload, val: local_port);
4078 mlxsw_reg_qtct_switch_prio_set(buf: payload, val: switch_prio);
4079 mlxsw_reg_qtct_tclass_set(buf: payload, val: tclass);
4080}
4081
4082/* QEEC - QoS ETS Element Configuration Register
4083 * ---------------------------------------------
4084 * Configures the ETS elements.
4085 */
4086#define MLXSW_REG_QEEC_ID 0x400D
4087#define MLXSW_REG_QEEC_LEN 0x20
4088
4089MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
4090
4091/* reg_qeec_local_port
4092 * Local port number.
4093 * Access: Index
4094 *
4095 * Note: CPU port is supported.
4096 */
4097MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12);
4098
4099enum mlxsw_reg_qeec_hr {
4100 MLXSW_REG_QEEC_HR_PORT,
4101 MLXSW_REG_QEEC_HR_GROUP,
4102 MLXSW_REG_QEEC_HR_SUBGROUP,
4103 MLXSW_REG_QEEC_HR_TC,
4104};
4105
4106/* reg_qeec_element_hierarchy
4107 * 0 - Port
4108 * 1 - Group
4109 * 2 - Subgroup
4110 * 3 - Traffic Class
4111 * Access: Index
4112 */
4113MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
4114
4115/* reg_qeec_element_index
4116 * The index of the element in the hierarchy.
4117 * Access: Index
4118 */
4119MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
4120
4121/* reg_qeec_next_element_index
4122 * The index of the next (lower) element in the hierarchy.
4123 * Access: RW
4124 *
4125 * Note: Reserved for element_hierarchy 0.
4126 */
4127MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
4128
4129/* reg_qeec_mise
4130 * Min shaper configuration enable. Enables configuration of the min
4131 * shaper on this ETS element
4132 * 0 - Disable
4133 * 1 - Enable
4134 * Access: RW
4135 */
4136MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
4137
4138/* reg_qeec_ptps
4139 * PTP shaper
4140 * 0: regular shaper mode
4141 * 1: PTP oriented shaper
4142 * Allowed only for hierarchy 0
4143 * Not supported for CPU port
4144 * Note that ptps mode may affect the shaper rates of all hierarchies
4145 * Supported only on Spectrum-1
4146 * Access: RW
4147 */
4148MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
4149
4150enum {
4151 MLXSW_REG_QEEC_BYTES_MODE,
4152 MLXSW_REG_QEEC_PACKETS_MODE,
4153};
4154
4155/* reg_qeec_pb
4156 * Packets or bytes mode.
4157 * 0 - Bytes mode
4158 * 1 - Packets mode
4159 * Access: RW
4160 *
4161 * Note: Used for max shaper configuration. For Spectrum, packets mode
4162 * is supported only for traffic classes of CPU port.
4163 */
4164MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
4165
4166/* The smallest permitted min shaper rate. */
4167#define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */
4168
4169/* reg_qeec_min_shaper_rate
4170 * Min shaper information rate.
4171 * For CPU port, can only be configured for port hierarchy.
4172 * When in bytes mode, value is specified in units of 1000bps.
4173 * Access: RW
4174 */
4175MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
4176
4177/* reg_qeec_mase
4178 * Max shaper configuration enable. Enables configuration of the max
4179 * shaper on this ETS element.
4180 * 0 - Disable
4181 * 1 - Enable
4182 * Access: RW
4183 */
4184MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
4185
4186/* The largest max shaper value possible to disable the shaper. */
4187#define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */
4188
4189/* reg_qeec_max_shaper_rate
4190 * Max shaper information rate.
4191 * For CPU port, can only be configured for port hierarchy.
4192 * When in bytes mode, value is specified in units of 1000bps.
4193 * Access: RW
4194 */
4195MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31);
4196
4197/* reg_qeec_de
4198 * DWRR configuration enable. Enables configuration of the dwrr and
4199 * dwrr_weight.
4200 * 0 - Disable
4201 * 1 - Enable
4202 * Access: RW
4203 */
4204MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
4205
4206/* reg_qeec_dwrr
4207 * Transmission selection algorithm to use on the link going down from
4208 * the ETS element.
4209 * 0 - Strict priority
4210 * 1 - DWRR
4211 * Access: RW
4212 */
4213MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
4214
4215/* reg_qeec_dwrr_weight
4216 * DWRR weight on the link going down from the ETS element. The
4217 * percentage of bandwidth guaranteed to an ETS element within
4218 * its hierarchy. The sum of all weights across all ETS elements
4219 * within one hierarchy should be equal to 100. Reserved when
4220 * transmission selection algorithm is strict priority.
4221 * Access: RW
4222 */
4223MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
4224
4225/* reg_qeec_max_shaper_bs
4226 * Max shaper burst size
4227 * Burst size is 2^max_shaper_bs * 512 bits
4228 * For Spectrum-1: Range is: 5..25
4229 * For Spectrum-2: Range is: 11..25
4230 * Reserved when ptps = 1
4231 * Access: RW
4232 */
4233MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
4234
4235#define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25
4236#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5
4237#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11
4238#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11
4239#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11
4240
4241static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port,
4242 enum mlxsw_reg_qeec_hr hr, u8 index,
4243 u8 next_index)
4244{
4245 MLXSW_REG_ZERO(qeec, payload);
4246 mlxsw_reg_qeec_local_port_set(buf: payload, val: local_port);
4247 mlxsw_reg_qeec_element_hierarchy_set(buf: payload, val: hr);
4248 mlxsw_reg_qeec_element_index_set(buf: payload, val: index);
4249 mlxsw_reg_qeec_next_element_index_set(buf: payload, val: next_index);
4250}
4251
4252static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port,
4253 bool ptps)
4254{
4255 MLXSW_REG_ZERO(qeec, payload);
4256 mlxsw_reg_qeec_local_port_set(buf: payload, val: local_port);
4257 mlxsw_reg_qeec_element_hierarchy_set(buf: payload, val: MLXSW_REG_QEEC_HR_PORT);
4258 mlxsw_reg_qeec_ptps_set(buf: payload, val: ptps);
4259}
4260
4261/* QRWE - QoS ReWrite Enable
4262 * -------------------------
4263 * This register configures the rewrite enable per receive port.
4264 */
4265#define MLXSW_REG_QRWE_ID 0x400F
4266#define MLXSW_REG_QRWE_LEN 0x08
4267
4268MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
4269
4270/* reg_qrwe_local_port
4271 * Local port number.
4272 * Access: Index
4273 *
4274 * Note: CPU port is supported. No support for router port.
4275 */
4276MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12);
4277
4278/* reg_qrwe_dscp
4279 * Whether to enable DSCP rewrite (default is 0, don't rewrite).
4280 * Access: RW
4281 */
4282MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
4283
4284/* reg_qrwe_pcp
4285 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
4286 * Access: RW
4287 */
4288MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
4289
4290static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port,
4291 bool rewrite_pcp, bool rewrite_dscp)
4292{
4293 MLXSW_REG_ZERO(qrwe, payload);
4294 mlxsw_reg_qrwe_local_port_set(buf: payload, val: local_port);
4295 mlxsw_reg_qrwe_pcp_set(buf: payload, val: rewrite_pcp);
4296 mlxsw_reg_qrwe_dscp_set(buf: payload, val: rewrite_dscp);
4297}
4298
4299/* QPDSM - QoS Priority to DSCP Mapping
4300 * ------------------------------------
4301 * QoS Priority to DSCP Mapping Register
4302 */
4303#define MLXSW_REG_QPDSM_ID 0x4011
4304#define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
4305#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
4306#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
4307#define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \
4308 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \
4309 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
4310
4311MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
4312
4313/* reg_qpdsm_local_port
4314 * Local Port. Supported for data packets from CPU port.
4315 * Access: Index
4316 */
4317MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12);
4318
4319/* reg_qpdsm_prio_entry_color0_e
4320 * Enable update of the entry for color 0 and a given port.
4321 * Access: WO
4322 */
4323MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
4324 MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
4325 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4326
4327/* reg_qpdsm_prio_entry_color0_dscp
4328 * DSCP field in the outer label of the packet for color 0 and a given port.
4329 * Reserved when e=0.
4330 * Access: RW
4331 */
4332MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
4333 MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
4334 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4335
4336/* reg_qpdsm_prio_entry_color1_e
4337 * Enable update of the entry for color 1 and a given port.
4338 * Access: WO
4339 */
4340MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
4341 MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
4342 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4343
4344/* reg_qpdsm_prio_entry_color1_dscp
4345 * DSCP field in the outer label of the packet for color 1 and a given port.
4346 * Reserved when e=0.
4347 * Access: RW
4348 */
4349MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
4350 MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
4351 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4352
4353/* reg_qpdsm_prio_entry_color2_e
4354 * Enable update of the entry for color 2 and a given port.
4355 * Access: WO
4356 */
4357MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
4358 MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
4359 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4360
4361/* reg_qpdsm_prio_entry_color2_dscp
4362 * DSCP field in the outer label of the packet for color 2 and a given port.
4363 * Reserved when e=0.
4364 * Access: RW
4365 */
4366MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
4367 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
4368 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4369
4370static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port)
4371{
4372 MLXSW_REG_ZERO(qpdsm, payload);
4373 mlxsw_reg_qpdsm_local_port_set(buf: payload, val: local_port);
4374}
4375
4376static inline void
4377mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
4378{
4379 mlxsw_reg_qpdsm_prio_entry_color0_e_set(buf: payload, index: prio, val: 1);
4380 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(buf: payload, index: prio, val: dscp);
4381 mlxsw_reg_qpdsm_prio_entry_color1_e_set(buf: payload, index: prio, val: 1);
4382 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(buf: payload, index: prio, val: dscp);
4383 mlxsw_reg_qpdsm_prio_entry_color2_e_set(buf: payload, index: prio, val: 1);
4384 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(buf: payload, index: prio, val: dscp);
4385}
4386
4387/* QPDP - QoS Port DSCP to Priority Mapping Register
4388 * -------------------------------------------------
4389 * This register controls the port default Switch Priority and Color. The
4390 * default Switch Priority and Color are used for frames where the trust state
4391 * uses default values. All member ports of a LAG should be configured with the
4392 * same default values.
4393 */
4394#define MLXSW_REG_QPDP_ID 0x4007
4395#define MLXSW_REG_QPDP_LEN 0x8
4396
4397MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN);
4398
4399/* reg_qpdp_local_port
4400 * Local Port. Supported for data packets from CPU port.
4401 * Access: Index
4402 */
4403MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12);
4404
4405/* reg_qpdp_switch_prio
4406 * Default port Switch Priority (default 0)
4407 * Access: RW
4408 */
4409MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
4410
4411static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port,
4412 u8 switch_prio)
4413{
4414 MLXSW_REG_ZERO(qpdp, payload);
4415 mlxsw_reg_qpdp_local_port_set(buf: payload, val: local_port);
4416 mlxsw_reg_qpdp_switch_prio_set(buf: payload, val: switch_prio);
4417}
4418
4419/* QPDPM - QoS Port DSCP to Priority Mapping Register
4420 * --------------------------------------------------
4421 * This register controls the mapping from DSCP field to
4422 * Switch Priority for IP packets.
4423 */
4424#define MLXSW_REG_QPDPM_ID 0x4013
4425#define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
4426#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
4427#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
4428#define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \
4429 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \
4430 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
4431
4432MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
4433
4434/* reg_qpdpm_local_port
4435 * Local Port. Supported for data packets from CPU port.
4436 * Access: Index
4437 */
4438MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12);
4439
4440/* reg_qpdpm_dscp_e
4441 * Enable update of the specific entry. When cleared, the switch_prio and color
4442 * fields are ignored and the previous switch_prio and color values are
4443 * preserved.
4444 * Access: WO
4445 */
4446MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
4447 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4448
4449/* reg_qpdpm_dscp_prio
4450 * The new Switch Priority value for the relevant DSCP value.
4451 * Access: RW
4452 */
4453MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
4454 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
4455 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4456
4457static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port)
4458{
4459 MLXSW_REG_ZERO(qpdpm, payload);
4460 mlxsw_reg_qpdpm_local_port_set(buf: payload, val: local_port);
4461}
4462
4463static inline void
4464mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
4465{
4466 mlxsw_reg_qpdpm_dscp_entry_e_set(buf: payload, index: dscp, val: 1);
4467 mlxsw_reg_qpdpm_dscp_entry_prio_set(buf: payload, index: dscp, val: prio);
4468}
4469
4470/* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
4471 * ------------------------------------------------------------------
4472 * This register configures if the Switch Priority to Traffic Class mapping is
4473 * based on Multicast packet indication. If so, then multicast packets will get
4474 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
4475 * QTCT.
4476 * By default, Switch Priority to Traffic Class mapping is not based on
4477 * Multicast packet indication.
4478 */
4479#define MLXSW_REG_QTCTM_ID 0x401A
4480#define MLXSW_REG_QTCTM_LEN 0x08
4481
4482MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
4483
4484/* reg_qtctm_local_port
4485 * Local port number.
4486 * No support for CPU port.
4487 * Access: Index
4488 */
4489MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12);
4490
4491/* reg_qtctm_mc
4492 * Multicast Mode
4493 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
4494 * indication (default is 0, not based on Multicast packet indication).
4495 */
4496MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
4497
4498static inline void
4499mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc)
4500{
4501 MLXSW_REG_ZERO(qtctm, payload);
4502 mlxsw_reg_qtctm_local_port_set(buf: payload, val: local_port);
4503 mlxsw_reg_qtctm_mc_set(buf: payload, val: mc);
4504}
4505
4506/* QPSC - QoS PTP Shaper Configuration Register
4507 * --------------------------------------------
4508 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1.
4509 * Supported only on Spectrum-1.
4510 */
4511#define MLXSW_REG_QPSC_ID 0x401B
4512#define MLXSW_REG_QPSC_LEN 0x28
4513
4514MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
4515
4516enum mlxsw_reg_qpsc_port_speed {
4517 MLXSW_REG_QPSC_PORT_SPEED_100M,
4518 MLXSW_REG_QPSC_PORT_SPEED_1G,
4519 MLXSW_REG_QPSC_PORT_SPEED_10G,
4520 MLXSW_REG_QPSC_PORT_SPEED_25G,
4521};
4522
4523/* reg_qpsc_port_speed
4524 * Port speed.
4525 * Access: Index
4526 */
4527MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
4528
4529/* reg_qpsc_shaper_time_exp
4530 * The base-time-interval for updating the shapers tokens (for all hierarchies).
4531 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
4532 * shaper_rate = 64bit * shaper_inc / shaper_update_rate
4533 * Access: RW
4534 */
4535MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
4536
4537/* reg_qpsc_shaper_time_mantissa
4538 * The base-time-interval for updating the shapers tokens (for all hierarchies).
4539 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
4540 * shaper_rate = 64bit * shaper_inc / shaper_update_rate
4541 * Access: RW
4542 */
4543MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
4544
4545/* reg_qpsc_shaper_inc
4546 * Number of tokens added to shaper on each update.
4547 * Units of 8B.
4548 * Access: RW
4549 */
4550MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
4551
4552/* reg_qpsc_shaper_bs
4553 * Max shaper Burst size.
4554 * Burst size is 2 ^ max_shaper_bs * 512 [bits]
4555 * Range is: 5..25 (from 2KB..2GB)
4556 * Access: RW
4557 */
4558MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
4559
4560/* reg_qpsc_ptsc_we
4561 * Write enable to port_to_shaper_credits.
4562 * Access: WO
4563 */
4564MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
4565
4566/* reg_qpsc_port_to_shaper_credits
4567 * For split ports: range 1..57
4568 * For non-split ports: range 1..112
4569 * Written only when ptsc_we is set.
4570 * Access: RW
4571 */
4572MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
4573
4574/* reg_qpsc_ing_timestamp_inc
4575 * Ingress timestamp increment.
4576 * 2's complement.
4577 * The timestamp of MTPPTR at ingress will be incremented by this value. Global
4578 * value for all ports.
4579 * Same units as used by MTPPTR.
4580 * Access: RW
4581 */
4582MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
4583
4584/* reg_qpsc_egr_timestamp_inc
4585 * Egress timestamp increment.
4586 * 2's complement.
4587 * The timestamp of MTPPTR at egress will be incremented by this value. Global
4588 * value for all ports.
4589 * Same units as used by MTPPTR.
4590 * Access: RW
4591 */
4592MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
4593
4594static inline void
4595mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
4596 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
4597 u8 shaper_bs, u8 port_to_shaper_credits,
4598 int ing_timestamp_inc, int egr_timestamp_inc)
4599{
4600 MLXSW_REG_ZERO(qpsc, payload);
4601 mlxsw_reg_qpsc_port_speed_set(buf: payload, val: port_speed);
4602 mlxsw_reg_qpsc_shaper_time_exp_set(buf: payload, val: shaper_time_exp);
4603 mlxsw_reg_qpsc_shaper_time_mantissa_set(buf: payload, val: shaper_time_mantissa);
4604 mlxsw_reg_qpsc_shaper_inc_set(buf: payload, val: shaper_inc);
4605 mlxsw_reg_qpsc_shaper_bs_set(buf: payload, val: shaper_bs);
4606 mlxsw_reg_qpsc_ptsc_we_set(buf: payload, val: true);
4607 mlxsw_reg_qpsc_port_to_shaper_credits_set(buf: payload, val: port_to_shaper_credits);
4608 mlxsw_reg_qpsc_ing_timestamp_inc_set(buf: payload, val: ing_timestamp_inc);
4609 mlxsw_reg_qpsc_egr_timestamp_inc_set(buf: payload, val: egr_timestamp_inc);
4610}
4611
4612/* PMLP - Ports Module to Local Port Register
4613 * ------------------------------------------
4614 * Configures the assignment of modules to local ports.
4615 */
4616#define MLXSW_REG_PMLP_ID 0x5002
4617#define MLXSW_REG_PMLP_LEN 0x40
4618
4619MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
4620
4621/* reg_pmlp_rxtx
4622 * 0 - Tx value is used for both Tx and Rx.
4623 * 1 - Rx value is taken from a separte field.
4624 * Access: RW
4625 */
4626MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
4627
4628/* reg_pmlp_local_port
4629 * Local port number.
4630 * Access: Index
4631 */
4632MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12);
4633
4634/* reg_pmlp_width
4635 * 0 - Unmap local port.
4636 * 1 - Lane 0 is used.
4637 * 2 - Lanes 0 and 1 are used.
4638 * 4 - Lanes 0, 1, 2 and 3 are used.
4639 * 8 - Lanes 0-7 are used.
4640 * Access: RW
4641 */
4642MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
4643
4644/* reg_pmlp_module
4645 * Module number.
4646 * Access: RW
4647 */
4648MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
4649
4650/* reg_pmlp_slot_index
4651 * Module number.
4652 * Slot_index
4653 * Slot_index = 0 represent the onboard (motherboard).
4654 * In case of non-modular system only slot_index = 0 is available.
4655 * Access: RW
4656 */
4657MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false);
4658
4659/* reg_pmlp_tx_lane
4660 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
4661 * Access: RW
4662 */
4663MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);
4664
4665/* reg_pmlp_rx_lane
4666 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
4667 * equal to Tx lane.
4668 * Access: RW
4669 */
4670MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
4671
4672static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port)
4673{
4674 MLXSW_REG_ZERO(pmlp, payload);
4675 mlxsw_reg_pmlp_local_port_set(buf: payload, val: local_port);
4676}
4677
4678/* PMTU - Port MTU Register
4679 * ------------------------
4680 * Configures and reports the port MTU.
4681 */
4682#define MLXSW_REG_PMTU_ID 0x5003
4683#define MLXSW_REG_PMTU_LEN 0x10
4684
4685MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
4686
4687/* reg_pmtu_local_port
4688 * Local port number.
4689 * Access: Index
4690 */
4691MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12);
4692
4693/* reg_pmtu_max_mtu
4694 * Maximum MTU.
4695 * When port type (e.g. Ethernet) is configured, the relevant MTU is
4696 * reported, otherwise the minimum between the max_mtu of the different
4697 * types is reported.
4698 * Access: RO
4699 */
4700MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4701
4702/* reg_pmtu_admin_mtu
4703 * MTU value to set port to. Must be smaller or equal to max_mtu.
4704 * Note: If port type is Infiniband, then port must be disabled, when its
4705 * MTU is set.
4706 * Access: RW
4707 */
4708MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4709
4710/* reg_pmtu_oper_mtu
4711 * The actual MTU configured on the port. Packets exceeding this size
4712 * will be dropped.
4713 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
4714 * oper_mtu might be smaller than admin_mtu.
4715 * Access: RO
4716 */
4717MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4718
4719static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port,
4720 u16 new_mtu)
4721{
4722 MLXSW_REG_ZERO(pmtu, payload);
4723 mlxsw_reg_pmtu_local_port_set(buf: payload, val: local_port);
4724 mlxsw_reg_pmtu_max_mtu_set(buf: payload, val: 0);
4725 mlxsw_reg_pmtu_admin_mtu_set(buf: payload, val: new_mtu);
4726 mlxsw_reg_pmtu_oper_mtu_set(buf: payload, val: 0);
4727}
4728
4729/* PTYS - Port Type and Speed Register
4730 * -----------------------------------
4731 * Configures and reports the port speed type.
4732 *
4733 * Note: When set while the link is up, the changes will not take effect
4734 * until the port transitions from down to up state.
4735 */
4736#define MLXSW_REG_PTYS_ID 0x5004
4737#define MLXSW_REG_PTYS_LEN 0x40
4738
4739MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
4740
4741/* an_disable_admin
4742 * Auto negotiation disable administrative configuration
4743 * 0 - Device doesn't support AN disable.
4744 * 1 - Device supports AN disable.
4745 * Access: RW
4746 */
4747MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4748
4749/* reg_ptys_local_port
4750 * Local port number.
4751 * Access: Index
4752 */
4753MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12);
4754
4755#define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
4756#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
4757
4758/* reg_ptys_proto_mask
4759 * Protocol mask. Indicates which protocol is used.
4760 * 0 - Infiniband.
4761 * 1 - Fibre Channel.
4762 * 2 - Ethernet.
4763 * Access: Index
4764 */
4765MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4766
4767enum {
4768 MLXSW_REG_PTYS_AN_STATUS_NA,
4769 MLXSW_REG_PTYS_AN_STATUS_OK,
4770 MLXSW_REG_PTYS_AN_STATUS_FAIL,
4771};
4772
4773/* reg_ptys_an_status
4774 * Autonegotiation status.
4775 * Access: RO
4776 */
4777MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4778
4779#define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0)
4780#define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1)
4781#define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3)
4782#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4)
4783#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5)
4784#define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6)
4785#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7)
4786#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8)
4787#define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9)
4788#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10)
4789#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12)
4790#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15)
4791#define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8 BIT(19)
4792
4793/* reg_ptys_ext_eth_proto_cap
4794 * Extended Ethernet port supported speeds and protocols.
4795 * Access: RO
4796 */
4797MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4798
4799#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
4800#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
4801#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
4802#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
4803#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
4804#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
4805#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
4806#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
4807#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
4808#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
4809#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
4810#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
4811#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
4812#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
4813#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
4814#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
4815#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
4816#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
4817#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24)
4818#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25)
4819#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
4820#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
4821#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
4822#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
4823#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
4824
4825/* reg_ptys_eth_proto_cap
4826 * Ethernet port supported speeds and protocols.
4827 * Access: RO
4828 */
4829MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);