1/* SPDX-License-Identifier: GPL-2.0+
2 * Microchip Sparx5 Switch driver
3 *
4 * Copyright (c) 2021 Microchip Technology Inc.
5 */
6
7/* This file is autogenerated by cml-utils 2023-02-10 11:18:53 +0100.
8 * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada
9 */
10
11#ifndef _SPARX5_MAIN_REGS_H_
12#define _SPARX5_MAIN_REGS_H_
13
14#include <linux/bitfield.h>
15#include <linux/types.h>
16#include <linux/bug.h>
17
18enum sparx5_target {
19 TARGET_ANA_AC = 1,
20 TARGET_ANA_ACL = 2,
21 TARGET_ANA_AC_POL = 4,
22 TARGET_ANA_AC_SDLB = 5,
23 TARGET_ANA_CL = 6,
24 TARGET_ANA_L2 = 7,
25 TARGET_ANA_L3 = 8,
26 TARGET_ASM = 9,
27 TARGET_CLKGEN = 11,
28 TARGET_CPU = 12,
29 TARGET_DEV10G = 17,
30 TARGET_DEV25G = 29,
31 TARGET_DEV2G5 = 37,
32 TARGET_DEV5G = 102,
33 TARGET_DSM = 115,
34 TARGET_EACL = 116,
35 TARGET_FDMA = 117,
36 TARGET_GCB = 118,
37 TARGET_HSCH = 119,
38 TARGET_LRN = 122,
39 TARGET_PCEP = 129,
40 TARGET_PCS10G_BR = 132,
41 TARGET_PCS25G_BR = 144,
42 TARGET_PCS5G_BR = 160,
43 TARGET_PORT_CONF = 173,
44 TARGET_PTP = 174,
45 TARGET_QFWD = 175,
46 TARGET_QRES = 176,
47 TARGET_QS = 177,
48 TARGET_QSYS = 178,
49 TARGET_REW = 179,
50 TARGET_VCAP_ES0 = 323,
51 TARGET_VCAP_ES2 = 324,
52 TARGET_VCAP_SUPER = 326,
53 TARGET_VOP = 327,
54 TARGET_XQS = 331,
55 NUM_TARGETS = 332
56};
57
58#define __REG(...) __VA_ARGS__
59
60/* ANA_AC:RAM_CTRL:RAM_INIT */
61#define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC,\
62 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4)
63
64#define ANA_AC_RAM_INIT_RAM_INIT BIT(1)
65#define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\
66 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
67#define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\
68 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
69
70#define ANA_AC_RAM_INIT_RAM_CFG_HOOK BIT(0)
71#define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\
72 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
73#define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\
74 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
75
76/* ANA_AC:PS_COMMON:OWN_UPSID */
77#define ANA_AC_OWN_UPSID(r) __REG(TARGET_ANA_AC,\
78 0, 1, 894472, 0, 1, 352, 52, r, 3, 4)
79
80#define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0)
81#define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\
82 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
83#define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\
84 FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x)
85
86/* ANA_AC:SRC:SRC_CFG */
87#define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC,\
88 0, 1, 849920, g, 102, 16, 0, 0, 1, 4)
89
90/* ANA_AC:SRC:SRC_CFG1 */
91#define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC,\
92 0, 1, 849920, g, 102, 16, 4, 0, 1, 4)
93
94/* ANA_AC:SRC:SRC_CFG2 */
95#define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC,\
96 0, 1, 849920, g, 102, 16, 8, 0, 1, 4)
97
98#define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0)
99#define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\
100 FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x)
101#define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\
102 FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x)
103
104/* ANA_AC:PGID:PGID_CFG */
105#define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC,\
106 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4)
107
108/* ANA_AC:PGID:PGID_CFG1 */
109#define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC,\
110 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4)
111
112/* ANA_AC:PGID:PGID_CFG2 */
113#define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC,\
114 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4)
115
116#define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0)
117#define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\
118 FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x)
119#define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\
120 FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x)
121
122/* ANA_AC:PGID:PGID_MISC_CFG */
123#define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC,\
124 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4)
125
126#define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4)
127#define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\
128 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
129#define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\
130 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
131
132#define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1)
133#define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\
134 FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
135#define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\
136 FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
137
138#define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA BIT(0)
139#define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\
140 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
141#define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\
142 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
143
144/* ANA_AC:TSN_SF:TSN_SF */
145#define ANA_AC_TSN_SF __REG(TARGET_ANA_AC,\
146 0, 1, 839136, 0, 1, 4, 0, 0, 1, 4)
147
148#define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY BIT(9)
149#define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\
150 FIELD_PREP(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x)
151#define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\
152 FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x)
153
154#define ANA_AC_TSN_SF_PORT_NUM GENMASK(8, 0)
155#define ANA_AC_TSN_SF_PORT_NUM_SET(x)\
156 FIELD_PREP(ANA_AC_TSN_SF_PORT_NUM, x)
157#define ANA_AC_TSN_SF_PORT_NUM_GET(x)\
158 FIELD_GET(ANA_AC_TSN_SF_PORT_NUM, x)
159
160/* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */
161#define ANA_AC_TSN_SF_CFG(g) __REG(TARGET_ANA_AC,\
162 0, 1, 839680, g, 1024, 4, 0, 0, 1, 4)
163
164#define ANA_AC_TSN_SF_CFG_TSN_SGID GENMASK(25, 16)
165#define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\
166 FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_SGID, x)
167#define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\
168 FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_SGID, x)
169
170#define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU GENMASK(15, 2)
171#define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\
172 FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x)
173#define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x)\
174 FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x)
175
176#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA BIT(1)
177#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x)\
178 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x)
179#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x)\
180 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x)
181
182#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE BIT(0)
183#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x)\
184 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x)
185#define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\
186 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x)
187
188/* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */
189#define ANA_AC_TSN_SF_STATUS __REG(TARGET_ANA_AC,\
190 0, 1, 839072, 0, 1, 16, 0, 0, 1, 4)
191
192#define ANA_AC_TSN_SF_STATUS_FRM_LEN GENMASK(25, 12)
193#define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\
194 FIELD_PREP(ANA_AC_TSN_SF_STATUS_FRM_LEN, x)
195#define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x)\
196 FIELD_GET(ANA_AC_TSN_SF_STATUS_FRM_LEN, x)
197
198#define ANA_AC_TSN_SF_STATUS_DLB_DROP BIT(11)
199#define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x)\
200 FIELD_PREP(ANA_AC_TSN_SF_STATUS_DLB_DROP, x)
201#define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\
202 FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x)
203
204#define ANA_AC_TSN_SF_STATUS_TSN_SFID GENMASK(10, 1)
205#define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\
206 FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSN_SFID, x)
207#define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\
208 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSN_SFID, x)
209
210#define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD BIT(0)
211#define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\
212 FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x)
213#define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\
214 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x)
215
216/* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */
217#define ANA_AC_SG_ACCESS_CTRL __REG(TARGET_ANA_AC,\
218 0, 1, 839140, 0, 1, 12, 0, 0, 1, 4)
219
220#define ANA_AC_SG_ACCESS_CTRL_SGID GENMASK(9, 0)
221#define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\
222 FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_SGID, x)
223#define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\
224 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_SGID, x)
225
226#define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28)
227#define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\
228 FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x)
229#define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\
230 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x)
231
232/* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */
233#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD __REG(TARGET_ANA_AC,\
234 0, 1, 839140, 0, 1, 12, 8, 0, 1, 4)
235
236#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS GENMASK(15, 0)
237#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\
238 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x)
239#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x)\
240 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x)
241
242#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA BIT(31)
243#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x)\
244 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x)
245#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\
246 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x)
247
248/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */
249#define ANA_AC_SG_CONFIG_REG_1 __REG(TARGET_ANA_AC,\
250 0, 1, 851584, 0, 1, 128, 48, 0, 1, 4)
251
252/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */
253#define ANA_AC_SG_CONFIG_REG_2 __REG(TARGET_ANA_AC,\
254 0, 1, 851584, 0, 1, 128, 52, 0, 1, 4)
255
256/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */
257#define ANA_AC_SG_CONFIG_REG_3 __REG(TARGET_ANA_AC,\
258 0, 1, 851584, 0, 1, 128, 56, 0, 1, 4)
259
260#define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB GENMASK(15, 0)
261#define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\
262 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x)
263#define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x)\
264 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x)
265
266#define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH GENMASK(18, 16)
267#define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x)\
268 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x)
269#define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x)\
270 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x)
271
272#define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
273#define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x)\
274 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x)
275#define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x)\
276 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x)
277
278#define ANA_AC_SG_CONFIG_REG_3_INIT_IPS GENMASK(24, 21)
279#define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x)\
280 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x)
281#define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x)\
282 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x)
283
284#define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25)
285#define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x)\
286 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x)
287#define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x)\
288 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x)
289
290#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA BIT(26)
291#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x)\
292 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x)
293#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x)\
294 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x)
295
296#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX BIT(27)
297#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x)\
298 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x)
299#define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x)\
300 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x)
301
302#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA BIT(28)
303#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x)\
304 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x)
305#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x)\
306 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x)
307
308#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED BIT(29)
309#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x)\
310 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x)
311#define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\
312 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x)
313
314/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */
315#define ANA_AC_SG_CONFIG_REG_4 __REG(TARGET_ANA_AC,\
316 0, 1, 851584, 0, 1, 128, 60, 0, 1, 4)
317
318/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */
319#define ANA_AC_SG_CONFIG_REG_5 __REG(TARGET_ANA_AC,\
320 0, 1, 851584, 0, 1, 128, 64, 0, 1, 4)
321
322/* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */
323#define ANA_AC_SG_GCL_GS_CONFIG(r) __REG(TARGET_ANA_AC,\
324 0, 1, 851584, 0, 1, 128, 0, r, 4, 4)
325
326#define ANA_AC_SG_GCL_GS_CONFIG_IPS GENMASK(3, 0)
327#define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\
328 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_IPS, x)
329#define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x)\
330 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_IPS, x)
331
332#define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE BIT(4)
333#define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x)\
334 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x)
335#define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\
336 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x)
337
338/* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */
339#define ANA_AC_SG_GCL_TI_CONFIG(r) __REG(TARGET_ANA_AC,\
340 0, 1, 851584, 0, 1, 128, 16, r, 4, 4)
341
342/* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */
343#define ANA_AC_SG_GCL_OCT_CONFIG(r) __REG(TARGET_ANA_AC,\
344 0, 1, 851584, 0, 1, 128, 32, r, 4, 4)
345
346/* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */
347#define ANA_AC_SG_STATUS_REG_1 __REG(TARGET_ANA_AC,\
348 0, 1, 839088, 0, 1, 16, 0, 0, 1, 4)
349
350/* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */
351#define ANA_AC_SG_STATUS_REG_2 __REG(TARGET_ANA_AC,\
352 0, 1, 839088, 0, 1, 16, 4, 0, 1, 4)
353
354/* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */
355#define ANA_AC_SG_STATUS_REG_3 __REG(TARGET_ANA_AC,\
356 0, 1, 839088, 0, 1, 16, 8, 0, 1, 4)
357
358#define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB GENMASK(15, 0)
359#define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\
360 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x)
361#define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x)\
362 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x)
363
364#define ANA_AC_SG_STATUS_REG_3_GATE_STATE BIT(16)
365#define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x)\
366 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x)
367#define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x)\
368 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x)
369
370#define ANA_AC_SG_STATUS_REG_3_IPS GENMASK(23, 20)
371#define ANA_AC_SG_STATUS_REG_3_IPS_SET(x)\
372 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_IPS, x)
373#define ANA_AC_SG_STATUS_REG_3_IPS_GET(x)\
374 FIELD_GET(ANA_AC_SG_STATUS_REG_3_IPS, x)
375
376#define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING BIT(24)
377#define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x)\
378 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x)
379#define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x)\
380 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x)
381
382#define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX GENMASK(27, 25)
383#define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x)\
384 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x)
385#define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\
386 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x)
387
388/* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */
389#define ANA_AC_SG_STATUS_REG_4 __REG(TARGET_ANA_AC,\
390 0, 1, 839088, 0, 1, 16, 12, 0, 1, 4)
391
392/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */
393#define ANA_AC_PORT_SGE_CFG(r) __REG(TARGET_ANA_AC,\
394 0, 1, 851552, 0, 1, 20, 0, r, 4, 4)
395
396#define ANA_AC_PORT_SGE_CFG_MASK GENMASK(15, 0)
397#define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\
398 FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x)
399#define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\
400 FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x)
401
402/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */
403#define ANA_AC_STAT_RESET __REG(TARGET_ANA_AC,\
404 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4)
405
406#define ANA_AC_STAT_RESET_RESET BIT(0)
407#define ANA_AC_STAT_RESET_RESET_SET(x)\
408 FIELD_PREP(ANA_AC_STAT_RESET_RESET, x)
409#define ANA_AC_STAT_RESET_RESET_GET(x)\
410 FIELD_GET(ANA_AC_STAT_RESET_RESET, x)
411
412/* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */
413#define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC,\
414 0, 1, 843776, g, 70, 64, 4, r, 4, 4)
415
416#define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4)
417#define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\
418 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
419#define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\
420 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
421
422#define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1)
423#define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\
424 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
425#define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\
426 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
427
428#define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE BIT(0)
429#define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\
430 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
431#define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\
432 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
433
434/* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */
435#define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC,\
436 0, 1, 843776, g, 70, 64, 20, r, 4, 4)
437
438/* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */
439#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r) __REG(TARGET_ANA_AC,\
440 0, 1, 893792, 0, 1, 24, 0, r, 2, 4)
441
442#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE GENMASK(2, 0)
443#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\
444 FIELD_PREP(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x)
445#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\
446 FIELD_GET(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x)
447
448/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */
449#define ANA_AC_ACL_STAT_GLOBAL_CFG(r) __REG(TARGET_ANA_AC,\
450 0, 1, 893792, 0, 1, 24, 8, r, 2, 4)
451
452#define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE BIT(0)
453#define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\
454 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x)
455#define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\
456 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x)
457
458/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */
459#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r) __REG(TARGET_ANA_AC,\
460 0, 1, 893792, 0, 1, 24, 16, r, 2, 4)
461
462#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK GENMASK(3, 0)
463#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\
464 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x)
465#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\
466 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x)
467
468/* ANA_ACL:COMMON:VCAP_S2_CFG */
469#define ANA_ACL_VCAP_S2_CFG(r) __REG(TARGET_ANA_ACL,\
470 0, 1, 32768, 0, 1, 592, 0, r, 70, 4)
471
472#define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28)
473#define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\
474 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x)
475#define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\
476 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x)
477
478#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA GENMASK(27, 26)
479#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\
480 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x)
481#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\
482 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x)
483
484#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA GENMASK(25, 24)
485#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\
486 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x)
487#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\
488 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x)
489
490#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA GENMASK(23, 22)
491#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\
492 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x)
493#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\
494 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x)
495
496#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA GENMASK(21, 20)
497#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\
498 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x)
499#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\
500 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x)
501
502#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA GENMASK(19, 18)
503#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\
504 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x)
505#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\
506 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x)
507
508#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA GENMASK(17, 16)
509#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\
510 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x)
511#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\
512 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x)
513
514#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA GENMASK(15, 14)
515#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\
516 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x)
517#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\
518 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x)
519
520#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA GENMASK(13, 12)
521#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\
522 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x)
523#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\
524 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x)
525
526#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA GENMASK(11, 10)
527#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\
528 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x)
529#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\
530 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x)
531
532#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA GENMASK(9, 8)
533#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\
534 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x)
535#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\
536 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x)
537
538#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA GENMASK(7, 6)
539#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\
540 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x)
541#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\
542 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x)
543
544#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA GENMASK(5, 4)
545#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\
546 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x)
547#define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\
548 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x)
549
550#define ANA_ACL_VCAP_S2_CFG_SEC_ENA GENMASK(3, 0)
551#define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\
552 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x)
553#define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\
554 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x)
555
556/* ANA_ACL:COMMON:SWAP_IP_CTRL */
557#define ANA_ACL_SWAP_IP_CTRL __REG(TARGET_ANA_ACL,\
558 0, 1, 32768, 0, 1, 592, 412, 0, 1, 4)
559
560#define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18)
561#define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\
562 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x)
563#define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\
564 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x)
565
566#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL GENMASK(17, 10)
567#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\
568 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x)
569#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\
570 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x)
571
572#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL GENMASK(9, 2)
573#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\
574 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x)
575#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\
576 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x)
577
578#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA BIT(1)
579#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\
580 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x)
581#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\
582 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x)
583
584#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA BIT(0)
585#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\
586 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x)
587#define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\
588 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x)
589
590/* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */
591#define ANA_ACL_VCAP_S2_RLEG_STAT(r) __REG(TARGET_ANA_ACL,\
592 0, 1, 32768, 0, 1, 592, 424, r, 4, 4)
593
594#define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6)
595#define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\
596 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x)
597#define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\
598 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x)
599
600#define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK GENMASK(5, 0)
601#define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\
602 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x)
603#define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\
604 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x)
605
606/* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */
607#define ANA_ACL_VCAP_S2_FRAGMENT_CFG __REG(TARGET_ANA_ACL,\
608 0, 1, 32768, 0, 1, 592, 440, 0, 1, 4)
609
610#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN GENMASK(9, 5)
611#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\
612 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x)
613#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\
614 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x)
615
616#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS BIT(4)
617#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\
618 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x)
619#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\
620 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x)
621
622#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES GENMASK(3, 0)
623#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\
624 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x)
625#define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\
626 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x)
627
628/* ANA_ACL:COMMON:OWN_UPSID */
629#define ANA_ACL_OWN_UPSID(r) __REG(TARGET_ANA_ACL,\
630 0, 1, 32768, 0, 1, 592, 580, r, 3, 4)
631
632#define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0)
633#define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\
634 FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
635#define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\
636 FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
637
638/* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */
639#define ANA_ACL_VCAP_S2_KEY_SEL(g, r) __REG(TARGET_ANA_ACL,\
640 0, 1, 34200, g, 134, 16, 0, r, 4, 4)
641
642#define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA BIT(13)
643#define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\
644 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x)
645#define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\
646 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x)
647
648#define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL BIT(12)
649#define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\
650 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x)
651#define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\
652 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x)
653
654#define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL GENMASK(11, 10)
655#define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\
656 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x)
657#define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\
658 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x)
659
660#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL GENMASK(9, 8)
661#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\
662 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x)
663#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\
664 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x)
665
666#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL GENMASK(7, 6)
667#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\
668 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x)
669#define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\
670 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x)
671
672#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL GENMASK(5, 3)
673#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\
674 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x)
675#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\
676 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x)
677
678#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL GENMASK(2, 1)
679#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\
680 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x)
681#define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\
682 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x)
683
684#define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL BIT(0)
685#define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\
686 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x)
687#define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\
688 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x)
689
690/* ANA_ACL:CNT_A:CNT_A */
691#define ANA_ACL_CNT_A(g) __REG(TARGET_ANA_ACL,\
692 0, 1, 0, g, 4096, 4, 0, 0, 1, 4)
693
694/* ANA_ACL:CNT_B:CNT_B */
695#define ANA_ACL_CNT_B(g) __REG(TARGET_ANA_ACL,\
696 0, 1, 16384, g, 4096, 4, 0, 0, 1, 4)
697
698/* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */
699#define ANA_ACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_ANA_ACL,\
700 0, 1, 36408, 0, 1, 16, 0, r, 4, 4)
701
702#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY BIT(17)
703#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\
704 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x)
705#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\
706 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x)
707
708#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY BIT(16)
709#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\
710 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x)
711#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\
712 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x)
713
714#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY BIT(15)
715#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\
716 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x)
717#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\
718 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x)
719
720#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY BIT(14)
721#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\
722 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x)
723#define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\
724 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x)
725
726#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY BIT(13)
727#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\
728 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x)
729#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\
730 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x)
731
732#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY BIT(12)
733#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\
734 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x)
735#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\
736 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x)
737
738#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY BIT(11)
739#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\
740 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x)
741#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\
742 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x)
743
744#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(10)
745#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\
746 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
747#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\
748 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
749
750#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(9)
751#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\
752 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
753#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\
754 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
755
756#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY BIT(8)
757#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\
758 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x)
759#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\
760 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x)
761
762#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7)
763#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\
764 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
765#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\
766 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
767
768#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(6)
769#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\
770 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
771#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\
772 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
773
774#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(5)
775#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\
776 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
777#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\
778 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
779
780#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(4)
781#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\
782 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
783#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\
784 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
785
786#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(3)
787#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\
788 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
789#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\
790 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
791
792#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY BIT(2)
793#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\
794 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x)
795#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\
796 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x)
797
798#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY BIT(1)
799#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\
800 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x)
801#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\
802 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x)
803
804#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0)
805#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\
806 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
807#define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\
808 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
809
810/* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */
811#define ANA_AC_POL_POL_UPD_INT_CFG __REG(TARGET_ANA_AC_POL,\
812 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4)
813
814#define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0)
815#define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\
816 FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
817#define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\
818 FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
819
820/* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */
821#define ANA_AC_POL_BDLB_DLB_CTRL __REG(TARGET_ANA_AC_POL,\
822 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4)
823
824#define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19)
825#define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
826 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
827#define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
828 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
829
830#define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4)
831#define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
832 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
833#define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
834 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
835
836#define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA BIT(1)
837#define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\
838 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
839#define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\
840 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
841
842#define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA BIT(0)
843#define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
844 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
845#define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
846 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
847
848/* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */
849#define ANA_AC_POL_SLB_DLB_CTRL __REG(TARGET_ANA_AC_POL,\
850 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4)
851
852#define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19)
853#define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
854 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
855#define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
856 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
857
858#define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4)
859#define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
860 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
861#define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
862 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
863
864#define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA BIT(1)
865#define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\
866 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
867#define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\
868 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
869
870#define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA BIT(0)
871#define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
872 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
873#define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
874 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
875
876/* ANA_AC_SDLB:LBGRP_TBL:XLB_START */
877#define ANA_AC_SDLB_XLB_START(g) __REG(TARGET_ANA_AC_SDLB,\
878 0, 1, 295468, g, 10, 24, 0, 0, 1, 4)
879
880#define ANA_AC_SDLB_XLB_START_LBSET_START GENMASK(12, 0)
881#define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\
882 FIELD_PREP(ANA_AC_SDLB_XLB_START_LBSET_START, x)
883#define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\
884 FIELD_GET(ANA_AC_SDLB_XLB_START_LBSET_START, x)
885
886/* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */
887#define ANA_AC_SDLB_PUP_INTERVAL(g) __REG(TARGET_ANA_AC_SDLB,\
888 0, 1, 295468, g, 10, 24, 4, 0, 1, 4)
889
890#define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL GENMASK(19, 0)
891#define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\
892 FIELD_PREP(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x)
893#define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\
894 FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x)
895
896/* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */
897#define ANA_AC_SDLB_PUP_CTRL(g) __REG(TARGET_ANA_AC_SDLB,\
898 0, 1, 295468, g, 10, 24, 8, 0, 1, 4)
899
900#define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT GENMASK(18, 0)
901#define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\
902 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x)
903#define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x)\
904 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x)
905
906#define ANA_AC_SDLB_PUP_CTRL_PUP_ENA BIT(24)
907#define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x)\
908 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x)
909#define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\
910 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x)
911
912/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */
913#define ANA_AC_SDLB_LBGRP_MISC(g) __REG(TARGET_ANA_AC_SDLB,\
914 0, 1, 295468, g, 10, 24, 12, 0, 1, 4)
915
916#define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT GENMASK(12, 8)
917#define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\
918 FIELD_PREP(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x)
919#define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\
920 FIELD_GET(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x)
921
922/* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */
923#define ANA_AC_SDLB_FRM_RATE_TOKENS(g) __REG(TARGET_ANA_AC_SDLB,\
924 0, 1, 295468, g, 10, 24, 16, 0, 1, 4)
925
926#define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS GENMASK(12, 0)
927#define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\
928 FIELD_PREP(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x)
929#define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\
930 FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x)
931
932/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */
933#define ANA_AC_SDLB_LBGRP_STATE_TBL(g) __REG(TARGET_ANA_AC_SDLB,\
934 0, 1, 295468, g, 10, 24, 20, 0, 1, 4)
935
936#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING BIT(0)
937#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\
938 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x)
939#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x)\
940 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x)
941
942#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK BIT(1)
943#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x)\
944 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x)
945#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\
946 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x)
947
948#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT GENMASK(28, 16)
949#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\
950 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x)
951#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\
952 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x)
953
954/* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */
955#define ANA_AC_SDLB_PUP_TOKENS(g, r) __REG(TARGET_ANA_AC_SDLB,\
956 0, 1, 0, g, 4616, 64, 0, r, 2, 4)
957
958#define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS GENMASK(12, 0)
959#define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\
960 FIELD_PREP(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x)
961#define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\
962 FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x)
963
964/* ANA_AC_SDLB:LBSET_TBL:THRES */
965#define ANA_AC_SDLB_THRES(g, r) __REG(TARGET_ANA_AC_SDLB,\
966 0, 1, 0, g, 4616, 64, 8, r, 2, 4)
967
968#define ANA_AC_SDLB_THRES_THRES GENMASK(9, 0)
969#define ANA_AC_SDLB_THRES_THRES_SET(x)\
970 FIELD_PREP(ANA_AC_SDLB_THRES_THRES, x)
971#define ANA_AC_SDLB_THRES_THRES_GET(x)\
972 FIELD_GET(ANA_AC_SDLB_THRES_THRES, x)
973
974#define ANA_AC_SDLB_THRES_THRES_HYS GENMASK(25, 16)
975#define ANA_AC_SDLB_THRES_THRES_HYS_SET(x)\
976 FIELD_PREP(ANA_AC_SDLB_THRES_THRES_HYS, x)
977#define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\
978 FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x)
979
980/* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */
981#define ANA_AC_SDLB_XLB_NEXT(g) __REG(TARGET_ANA_AC_SDLB,\
982 0, 1, 0, g, 4616, 64, 16, 0, 1, 4)
983
984#define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT GENMASK(12, 0)
985#define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\
986 FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x)
987#define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\
988 FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x)
989
990#define ANA_AC_SDLB_XLB_NEXT_LBGRP GENMASK(27, 24)
991#define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\
992 FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBGRP, x)
993#define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\
994 FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBGRP, x)
995
996/* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */
997#define ANA_AC_SDLB_INH_CTRL(g, r) __REG(TARGET_ANA_AC_SDLB,\
998 0, 1, 0, g, 4616, 64, 20, r, 2, 4)
999
1000#define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX GENMASK(12, 0)
1001#define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\
1002 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x)
1003#define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x)\
1004 FIELD_GET(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x)
1005
1006#define ANA_AC_SDLB_INH_CTRL_INH_MODE GENMASK(21, 20)
1007#define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x)\
1008 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_MODE, x)
1009#define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x)\
1010 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_MODE, x)
1011
1012#define ANA_AC_SDLB_INH_CTRL_INH_LB BIT(24)
1013#define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x)\
1014 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_LB, x)
1015#define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\
1016 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x)
1017
1018/* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */
1019#define ANA_AC_SDLB_INH_LBSET_ADDR(g) __REG(TARGET_ANA_AC_SDLB,\
1020 0, 1, 0, g, 4616, 64, 28, 0, 1, 4)
1021
1022#define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR GENMASK(12, 0)
1023#define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\
1024 FIELD_PREP(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x)
1025#define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\
1026 FIELD_GET(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x)
1027
1028/* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */
1029#define ANA_AC_SDLB_DLB_MISC(g) __REG(TARGET_ANA_AC_SDLB,\
1030 0, 1, 0, g, 4616, 64, 32, 0, 1, 4)
1031
1032#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA BIT(0)
1033#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\
1034 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x)
1035#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x)\
1036 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x)
1037
1038#define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA BIT(6)
1039#define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x)\
1040 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x)
1041#define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x)\
1042 FIELD_GET(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x)
1043
1044#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ GENMASK(14, 8)
1045#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x)\
1046 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x)
1047#define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\
1048 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x)
1049
1050/* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */
1051#define ANA_AC_SDLB_DLB_CFG(g) __REG(TARGET_ANA_AC_SDLB,\
1052 0, 1, 0, g, 4616, 64, 36, 0, 1, 4)
1053
1054#define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA BIT(11)
1055#define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\
1056 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x)
1057#define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x)\
1058 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x)
1059
1060#define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL GENMASK(10, 9)
1061#define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x)\
1062 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x)
1063#define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x)\
1064 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x)
1065
1066#define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS BIT(8)
1067#define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x)\
1068 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x)
1069#define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x)\
1070 FIELD_GET(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x)
1071
1072#define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS BIT(7)
1073#define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x)\
1074 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x)
1075#define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x)\
1076 FIELD_GET(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x)
1077
1078#define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL GENMASK(6, 5)
1079#define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x)\
1080 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x)
1081#define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x)\
1082 FIELD_GET(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x)
1083
1084#define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL GENMASK(4, 3)
1085#define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x)\
1086 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x)
1087#define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x)\
1088 FIELD_GET(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x)
1089
1090#define ANA_AC_SDLB_DLB_CFG_DLB_MODE BIT(2)
1091#define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x)\
1092 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x)
1093#define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x)\
1094 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x)
1095
1096#define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK GENMASK(1, 0)
1097#define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x)\
1098 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x)
1099#define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\
1100 FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x)
1101
1102/* ANA_CL:PORT:FILTER_CTRL */
1103#define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\
1104 0, 1, 131072, g, 70, 512, 4, 0, 1, 4)
1105
1106#define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS BIT(2)
1107#define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\
1108 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
1109#define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\
1110 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
1111
1112#define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS BIT(1)
1113#define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\
1114 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
1115#define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\
1116 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
1117
1118#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA BIT(0)
1119#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\
1120 FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
1121#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\
1122 FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
1123
1124/* ANA_CL:PORT:VLAN_FILTER_CTRL */
1125#define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL,\
1126 0, 1, 131072, g, 70, 512, 8, r, 3, 4)
1127
1128#define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10)
1129#define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\
1130 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
1131#define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\
1132 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
1133
1134#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS BIT(9)
1135#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\
1136 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
1137#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\
1138 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
1139
1140#define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS BIT(8)
1141#define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\
1142 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
1143#define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\
1144 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
1145
1146#define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS BIT(7)
1147#define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\
1148 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
1149#define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\
1150 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
1151
1152#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS BIT(6)
1153#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\
1154 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
1155#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\
1156 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
1157
1158#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS BIT(5)
1159#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\
1160 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
1161#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\
1162 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
1163
1164#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4)
1165#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\
1166 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
1167#define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\
1168 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
1169
1170#define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS BIT(3)
1171#define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\
1172 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
1173#define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\
1174 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
1175
1176#define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS BIT(2)
1177#define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\
1178 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
1179#define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\
1180 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
1181
1182#define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS BIT(1)
1183#define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\
1184 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
1185#define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\
1186 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
1187
1188#define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS BIT(0)
1189#define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\
1190 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
1191#define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\
1192 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
1193
1194/* ANA_CL:PORT:ETAG_FILTER_CTRL */
1195#define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\
1196 0, 1, 131072, g, 70, 512, 20, 0, 1, 4)
1197
1198#define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1)
1199#define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\
1200 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
1201#define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\
1202 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
1203
1204#define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS BIT(0)
1205#define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\
1206 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
1207#define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\
1208 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
1209
1210/* ANA_CL:PORT:VLAN_CTRL */
1211#define ANA_CL_VLAN_CTRL(g) __REG(TARGET_ANA_CL,\
1212 0, 1, 131072, g, 70, 512, 32, 0, 1, 4)
1213
1214#define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26)
1215#define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\
1216 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
1217#define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\
1218 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
1219
1220#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP GENMASK(25, 23)
1221#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\
1222 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
1223#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\
1224 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
1225
1226#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI BIT(22)
1227#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\
1228 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
1229#define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\
1230 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
1231
1232#define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA BIT(21)
1233#define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\
1234 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
1235#define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\
1236 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
1237
1238#define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL BIT(20)
1239#define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\
1240 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
1241#define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\
1242 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
1243
1244#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA BIT(19)
1245#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\
1246 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
1247#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\
1248 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
1249
1250#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT GENMASK(18, 17)
1251#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\
1252 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
1253#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\
1254 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
1255
1256#define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE BIT(16)
1257#define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\
1258 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
1259#define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\
1260 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
1261
1262#define ANA_CL_VLAN_CTRL_PORT_PCP GENMASK(15, 13)
1263#define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\
1264 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x)
1265#define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\
1266 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x)
1267
1268#define ANA_CL_VLAN_CTRL_PORT_DEI BIT(12)
1269#define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\
1270 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x)
1271#define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\
1272 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x)
1273
1274#define ANA_CL_VLAN_CTRL_PORT_VID GENMASK(11, 0)
1275#define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\
1276 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x)
1277#define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\
1278 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x)
1279
1280/* ANA_CL:PORT:VLAN_CTRL_2 */
1281#define ANA_CL_VLAN_CTRL_2(g) __REG(TARGET_ANA_CL,\
1282 0, 1, 131072, g, 70, 512, 36, 0, 1, 4)
1283
1284#define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0)
1285#define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\
1286 FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
1287#define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\
1288 FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
1289
1290/* ANA_CL:PORT:PCP_DEI_MAP_CFG */
1291#define ANA_CL_PCP_DEI_MAP_CFG(g, r) __REG(TARGET_ANA_CL,\
1292 0, 1, 131072, g, 70, 512, 108, r, 16, 4)
1293
1294#define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL GENMASK(4, 3)
1295#define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\
1296 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x)
1297#define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x)\
1298 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x)
1299
1300#define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL GENMASK(2, 0)
1301#define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x)\
1302 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x)
1303#define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\
1304 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x)
1305
1306/* ANA_CL:PORT:QOS_CFG */
1307#define ANA_CL_QOS_CFG(g) __REG(TARGET_ANA_CL,\
1308 0, 1, 131072, g, 70, 512, 172, 0, 1, 4)
1309
1310#define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA BIT(17)
1311#define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\
1312 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x)
1313#define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x)\
1314 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x)
1315
1316#define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL GENMASK(16, 14)
1317#define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x)\
1318 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x)
1319#define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x)\
1320 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x)
1321
1322#define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL GENMASK(13, 12)
1323#define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x)\
1324 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x)
1325#define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x)\
1326 FIELD_GET(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x)
1327
1328#define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA BIT(11)
1329#define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x)\
1330 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x)
1331#define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x)\
1332 FIELD_GET(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x)
1333
1334#define ANA_CL_QOS_CFG_DSCP_KEEP_ENA BIT(10)
1335#define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x)\
1336 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x)
1337#define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x)\
1338 FIELD_GET(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x)
1339
1340#define ANA_CL_QOS_CFG_KEEP_ENA BIT(9)
1341#define ANA_CL_QOS_CFG_KEEP_ENA_SET(x)\
1342 FIELD_PREP(ANA_CL_QOS_CFG_KEEP_ENA, x)
1343#define ANA_CL_QOS_CFG_KEEP_ENA_GET(x)\
1344 FIELD_GET(ANA_CL_QOS_CFG_KEEP_ENA, x)
1345
1346#define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA BIT(8)
1347#define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x)\
1348 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x)
1349#define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x)\
1350 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x)
1351
1352#define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA BIT(7)
1353#define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x)\
1354 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x)
1355#define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x)\
1356 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x)
1357
1358#define ANA_CL_QOS_CFG_DSCP_DP_ENA BIT(6)
1359#define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x)\
1360 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_DP_ENA, x)
1361#define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x)\
1362 FIELD_GET(ANA_CL_QOS_CFG_DSCP_DP_ENA, x)
1363
1364#define ANA_CL_QOS_CFG_DSCP_QOS_ENA BIT(5)
1365#define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x)\
1366 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x)
1367#define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x)\
1368 FIELD_GET(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x)
1369
1370#define ANA_CL_QOS_CFG_DEFAULT_DP_VAL GENMASK(4, 3)
1371#define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x)\
1372 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x)
1373#define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x)\
1374 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x)
1375
1376#define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL GENMASK(2, 0)
1377#define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x)\
1378 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x)
1379#define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\
1380 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x)
1381
1382/* ANA_CL:PORT:CAPTURE_BPDU_CFG */
1383#define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL,\
1384 0, 1, 131072, g, 70, 512, 196, 0, 1, 4)
1385
1386/* ANA_CL:PORT:ADV_CL_CFG_2 */
1387#define ANA_CL_ADV_CL_CFG_2(g, r) __REG(TARGET_ANA_CL,\
1388 0, 1, 131072, g, 70, 512, 200, r, 6, 4)
1389
1390#define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA BIT(1)
1391#define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\
1392 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x)
1393#define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_GET(x)\
1394 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x)
1395
1396#define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA BIT(0)
1397#define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_SET(x)\
1398 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x)
1399#define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\
1400 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x)
1401
1402/* ANA_CL:PORT:ADV_CL_CFG */
1403#define ANA_CL_ADV_CL_CFG(g, r) __REG(TARGET_ANA_CL,\
1404 0, 1, 131072, g, 70, 512, 224, r, 6, 4)
1405
1406#define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL GENMASK(30, 26)
1407#define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\
1408 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x)
1409#define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(x)\
1410 FIELD_GET(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x)
1411
1412#define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL GENMASK(25, 21)
1413#define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(x)\
1414 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x)
1415#define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(x)\
1416 FIELD_GET(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x)
1417
1418#define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL GENMASK(20, 16)
1419#define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_SET(x)\
1420 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x)
1421#define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_GET(x)\
1422 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x)
1423
1424#define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL GENMASK(15, 11)
1425#define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(x)\
1426 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x)
1427#define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_GET(x)\
1428 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x)
1429
1430#define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL GENMASK(10, 6)
1431#define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(x)\
1432 FIELD_PREP(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x)
1433#define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_GET(x)\
1434 FIELD_GET(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x)
1435
1436#define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL GENMASK(5, 1)
1437#define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(x)\
1438 FIELD_PREP(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x)
1439#define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_GET(x)\
1440 FIELD_GET(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x)
1441
1442#define ANA_CL_ADV_CL_CFG_LOOKUP_ENA BIT(0)
1443#define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(x)\
1444 FIELD_PREP(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x)
1445#define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\
1446 FIELD_GET(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x)
1447
1448/* ANA_CL:COMMON:OWN_UPSID */
1449#define ANA_CL_OWN_UPSID(r) __REG(TARGET_ANA_CL,\
1450 0, 1, 166912, 0, 1, 756, 0, r, 3, 4)
1451
1452#define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0)
1453#define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\
1454 FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x)
1455#define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\
1456 FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x)
1457
1458/* ANA_CL:COMMON:DSCP_CFG */
1459#define ANA_CL_DSCP_CFG(r) __REG(TARGET_ANA_CL,\
1460 0, 1, 166912, 0, 1, 756, 256, r, 64, 4)
1461
1462#define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL GENMASK(12, 7)
1463#define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\
1464 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x)
1465#define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x)\
1466 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x)
1467
1468#define ANA_CL_DSCP_CFG_DSCP_QOS_VAL GENMASK(6, 4)
1469#define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x)\
1470 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x)
1471#define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x)\
1472 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x)
1473
1474#define ANA_CL_DSCP_CFG_DSCP_DP_VAL GENMASK(3, 2)
1475#define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x)\
1476 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x)
1477#define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x)\
1478 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x)
1479
1480#define ANA_CL_DSCP_CFG_DSCP_REWR_ENA BIT(1)
1481#define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x)\
1482 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x)
1483#define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x)\
1484 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x)
1485
1486#define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA BIT(0)
1487#define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\
1488 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x)
1489#define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\
1490 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x)
1491
1492/* ANA_CL:COMMON:QOS_MAP_CFG */
1493#define ANA_CL_QOS_MAP_CFG(r) __REG(TARGET_ANA_CL,\
1494 0, 1, 166912, 0, 1, 756, 512, r, 32, 4)
1495
1496#define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL GENMASK(9, 4)
1497#define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\
1498 FIELD_PREP(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x)
1499#define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\
1500 FIELD_GET(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x)
1501
1502/* ANA_L2:COMMON:FWD_CFG */
1503#define ANA_L2_FWD_CFG __REG(TARGET_ANA_L2,\
1504 0, 1, 566024, 0, 1, 700, 0, 0, 1, 4)
1505
1506#define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL GENMASK(21, 20)
1507#define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\
1508 FIELD_PREP(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x)
1509#define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_GET(x)\
1510 FIELD_GET(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x)
1511
1512#define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA BIT(18)
1513#define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_SET(x)\
1514 FIELD_PREP(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x)
1515#define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_GET(x)\
1516 FIELD_GET(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x)
1517
1518#define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA BIT(17)
1519#define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_SET(x)\
1520 FIELD_PREP(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x)
1521#define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_GET(x)\
1522 FIELD_GET(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x)
1523
1524#define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA BIT(16)
1525#define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(x)\
1526 FIELD_PREP(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x)
1527#define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_GET(x)\
1528 FIELD_GET(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x)
1529
1530#define ANA_L2_FWD_CFG_CPU_DMAC_QU GENMASK(10, 8)
1531#define ANA_L2_FWD_CFG_CPU_DMAC_QU_SET(x)\
1532 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_QU, x)
1533#define ANA_L2_FWD_CFG_CPU_DMAC_QU_GET(x)\
1534 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_QU, x)
1535
1536#define ANA_L2_FWD_CFG_LOOPBACK_ENA BIT(7)
1537#define ANA_L2_FWD_CFG_LOOPBACK_ENA_SET(x)\
1538 FIELD_PREP(ANA_L2_FWD_CFG_LOOPBACK_ENA, x)
1539#define ANA_L2_FWD_CFG_LOOPBACK_ENA_GET(x)\
1540 FIELD_GET(ANA_L2_FWD_CFG_LOOPBACK_ENA, x)
1541
1542#define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6)
1543#define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x)\
1544 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)
1545#define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x)\
1546 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)
1547
1548#define ANA_L2_FWD_CFG_FILTER_MODE_SEL BIT(4)
1549#define ANA_L2_FWD_CFG_FILTER_MODE_SEL_SET(x)\
1550 FIELD_PREP(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x)
1551#define ANA_L2_FWD_CFG_FILTER_MODE_SEL_GET(x)\
1552 FIELD_GET(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x)
1553
1554#define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA BIT(3)
1555#define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_SET(x)\
1556 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x)
1557#define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_GET(x)\
1558 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x)
1559
1560#define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA BIT(2)
1561#define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_SET(x)\
1562 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x)
1563#define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_GET(x)\
1564 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x)
1565
1566#define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA BIT(1)
1567#define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_SET(x)\
1568 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x)
1569#define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_GET(x)\
1570 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x)
1571
1572#define ANA_L2_FWD_CFG_FWD_ENA BIT(0)
1573#define ANA_L2_FWD_CFG_FWD_ENA_SET(x)\
1574 FIELD_PREP(ANA_L2_FWD_CFG_FWD_ENA, x)
1575#define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\
1576 FIELD_GET(ANA_L2_FWD_CFG_FWD_ENA, x)
1577
1578/* ANA_L2:COMMON:AUTO_LRN_CFG */
1579#define ANA_L2_AUTO_LRN_CFG __REG(TARGET_ANA_L2,\
1580 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4)
1581
1582/* ANA_L2:COMMON:AUTO_LRN_CFG1 */
1583#define ANA_L2_AUTO_LRN_CFG1 __REG(TARGET_ANA_L2,\
1584 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4)
1585
1586/* ANA_L2:COMMON:AUTO_LRN_CFG2 */
1587#define ANA_L2_AUTO_LRN_CFG2 __REG(TARGET_ANA_L2,\
1588 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4)
1589
1590#define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 BIT(0)
1591#define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\
1592 FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
1593#define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\
1594 FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
1595
1596/* ANA_L2:COMMON:OWN_UPSID */
1597#define ANA_L2_OWN_UPSID(r) __REG(TARGET_ANA_L2,\
1598 0, 1, 566024, 0, 1, 700, 672, r, 3, 4)
1599
1600#define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0)
1601#define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\
1602 FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x)
1603#define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\
1604 FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x)
1605
1606/* ANA_L2:ISDX:DLB_CFG */
1607#define ANA_L2_DLB_CFG(g) __REG(TARGET_ANA_L2,\
1608 0, 1, 0, g, 4096, 128, 56, 0, 1, 4)
1609
1610#define ANA_L2_DLB_CFG_DLB_IDX GENMASK(12, 0)
1611#define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\
1612 FIELD_PREP(ANA_L2_DLB_CFG_DLB_IDX, x)
1613#define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\
1614 FIELD_GET(ANA_L2_DLB_CFG_DLB_IDX, x)
1615
1616/* ANA_L2:ISDX:TSN_CFG */
1617#define ANA_L2_TSN_CFG(g) __REG(TARGET_ANA_L2,\
1618 0, 1, 0, g, 4096, 128, 100, 0, 1, 4)
1619
1620#define ANA_L2_TSN_CFG_TSN_SFID GENMASK(9, 0)
1621#define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\
1622 FIELD_PREP(ANA_L2_TSN_CFG_TSN_SFID, x)
1623#define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\
1624 FIELD_GET(ANA_L2_TSN_CFG_TSN_SFID, x)
1625
1626/* ANA_L3:COMMON:VLAN_CTRL */
1627#define ANA_L3_VLAN_CTRL __REG(TARGET_ANA_L3,\
1628 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4)
1629
1630#define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0)
1631#define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\
1632 FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
1633#define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\
1634 FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
1635
1636/* ANA_L3:VLAN:VLAN_CFG */
1637#define ANA_L3_VLAN_CFG(g) __REG(TARGET_ANA_L3,\
1638 0, 1, 0, g, 5120, 64, 8, 0, 1, 4)
1639
1640#define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24)
1641#define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\
1642 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
1643#define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\
1644 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
1645
1646#define ANA_L3_VLAN_CFG_VLAN_FID GENMASK(20, 8)
1647#define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\
1648 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x)
1649#define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\
1650 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x)
1651
1652#define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA BIT(6)
1653#define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\
1654 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
1655#define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\
1656 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
1657
1658#define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA BIT(5)
1659#define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\
1660 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
1661#define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\
1662 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
1663
1664#define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS BIT(4)
1665#define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\
1666 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
1667#define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\
1668 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
1669
1670#define ANA_L3_VLAN_CFG_VLAN_LRN_DIS BIT(3)
1671#define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\
1672 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
1673#define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\
1674 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
1675
1676#define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA BIT(2)
1677#define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\
1678 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
1679#define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\
1680 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
1681
1682#define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA BIT(1)
1683#define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\
1684 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
1685#define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\
1686 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
1687
1688#define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA BIT(0)
1689#define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\
1690 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
1691#define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\
1692 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
1693
1694/* ANA_L3:VLAN:VLAN_MASK_CFG */
1695#define ANA_L3_VLAN_MASK_CFG(g) __REG(TARGET_ANA_L3,\
1696 0, 1, 0, g, 5120, 64, 16, 0, 1, 4)
1697
1698/* ANA_L3:VLAN:VLAN_MASK_CFG1 */
1699#define ANA_L3_VLAN_MASK_CFG1(g) __REG(TARGET_ANA_L3,\
1700 0, 1, 0, g, 5120, 64, 20, 0, 1, 4)
1701
1702/* ANA_L3:VLAN:VLAN_MASK_CFG2 */
1703#define ANA_L3_VLAN_MASK_CFG2(g) __REG(TARGET_ANA_L3,\
1704 0, 1, 0, g, 5120, 64, 24, 0, 1, 4)
1705
1706#define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 BIT(0)
1707#define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\
1708 FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
1709#define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\
1710 FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
1711
1712/* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */
1713#define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM,\
1714 0, 1, 0, g, 65, 512, 0, 0, 1, 4)
1715
1716/* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */
1717#define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\
1718 0, 1, 0, g, 65, 512, 4, 0, 1, 4)
1719
1720/* ASM:DEV_STATISTICS:RX_PAUSE_CNT */
1721#define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\
1722 0, 1, 0, g, 65, 512, 8, 0, 1, 4)
1723
1724/* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */
1725#define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\
1726 0, 1, 0, g, 65, 512, 12, 0, 1, 4)
1727
1728/* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */
1729#define ASM_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\
1730 0, 1, 0, g, 65, 512, 16, 0, 1, 4)
1731
1732/* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */
1733#define ASM_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\
1734 0, 1, 0, g, 65, 512, 20, 0, 1, 4)
1735
1736/* ASM:DEV_STATISTICS:RX_UC_CNT */
1737#define ASM_RX_UC_CNT(g) __REG(TARGET_ASM,\
1738 0, 1, 0, g, 65, 512, 24, 0, 1, 4)
1739
1740/* ASM:DEV_STATISTICS:RX_MC_CNT */
1741#define ASM_RX_MC_CNT(g) __REG(TARGET_ASM,\
1742 0, 1, 0, g, 65, 512, 28, 0, 1, 4)
1743
1744/* ASM:DEV_STATISTICS:RX_BC_CNT */
1745#define ASM_RX_BC_CNT(g) __REG(TARGET_ASM,\
1746 0, 1, 0, g, 65, 512, 32, 0, 1, 4)
1747
1748/* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */
1749#define ASM_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\
1750 0, 1, 0, g, 65, 512, 36, 0, 1, 4)
1751
1752/* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */
1753#define ASM_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\
1754 0, 1, 0, g, 65, 512, 40, 0, 1, 4)
1755
1756/* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */
1757#define ASM_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\
1758 0, 1, 0, g, 65, 512, 44, 0, 1, 4)
1759
1760/* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */
1761#define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\
1762 0, 1, 0, g, 65, 512, 48, 0, 1, 4)
1763
1764/* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */
1765#define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\
1766 0, 1, 0, g, 65, 512, 52, 0, 1, 4)
1767
1768/* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */
1769#define ASM_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\
1770 0, 1, 0, g, 65, 512, 56, 0, 1, 4)
1771
1772/* ASM:DEV_STATISTICS:RX_JABBERS_CNT */
1773#define ASM_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\
1774 0, 1, 0, g, 65, 512, 60, 0, 1, 4)
1775
1776/* ASM:DEV_STATISTICS:RX_SIZE64_CNT */
1777#define ASM_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\
1778 0, 1, 0, g, 65, 512, 64, 0, 1, 4)
1779
1780/* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */
1781#define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\
1782 0, 1, 0, g, 65, 512, 68, 0, 1, 4)
1783
1784/* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */
1785#define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\
1786 0, 1, 0, g, 65, 512, 72, 0, 1, 4)
1787
1788/* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */
1789#define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\
1790 0, 1, 0, g, 65, 512, 76, 0, 1, 4)
1791
1792/* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */
1793#define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\
1794 0, 1, 0, g, 65, 512, 80, 0, 1, 4)
1795
1796/* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */
1797#define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\
1798 0, 1, 0, g, 65, 512, 84, 0, 1, 4)
1799
1800/* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */
1801#define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\
1802 0, 1, 0, g, 65, 512, 88, 0, 1, 4)
1803
1804/* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */
1805#define ASM_RX_IPG_SHRINK_CNT(g) __REG(TARGET_ASM,\
1806 0, 1, 0, g, 65, 512, 92, 0, 1, 4)
1807
1808/* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */
1809#define ASM_TX_OUT_BYTES_CNT(g) __REG(TARGET_ASM,\
1810 0, 1, 0, g, 65, 512, 96, 0, 1, 4)
1811
1812/* ASM:DEV_STATISTICS:TX_PAUSE_CNT */
1813#define ASM_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\
1814 0, 1, 0, g, 65, 512, 100, 0, 1, 4)
1815
1816/* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */
1817#define ASM_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\
1818 0, 1, 0, g, 65, 512, 104, 0, 1, 4)
1819
1820/* ASM:DEV_STATISTICS:TX_UC_CNT */
1821#define ASM_TX_UC_CNT(g) __REG(TARGET_ASM,\
1822 0, 1, 0, g, 65, 512, 108, 0, 1, 4)
1823
1824/* ASM:DEV_STATISTICS:TX_MC_CNT */
1825#define ASM_TX_MC_CNT(g) __REG(TARGET_ASM,\
1826 0, 1, 0, g, 65, 512, 112, 0, 1, 4)
1827
1828/* ASM:DEV_STATISTICS:TX_BC_CNT */
1829#define ASM_TX_BC_CNT(g) __REG(TARGET_ASM,\
1830 0, 1, 0, g, 65, 512, 116, 0, 1, 4)
1831
1832/* ASM:DEV_STATISTICS:TX_SIZE64_CNT */
1833#define ASM_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\
1834 0, 1, 0, g, 65, 512, 120, 0, 1, 4)
1835
1836/* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */
1837#define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\
1838 0, 1, 0, g, 65, 512, 124, 0, 1, 4)
1839
1840/* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */
1841#define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\
1842 0, 1, 0, g, 65, 512, 128, 0, 1, 4)
1843
1844/* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */
1845#define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\
1846 0, 1, 0, g, 65, 512, 132, 0, 1, 4)
1847
1848/* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */
1849#define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\
1850 0, 1, 0, g, 65, 512, 136, 0, 1, 4)
1851
1852/* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */
1853#define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\
1854 0, 1, 0, g, 65, 512, 140, 0, 1, 4)
1855
1856/* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */
1857#define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\
1858 0, 1, 0, g, 65, 512, 144, 0, 1, 4)
1859
1860/* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */
1861#define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\
1862 0, 1, 0, g, 65, 512, 148, 0, 1, 4)
1863
1864/* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */
1865#define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\
1866 0, 1, 0, g, 65, 512, 152, 0, 1, 4)
1867
1868/* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */
1869#define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\
1870 0, 1, 0, g, 65, 512, 156, 0, 1, 4)
1871
1872/* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */
1873#define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\
1874 0, 1, 0, g, 65, 512, 160, 0, 1, 4)
1875
1876/* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */
1877#define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\
1878 0, 1, 0, g, 65, 512, 164, 0, 1, 4)
1879
1880/* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */
1881#define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\
1882 0, 1, 0, g, 65, 512, 168, 0, 1, 4)
1883
1884/* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */
1885#define ASM_PMAC_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\
1886 0, 1, 0, g, 65, 512, 172, 0, 1, 4)
1887
1888/* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */
1889#define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\
1890 0, 1, 0, g, 65, 512, 176, 0, 1, 4)
1891
1892/* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */
1893#define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\
1894 0, 1, 0, g, 65, 512, 180, 0, 1, 4)
1895
1896/* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */
1897#define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\
1898 0, 1, 0, g, 65, 512, 184, 0, 1, 4)
1899
1900/* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */
1901#define ASM_PMAC_RX_UC_CNT(g) __REG(TARGET_ASM,\
1902 0, 1, 0, g, 65, 512, 188, 0, 1, 4)
1903
1904/* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */
1905#define ASM_PMAC_RX_MC_CNT(g) __REG(TARGET_ASM,\
1906 0, 1, 0, g, 65, 512, 192, 0, 1, 4)
1907
1908/* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */
1909#define ASM_PMAC_RX_BC_CNT(g) __REG(TARGET_ASM,\
1910 0, 1, 0, g, 65, 512, 196, 0, 1, 4)
1911
1912/* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */
1913#define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\
1914 0, 1, 0, g, 65, 512, 200, 0, 1, 4)
1915
1916/* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */
1917#define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\
1918 0, 1, 0, g, 65, 512, 204, 0, 1, 4)
1919
1920/* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */
1921#define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\
1922 0, 1, 0, g, 65, 512, 208, 0, 1, 4)
1923
1924/* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */
1925#define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\
1926 0, 1, 0, g, 65, 512, 212, 0, 1, 4)
1927
1928/* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */
1929#define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\
1930 0, 1, 0, g, 65, 512, 216, 0, 1, 4)
1931
1932/* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */
1933#define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\
1934 0, 1, 0, g, 65, 512, 220, 0, 1, 4)
1935
1936/* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */
1937#define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\
1938 0, 1, 0, g, 65, 512, 224, 0, 1, 4)
1939
1940/* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */
1941#define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\
1942 0, 1, 0, g, 65, 512, 228, 0, 1, 4)
1943
1944/* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */
1945#define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\
1946 0, 1, 0, g, 65, 512, 232, 0, 1, 4)
1947
1948/* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */
1949#define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\
1950 0, 1, 0, g, 65, 512, 236, 0, 1, 4)
1951
1952/* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */
1953#define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\
1954 0, 1, 0, g, 65, 512, 240, 0, 1, 4)
1955
1956/* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */
1957#define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\
1958 0, 1, 0, g, 65, 512, 244, 0, 1, 4)
1959
1960/* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */
1961#define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\
1962 0, 1, 0, g, 65, 512, 248, 0, 1, 4)
1963
1964/* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */
1965#define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\
1966 0, 1, 0, g, 65, 512, 252, 0, 1, 4)
1967
1968/* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */
1969#define ASM_PMAC_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\
1970 0, 1, 0, g, 65, 512, 256, 0, 1, 4)
1971
1972/* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */
1973#define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\
1974 0, 1, 0, g, 65, 512, 260, 0, 1, 4)
1975
1976/* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */
1977#define ASM_PMAC_TX_UC_CNT(g) __REG(TARGET_ASM,\
1978 0, 1, 0, g, 65, 512, 264, 0, 1, 4)
1979
1980/* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */
1981#define ASM_PMAC_TX_MC_CNT(g) __REG(TARGET_ASM,\
1982 0, 1, 0, g, 65, 512, 268, 0, 1, 4)
1983
1984/* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */
1985#define ASM_PMAC_TX_BC_CNT(g) __REG(TARGET_ASM,\
1986 0, 1, 0, g, 65, 512, 272, 0, 1, 4)
1987
1988/* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */
1989#define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\
1990 0, 1, 0, g, 65, 512, 276, 0, 1, 4)
1991
1992/* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */
1993#define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\
1994 0, 1, 0, g, 65, 512, 280, 0, 1, 4)
1995
1996/* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */
1997#define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\
1998 0, 1, 0, g, 65, 512, 284, 0, 1, 4)
1999
2000/* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */
2001#define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\
2002 0, 1, 0, g, 65, 512, 288, 0, 1, 4)
2003
2004/* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */
2005#define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\
2006 0, 1, 0, g, 65, 512, 292, 0, 1, 4)
2007
2008/* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */
2009#define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\
2010 0, 1, 0, g, 65, 512, 296, 0, 1, 4)
2011
2012/* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */
2013#define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\
2014 0, 1, 0, g, 65, 512, 300, 0, 1, 4)
2015
2016/* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */
2017#define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\
2018 0, 1, 0, g, 65, 512, 304, 0, 1, 4)
2019
2020/* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */
2021#define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM,\
2022 0, 1, 0, g, 65, 512, 308, 0, 1, 4)
2023
2024/* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */
2025#define ASM_MM_RX_SMD_ERR_CNT(g) __REG(TARGET_ASM,\
2026 0, 1, 0, g, 65, 512, 312, 0, 1, 4)
2027
2028/* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */
2029#define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM,\
2030 0, 1, 0, g, 65, 512, 316, 0, 1, 4)
2031
2032/* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */
2033#define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM,\
2034 0, 1, 0, g, 65, 512, 320, 0, 1, 4)
2035
2036/* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */
2037#define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM,\
2038 0, 1, 0, g, 65, 512, 324, 0, 1, 4)
2039
2040/* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */
2041#define ASM_TX_MULTI_COLL_CNT(g) __REG(TARGET_ASM,\
2042 0, 1, 0, g, 65, 512, 328, 0, 1, 4)
2043
2044/* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */
2045#define ASM_TX_LATE_COLL_CNT(g) __REG(TARGET_ASM,\
2046 0, 1, 0, g, 65, 512, 332, 0, 1, 4)
2047
2048/* ASM:DEV_STATISTICS:TX_XCOLL_CNT */
2049#define ASM_TX_XCOLL_CNT(g) __REG(TARGET_ASM,\
2050 0, 1, 0, g, 65, 512, 336, 0, 1, 4)
2051
2052/* ASM:DEV_STATISTICS:TX_DEFER_CNT */
2053#define ASM_TX_DEFER_CNT(g) __REG(TARGET_ASM,\
2054 0, 1, 0, g, 65, 512, 340, 0, 1, 4)
2055
2056/* ASM:DEV_STATISTICS:TX_XDEFER_CNT */
2057#define ASM_TX_XDEFER_CNT(g) __REG(TARGET_ASM,\
2058 0, 1, 0, g, 65, 512, 344, 0, 1, 4)
2059
2060/* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */
2061#define ASM_TX_BACKOFF1_CNT(g) __REG(TARGET_ASM,\
2062 0, 1, 0, g, 65, 512, 348, 0, 1, 4)
2063
2064/* ASM:DEV_STATISTICS:TX_CSENSE_CNT */
2065#define ASM_TX_CSENSE_CNT(g) __REG(TARGET_ASM,\
2066 0, 1, 0, g, 65, 512, 352, 0, 1, 4)
2067
2068/* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */
2069#define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\
2070 0, 1, 0, g, 65, 512, 356, 0, 1, 4)
2071
2072#define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0)
2073#define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\
2074 FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2075#define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\
2076 FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2077
2078/* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */
2079#define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\
2080 0, 1, 0, g, 65, 512, 360, 0, 1, 4)
2081
2082#define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0)
2083#define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\
2084 FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2085#define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\
2086 FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2087
2088/* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */
2089#define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\
2090 0, 1, 0, g, 65, 512, 364, 0, 1, 4)
2091
2092#define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0)
2093#define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\
2094 FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2095#define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\
2096 FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2097
2098/* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */
2099#define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\
2100 0, 1, 0, g, 65, 512, 368, 0, 1, 4)
2101
2102#define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0)
2103#define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\
2104 FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2105#define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\
2106 FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2107
2108/* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */
2109#define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\
2110 0, 1, 0, g, 65, 512, 372, 0, 1, 4)
2111
2112#define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0)
2113#define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\
2114 FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2115#define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\
2116 FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2117
2118/* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */
2119#define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\
2120 0, 1, 0, g, 65, 512, 376, 0, 1, 4)
2121
2122#define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0)
2123#define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\
2124 FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2125#define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\
2126 FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2127
2128/* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */
2129#define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\
2130 0, 1, 0, g, 65, 512, 380, 0, 1, 4)
2131
2132#define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0)
2133#define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\
2134 FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2135#define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\
2136 FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2137
2138/* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */
2139#define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\
2140 0, 1, 0, g, 65, 512, 384, 0, 1, 4)
2141
2142#define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0)
2143#define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\
2144 FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2145#define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\
2146 FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2147
2148/* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */
2149#define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM,\
2150 0, 1, 0, g, 65, 512, 388, 0, 1, 4)
2151
2152/* ASM:CFG:STAT_CFG */
2153#define ASM_STAT_CFG __REG(TARGET_ASM,\
2154 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4)
2155
2156#define ASM_STAT_CFG_STAT_CNT_CLR_SHOT BIT(0)
2157#define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\
2158 FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
2159#define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\
2160 FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
2161
2162/* ASM:CFG:PORT_CFG */
2163#define ASM_PORT_CFG(r) __REG(TARGET_ASM,\
2164 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4)
2165
2166#define ASM_PORT_CFG_CSC_STAT_DIS BIT(12)
2167#define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\
2168 FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x)
2169#define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\
2170 FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x)
2171
2172#define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA BIT(11)
2173#define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\
2174 FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
2175#define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\
2176 FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
2177
2178#define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA BIT(10)
2179#define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\
2180 FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
2181#define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\
2182 FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
2183
2184#define ASM_PORT_CFG_NO_PREAMBLE_ENA BIT(9)
2185#define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\
2186 FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
2187#define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\
2188 FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
2189
2190#define ASM_PORT_CFG_SKIP_PREAMBLE_ENA BIT(8)
2191#define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\
2192 FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
2193#define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\
2194 FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
2195
2196#define ASM_PORT_CFG_FRM_AGING_DIS BIT(7)
2197#define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\
2198 FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x)
2199#define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\
2200 FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x)
2201
2202#define ASM_PORT_CFG_PAD_ENA BIT(6)
2203#define ASM_PORT_CFG_PAD_ENA_SET(x)\
2204 FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x)
2205#define ASM_PORT_CFG_PAD_ENA_GET(x)\
2206 FIELD_GET(ASM_PORT_CFG_PAD_ENA, x)
2207
2208#define ASM_PORT_CFG_INJ_DISCARD_CFG GENMASK(5, 4)
2209#define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\
2210 FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
2211#define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\
2212 FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
2213
2214#define ASM_PORT_CFG_INJ_FORMAT_CFG GENMASK(3, 2)
2215#define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\
2216 FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
2217#define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\
2218 FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
2219
2220#define ASM_PORT_CFG_VSTAX2_AWR_ENA BIT(1)
2221#define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\
2222 FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
2223#define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\
2224 FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
2225
2226#define ASM_PORT_CFG_PFRM_FLUSH BIT(0)
2227#define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\
2228 FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x)
2229#define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\
2230 FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x)
2231
2232/* ASM:RAM_CTRL:RAM_INIT */
2233#define ASM_RAM_INIT __REG(TARGET_ASM,\
2234 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4)
2235
2236#define ASM_RAM_INIT_RAM_INIT BIT(1)
2237#define ASM_RAM_INIT_RAM_INIT_SET(x)\
2238 FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x)
2239#define ASM_RAM_INIT_RAM_INIT_GET(x)\
2240 FIELD_GET(ASM_RAM_INIT_RAM_INIT, x)
2241
2242#define ASM_RAM_INIT_RAM_CFG_HOOK BIT(0)
2243#define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\
2244 FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x)
2245#define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\
2246 FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x)
2247
2248/* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */
2249#define CLKGEN_LCPLL1_CORE_CLK_CFG __REG(TARGET_CLKGEN,\
2250 0, 1, 12, 0, 1, 36, 0, 0, 1, 4)
2251
2252#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0)
2253#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\
2254 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
2255#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\
2256 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
2257
2258#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV GENMASK(10, 8)
2259#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\
2260 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
2261#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\
2262 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
2263
2264#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR BIT(11)
2265#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\
2266 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
2267#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\
2268 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
2269
2270#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL GENMASK(13, 12)
2271#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\
2272 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
2273#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\
2274 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
2275
2276#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA BIT(14)
2277#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\
2278 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
2279#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\
2280 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
2281
2282#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA BIT(15)
2283#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\
2284 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
2285#define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\
2286 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
2287
2288/* CPU:CPU_REGS:PROC_CTRL */
2289#define CPU_PROC_CTRL __REG(TARGET_CPU,\
2290 0, 1, 0, 0, 1, 204, 176, 0, 1, 4)
2291
2292#define CPU_PROC_CTRL_AARCH64_MODE_ENA BIT(12)
2293#define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\
2294 FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
2295#define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\
2296 FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
2297
2298#define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS BIT(11)
2299#define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\
2300 FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
2301#define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\
2302 FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
2303
2304#define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS BIT(10)
2305#define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\
2306 FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
2307#define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\
2308 FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
2309
2310#define CPU_PROC_CTRL_BE_EXCEP_MODE BIT(9)
2311#define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\
2312 FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
2313#define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\
2314 FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
2315
2316#define CPU_PROC_CTRL_VINITHI BIT(8)
2317#define CPU_PROC_CTRL_VINITHI_SET(x)\
2318 FIELD_PREP(CPU_PROC_CTRL_VINITHI, x)
2319#define CPU_PROC_CTRL_VINITHI_GET(x)\
2320 FIELD_GET(CPU_PROC_CTRL_VINITHI, x)
2321
2322#define CPU_PROC_CTRL_CFGTE BIT(7)
2323#define CPU_PROC_CTRL_CFGTE_SET(x)\
2324 FIELD_PREP(CPU_PROC_CTRL_CFGTE, x)
2325#define CPU_PROC_CTRL_CFGTE_GET(x)\
2326 FIELD_GET(CPU_PROC_CTRL_CFGTE, x)
2327
2328#define CPU_PROC_CTRL_CP15S_DISABLE BIT(6)
2329#define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\
2330 FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x)
2331#define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\
2332 FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x)
2333
2334#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE BIT(5)
2335#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\
2336 FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
2337#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\
2338 FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
2339
2340#define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA BIT(4)
2341#define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\
2342 FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
2343#define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\
2344 FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
2345
2346#define CPU_PROC_CTRL_ACP_AWCACHE BIT(3)
2347#define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\
2348 FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x)
2349#define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\
2350 FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x)
2351
2352#define CPU_PROC_CTRL_ACP_ARCACHE BIT(2)
2353#define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\
2354 FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x)
2355#define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\
2356 FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x)
2357
2358#define CPU_PROC_CTRL_L2_FLUSH_REQ BIT(1)
2359#define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\
2360 FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
2361#define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\
2362 FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
2363
2364#define CPU_PROC_CTRL_ACP_DISABLE BIT(0)
2365#define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\
2366 FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x)
2367#define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\
2368 FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x)
2369
2370/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
2371#define DEV10G_MAC_ENA_CFG(t) __REG(TARGET_DEV10G,\
2372 t, 12, 0, 0, 1, 60, 0, 0, 1, 4)
2373
2374#define DEV10G_MAC_ENA_CFG_RX_ENA BIT(4)
2375#define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\
2376 FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x)
2377#define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\
2378 FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x)
2379
2380#define DEV10G_MAC_ENA_CFG_TX_ENA BIT(0)
2381#define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\
2382 FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x)
2383#define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\
2384 FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x)
2385
2386/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
2387#define DEV10G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV10G,\
2388 t, 12, 0, 0, 1, 60, 8, 0, 1, 4)
2389
2390#define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16)
2391#define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
2392 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2393#define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
2394 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2395
2396#define DEV10G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)
2397#define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
2398 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
2399#define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
2400 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
2401
2402/* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */
2403#define DEV10G_MAC_NUM_TAGS_CFG(t) __REG(TARGET_DEV10G,\
2404 t, 12, 0, 0, 1, 60, 12, 0, 1, 4)
2405
2406#define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0)
2407#define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\
2408 FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
2409#define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\
2410 FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
2411
2412/* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */
2413#define DEV10G_MAC_TAGS_CFG(t, r) __REG(TARGET_DEV10G,\
2414 t, 12, 0, 0, 1, 60, 16, r, 3, 4)
2415
2416#define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16)
2417#define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\
2418 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
2419#define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\
2420 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
2421
2422#define DEV10G_MAC_TAGS_CFG_TAG_ENA BIT(4)
2423#define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\
2424 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
2425#define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\
2426 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
2427
2428/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
2429#define DEV10G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV10G,\
2430 t, 12, 0, 0, 1, 60, 28, 0, 1, 4)
2431
2432#define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24)
2433#define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
2434 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2435#define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
2436 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2437
2438#define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20)
2439#define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
2440 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2441#define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
2442 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2443
2444#define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16)
2445#define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
2446 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2447#define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
2448 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2449
2450#define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12)
2451#define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
2452 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2453#define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
2454 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2455
2456#define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8)
2457#define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
2458 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2459#define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
2460 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2461
2462#define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4)
2463#define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
2464 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2465#define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
2466 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2467
2468#define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0)
2469#define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
2470 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2471#define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
2472 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2473
2474/* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */
2475#define DEV10G_MAC_TX_MONITOR_STICKY(t) __REG(TARGET_DEV10G,\
2476 t, 12, 0, 0, 1, 60, 48, 0, 1, 4)
2477
2478#define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4)
2479#define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\
2480 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
2481#define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\
2482 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
2483
2484#define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY BIT(3)
2485#define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\
2486 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
2487#define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\
2488 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
2489
2490#define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY BIT(2)
2491#define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\
2492 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
2493#define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\
2494 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
2495
2496#define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1)
2497#define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\
2498 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
2499#define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\
2500 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
2501
2502#define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY BIT(0)
2503#define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\
2504 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
2505#define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\
2506 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
2507
2508/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
2509#define DEV10G_DEV_RST_CTRL(t) __REG(TARGET_DEV10G,\
2510 t, 12, 436, 0, 1, 52, 0, 0, 1, 4)
2511
2512#define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28)
2513#define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
2514 FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2515#define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
2516 FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2517
2518#define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
2519#define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
2520 FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2521#define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
2522 FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2523
2524#define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
2525#define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
2526 FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2527#define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
2528 FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2529
2530#define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23)
2531#define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
2532 FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2533#define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
2534 FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2535
2536#define DEV10G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)
2537#define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
2538 FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
2539#define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
2540 FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
2541
2542#define DEV10G_DEV_RST_CTRL_PCS_TX_RST BIT(12)
2543#define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
2544 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
2545#define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
2546 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
2547
2548#define DEV10G_DEV_RST_CTRL_PCS_RX_RST BIT(8)
2549#define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
2550 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
2551#define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
2552 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
2553
2554#define DEV10G_DEV_RST_CTRL_MAC_TX_RST BIT(4)
2555#define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
2556 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
2557#define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
2558 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
2559
2560#define DEV10G_DEV_RST_CTRL_MAC_RX_RST BIT(0)
2561#define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
2562 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
2563#define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
2564 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
2565
2566/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */
2567#define DEV10G_PCS25G_CFG(t) __REG(TARGET_DEV10G,\
2568 t, 12, 488, 0, 1, 32, 0, 0, 1, 4)
2569
2570#define DEV10G_PCS25G_CFG_PCS25G_ENA BIT(0)
2571#define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\
2572 FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
2573#define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\
2574 FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
2575
2576/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
2577#define DEV25G_MAC_ENA_CFG(t) __REG(TARGET_DEV25G,\
2578 t, 8, 0, 0, 1, 60, 0, 0, 1, 4)
2579
2580#define DEV25G_MAC_ENA_CFG_RX_ENA BIT(4)
2581#define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\
2582 FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x)
2583#define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\
2584 FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x)
2585
2586#define DEV25G_MAC_ENA_CFG_TX_ENA BIT(0)
2587#define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\
2588 FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x)
2589#define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\
2590 FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x)
2591
2592/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
2593#define DEV25G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV25G,\
2594 t, 8, 0, 0, 1, 60, 8, 0, 1, 4)
2595
2596#define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16)
2597#define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
2598 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2599#define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
2600 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2601
2602#define DEV25G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)
2603#define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
2604 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
2605#define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
2606 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
2607
2608/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
2609#define DEV25G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV25G,\
2610 t, 8, 0, 0, 1, 60, 28, 0, 1, 4)
2611
2612#define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24)
2613#define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
2614 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2615#define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
2616 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2617
2618#define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20)
2619#define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
2620 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2621#define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
2622 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2623
2624#define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16)
2625#define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
2626 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2627#define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
2628 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2629
2630#define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12)
2631#define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
2632 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2633#define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
2634 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2635
2636#define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8)
2637#define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
2638 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2639#define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
2640 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2641
2642#define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4)
2643#define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
2644 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2645#define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
2646 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2647
2648#define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0)
2649#define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
2650 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2651#define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
2652 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2653
2654/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
2655#define DEV25G_DEV_RST_CTRL(t) __REG(TARGET_DEV25G,\
2656 t, 8, 436, 0, 1, 52, 0, 0, 1, 4)
2657
2658#define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28)
2659#define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
2660 FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2661#define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
2662 FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2663
2664#define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
2665#define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
2666 FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2667#define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
2668 FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2669
2670#define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
2671#define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
2672 FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2673#define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
2674 FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2675
2676#define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23)
2677#define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
2678 FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2679#define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
2680 FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2681
2682#define DEV25G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)
2683#define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
2684 FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
2685#define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
2686 FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
2687
2688#define DEV25G_DEV_RST_CTRL_PCS_TX_RST BIT(12)
2689#define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
2690 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
2691#define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
2692 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
2693
2694#define DEV25G_DEV_RST_CTRL_PCS_RX_RST BIT(8)
2695#define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
2696 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
2697#define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
2698 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
2699
2700#define DEV25G_DEV_RST_CTRL_MAC_TX_RST BIT(4)
2701#define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
2702 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
2703#define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
2704 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
2705
2706#define DEV25G_DEV_RST_CTRL_MAC_RX_RST BIT(0)
2707#define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
2708 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
2709#define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
2710 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
2711
2712/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */
2713#define DEV25G_PCS25G_CFG(t) __REG(TARGET_DEV25G,\
2714 t, 8, 488, 0, 1, 32, 0, 0, 1, 4)
2715
2716#define DEV25G_PCS25G_CFG_PCS25G_ENA BIT(0)
2717#define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\
2718 FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
2719#define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\
2720 FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
2721
2722/* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */
2723#define DEV25G_PCS25G_SD_CFG(t) __REG(TARGET_DEV25G,\
2724 t, 8, 488, 0, 1, 32, 4, 0, 1, 4)
2725
2726#define DEV25G_PCS25G_SD_CFG_SD_SEL BIT(8)
2727#define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\
2728 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
2729#define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\
2730 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
2731
2732#define DEV25G_PCS25G_SD_CFG_SD_POL BIT(4)
2733#define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\
2734 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x)
2735#define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\
2736 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x)
2737
2738#define DEV25G_PCS25G_SD_CFG_SD_ENA BIT(0)
2739#define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\
2740 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
2741#define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\
2742 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
2743
2744/* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */
2745#define DEV2G5_DEV_RST_CTRL(t) __REG(TARGET_DEV2G5,\
2746 t, 65, 0, 0, 1, 36, 0, 0, 1, 4)
2747
2748#define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23)
2749#define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
2750 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2751#define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
2752 FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2753
2754#define DEV2G5_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)
2755#define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\
2756 FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
2757#define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\
2758 FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
2759
2760#define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST BIT(17)
2761#define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\
2762 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
2763#define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\
2764 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
2765
2766#define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST BIT(16)
2767#define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\
2768 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
2769#define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\
2770 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
2771
2772#define DEV2G5_DEV_RST_CTRL_PCS_TX_RST BIT(12)
2773#define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
2774 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
2775#define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
2776 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
2777
2778#define DEV2G5_DEV_RST_CTRL_PCS_RX_RST BIT(8)
2779#define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
2780 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
2781#define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
2782 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
2783
2784#define DEV2G5_DEV_RST_CTRL_MAC_TX_RST BIT(4)
2785#define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
2786 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
2787#define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
2788 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
2789
2790#define DEV2G5_DEV_RST_CTRL_MAC_RX_RST BIT(0)
2791#define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
2792 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
2793#define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
2794 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
2795
2796/* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */
2797#define DEV2G5_MAC_ENA_CFG(t) __REG(TARGET_DEV2G5,\
2798 t, 65, 52, 0, 1, 36, 0, 0, 1, 4)
2799
2800#define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4)
2801#define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\
2802 FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
2803#define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\
2804 FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
2805
2806#define DEV2G5_MAC_ENA_CFG_TX_ENA BIT(0)
2807#define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\
2808 FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
2809#define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\
2810 FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
2811
2812/* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */
2813#define DEV2G5_MAC_MODE_CFG(t) __REG(TARGET_DEV2G5,\
2814 t, 65, 52, 0, 1, 36, 4, 0, 1, 4)
2815
2816#define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8)
2817#define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\
2818 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
2819#define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\
2820 FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
2821
2822#define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
2823#define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\
2824 FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
2825#define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\
2826 FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
2827
2828#define DEV2G5_MAC_MODE_CFG_FDX_ENA BIT(0)
2829#define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\
2830 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
2831#define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\
2832 FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
2833
2834/* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
2835#define DEV2G5_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV2G5,\
2836 t, 65, 52, 0, 1, 36, 8, 0, 1, 4)
2837
2838#define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)
2839#define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
2840 FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
2841#define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
2842 FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
2843
2844/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */
2845#define DEV2G5_MAC_TAGS_CFG(t) __REG(TARGET_DEV2G5,\
2846 t, 65, 52, 0, 1, 36, 12, 0, 1, 4)
2847
2848#define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16)
2849#define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\
2850 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
2851#define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\
2852 FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
2853
2854#define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3)
2855#define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\
2856 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
2857#define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\
2858 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
2859
2860#define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1)
2861#define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\
2862 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
2863#define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\
2864 FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
2865
2866#define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
2867#define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\
2868 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
2869#define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\
2870 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
2871
2872/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */
2873#define DEV2G5_MAC_TAGS_CFG2(t) __REG(TARGET_DEV2G5,\
2874 t, 65, 52, 0, 1, 36, 16, 0, 1, 4)
2875
2876#define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16)
2877#define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\
2878 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
2879#define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\
2880 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
2881
2882#define DEV2G5_MAC_TAGS_CFG2_TAG_ID2 GENMASK(15, 0)
2883#define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\
2884 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
2885#define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\
2886 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
2887
2888/* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
2889#define DEV2G5_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV2G5,\
2890 t, 65, 52, 0, 1, 36, 20, 0, 1, 4)
2891
2892#define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0)
2893#define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\
2894 FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
2895#define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\
2896 FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
2897
2898/* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */
2899#define DEV2G5_MAC_IFG_CFG(t) __REG(TARGET_DEV2G5,\
2900 t, 65, 52, 0, 1, 36, 24, 0, 1, 4)
2901
2902#define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
2903#define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\
2904 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
2905#define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\
2906 FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
2907
2908#define DEV2G5_MAC_IFG_CFG_TX_IFG GENMASK(12, 8)
2909#define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\
2910 FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
2911#define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\
2912 FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
2913
2914#define DEV2G5_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4)
2915#define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\
2916 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
2917#define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\
2918 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
2919
2920#define DEV2G5_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0)
2921#define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\
2922 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
2923#define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\
2924 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
2925
2926/* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */
2927#define DEV2G5_MAC_HDX_CFG(t) __REG(TARGET_DEV2G5,\
2928 t, 65, 52, 0, 1, 36, 28, 0, 1, 4)
2929
2930#define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26)
2931#define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\
2932 FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
2933#define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\
2934 FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
2935
2936#define DEV2G5_MAC_HDX_CFG_SEED GENMASK(23, 16)
2937#define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\
2938 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x)
2939#define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\
2940 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x)
2941
2942#define DEV2G5_MAC_HDX_CFG_SEED_LOAD BIT(12)
2943#define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\
2944 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
2945#define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\
2946 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
2947
2948#define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
2949#define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\
2950 FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
2951#define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\
2952 FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
2953
2954#define DEV2G5_MAC_HDX_CFG_LATE_COL_POS GENMASK(6, 0)
2955#define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\
2956 FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
2957#define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\
2958 FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
2959
2960/* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */
2961#define DEV2G5_PCS1G_CFG(t) __REG(TARGET_DEV2G5,\
2962 t, 65, 88, 0, 1, 68, 0, 0, 1, 4)
2963
2964#define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE BIT(4)
2965#define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\
2966 FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
2967#define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\
2968 FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
2969
2970#define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
2971#define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\
2972 FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
2973#define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\
2974 FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
2975
2976#define DEV2G5_PCS1G_CFG_PCS_ENA BIT(0)
2977#define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\
2978 FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x)
2979#define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\
2980 FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x)
2981
2982/* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */
2983#define DEV2G5_PCS1G_MODE_CFG(t) __REG(TARGET_DEV2G5,\
2984 t, 65, 88, 0, 1, 68, 4, 0, 1, 4)
2985
2986#define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
2987#define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\
2988 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
2989#define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\
2990 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
2991
2992#define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1)
2993#define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\
2994 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
2995#define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\
2996 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
2997
2998#define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
2999#define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\
3000 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
3001#define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\
3002 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
3003
3004/* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */
3005#define DEV2G5_PCS1G_SD_CFG(t) __REG(TARGET_DEV2G5,\
3006 t, 65, 88, 0, 1, 68, 8, 0, 1, 4)
3007
3008#define DEV2G5_PCS1G_SD_CFG_SD_SEL BIT(8)
3009#define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\
3010 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
3011#define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\
3012 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
3013
3014#define DEV2G5_PCS1G_SD_CFG_SD_POL BIT(4)
3015#define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\
3016 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
3017#define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\
3018 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
3019
3020#define DEV2G5_PCS1G_SD_CFG_SD_ENA BIT(0)
3021#define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\
3022 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
3023#define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\
3024 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
3025
3026/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */
3027#define DEV2G5_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV2G5,\
3028 t, 65, 88, 0, 1, 68, 12, 0, 1, 4)
3029
3030#define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16)
3031#define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\
3032 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
3033#define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\
3034 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
3035
3036#define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
3037#define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\
3038 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
3039#define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\
3040 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
3041
3042#define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
3043#define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\
3044 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
3045#define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\
3046 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
3047
3048#define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA BIT(0)
3049#define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\
3050 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
3051#define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\
3052 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
3053
3054/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */
3055#define DEV2G5_PCS1G_LB_CFG(t) __REG(TARGET_DEV2G5,\
3056 t, 65, 88, 0, 1, 68, 20, 0, 1, 4)
3057
3058#define DEV2G5_PCS1G_LB_CFG_RA_ENA BIT(4)
3059#define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\
3060 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
3061#define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\
3062 FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
3063
3064#define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
3065#define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\
3066 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
3067#define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\
3068 FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
3069
3070#define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0)
3071#define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\
3072 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
3073#define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\
3074 FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
3075
3076/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */
3077#define DEV2G5_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV2G5,\
3078 t, 65, 88, 0, 1, 68, 32, 0, 1, 4)
3079
3080#define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16)
3081#define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\
3082 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
3083#define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\
3084 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
3085
3086#define DEV2G5_PCS1G_ANEG_STATUS_PR BIT(4)
3087#define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\
3088 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
3089#define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\
3090 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
3091
3092#define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3)
3093#define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\
3094 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
3095#define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\
3096 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
3097
3098#define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
3099#define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\
3100 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
3101#define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\
3102 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
3103
3104/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */
3105#define DEV2G5_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV2G5,\
3106 t, 65, 88, 0, 1, 68, 40, 0, 1, 4)
3107
3108#define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12)
3109#define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\
3110 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
3111#define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\
3112 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
3113
3114#define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8)
3115#define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\
3116 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
3117#define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\
3118 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
3119
3120#define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
3121#define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\
3122 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
3123#define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\
3124 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
3125
3126#define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
3127#define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\
3128 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
3129#define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\
3130 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
3131
3132/* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */
3133#define DEV2G5_PCS1G_STICKY(t) __REG(TARGET_DEV2G5,\
3134 t, 65, 88, 0, 1, 68, 48, 0, 1, 4)
3135
3136#define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
3137#define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\
3138 FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
3139#define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\
3140 FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
3141
3142#define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0)
3143#define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\
3144 FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
3145#define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\
3146 FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
3147
3148/* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */
3149#define DEV2G5_PCS_FX100_CFG(t) __REG(TARGET_DEV2G5,\
3150 t, 65, 164, 0, 1, 4, 0, 0, 1, 4)
3151
3152#define DEV2G5_PCS_FX100_CFG_SD_SEL BIT(26)
3153#define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\
3154 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
3155#define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\
3156 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
3157
3158#define DEV2G5_PCS_FX100_CFG_SD_POL BIT(25)
3159#define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\
3160 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x)
3161#define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\
3162 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x)
3163
3164#define DEV2G5_PCS_FX100_CFG_SD_ENA BIT(24)
3165#define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\
3166 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
3167#define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\
3168 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
3169
3170#define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA BIT(20)
3171#define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\
3172 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
3173#define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\
3174 FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
3175
3176#define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA BIT(16)
3177#define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\
3178 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
3179#define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\
3180 FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
3181
3182#define DEV2G5_PCS_FX100_CFG_RXBITSEL GENMASK(15, 12)
3183#define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\
3184 FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
3185#define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\
3186 FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
3187
3188#define DEV2G5_PCS_FX100_CFG_SIGDET_CFG GENMASK(10, 9)
3189#define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\
3190 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
3191#define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\
3192 FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
3193
3194#define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8)
3195#define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\
3196 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
3197#define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\
3198 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
3199
3200#define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER GENMASK(7, 4)
3201#define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\
3202 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
3203#define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\
3204 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
3205
3206#define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3)
3207#define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\
3208 FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
3209#define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\
3210 FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
3211
3212#define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA BIT(2)
3213#define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\
3214 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
3215#define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\
3216 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
3217
3218#define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
3219#define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\
3220 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
3221#define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\
3222 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
3223
3224#define DEV2G5_PCS_FX100_CFG_PCS_ENA BIT(0)
3225#define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\
3226 FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
3227#define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\
3228 FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
3229
3230/* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */
3231#define DEV2G5_PCS_FX100_STATUS(t) __REG(TARGET_DEV2G5,\
3232 t, 65, 168, 0, 1, 4, 0, 0, 1, 4)
3233
3234#define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8)
3235#define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\
3236 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
3237#define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\
3238 FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
3239
3240#define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7)
3241#define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\
3242 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
3243#define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\
3244 FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
3245
3246#define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6)
3247#define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\
3248 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
3249#define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\
3250 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
3251
3252#define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5)
3253#define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\
3254 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
3255#define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\
3256 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
3257
3258#define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
3259#define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\
3260 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
3261#define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\
3262 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
3263
3264#define DEV2G5_PCS_FX100_STATUS_FEF_STATUS BIT(2)
3265#define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\
3266 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
3267#define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\
3268 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
3269
3270#define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
3271#define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\
3272 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
3273#define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\
3274 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
3275
3276#define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS BIT(0)
3277#define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\
3278 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
3279#define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\
3280 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
3281
3282/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
3283#define DEV5G_MAC_ENA_CFG(t) __REG(TARGET_DEV5G,\
3284 t, 13, 0, 0, 1, 60, 0, 0, 1, 4)
3285
3286#define DEV5G_MAC_ENA_CFG_RX_ENA BIT(4)
3287#define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\
3288 FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x)
3289#define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\
3290 FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x)
3291
3292#define DEV5G_MAC_ENA_CFG_TX_ENA BIT(0)
3293#define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\
3294 FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x)
3295#define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\
3296 FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x)
3297
3298/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
3299#define DEV5G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV5G,\
3300 t, 13, 0, 0, 1, 60, 8, 0, 1, 4)
3301
3302#define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16)
3303#define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
3304 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
3305#define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
3306 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
3307
3308#define DEV5G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0)
3309#define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
3310 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
3311#define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
3312 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
3313
3314/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
3315#define DEV5G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV5G,\
3316 t, 13, 0, 0, 1, 60, 28, 0, 1, 4)
3317
3318#define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24)
3319#define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
3320 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
3321#define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
3322 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
3323
3324#define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20)
3325#define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
3326 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
3327#define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
3328 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
3329
3330#define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16)
3331#define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
3332 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
3333#define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
3334 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
3335
3336#define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12)
3337#define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
3338 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
3339#define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
3340 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
3341
3342#define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8)
3343#define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
3344 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
3345#define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
3346 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
3347
3348#define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4)
3349#define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
3350 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
3351#define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
3352 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
3353
3354#define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0)
3355#define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
3356 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
3357#define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
3358 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
3359
3360/* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */
3361#define DEV5G_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G,\
3362 t, 13, 60, 0, 1, 312, 0, 0, 1, 4)
3363
3364/* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */
3365#define DEV5G_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\
3366 t, 13, 60, 0, 1, 312, 4, 0, 1, 4)
3367
3368/* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */
3369#define DEV5G_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G,\
3370 t, 13, 60, 0, 1, 312, 8, 0, 1, 4)
3371
3372/* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */
3373#define DEV5G_RX_UC_CNT(t) __REG(TARGET_DEV5G,\
3374 t, 13, 60, 0, 1, 312, 12, 0, 1, 4)
3375
3376/* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */
3377#define DEV5G_RX_MC_CNT(t) __REG(TARGET_DEV5G,\
3378 t, 13, 60, 0, 1, 312, 16, 0, 1, 4)
3379
3380/* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */
3381#define DEV5G_RX_BC_CNT(t) __REG(TARGET_DEV5G,\
3382 t, 13, 60, 0, 1, 312, 20, 0, 1, 4)
3383
3384/* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */
3385#define DEV5G_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G,\
3386 t, 13, 60, 0, 1, 312, 24, 0, 1, 4)
3387
3388/* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */
3389#define DEV5G_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G,\
3390 t, 13, 60, 0, 1, 312, 28, 0, 1, 4)
3391
3392/* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */
3393#define DEV5G_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G,\
3394 t, 13, 60, 0, 1, 312, 32, 0, 1, 4)
3395
3396/* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */
3397#define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\
3398 t, 13, 60, 0, 1, 312, 36, 0, 1, 4)
3399
3400/* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */
3401#define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\
3402 t, 13, 60, 0, 1, 312, 40, 0, 1, 4)
3403
3404/* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */
3405#define DEV5G_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G,\
3406 t, 13, 60, 0, 1, 312, 44, 0, 1, 4)
3407
3408/* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */
3409#define DEV5G_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G,\
3410 t, 13, 60, 0, 1, 312, 48, 0, 1, 4)
3411
3412/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */
3413#define DEV5G_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\
3414 t, 13, 60, 0, 1, 312, 52, 0, 1, 4)
3415
3416/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */
3417#define DEV5G_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\
3418 t, 13, 60, 0, 1, 312, 56, 0, 1, 4)
3419
3420/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */
3421#define DEV5G_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\
3422 t, 13, 60, 0, 1, 312, 60, 0, 1, 4)
3423
3424/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */
3425#define DEV5G_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\
3426 t, 13, 60, 0, 1, 312, 64, 0, 1, 4)
3427
3428/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */
3429#define DEV5G_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\
3430 t, 13, 60, 0, 1, 312, 68, 0, 1, 4)
3431
3432/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */
3433#define DEV5G_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\
3434 t, 13, 60, 0, 1, 312, 72, 0, 1, 4)
3435
3436/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */
3437#define DEV5G_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\
3438 t, 13, 60, 0, 1, 312, 76, 0, 1, 4)
3439
3440/* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */
3441#define DEV5G_RX_IPG_SHRINK_CNT(t) __REG(TARGET_DEV5G,\
3442 t, 13, 60, 0, 1, 312, 80, 0, 1, 4)
3443
3444/* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */
3445#define DEV5G_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\
3446 t, 13, 60, 0, 1, 312, 84, 0, 1, 4)
3447
3448/* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */
3449#define DEV5G_TX_UC_CNT(t) __REG(TARGET_DEV5G,\
3450 t, 13, 60, 0, 1, 312, 88, 0, 1, 4)
3451
3452/* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */
3453#define DEV5G_TX_MC_CNT(t) __REG(TARGET_DEV5G,\
3454 t, 13, 60, 0, 1, 312, 92, 0, 1, 4)
3455
3456/* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */
3457#define DEV5G_TX_BC_CNT(t) __REG(TARGET_DEV5G,\
3458 t, 13, 60, 0, 1, 312, 96, 0, 1, 4)
3459
3460/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */
3461#define DEV5G_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\
3462 t, 13, 60, 0, 1, 312, 100, 0, 1, 4)
3463
3464/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */
3465#define DEV5G_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\
3466 t, 13, 60, 0, 1, 312, 104, 0, 1, 4)
3467
3468/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */
3469#define DEV5G_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\
3470 t, 13, 60, 0, 1, 312, 108, 0, 1, 4)
3471
3472/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */
3473#define DEV5G_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\
3474 t, 13, 60, 0, 1, 312, 112, 0, 1, 4)
3475
3476/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */
3477#define DEV5G_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\
3478 t, 13, 60, 0, 1, 312, 116, 0, 1, 4)
3479
3480/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */
3481#define DEV5G_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\
3482 t, 13, 60, 0, 1, 312, 120, 0, 1, 4)
3483
3484/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */
3485#define DEV5G_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\
3486 t, 13, 60, 0, 1, 312, 124, 0, 1, 4)
3487
3488/* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */
3489#define DEV5G_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G,\
3490 t, 13, 60, 0, 1, 312, 128, 0, 1, 4)
3491
3492/* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */
3493#define DEV5G_RX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\
3494 t, 13, 60, 0, 1, 312, 132, 0, 1, 4)
3495
3496/* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */
3497#define DEV5G_RX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\
3498 t, 13, 60, 0, 1, 312, 136, 0, 1, 4)
3499
3500/* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */
3501#define DEV5G_TX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\
3502 t, 13, 60, 0, 1, 312, 140, 0, 1, 4)
3503
3504/* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */
3505#define DEV5G_TX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\
3506 t, 13, 60, 0, 1, 312, 144, 0, 1, 4)
3507
3508/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */
3509#define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G,\
3510 t, 13, 60, 0, 1, 312, 148, 0, 1, 4)
3511
3512/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */
3513#define DEV5G_PMAC_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\
3514 t, 13, 60, 0, 1, 312, 152, 0, 1, 4)
3515
3516/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */
3517#define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G,\
3518 t, 13, 60, 0, 1, 312, 156, 0, 1, 4)
3519
3520/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */
3521#define DEV5G_PMAC_RX_UC_CNT(t) __REG(TARGET_DEV5G,\
3522 t, 13, 60, 0, 1, 312, 160, 0, 1, 4)
3523
3524/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */
3525#define DEV5G_PMAC_RX_MC_CNT(t) __REG(TARGET_DEV5G,\
3526 t, 13, 60, 0, 1, 312, 164, 0, 1, 4)
3527
3528/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */
3529#define DEV5G_PMAC_RX_BC_CNT(t) __REG(TARGET_DEV5G,\
3530 t, 13, 60, 0, 1, 312, 168, 0, 1, 4)
3531
3532/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */
3533#define DEV5G_PMAC_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G,\
3534 t, 13, 60, 0, 1, 312, 172, 0, 1, 4)
3535
3536/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */
3537#define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G,\
3538 t, 13, 60, 0, 1, 312, 176, 0, 1, 4)
3539
3540/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */
3541#define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G,\
3542 t, 13, 60, 0, 1, 312, 180, 0, 1, 4)
3543
3544/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */
3545#define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\
3546 t, 13, 60, 0, 1, 312, 184, 0, 1, 4)
3547
3548/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */
3549#define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\
3550 t, 13, 60, 0, 1, 312, 188, 0, 1, 4)
3551
3552/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */
3553#define DEV5G_PMAC_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G,\
3554 t, 13, 60, 0, 1, 312, 192, 0, 1, 4)
3555
3556/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */
3557#define DEV5G_PMAC_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G,\
3558 t, 13, 60, 0, 1, 312, 196, 0, 1, 4)
3559
3560/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */
3561#define DEV5G_PMAC_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\
3562 t, 13, 60, 0, 1, 312, 200, 0, 1, 4)
3563
3564/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */
3565#define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\
3566 t, 13, 60, 0, 1, 312, 204, 0, 1, 4)
3567
3568/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */
3569#define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\
3570 t, 13, 60, 0, 1, 312, 208, 0, 1, 4)
3571
3572/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */
3573#define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\
3574 t, 13, 60, 0, 1, 312, 212, 0, 1, 4)
3575
3576/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */
3577#define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\
3578 t, 13, 60, 0, 1, 312, 216, 0, 1, 4)
3579
3580/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */
3581#define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\
3582 t, 13, 60, 0, 1, 312, 220, 0, 1, 4)
3583
3584/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */
3585#define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\
3586 t, 13, 60, 0, 1, 312, 224, 0, 1, 4)
3587
3588/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */
3589#define DEV5G_PMAC_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\
3590 t, 13, 60, 0, 1, 312, 228, 0, 1, 4)
3591
3592/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */
3593#define DEV5G_PMAC_TX_UC_CNT(t) __REG(TARGET_DEV5G,\
3594 t, 13, 60, 0, 1, 312, 232, 0, 1, 4)
3595
3596/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */
3597#define DEV5G_PMAC_TX_MC_CNT(t) __REG(TARGET_DEV5G,\
3598 t, 13, 60, 0, 1, 312, 236, 0, 1, 4)
3599
3600/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */
3601#define DEV5G_PMAC_TX_BC_CNT(t) __REG(TARGET_DEV5G,\
3602 t, 13, 60, 0, 1, 312, 240, 0, 1, 4)
3603
3604/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */
3605#define DEV5G_PMAC_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\
3606 t, 13, 60, 0, 1, 312, 244, 0, 1, 4)
3607
3608/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */
3609#define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\
3610 t, 13, 60, 0, 1, 312, 248, 0, 1, 4)
3611
3612/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */
3613#define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\
3614 t, 13, 60, 0, 1, 312, 252, 0, 1, 4)
3615
3616/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */
3617#define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\
3618 t, 13, 60, 0, 1, 312, 256, 0, 1, 4)
3619
3620/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */
3621#define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\
3622 t, 13, 60, 0, 1, 312, 260, 0, 1, 4)
3623
3624/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */
3625#define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\
3626 t, 13, 60, 0, 1, 312, 264, 0, 1, 4)
3627
3628/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */
3629#define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\
3630 t, 13, 60, 0, 1, 312, 268, 0, 1, 4)
3631
3632/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */
3633#define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G,\
3634 t, 13, 60, 0, 1, 312, 272, 0, 1, 4)
3635
3636/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */
3637#define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) __REG(TARGET_DEV5G,\
3638 t, 13, 60, 0, 1, 312, 276, 0, 1, 4)
3639
3640/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */
3641#define DEV5G_MM_RX_SMD_ERR_CNT(t) __REG(TARGET_DEV5G,\
3642 t, 13, 60, 0, 1, 312, 280, 0, 1, 4)
3643
3644/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */
3645#define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) __REG(TARGET_DEV5G,\
3646 t, 13, 60, 0, 1, 312, 284, 0, 1, 4)
3647
3648/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */
3649#define DEV5G_MM_RX_MERGE_FRAG_CNT(t) __REG(TARGET_DEV5G,\
3650 t, 13, 60, 0, 1, 312, 288, 0, 1, 4)
3651
3652/* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */
3653#define DEV5G_MM_TX_PFRAGMENT_CNT(t) __REG(TARGET_DEV5G,\
3654 t, 13, 60, 0, 1, 312, 292, 0, 1, 4)
3655
3656/* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */
3657#define DEV5G_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G,\
3658 t, 13, 60, 0, 1, 312, 296, 0, 1, 4)
3659
3660/* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */
3661#define DEV5G_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G,\
3662 t, 13, 60, 0, 1, 312, 300, 0, 1, 4)
3663
3664/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */
3665#define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G,\
3666 t, 13, 60, 0, 1, 312, 304, 0, 1, 4)
3667
3668/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */
3669#define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G,\
3670 t, 13, 60, 0, 1, 312, 308, 0, 1, 4)
3671
3672/* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */
3673#define DEV5G_RX_IN_BYTES_CNT(t) __REG(TARGET_DEV5G,\
3674 t, 13, 372, 0, 1, 64, 0, 0, 1, 4)
3675
3676/* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */
3677#define DEV5G_RX_IN_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\
3678 t, 13, 372, 0, 1, 64, 4, 0, 1, 4)
3679
3680#define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0)
3681#define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\
3682 FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
3683#define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\
3684 FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
3685
3686/* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */
3687#define DEV5G_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\
3688 t, 13, 372, 0, 1, 64, 8, 0, 1, 4)
3689
3690/* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */
3691#define DEV5G_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\
3692 t, 13, 372, 0, 1, 64, 12, 0, 1, 4)
3693
3694#define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0)
3695#define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\
3696 FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
3697#define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\
3698 FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
3699
3700/* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */
3701#define DEV5G_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G,\
3702 t, 13, 372, 0, 1, 64, 16, 0, 1, 4)
3703
3704/* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */
3705#define DEV5G_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\
3706 t, 13, 372, 0, 1, 64, 20, 0, 1, 4)
3707
3708#define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0)
3709#define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\
3710 FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
3711#define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\
3712 FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
3713
3714/* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */
3715#define DEV5G_TX_OUT_BYTES_CNT(t) __REG(TARGET_DEV5G,\
3716 t, 13, 372, 0, 1, 64, 24, 0, 1, 4)
3717
3718/* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */
3719#define DEV5G_TX_OUT_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\
3720 t, 13, 372, 0, 1, 64, 28, 0, 1, 4)
3721
3722#define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0)
3723#define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\
3724 FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
3725#define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\
3726 FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
3727
3728/* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */
3729#define DEV5G_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\
3730 t, 13, 372, 0, 1, 64, 32, 0, 1, 4)
3731
3732/* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */
3733#define DEV5G_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\
3734 t, 13, 372, 0, 1, 64, 36, 0, 1, 4)
3735
3736#define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0)
3737#define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\
3738 FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
3739#define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\
3740 FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
3741
3742/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */
3743#define DEV5G_PMAC_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\
3744 t, 13, 372, 0, 1, 64, 40, 0, 1, 4)
3745
3746/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */
3747#define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\
3748 t, 13, 372, 0, 1, 64, 44, 0, 1, 4)
3749
3750#define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0)
3751#define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\
3752 FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
3753#define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\
3754 FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
3755
3756/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */
3757#define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G,\
3758 t, 13, 372, 0, 1, 64, 48, 0, 1, 4)
3759
3760/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */
3761#define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\
3762 t, 13, 372, 0, 1, 64, 52, 0, 1, 4)
3763
3764#define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0)
3765#define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\
3766 FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
3767#define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\
3768 FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
3769
3770/* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */
3771#define DEV5G_PMAC_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\
3772 t, 13, 372, 0, 1, 64, 56, 0, 1, 4)
3773
3774/* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */
3775#define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\
3776 t, 13, 372, 0, 1, 64, 60, 0, 1, 4)
3777
3778#define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0)
3779#define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\
3780 FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
3781#define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\
3782 FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
3783
3784/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
3785#define DEV5G_DEV_RST_CTRL(t) __REG(TARGET_DEV5G,\
3786 t, 13, 436, 0, 1, 52, 0, 0, 1, 4)
3787
3788#define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28)
3789#define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
3790 FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
3791#define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
3792 FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
3793
3794#define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
3795#define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
3796 FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3797#define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
3798 FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3799
3800#define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
3801#define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
3802 FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
3803#define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
3804 FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
3805
3806#define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23)
3807#define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
3808 FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
3809#define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
3810 FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
3811
3812#define DEV5G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)
3813#define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
3814 FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
3815#define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
3816 FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
3817
3818#define DEV5G_DEV_RST_CTRL_PCS_TX_RST BIT(12)
3819#define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
3820 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
3821#define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
3822 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
3823
3824#define DEV5G_DEV_RST_CTRL_PCS_RX_RST BIT(8)
3825#define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
3826 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
3827#define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
3828 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
3829
3830#define DEV5G_DEV_RST_CTRL_MAC_TX_RST BIT(4)
3831#define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
3832 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
3833#define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
3834 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
3835
3836#define DEV5G_DEV_RST_CTRL_MAC_RX_RST BIT(0)
3837#define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
3838 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
3839#define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
3840 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
3841
3842/* DSM:RAM_CTRL:RAM_INIT */
3843#define DSM_RAM_INIT __REG(TARGET_DSM,\
3844 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
3845
3846#define DSM_RAM_INIT_RAM_INIT BIT(1)
3847#define DSM_RAM_INIT_RAM_INIT_SET(x)\
3848 FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x)
3849#define DSM_RAM_INIT_RAM_INIT_GET(x)\
3850 FIELD_GET(DSM_RAM_INIT_RAM_INIT, x)
3851
3852#define DSM_RAM_INIT_RAM_CFG_HOOK BIT(0)
3853#define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\
3854 FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x)
3855#define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\
3856 FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x)
3857
3858/* DSM:CFG:BUF_CFG */
3859#define DSM_BUF_CFG(r) __REG(TARGET_DSM,\
3860 0, 1, 20, 0, 1, 3528, 0, r, 67, 4)
3861
3862#define DSM_BUF_CFG_CSC_STAT_DIS BIT(13)
3863#define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\
3864 FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x)
3865#define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\
3866 FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x)
3867
3868#define DSM_BUF_CFG_AGING_ENA BIT(12)
3869#define DSM_BUF_CFG_AGING_ENA_SET(x)\
3870 FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x)
3871#define DSM_BUF_CFG_AGING_ENA_GET(x)\
3872 FIELD_GET(DSM_BUF_CFG_AGING_ENA, x)
3873
3874#define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS BIT(11)
3875#define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\
3876 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
3877#define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\
3878 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
3879
3880#define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT GENMASK(10, 0)
3881#define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\
3882 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
3883#define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\
3884 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
3885
3886/* DSM:CFG:DEV_TX_STOP_WM_CFG */
3887#define DSM_DEV_TX_STOP_WM_CFG(r) __REG(TARGET_DSM,\
3888 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4)
3889
3890#define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA BIT(9)
3891#define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\
3892 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
3893#define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\
3894 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
3895
3896#define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA BIT(8)
3897#define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\
3898 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
3899#define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\
3900 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
3901
3902#define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM GENMASK(7, 1)
3903#define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\
3904 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
3905#define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\
3906 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
3907
3908#define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR BIT(0)
3909#define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\
3910 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
3911#define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\
3912 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
3913
3914/* DSM:CFG:RX_PAUSE_CFG */
3915#define DSM_RX_PAUSE_CFG(r) __REG(TARGET_DSM,\
3916 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4)
3917
3918#define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1)
3919#define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\
3920 FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
3921#define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\
3922 FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
3923
3924#define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL BIT(0)
3925#define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\
3926 FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
3927#define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\
3928 FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
3929
3930/* DSM:CFG:MAC_CFG */
3931#define DSM_MAC_CFG(r) __REG(TARGET_DSM,\
3932 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4)
3933
3934#define DSM_MAC_CFG_TX_PAUSE_VAL GENMASK(31, 16)
3935#define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\
3936 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x)
3937#define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\
3938 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x)
3939
3940#define DSM_MAC_CFG_HDX_BACKPREASSURE BIT(2)
3941#define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\
3942 FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
3943#define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\
3944 FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
3945
3946#define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE BIT(1)
3947#define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\
3948 FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
3949#define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\
3950 FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
3951
3952#define DSM_MAC_CFG_TX_PAUSE_XON_XOFF BIT(0)
3953#define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\
3954 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
3955#define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\
3956 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
3957
3958/* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */
3959#define DSM_MAC_ADDR_BASE_HIGH_CFG(r) __REG(TARGET_DSM,\
3960 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4)
3961
3962#define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0)
3963#define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\
3964 FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
3965#define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\
3966 FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
3967
3968/* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */
3969#define DSM_MAC_ADDR_BASE_LOW_CFG(r) __REG(TARGET_DSM,\
3970 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4)
3971
3972#define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW GENMASK(23, 0)
3973#define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\
3974 FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
3975#define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\
3976 FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
3977
3978/* DSM:CFG:TAXI_CAL_CFG */
3979#define DSM_TAXI_CAL_CFG(r) __REG(TARGET_DSM,\
3980 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4)
3981
3982#define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15)
3983#define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\
3984 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x)
3985#define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\
3986 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x)
3987
3988#define DSM_TAXI_CAL_CFG_CAL_CUR_LEN GENMASK(14, 9)
3989#define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\
3990 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
3991#define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\
3992 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
3993
3994#define DSM_TAXI_CAL_CFG_CAL_CUR_VAL GENMASK(8, 5)
3995#define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\
3996 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
3997#define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\
3998 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
3999
4000#define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1)
4001#define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\
4002 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
4003#define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\
4004 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
4005
4006#define DSM_TAXI_CAL_CFG_CAL_PGM_ENA BIT(0)
4007#define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\
4008 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
4009#define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\
4010 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
4011
4012/* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */
4013#define EACL_VCAP_ES2_KEY_SEL(g, r) __REG(TARGET_EACL,\
4014 0, 1, 149504, g, 138, 8, 0, r, 2, 4)
4015
4016#define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL GENMASK(7, 5)
4017#define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\
4018 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x)
4019#define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_GET(x)\
4020 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x)
4021
4022#define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL GENMASK(4, 2)
4023#define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(x)\
4024 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x)
4025#define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_GET(x)\
4026 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x)
4027
4028#define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL BIT(1)
4029#define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(x)\
4030 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x)
4031#define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_GET(x)\
4032 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x)
4033
4034#define EACL_VCAP_ES2_KEY_SEL_KEY_ENA BIT(0)
4035#define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(x)\
4036 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x)
4037#define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\
4038 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x)
4039
4040/* EACL:CNT_TBL:ES2_CNT */
4041#define EACL_ES2_CNT(g) __REG(TARGET_EACL,\
4042 0, 1, 122880, g, 2048, 4, 0, 0, 1, 4)
4043
4044/* EACL:POL_CFG:POL_EACL_CFG */
4045#define EACL_POL_EACL_CFG __REG(TARGET_EACL,\
4046 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4)
4047
4048#define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5)
4049#define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\
4050 FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
4051#define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\
4052 FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
4053
4054#define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY BIT(4)
4055#define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\
4056 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
4057#define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\
4058 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
4059
4060#define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY BIT(3)
4061#define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\
4062 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
4063#define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\
4064 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
4065
4066#define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE BIT(2)
4067#define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\
4068 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
4069#define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\
4070 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
4071
4072#define EACL_POL_EACL_CFG_EACL_FORCE_OPEN BIT(1)
4073#define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\
4074 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
4075#define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\
4076 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
4077
4078#define EACL_POL_EACL_CFG_EACL_FORCE_INIT BIT(0)
4079#define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\
4080 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
4081#define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\
4082 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
4083
4084/* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */
4085#define EACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_EACL,\
4086 0, 1, 118696, 0, 1, 8, 0, r, 2, 4)
4087
4088#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7)
4089#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\
4090 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
4091#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\
4092 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
4093
4094#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(6)
4095#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\
4096 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
4097#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\
4098 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
4099
4100#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(5)
4101#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\
4102 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
4103#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\
4104 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
4105
4106#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(4)
4107#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\
4108 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
4109#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\
4110 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
4111
4112#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(3)
4113#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\
4114 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
4115#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\
4116 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
4117
4118#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(2)
4119#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\
4120 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
4121#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\
4122 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
4123
4124#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(1)
4125#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\
4126 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
4127#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\
4128 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
4129
4130#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0)
4131#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\
4132 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
4133#define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\
4134 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
4135
4136/* EACL:RAM_CTRL:RAM_INIT */
4137#define EACL_RAM_INIT __REG(TARGET_EACL,\
4138 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4)
4139
4140#define EACL_RAM_INIT_RAM_INIT BIT(1)
4141#define EACL_RAM_INIT_RAM_INIT_SET(x)\
4142 FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x)
4143#define EACL_RAM_INIT_RAM_INIT_GET(x)\
4144 FIELD_GET(EACL_RAM_INIT_RAM_INIT, x)
4145
4146#define EACL_RAM_INIT_RAM_CFG_HOOK BIT(0)
4147#define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4148 FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x)
4149#define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4150 FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x)
4151
4152/* FDMA:FDMA:FDMA_CH_ACTIVATE */
4153#define FDMA_CH_ACTIVATE __REG(TARGET_FDMA,\
4154 0, 1, 8, 0, 1, 428, 0, 0, 1, 4)
4155
4156#define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0)
4157#define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\
4158 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
4159#define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\
4160 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
4161
4162/* FDMA:FDMA:FDMA_CH_RELOAD */
4163#define FDMA_CH_RELOAD __REG(TARGET_FDMA,\
4164 0, 1, 8, 0, 1, 428, 4, 0, 1, 4)
4165
4166#define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0)
4167#define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\
4168 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
4169#define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\
4170 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)
4171
4172/* FDMA:FDMA:FDMA_CH_DISABLE */
4173#define FDMA_CH_DISABLE __REG(TARGET_FDMA,\
4174 0, 1, 8, 0, 1, 428, 8, 0, 1, 4)
4175
4176#define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0)
4177#define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\
4178 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
4179#define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\
4180 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)
4181
4182/* FDMA:FDMA:FDMA_DCB_LLP */
4183#define FDMA_DCB_LLP(r) __REG(TARGET_FDMA,\
4184 0, 1, 8, 0, 1, 428, 52, r, 8, 4)
4185
4186/* FDMA:FDMA:FDMA_DCB_LLP1 */
4187#define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA,\
4188 0, 1, 8, 0, 1, 428, 84, r, 8, 4)
4189
4190/* FDMA:FDMA:FDMA_DCB_LLP_PREV */
4191#define FDMA_DCB_LLP_PREV(r) __REG(TARGET_FDMA,\
4192 0, 1, 8, 0, 1, 428, 116, r, 8, 4)
4193
4194/* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */
4195#define FDMA_DCB_LLP_PREV1(r) __REG(TARGET_FDMA,\
4196 0, 1, 8, 0, 1, 428, 148, r, 8, 4)
4197
4198/* FDMA:FDMA:FDMA_CH_CFG */
4199#define FDMA_CH_CFG(r) __REG(TARGET_FDMA,\
4200 0, 1, 8, 0, 1, 428, 224, r, 8, 4)
4201
4202#define FDMA_CH_CFG_CH_XTR_STATUS_MODE BIT(7)
4203#define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\
4204 FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
4205#define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\
4206 FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
4207
4208#define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(6)
4209#define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\
4210 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
4211#define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\
4212 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
4213
4214#define FDMA_CH_CFG_CH_INJ_PORT BIT(5)
4215#define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\
4216 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x)
4217#define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\
4218 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x)
4219
4220#define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(4, 1)
4221#define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\
4222 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
4223#define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\
4224 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
4225
4226#define FDMA_CH_CFG_CH_MEM BIT(0)
4227#define FDMA_CH_CFG_CH_MEM_SET(x)\
4228 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
4229#define FDMA_CH_CFG_CH_MEM_GET(x)\
4230 FIELD_GET(FDMA_CH_CFG_CH_MEM, x)
4231
4232/* FDMA:FDMA:FDMA_CH_TRANSLATE */
4233#define FDMA_CH_TRANSLATE(r) __REG(TARGET_FDMA,\
4234 0, 1, 8, 0, 1, 428, 256, r, 8, 4)
4235
4236#define FDMA_CH_TRANSLATE_OFFSET GENMASK(15, 0)
4237#define FDMA_CH_TRANSLATE_OFFSET_SET(x)\
4238 FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x)
4239#define FDMA_CH_TRANSLATE_OFFSET_GET(x)\
4240 FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x)
4241
4242/* FDMA:FDMA:FDMA_XTR_CFG */
4243#define FDMA_XTR_CFG __REG(TARGET_FDMA,\
4244 0, 1, 8, 0, 1, 428, 364, 0, 1, 4)
4245
4246#define FDMA_XTR_CFG_XTR_FIFO_WM GENMASK(15, 11)
4247#define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\
4248 FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x)
4249#define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\
4250 FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x)
4251
4252#define FDMA_XTR_CFG_XTR_ARB_SAT GENMASK(10, 0)
4253#define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\
4254 FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x)
4255#define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\
4256 FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x)
4257
4258/* FDMA:FDMA:FDMA_PORT_CTRL */
4259#define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA,\
4260 0, 1, 8, 0, 1, 428, 376, r, 2, 4)
4261
4262#define FDMA_PORT_CTRL_INJ_STOP BIT(4)
4263#define FDMA_PORT_CTRL_INJ_STOP_SET(x)\
4264 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
4265#define FDMA_PORT_CTRL_INJ_STOP_GET(x)\
4266 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)
4267
4268#define FDMA_PORT_CTRL_INJ_STOP_FORCE BIT(3)
4269#define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\
4270 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
4271#define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\
4272 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
4273
4274#define FDMA_PORT_CTRL_XTR_STOP BIT(2)
4275#define FDMA_PORT_CTRL_XTR_STOP_SET(x)\
4276 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
4277#define FDMA_PORT_CTRL_XTR_STOP_GET(x)\
4278 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)
4279
4280#define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY BIT(1)
4281#define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\
4282 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
4283#define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\
4284 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
4285
4286#define FDMA_PORT_CTRL_XTR_BUF_RST BIT(0)
4287#define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\
4288 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x)
4289#define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\
4290 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x)
4291
4292/* FDMA:FDMA:FDMA_INTR_DCB */
4293#define FDMA_INTR_DCB __REG(TARGET_FDMA,\
4294 0, 1, 8, 0, 1, 428, 384, 0, 1, 4)
4295
4296#define FDMA_INTR_DCB_INTR_DCB GENMASK(7, 0)
4297#define FDMA_INTR_DCB_INTR_DCB_SET(x)\
4298 FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x)
4299#define FDMA_INTR_DCB_INTR_DCB_GET(x)\
4300 FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x)
4301
4302/* FDMA:FDMA:FDMA_INTR_DCB_ENA */
4303#define FDMA_INTR_DCB_ENA __REG(TARGET_FDMA,\
4304 0, 1, 8, 0, 1, 428, 388, 0, 1, 4)
4305
4306#define FDMA_INTR_DCB_ENA_INTR_DCB_ENA GENMASK(7, 0)
4307#define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\
4308 FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
4309#define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\
4310 FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
4311
4312/* FDMA:FDMA:FDMA_INTR_DB */
4313#define FDMA_INTR_DB __REG(TARGET_FDMA,\
4314 0, 1, 8, 0, 1, 428, 392, 0, 1, 4)
4315
4316#define FDMA_INTR_DB_INTR_DB GENMASK(7, 0)
4317#define FDMA_INTR_DB_INTR_DB_SET(x)\
4318 FIELD_PREP(FDMA_INTR_DB_INTR_DB, x)
4319#define FDMA_INTR_DB_INTR_DB_GET(x)\
4320 FIELD_GET(FDMA_INTR_DB_INTR_DB, x)
4321
4322/* FDMA:FDMA:FDMA_INTR_DB_ENA */
4323#define FDMA_INTR_DB_ENA __REG(TARGET_FDMA,\
4324 0, 1, 8, 0, 1, 428, 396, 0, 1, 4)
4325
4326#define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0)
4327#define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\
4328 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
4329#define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\
4330 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
4331
4332/* FDMA:FDMA:FDMA_INTR_ERR */
4333#define FDMA_INTR_ERR __REG(TARGET_FDMA,\
4334 0, 1, 8, 0, 1, 428, 400, 0, 1, 4)
4335
4336#define FDMA_INTR_ERR_INTR_PORT_ERR GENMASK(9, 8)
4337#define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\
4338 FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x)
4339#define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\
4340 FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x)
4341
4342#define FDMA_INTR_ERR_INTR_CH_ERR GENMASK(7, 0)
4343#define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\
4344 FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x)
4345#define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\
4346 FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x)
4347
4348/* FDMA:FDMA:FDMA_ERRORS */
4349#define FDMA_ERRORS __REG(TARGET_FDMA,\
4350 0, 1, 8, 0, 1, 428, 412, 0, 1, 4)
4351
4352#define FDMA_ERRORS_ERR_XTR_WR GENMASK(31, 30)
4353#define FDMA_ERRORS_ERR_XTR_WR_SET(x)\
4354 FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x)
4355#define FDMA_ERRORS_ERR_XTR_WR_GET(x)\
4356 FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x)
4357
4358#define FDMA_ERRORS_ERR_XTR_OVF GENMASK(29, 28)
4359#define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\
4360 FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x)
4361#define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\
4362 FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x)
4363
4364#define FDMA_ERRORS_ERR_XTR_TAXI32_OVF GENMASK(27, 26)
4365#define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\
4366 FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
4367#define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\
4368 FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
4369
4370#define FDMA_ERRORS_ERR_DCB_XTR_DATAL GENMASK(25, 24)
4371#define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\
4372 FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
4373#define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\
4374 FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
4375
4376#define FDMA_ERRORS_ERR_DCB_RD GENMASK(23, 16)
4377#define FDMA_ERRORS_ERR_DCB_RD_SET(x)\
4378 FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x)
4379#define FDMA_ERRORS_ERR_DCB_RD_GET(x)\
4380 FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x)
4381
4382#define FDMA_ERRORS_ERR_INJ_RD GENMASK(15, 10)
4383#define FDMA_ERRORS_ERR_INJ_RD_SET(x)\
4384 FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x)
4385#define FDMA_ERRORS_ERR_INJ_RD_GET(x)\
4386 FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x)
4387
4388#define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC GENMASK(9, 8)
4389#define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\
4390 FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
4391#define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\
4392 FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
4393
4394#define FDMA_ERRORS_ERR_CH_WR GENMASK(7, 0)
4395#define FDMA_ERRORS_ERR_CH_WR_SET(x)\
4396 FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x)
4397#define FDMA_ERRORS_ERR_CH_WR_GET(x)\
4398 FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x)
4399
4400/* FDMA:FDMA:FDMA_ERRORS_2 */
4401#define FDMA_ERRORS_2 __REG(TARGET_FDMA,\
4402 0, 1, 8, 0, 1, 428, 416, 0, 1, 4)
4403
4404#define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0)
4405#define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\
4406 FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
4407#define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\
4408 FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
4409
4410/* FDMA:FDMA:FDMA_CTRL */
4411#define FDMA_CTRL __REG(TARGET_FDMA,\
4412 0, 1, 8, 0, 1, 428, 424, 0, 1, 4)
4413
4414#define FDMA_CTRL_NRESET BIT(0)
4415#define FDMA_CTRL_NRESET_SET(x)\
4416 FIELD_PREP(FDMA_CTRL_NRESET, x)
4417#define FDMA_CTRL_NRESET_GET(x)\
4418 FIELD_GET(FDMA_CTRL_NRESET, x)
4419
4420/* DEVCPU_GCB:CHIP_REGS:CHIP_ID */
4421#define GCB_CHIP_ID __REG(TARGET_GCB,\
4422 0, 1, 0, 0, 1, 424, 0, 0, 1, 4)
4423
4424#define GCB_CHIP_ID_REV_ID GENMASK(31, 28)
4425#define GCB_CHIP_ID_REV_ID_SET(x)\
4426 FIELD_PREP(GCB_CHIP_ID_REV_ID, x)
4427#define GCB_CHIP_ID_REV_ID_GET(x)\
4428 FIELD_GET(GCB_CHIP_ID_REV_ID, x)
4429
4430#define GCB_CHIP_ID_PART_ID GENMASK(27, 12)
4431#define GCB_CHIP_ID_PART_ID_SET(x)\
4432 FIELD_PREP(GCB_CHIP_ID_PART_ID, x)
4433#define GCB_CHIP_ID_PART_ID_GET(x)\
4434 FIELD_GET(GCB_CHIP_ID_PART_ID, x)
4435
4436#define GCB_CHIP_ID_MFG_ID GENMASK(11, 1)
4437#define GCB_CHIP_ID_MFG_ID_SET(x)\
4438 FIELD_PREP(GCB_CHIP_ID_MFG_ID, x)
4439#define GCB_CHIP_ID_MFG_ID_GET(x)\
4440 FIELD_GET(GCB_CHIP_ID_MFG_ID, x)
4441
4442#define GCB_CHIP_ID_ONE BIT(0)
4443#define GCB_CHIP_ID_ONE_SET(x)\
4444 FIELD_PREP(GCB_CHIP_ID_ONE, x)
4445#define GCB_CHIP_ID_ONE_GET(x)\
4446 FIELD_GET(GCB_CHIP_ID_ONE, x)
4447
4448/* DEVCPU_GCB:CHIP_REGS:SOFT_RST */
4449#define GCB_SOFT_RST __REG(TARGET_GCB,\
4450 0, 1, 0, 0, 1, 424, 8, 0, 1, 4)
4451
4452#define GCB_SOFT_RST_SOFT_NON_CFG_RST BIT(2)
4453#define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\
4454 FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
4455#define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\
4456 FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
4457
4458#define GCB_SOFT_RST_SOFT_SWC_RST BIT(1)
4459#define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\
4460 FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x)
4461#define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\
4462 FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x)
4463
4464#define GCB_SOFT_RST_SOFT_CHIP_RST BIT(0)
4465#define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\
4466 FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x)
4467#define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\
4468 FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x)
4469
4470/* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */
4471#define GCB_HW_SGPIO_SD_CFG __REG(TARGET_GCB,\
4472 0, 1, 0, 0, 1, 424, 20, 0, 1, 4)
4473
4474#define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1)
4475#define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\
4476 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
4477#define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\
4478 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
4479
4480#define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL BIT(0)
4481#define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\
4482 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
4483#define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\
4484 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
4485
4486/* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */
4487#define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) __REG(TARGET_GCB,\
4488 0, 1, 0, 0, 1, 424, 24, r, 65, 4)
4489
4490#define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL GENMASK(8, 0)
4491#define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\
4492 FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
4493#define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\
4494 FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
4495
4496/* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */
4497#define GCB_SIO_CLOCK(g) __REG(TARGET_GCB,\
4498 0, 1, 876, g, 3, 280, 20, 0, 1, 4)
4499
4500#define GCB_SIO_CLOCK_SIO_CLK_FREQ GENMASK(19, 8)
4501#define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\
4502 FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
4503#define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\
4504 FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
4505
4506#define GCB_SIO_CLOCK_SYS_CLK_PERIOD GENMASK(7, 0)
4507#define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\
4508 FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
4509#define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\
4510 FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
4511
4512/* HSCH:HSCH_CFG:CIR_CFG */
4513#define HSCH_CIR_CFG(g) __REG(TARGET_HSCH,\
4514 0, 1, 0, g, 5040, 32, 0, 0, 1, 4)
4515
4516#define HSCH_CIR_CFG_CIR_RATE GENMASK(22, 6)
4517#define HSCH_CIR_CFG_CIR_RATE_SET(x)\
4518 FIELD_PREP(HSCH_CIR_CFG_CIR_RATE, x)
4519#define HSCH_CIR_CFG_CIR_RATE_GET(x)\
4520 FIELD_GET(HSCH_CIR_CFG_CIR_RATE, x)
4521
4522#define HSCH_CIR_CFG_CIR_BURST GENMASK(5, 0)
4523#define HSCH_CIR_CFG_CIR_BURST_SET(x)\
4524 FIELD_PREP(HSCH_CIR_CFG_CIR_BURST, x)
4525#define HSCH_CIR_CFG_CIR_BURST_GET(x)\
4526 FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x)
4527
4528/* HSCH:HSCH_CFG:EIR_CFG */
4529#define HSCH_EIR_CFG(g) __REG(TARGET_HSCH,\
4530 0, 1, 0, g, 5040, 32, 4, 0, 1, 4)
4531
4532#define HSCH_EIR_CFG_EIR_RATE GENMASK(22, 6)
4533#define HSCH_EIR_CFG_EIR_RATE_SET(x)\
4534 FIELD_PREP(HSCH_EIR_CFG_EIR_RATE, x)
4535#define HSCH_EIR_CFG_EIR_RATE_GET(x)\
4536 FIELD_GET(HSCH_EIR_CFG_EIR_RATE, x)
4537
4538#define HSCH_EIR_CFG_EIR_BURST GENMASK(5, 0)
4539#define HSCH_EIR_CFG_EIR_BURST_SET(x)\
4540 FIELD_PREP(HSCH_EIR_CFG_EIR_BURST, x)
4541#define HSCH_EIR_CFG_EIR_BURST_GET(x)\
4542 FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x)
4543
4544/* HSCH:HSCH_CFG:SE_CFG */
4545#define HSCH_SE_CFG(g) __REG(TARGET_HSCH,\
4546 0, 1, 0, g, 5040, 32, 8, 0, 1, 4)
4547
4548#define HSCH_SE_CFG_SE_DWRR_CNT GENMASK(12, 6)
4549#define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\
4550 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_CNT, x)
4551#define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\
4552 FIELD_GET(HSCH_SE_CFG_SE_DWRR_CNT, x)
4553
4554#define HSCH_SE_CFG_SE_AVB_ENA BIT(5)
4555#define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\
4556 FIELD_PREP(HSCH_SE_CFG_SE_AVB_ENA, x)
4557#define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\
4558 FIELD_GET(HSCH_SE_CFG_SE_AVB_ENA, x)
4559
4560#define HSCH_SE_CFG_SE_FRM_MODE GENMASK(4, 3)
4561#define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\
4562 FIELD_PREP(HSCH_SE_CFG_SE_FRM_MODE, x)
4563#define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\
4564 FIELD_GET(HSCH_SE_CFG_SE_FRM_MODE, x)
4565
4566#define HSCH_SE_CFG_SE_DWRR_FRM_MODE GENMASK(2, 1)
4567#define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\
4568 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x)
4569#define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\
4570 FIELD_GET(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x)
4571
4572#define HSCH_SE_CFG_SE_STOP BIT(0)
4573#define HSCH_SE_CFG_SE_STOP_SET(x)\
4574 FIELD_PREP(HSCH_SE_CFG_SE_STOP, x)
4575#define HSCH_SE_CFG_SE_STOP_GET(x)\
4576 FIELD_GET(HSCH_SE_CFG_SE_STOP, x)
4577
4578/* HSCH:HSCH_CFG:SE_CONNECT */
4579#define HSCH_SE_CONNECT(g) __REG(TARGET_HSCH,\
4580 0, 1, 0, g, 5040, 32, 12, 0, 1, 4)
4581
4582#define HSCH_SE_CONNECT_SE_LEAK_LINK GENMASK(15, 0)
4583#define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\
4584 FIELD_PREP(HSCH_SE_CONNECT_SE_LEAK_LINK, x)
4585#define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\
4586 FIELD_GET(HSCH_SE_CONNECT_SE_LEAK_LINK, x)
4587
4588/* HSCH:HSCH_CFG:SE_DLB_SENSE */
4589#define HSCH_SE_DLB_SENSE(g) __REG(TARGET_HSCH,\
4590 0, 1, 0, g, 5040, 32, 16, 0, 1, 4)
4591
4592#define HSCH_SE_DLB_SENSE_SE_DLB_PRIO GENMASK(12, 10)
4593#define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\
4594 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x)
4595#define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\
4596 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x)
4597
4598#define HSCH_SE_DLB_SENSE_SE_DLB_DPORT GENMASK(9, 3)
4599#define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\
4600 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x)
4601#define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\
4602 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x)
4603
4604#define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA BIT(2)
4605#define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\
4606 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x)
4607#define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\
4608 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x)
4609
4610#define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(1)
4611#define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\
4612 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x)
4613#define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\
4614 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x)
4615
4616#define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0)
4617#define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\
4618 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x)
4619#define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\
4620 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x)
4621
4622/* HSCH:HSCH_DWRR:DWRR_ENTRY */
4623#define HSCH_DWRR_ENTRY(g) __REG(TARGET_HSCH,\
4624 0, 1, 162816, g, 72, 4, 0, 0, 1, 4)
4625
4626#define HSCH_DWRR_ENTRY_DWRR_COST GENMASK(24, 20)
4627#define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\
4628 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_COST, x)
4629#define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\
4630 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_COST, x)
4631
4632#define HSCH_DWRR_ENTRY_DWRR_BALANCE GENMASK(19, 0)
4633#define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\
4634 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_BALANCE, x)
4635#define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\
4636 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x)
4637
4638/* HSCH:HSCH_MISC:HSCH_CFG_CFG */
4639#define HSCH_HSCH_CFG_CFG __REG(TARGET_HSCH,\
4640 0, 1, 163104, 0, 1, 648, 284, 0, 1, 4)
4641
4642#define HSCH_HSCH_CFG_CFG_CFG_SE_IDX GENMASK(26, 14)
4643#define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\
4644 FIELD_PREP(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x)
4645#define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\
4646 FIELD_GET(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x)
4647
4648#define HSCH_HSCH_CFG_CFG_HSCH_LAYER GENMASK(13, 12)
4649#define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\
4650 FIELD_PREP(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x)
4651#define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\
4652 FIELD_GET(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x)
4653
4654#define HSCH_HSCH_CFG_CFG_CSR_GRANT GENMASK(11, 0)
4655#define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\
4656 FIELD_PREP(HSCH_HSCH_CFG_CFG_CSR_GRANT, x)
4657#define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\
4658 FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x)
4659
4660/* HSCH:HSCH_MISC:SYS_CLK_PER */
4661#define HSCH_SYS_CLK_PER __REG(TARGET_HSCH,\
4662 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4)
4663
4664#define HSCH_SYS_CLK_PER_100PS GENMASK(7, 0)
4665#define HSCH_SYS_CLK_PER_100PS_SET(x)\
4666 FIELD_PREP(HSCH_SYS_CLK_PER_100PS, x)
4667#define HSCH_SYS_CLK_PER_100PS_GET(x)\
4668 FIELD_GET(HSCH_SYS_CLK_PER_100PS, x)
4669
4670/* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */
4671#define HSCH_HSCH_TIMER_CFG(g, r) __REG(TARGET_HSCH,\
4672 0, 1, 161664, g, 4, 32, 0, r, 4, 4)
4673
4674#define HSCH_HSCH_TIMER_CFG_LEAK_TIME GENMASK(17, 0)
4675#define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\
4676 FIELD_PREP(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x)
4677#define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\
4678 FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x)
4679
4680/* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */
4681#define HSCH_HSCH_LEAK_CFG(g, r) __REG(TARGET_HSCH,\
4682 0, 1, 161664, g, 4, 32, 16, r, 4, 4)
4683
4684#define HSCH_HSCH_LEAK_CFG_LEAK_FIRST GENMASK(16, 1)
4685#define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\
4686 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x)
4687#define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\
4688 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x)
4689
4690#define HSCH_HSCH_LEAK_CFG_LEAK_ERR BIT(0)
4691#define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\
4692 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x)
4693#define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\
4694 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x)
4695
4696/* HSCH:SYSTEM:FLUSH_CTRL */
4697#define HSCH_FLUSH_CTRL __REG(TARGET_HSCH,\
4698 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4)
4699
4700#define HSCH_FLUSH_CTRL_FLUSH_ENA BIT(27)
4701#define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\
4702 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
4703#define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\
4704 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
4705
4706#define HSCH_FLUSH_CTRL_FLUSH_SRC BIT(26)
4707#define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\
4708 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
4709#define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\
4710 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
4711
4712#define HSCH_FLUSH_CTRL_FLUSH_DST BIT(25)
4713#define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\
4714 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x)
4715#define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\
4716 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x)
4717
4718#define HSCH_FLUSH_CTRL_FLUSH_PORT GENMASK(24, 18)
4719#define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\
4720 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
4721#define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\
4722 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
4723
4724#define HSCH_FLUSH_CTRL_FLUSH_QUEUE BIT(17)
4725#define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\
4726 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
4727#define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\
4728 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
4729
4730#define HSCH_FLUSH_CTRL_FLUSH_SE BIT(16)
4731#define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\
4732 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x)
4733#define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\
4734 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x)
4735
4736#define HSCH_FLUSH_CTRL_FLUSH_HIER GENMASK(15, 0)
4737#define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\
4738 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
4739#define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\
4740 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
4741
4742/* HSCH:SYSTEM:PORT_MODE */
4743#define HSCH_PORT_MODE(r) __REG(TARGET_HSCH,\
4744 0, 1, 184000, 0, 1, 312, 8, r, 70, 4)
4745
4746#define HSCH_PORT_MODE_DEQUEUE_DIS BIT(4)
4747#define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\
4748 FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x)
4749#define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\
4750 FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x)
4751
4752#define HSCH_PORT_MODE_AGE_DIS BIT(3)
4753#define HSCH_PORT_MODE_AGE_DIS_SET(x)\
4754 FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x)
4755#define HSCH_PORT_MODE_AGE_DIS_GET(x)\
4756 FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x)
4757
4758#define HSCH_PORT_MODE_TRUNC_ENA BIT(2)
4759#define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\
4760 FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x)
4761#define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\
4762 FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x)
4763
4764#define HSCH_PORT_MODE_EIR_REMARK_ENA BIT(1)
4765#define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\
4766 FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
4767#define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\
4768 FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
4769
4770#define HSCH_PORT_MODE_CPU_PRIO_MODE BIT(0)
4771#define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\
4772 FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
4773#define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\
4774 FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
4775
4776/* HSCH:SYSTEM:OUTB_SHARE_ENA */
4777#define HSCH_OUTB_SHARE_ENA(r) __REG(TARGET_HSCH,\
4778 0, 1, 184000, 0, 1, 312, 288, r, 5, 4)
4779
4780#define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA GENMASK(7, 0)
4781#define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\
4782 FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
4783#define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\
4784 FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
4785
4786/* HSCH:MMGT:RESET_CFG */
4787#define HSCH_RESET_CFG __REG(TARGET_HSCH,\
4788 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4)
4789
4790#define HSCH_RESET_CFG_CORE_ENA BIT(0)
4791#define HSCH_RESET_CFG_CORE_ENA_SET(x)\
4792 FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x)
4793#define HSCH_RESET_CFG_CORE_ENA_GET(x)\
4794 FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x)
4795
4796/* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */
4797#define HSCH_TAS_STATEMACHINE_CFG __REG(TARGET_HSCH,\
4798 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4)
4799
4800#define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY GENMASK(7, 0)
4801#define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\
4802 FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
4803#define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\
4804 FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
4805
4806/* LRN:COMMON:COMMON_ACCESS_CTRL */
4807#define LRN_COMMON_ACCESS_CTRL __REG(TARGET_LRN,\
4808 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
4809
4810#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20)
4811#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\
4812 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
4813#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\
4814 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
4815
4816#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE BIT(19)
4817#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\
4818 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
4819#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\
4820 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
4821
4822#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW GENMASK(18, 5)
4823#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\
4824 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
4825#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\
4826 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
4827
4828#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1)
4829#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\
4830 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
4831#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\
4832 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
4833
4834#define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0)
4835#define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\
4836 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
4837#define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\
4838 FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
4839
4840/* LRN:COMMON:MAC_ACCESS_CFG_0 */
4841#define LRN_MAC_ACCESS_CFG_0 __REG(TARGET_LRN,\
4842 0, 1, 0, 0, 1, 72, 4, 0, 1, 4)
4843
4844#define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16)
4845#define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\
4846 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
4847#define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\
4848 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
4849
4850#define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB GENMASK(15, 0)
4851#define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\
4852 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
4853#define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\
4854 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
4855
4856/* LRN:COMMON:MAC_ACCESS_CFG_1 */
4857#define LRN_MAC_ACCESS_CFG_1 __REG(TARGET_LRN,\
4858 0, 1, 0, 0, 1, 72, 8, 0, 1, 4)
4859
4860/* LRN:COMMON:MAC_ACCESS_CFG_2 */
4861#define LRN_MAC_ACCESS_CFG_2 __REG(TARGET_LRN,\
4862 0, 1, 0, 0, 1, 72, 12, 0, 1, 4)
4863
4864#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28)
4865#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\
4866 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
4867#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\
4868 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
4869
4870#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL BIT(27)
4871#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\
4872 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
4873#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\
4874 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
4875
4876#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU GENMASK(26, 24)
4877#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\
4878 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
4879#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\
4880 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
4881
4882#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY BIT(23)
4883#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\
4884 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
4885#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\
4886 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
4887
4888#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE BIT(22)
4889#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\
4890 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
4891#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\
4892 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
4893
4894#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR BIT(21)
4895#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\
4896 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
4897#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\
4898 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
4899
4900#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG GENMASK(20, 19)
4901#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\
4902 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
4903#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\
4904 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
4905
4906#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL GENMASK(18, 17)
4907#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\
4908 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
4909#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\
4910 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
4911
4912#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED BIT(16)
4913#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\
4914 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
4915#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\
4916 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
4917
4918#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD BIT(15)
4919#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\
4920 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
4921#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\
4922 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
4923
4924#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12)
4925#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\
4926 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
4927#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\
4928 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
4929
4930#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR GENMASK(11, 0)
4931#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\
4932 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
4933#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\
4934 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
4935
4936/* LRN:COMMON:MAC_ACCESS_CFG_3 */
4937#define LRN_MAC_ACCESS_CFG_3 __REG(TARGET_LRN,\
4938 0, 1, 0, 0, 1, 72, 16, 0, 1, 4)
4939
4940#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX GENMASK(10, 0)
4941#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\
4942 FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
4943#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\
4944 FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
4945
4946/* LRN:COMMON:SCAN_NEXT_CFG */
4947#define LRN_SCAN_NEXT_CFG __REG(TARGET_LRN,\
4948 0, 1, 0, 0, 1, 72, 20, 0, 1, 4)
4949
4950#define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19)
4951#define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\
4952 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
4953#define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\
4954 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
4955
4956#define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL GENMASK(18, 17)
4957#define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\
4958 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
4959#define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\
4960 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
4961
4962#define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL GENMASK(16, 15)
4963#define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\
4964 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
4965#define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\
4966 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
4967
4968#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA BIT(14)
4969#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\
4970 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
4971#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\
4972 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
4973
4974#define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA BIT(13)
4975#define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\
4976 FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
4977#define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\
4978 FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
4979
4980#define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA BIT(12)
4981#define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\
4982 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
4983#define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\
4984 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
4985
4986#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA BIT(11)
4987#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\
4988 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
4989#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\
4990 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
4991
4992#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA BIT(10)
4993#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\
4994 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
4995#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\
4996 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
4997
4998#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA BIT(9)
4999#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\
5000 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
5001#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\
5002 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
5003
5004#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA BIT(8)
5005#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\
5006 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
5007#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\
5008 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
5009
5010#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA BIT(7)
5011#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\
5012 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
5013#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\
5014 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
5015
5016#define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK GENMASK(6, 3)
5017#define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\
5018 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
5019#define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\
5020 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
5021
5022#define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA BIT(2)
5023#define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\
5024 FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
5025#define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\
5026 FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
5027
5028#define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA BIT(1)
5029#define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\
5030 FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
5031#define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\
5032 FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
5033
5034#define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA BIT(0)
5035#define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\
5036 FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
5037#define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\
5038 FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
5039
5040/* LRN:COMMON:SCAN_NEXT_CFG_1 */
5041#define LRN_SCAN_NEXT_CFG_1 __REG(TARGET_LRN,\
5042 0, 1, 0, 0, 1, 72, 24, 0, 1, 4)
5043
5044#define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR GENMASK(30, 16)
5045#define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\
5046 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
5047#define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\
5048 FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
5049
5050#define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK GENMASK(14, 0)
5051#define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\
5052 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
5053#define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\
5054 FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
5055
5056/* LRN:COMMON:AUTOAGE_CFG */
5057#define LRN_AUTOAGE_CFG(r) __REG(TARGET_LRN,\
5058 0, 1, 0, 0, 1, 72, 36, r, 4, 4)
5059
5060#define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28)
5061#define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\
5062 FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
5063#define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\
5064 FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
5065
5066#define LRN_AUTOAGE_CFG_PERIOD_VAL GENMASK(27, 0)
5067#define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\
5068 FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
5069#define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\
5070 FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
5071
5072/* LRN:COMMON:AUTOAGE_CFG_1 */
5073#define LRN_AUTOAGE_CFG_1 __REG(TARGET_LRN,\
5074 0, 1, 0, 0, 1, 72, 52, 0, 1, 4)
5075
5076#define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA BIT(25)
5077#define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\
5078 FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
5079#define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\
5080 FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
5081
5082#define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN GENMASK(24, 15)
5083#define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\
5084 FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
5085#define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\
5086 FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
5087
5088#define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS GENMASK(14, 7)
5089#define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\
5090 FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
5091#define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\
5092 FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
5093
5094#define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA BIT(6)
5095#define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\
5096 FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
5097#define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\
5098 FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
5099
5100#define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT GENMASK(5, 2)
5101#define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\
5102 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
5103#define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\
5104 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
5105
5106#define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1)
5107#define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\
5108 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
5109#define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\
5110 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
5111
5112#define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA BIT(0)
5113#define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\
5114 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
5115#define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\
5116 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
5117
5118/* LRN:COMMON:AUTOAGE_CFG_2 */
5119#define LRN_AUTOAGE_CFG_2 __REG(TARGET_LRN,\
5120 0, 1, 0, 0, 1, 72, 56, 0, 1, 4)
5121
5122#define LRN_AUTOAGE_CFG_2_NEXT_ROW GENMASK(17, 4)
5123#define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\
5124 FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
5125#define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\
5126 FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
5127
5128#define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS GENMASK(3, 0)
5129#define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\
5130 FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
5131#define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\
5132 FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
5133
5134/* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */
5135#define PCEP_RCTRL_2_OUT_0 __REG(TARGET_PCEP,\
5136 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4)
5137
5138#define PCEP_RCTRL_2_OUT_0_MSG_CODE GENMASK(7, 0)
5139#define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\
5140 FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
5141#define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\
5142 FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
5143
5144#define PCEP_RCTRL_2_OUT_0_TAG GENMASK(15, 8)
5145#define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\
5146 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x)
5147#define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\
5148 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x)
5149
5150#define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN BIT(16)
5151#define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\
5152 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
5153#define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\
5154 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
5155
5156#define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS BIT(19)
5157#define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\
5158 FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
5159#define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\
5160 FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
5161
5162#define PCEP_RCTRL_2_OUT_0_SNP BIT(20)
5163#define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\
5164 FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x)
5165#define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\
5166 FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x)
5167
5168#define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD BIT(22)
5169#define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\
5170 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
5171#define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\
5172 FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
5173
5174#define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN BIT(23)
5175#define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\
5176 FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
5177#define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\
5178 FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
5179
5180#define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE BIT(28)
5181#define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\
5182 FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
5183#define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\
5184 FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
5185
5186#define PCEP_RCTRL_2_OUT_0_INVERT_MODE BIT(29)
5187#define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\
5188 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
5189#define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\
5190 FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
5191
5192#define PCEP_RCTRL_2_OUT_0_REGION_EN BIT(31)
5193#define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\
5194 FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
5195#define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\
5196 FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
5197
5198/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */
5199#define PCEP_ADDR_LWR_OUT_0 __REG(TARGET_PCEP,\
5200 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4)
5201
5202#define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW GENMASK(15, 0)
5203#define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\
5204 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
5205#define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\
5206 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
5207
5208#define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW GENMASK(31, 16)
5209#define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\
5210 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
5211#define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\
5212 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
5213
5214/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */
5215#define PCEP_ADDR_UPR_OUT_0 __REG(TARGET_PCEP,\
5216 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4)
5217
5218/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */
5219#define PCEP_ADDR_LIM_OUT_0 __REG(TARGET_PCEP,\
5220 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4)
5221
5222#define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW GENMASK(15, 0)
5223#define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\
5224 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
5225#define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\
5226 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
5227
5228#define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW GENMASK(31, 16)
5229#define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\
5230 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
5231#define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\
5232 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
5233
5234/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */
5235#define PCEP_ADDR_LWR_TGT_OUT_0 __REG(TARGET_PCEP,\
5236 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4)
5237
5238/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */
5239#define PCEP_ADDR_UPR_TGT_OUT_0 __REG(TARGET_PCEP,\
5240 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4)
5241
5242/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */
5243#define PCEP_ADDR_UPR_LIM_OUT_0 __REG(TARGET_PCEP,\
5244 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4)
5245
5246#define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0)
5247#define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\
5248 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
5249#define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\
5250 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
5251
5252#define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW GENMASK(31, 2)
5253#define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\
5254 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
5255#define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\
5256 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
5257
5258/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
5259#define PCS10G_BR_PCS_CFG(t) __REG(TARGET_PCS10G_BR,\
5260 t, 12, 0, 0, 1, 56, 0, 0, 1, 4)
5261
5262#define PCS10G_BR_PCS_CFG_PCS_ENA BIT(31)
5263#define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\
5264 FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x)
5265#define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\
5266 FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x)
5267
5268#define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30)
5269#define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
5270 FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5271#define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
5272 FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5273
5274#define PCS10G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24)
5275#define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
5276 FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
5277#define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
5278 FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
5279
5280#define PCS10G_BR_PCS_CFG_RX_DATA_FLIP BIT(18)
5281#define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
5282 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
5283#define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
5284 FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
5285
5286#define PCS10G_BR_PCS_CFG_RESYNC_ENA BIT(15)
5287#define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
5288 FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
5289#define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
5290 FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
5291
5292#define PCS10G_BR_PCS_CFG_LF_GEN_DIS BIT(14)
5293#define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
5294 FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
5295#define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
5296 FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
5297
5298#define PCS10G_BR_PCS_CFG_RX_TEST_MODE BIT(13)
5299#define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
5300 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
5301#define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
5302 FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
5303
5304#define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12)
5305#define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
5306 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5307#define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
5308 FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5309
5310#define PCS10G_BR_PCS_CFG_TX_DATA_FLIP BIT(7)
5311#define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
5312 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
5313#define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
5314 FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
5315
5316#define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6)
5317#define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
5318 FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5319#define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
5320 FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5321
5322#define PCS10G_BR_PCS_CFG_TX_TEST_MODE BIT(4)
5323#define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
5324 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
5325#define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
5326 FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
5327
5328#define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3)
5329#define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
5330 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5331#define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
5332 FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5333
5334/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
5335#define PCS10G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS10G_BR,\
5336 t, 12, 0, 0, 1, 56, 4, 0, 1, 4)
5337
5338#define PCS10G_BR_PCS_SD_CFG_SD_SEL BIT(8)
5339#define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
5340 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
5341#define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
5342 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
5343
5344#define PCS10G_BR_PCS_SD_CFG_SD_POL BIT(4)
5345#define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\
5346 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
5347#define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\
5348 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
5349
5350#define PCS10G_BR_PCS_SD_CFG_SD_ENA BIT(0)
5351#define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
5352 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
5353#define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
5354 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
5355
5356/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
5357#define PCS25G_BR_PCS_CFG(t) __REG(TARGET_PCS25G_BR,\
5358 t, 8, 0, 0, 1, 56, 0, 0, 1, 4)
5359
5360#define PCS25G_BR_PCS_CFG_PCS_ENA BIT(31)
5361#define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\
5362 FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x)
5363#define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\
5364 FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x)
5365
5366#define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30)
5367#define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
5368 FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5369#define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
5370 FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5371
5372#define PCS25G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24)
5373#define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
5374 FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
5375#define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
5376 FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
5377
5378#define PCS25G_BR_PCS_CFG_RX_DATA_FLIP BIT(18)
5379#define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
5380 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
5381#define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
5382 FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
5383
5384#define PCS25G_BR_PCS_CFG_RESYNC_ENA BIT(15)
5385#define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
5386 FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
5387#define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
5388 FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
5389
5390#define PCS25G_BR_PCS_CFG_LF_GEN_DIS BIT(14)
5391#define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
5392 FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
5393#define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
5394 FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
5395
5396#define PCS25G_BR_PCS_CFG_RX_TEST_MODE BIT(13)
5397#define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
5398 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
5399#define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
5400 FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
5401
5402#define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12)
5403#define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
5404 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5405#define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
5406 FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5407
5408#define PCS25G_BR_PCS_CFG_TX_DATA_FLIP BIT(7)
5409#define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
5410 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
5411#define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
5412 FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
5413
5414#define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6)
5415#define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
5416 FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5417#define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
5418 FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5419
5420#define PCS25G_BR_PCS_CFG_TX_TEST_MODE BIT(4)
5421#define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
5422 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
5423#define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
5424 FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
5425
5426#define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3)
5427#define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
5428 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5429#define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
5430 FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5431
5432/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
5433#define PCS25G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS25G_BR,\
5434 t, 8, 0, 0, 1, 56, 4, 0, 1, 4)
5435
5436#define PCS25G_BR_PCS_SD_CFG_SD_SEL BIT(8)
5437#define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
5438 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
5439#define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
5440 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
5441
5442#define PCS25G_BR_PCS_SD_CFG_SD_POL BIT(4)
5443#define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\
5444 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
5445#define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\
5446 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
5447
5448#define PCS25G_BR_PCS_SD_CFG_SD_ENA BIT(0)
5449#define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
5450 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
5451#define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
5452 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
5453
5454/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
5455#define PCS5G_BR_PCS_CFG(t) __REG(TARGET_PCS5G_BR,\
5456 t, 13, 0, 0, 1, 56, 0, 0, 1, 4)
5457
5458#define PCS5G_BR_PCS_CFG_PCS_ENA BIT(31)
5459#define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\
5460 FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x)
5461#define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\
5462 FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x)
5463
5464#define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30)
5465#define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
5466 FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5467#define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
5468 FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5469
5470#define PCS5G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24)
5471#define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
5472 FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
5473#define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
5474 FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
5475
5476#define PCS5G_BR_PCS_CFG_RX_DATA_FLIP BIT(18)
5477#define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
5478 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
5479#define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
5480 FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
5481
5482#define PCS5G_BR_PCS_CFG_RESYNC_ENA BIT(15)
5483#define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
5484 FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
5485#define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
5486 FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
5487
5488#define PCS5G_BR_PCS_CFG_LF_GEN_DIS BIT(14)
5489#define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
5490 FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
5491#define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
5492 FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
5493
5494#define PCS5G_BR_PCS_CFG_RX_TEST_MODE BIT(13)
5495#define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
5496 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
5497#define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
5498 FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
5499
5500#define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12)
5501#define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
5502 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5503#define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
5504 FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5505
5506#define PCS5G_BR_PCS_CFG_TX_DATA_FLIP BIT(7)
5507#define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
5508 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
5509#define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
5510 FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
5511
5512#define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6)
5513#define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
5514 FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5515#define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
5516 FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5517
5518#define PCS5G_BR_PCS_CFG_TX_TEST_MODE BIT(4)
5519#define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
5520 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
5521#define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
5522 FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
5523
5524#define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3)
5525#define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
5526 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5527#define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
5528 FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5529
5530/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
5531#define PCS5G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS5G_BR,\
5532 t, 13, 0, 0, 1, 56, 4, 0, 1, 4)
5533
5534#define PCS5G_BR_PCS_SD_CFG_SD_SEL BIT(8)
5535#define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
5536 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
5537#define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
5538 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
5539
5540#define PCS5G_BR_PCS_SD_CFG_SD_POL BIT(4)
5541#define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\
5542 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
5543#define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\
5544 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
5545
5546#define PCS5G_BR_PCS_SD_CFG_SD_ENA BIT(0)
5547#define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
5548 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
5549#define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
5550 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
5551
5552/* PORT_CONF:HW_CFG:DEV5G_MODES */
5553#define PORT_CONF_DEV5G_MODES __REG(TARGET_PORT_CONF,\
5554 0, 1, 0, 0, 1, 24, 0, 0, 1, 4)
5555
5556#define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE BIT(0)
5557#define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\
5558 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
5559#define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\
5560 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
5561
5562#define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1)
5563#define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\
5564 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
5565#define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\
5566 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
5567
5568#define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE BIT(2)
5569#define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\
5570 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
5571#define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\
5572 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
5573
5574#define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE BIT(3)
5575#define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\
5576 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
5577#define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\
5578 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
5579
5580#define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE BIT(4)
5581#define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\
5582 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
5583#define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\
5584 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
5585
5586#define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE BIT(5)
5587#define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\
5588 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
5589#define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\
5590 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
5591
5592#define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE BIT(6)
5593#define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\
5594 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
5595#define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\
5596 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
5597
5598#define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE BIT(7)
5599#define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\
5600 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
5601#define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\
5602 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
5603
5604#define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE BIT(8)
5605#define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\
5606 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
5607#define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\
5608 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
5609
5610#define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE BIT(9)
5611#define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\
5612 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
5613#define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\
5614 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
5615
5616#define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE BIT(10)
5617#define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\
5618 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
5619#define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\
5620 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
5621
5622#define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE BIT(11)
5623#define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\
5624 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
5625#define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\
5626 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
5627
5628#define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12)
5629#define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\
5630 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
5631#define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\
5632 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
5633
5634/* PORT_CONF:HW_CFG:DEV10G_MODES */
5635#define PORT_CONF_DEV10G_MODES __REG(TARGET_PORT_CONF,\
5636 0, 1, 0, 0, 1, 24, 4, 0, 1, 4)
5637
5638#define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE BIT(0)
5639#define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\
5640 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
5641#define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\
5642 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
5643
5644#define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1)
5645#define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\
5646 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
5647#define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\
5648 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
5649
5650#define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE BIT(2)
5651#define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\
5652 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
5653#define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\
5654 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
5655
5656#define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE BIT(3)
5657#define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\
5658 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
5659#define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\
5660 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
5661
5662#define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE BIT(4)
5663#define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\
5664 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
5665#define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\
5666 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
5667
5668#define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE BIT(5)
5669#define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\
5670 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
5671#define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\
5672 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
5673
5674#define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE BIT(6)
5675#define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\
5676 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
5677#define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\
5678 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
5679
5680#define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE BIT(7)
5681#define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\
5682 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
5683#define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\
5684 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
5685
5686#define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE BIT(8)
5687#define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\
5688 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
5689#define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\
5690 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
5691
5692#define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE BIT(9)
5693#define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\
5694 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
5695#define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\
5696 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
5697
5698#define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE BIT(10)
5699#define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\
5700 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
5701#define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\
5702 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
5703
5704#define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE BIT(11)
5705#define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\
5706 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
5707#define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\
5708 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
5709
5710/* PORT_CONF:HW_CFG:DEV25G_MODES */
5711#define PORT_CONF_DEV25G_MODES __REG(TARGET_PORT_CONF,\
5712 0, 1, 0, 0, 1, 24, 8, 0, 1, 4)
5713
5714#define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE BIT(0)
5715#define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\
5716 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
5717#define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\
5718 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
5719
5720#define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE BIT(1)
5721#define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\
5722 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
5723#define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\
5724 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
5725
5726#define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE BIT(2)
5727#define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\
5728 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
5729#define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\
5730 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
5731
5732#define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE BIT(3)
5733#define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\
5734 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
5735#define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\
5736 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
5737
5738#define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE BIT(4)
5739#define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\
5740 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
5741#define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\
5742 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
5743
5744#define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE BIT(5)
5745#define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\
5746 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
5747#define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\
5748 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
5749
5750#define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE BIT(6)
5751#define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\
5752 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
5753#define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\
5754 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
5755
5756#define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE BIT(7)
5757#define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\
5758 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
5759#define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\
5760 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
5761
5762/* PORT_CONF:HW_CFG:QSGMII_ENA */
5763#define PORT_CONF_QSGMII_ENA __REG(TARGET_PORT_CONF,\
5764 0, 1, 0, 0, 1, 24, 12, 0, 1, 4)
5765
5766#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0 BIT(0)
5767#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\
5768 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
5769#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\
5770 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
5771
5772#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1 BIT(1)
5773#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\
5774 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
5775#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\
5776 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
5777
5778#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2 BIT(2)
5779#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\
5780 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
5781#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\
5782 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
5783
5784#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3 BIT(3)
5785#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\
5786 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
5787#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\
5788 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
5789
5790#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4 BIT(4)
5791#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\
5792 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
5793#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\
5794 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
5795
5796#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5 BIT(5)
5797#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\
5798 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
5799#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\
5800 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
5801
5802#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6 BIT(6)
5803#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\
5804 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
5805#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\
5806 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
5807
5808#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7 BIT(7)
5809#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\
5810 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
5811#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\
5812 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
5813
5814#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8 BIT(8)
5815#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\
5816 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
5817#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\
5818 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
5819
5820#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9 BIT(9)
5821#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\
5822 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
5823#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\
5824 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
5825
5826#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10 BIT(10)
5827#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\
5828 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
5829#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\
5830 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
5831
5832#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11 BIT(11)
5833#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\
5834 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
5835#define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\
5836 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
5837
5838/* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */
5839#define PORT_CONF_USGMII_CFG(g) __REG(TARGET_PORT_CONF,\
5840 0, 1, 72, g, 6, 8, 0, 0, 1, 4)
5841
5842#define PORT_CONF_USGMII_CFG_BYPASS_SCRAM BIT(9)
5843#define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\
5844 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
5845#define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\
5846 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
5847
5848#define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM BIT(8)
5849#define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\
5850 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
5851#define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\
5852 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
5853
5854#define PORT_CONF_USGMII_CFG_FLIP_LANES BIT(7)
5855#define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\
5856 FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
5857#define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\
5858 FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
5859
5860#define PORT_CONF_USGMII_CFG_SHYST_DIS BIT(6)
5861#define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\
5862 FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
5863#define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\
5864 FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
5865
5866#define PORT_CONF_USGMII_CFG_E_DET_ENA BIT(5)
5867#define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\
5868 FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
5869#define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\
5870 FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
5871
5872#define PORT_CONF_USGMII_CFG_USE_I1_ENA BIT(4)
5873#define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\
5874 FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
5875#define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\
5876 FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
5877
5878#define PORT_CONF_USGMII_CFG_QUAD_MODE BIT(1)
5879#define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\
5880 FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
5881#define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\
5882 FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
5883
5884/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */
5885#define PTP_PTP_PIN_INTR __REG(TARGET_PTP,\
5886 0, 1, 320, 0, 1, 16, 0, 0, 1, 4)
5887
5888#define PTP_PTP_PIN_INTR_INTR_PTP GENMASK(4, 0)
5889#define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\
5890 FIELD_PREP(PTP_PTP_PIN_INTR_INTR_PTP, x)
5891#define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\
5892 FIELD_GET(PTP_PTP_PIN_INTR_INTR_PTP, x)
5893
5894/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */
5895#define PTP_PTP_PIN_INTR_ENA __REG(TARGET_PTP,\
5896 0, 1, 320, 0, 1, 16, 4, 0, 1, 4)
5897
5898#define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA GENMASK(4, 0)
5899#define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\
5900 FIELD_PREP(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
5901#define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\
5902 FIELD_GET(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
5903
5904/* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */
5905#define PTP_PTP_INTR_IDENT __REG(TARGET_PTP,\
5906 0, 1, 320, 0, 1, 16, 8, 0, 1, 4)
5907
5908#define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT GENMASK(4, 0)
5909#define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\
5910 FIELD_PREP(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
5911#define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\
5912 FIELD_GET(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
5913
5914/* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */
5915#define PTP_PTP_DOM_CFG __REG(TARGET_PTP,\
5916 0, 1, 320, 0, 1, 16, 12, 0, 1, 4)
5917
5918#define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9)
5919#define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\
5920 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x)
5921#define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\
5922 FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x)
5923
5924#define PTP_PTP_DOM_CFG_PTP_HOLD GENMASK(8, 6)
5925#define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\
5926 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x)
5927#define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\
5928 FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x)
5929
5930#define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE GENMASK(5, 3)
5931#define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\
5932 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
5933#define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\
5934 FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
5935
5936#define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS GENMASK(2, 0)
5937#define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\
5938 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
5939#define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\
5940 FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
5941
5942/* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */
5943#define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP,\
5944 0, 1, 336, g, 3, 28, 0, r, 2, 4)
5945
5946/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */
5947#define PTP_PTP_CUR_NSEC(g) __REG(TARGET_PTP,\
5948 0, 1, 336, g, 3, 28, 8, 0, 1, 4)
5949
5950#define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC GENMASK(29, 0)
5951#define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\
5952 FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
5953#define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\
5954 FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
5955
5956/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */
5957#define PTP_PTP_CUR_NSEC_FRAC(g) __REG(TARGET_PTP,\
5958 0, 1, 336, g, 3, 28, 12, 0, 1, 4)
5959
5960#define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC GENMASK(7, 0)
5961#define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\
5962 FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
5963#define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\
5964 FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
5965
5966/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */
5967#define PTP_PTP_CUR_SEC_LSB(g) __REG(TARGET_PTP,\
5968 0, 1, 336, g, 3, 28, 16, 0, 1, 4)
5969
5970/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */
5971#define PTP_PTP_CUR_SEC_MSB(g) __REG(TARGET_PTP,\
5972 0, 1, 336, g, 3, 28, 20, 0, 1, 4)
5973
5974#define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB GENMASK(15, 0)
5975#define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\
5976 FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
5977#define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\
5978 FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
5979
5980/* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */
5981#define PTP_NTP_CUR_NSEC(g) __REG(TARGET_PTP,\
5982 0, 1, 336, g, 3, 28, 24, 0, 1, 4)
5983
5984/* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */
5985#define PTP_PTP_PIN_CFG(g) __REG(TARGET_PTP,\
5986 0, 1, 0, g, 5, 64, 0, 0, 1, 4)
5987
5988#define PTP_PTP_PIN_CFG_PTP_PIN_ACTION GENMASK(28, 26)
5989#define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\
5990 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
5991#define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\
5992 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
5993
5994#define PTP_PTP_PIN_CFG_PTP_PIN_SYNC GENMASK(25, 24)
5995#define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\
5996 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
5997#define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\
5998 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
5999
6000#define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL BIT(23)
6001#define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\
6002 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
6003#define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\
6004 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
6005
6006#define PTP_PTP_PIN_CFG_PTP_PIN_SELECT GENMASK(22, 21)
6007#define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\
6008 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
6009#define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\
6010 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
6011
6012#define PTP_PTP_PIN_CFG_PTP_CLK_SELECT GENMASK(20, 18)
6013#define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\
6014 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
6015#define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\
6016 FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
6017
6018#define PTP_PTP_PIN_CFG_PTP_PIN_DOM GENMASK(17, 16)
6019#define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\
6020 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
6021#define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\
6022 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
6023
6024#define PTP_PTP_PIN_CFG_PTP_PIN_OPT GENMASK(15, 14)
6025#define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\
6026 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
6027#define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\
6028 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
6029
6030#define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK BIT(13)
6031#define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\
6032 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
6033#define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\
6034 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
6035
6036#define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS GENMASK(12, 0)
6037#define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\
6038 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
6039#define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\
6040 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
6041
6042/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */
6043#define PTP_PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP,\
6044 0, 1, 0, g, 5, 64, 4, 0, 1, 4)
6045
6046#define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB GENMASK(15, 0)
6047#define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\
6048 FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
6049#define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\
6050 FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
6051
6052/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */
6053#define PTP_PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP,\
6054 0, 1, 0, g, 5, 64, 8, 0, 1, 4)
6055
6056/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */
6057#define PTP_PTP_TOD_NSEC(g) __REG(TARGET_PTP,\
6058 0, 1, 0, g, 5, 64, 12, 0, 1, 4)
6059
6060#define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC GENMASK(29, 0)
6061#define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\
6062 FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
6063#define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\
6064 FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
6065
6066/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */
6067#define PTP_PTP_TOD_NSEC_FRAC(g) __REG(TARGET_PTP,\
6068 0, 1, 0, g, 5, 64, 16, 0, 1, 4)
6069
6070#define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC GENMASK(7, 0)
6071#define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\
6072 FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
6073#define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\
6074 FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
6075
6076/* DEVCPU_PTP:PTP_PINS:NTP_NSEC */
6077#define PTP_NTP_NSEC(g) __REG(TARGET_PTP,\
6078 0, 1, 0, g, 5, 64, 20, 0, 1, 4)
6079
6080/* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */
6081#define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\
6082 0, 1, 0, g, 5, 64, 24, 0, 1, 4)
6083
6084#define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH GENMASK(29, 0)
6085#define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\
6086 FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
6087#define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\
6088 FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
6089
6090/* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */
6091#define PTP_PIN_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\
6092 0, 1, 0, g, 5, 64, 28, 0, 1, 4)
6093
6094#define PTP_PIN_WF_LOW_PERIOD_PIN_WFL GENMASK(29, 0)
6095#define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\
6096 FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
6097#define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\
6098 FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
6099
6100/* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */
6101#define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP,\
6102 0, 1, 0, g, 5, 64, 32, 0, 1, 4)
6103
6104#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL GENMASK(18, 3)
6105#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\
6106 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
6107#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\
6108 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
6109
6110#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG GENMASK(2, 0)
6111#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\
6112 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
6113#define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\
6114 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
6115
6116/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */
6117#define PTP_PHAD_CTRL(g) __REG(TARGET_PTP,\
6118 0, 1, 420, g, 5, 8, 0, 0, 1, 4)
6119
6120#define PTP_PHAD_CTRL_PHAD_ENA BIT(7)
6121#define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\
6122 FIELD_PREP(PTP_PHAD_CTRL_PHAD_ENA, x)
6123#define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\
6124 FIELD_GET(PTP_PHAD_CTRL_PHAD_ENA, x)
6125
6126#define PTP_PHAD_CTRL_PHAD_FAILED BIT(6)
6127#define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\
6128 FIELD_PREP(PTP_PHAD_CTRL_PHAD_FAILED, x)
6129#define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\
6130 FIELD_GET(PTP_PHAD_CTRL_PHAD_FAILED, x)
6131
6132#define PTP_PHAD_CTRL_REDUCED_RES GENMASK(5, 3)
6133#define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\
6134 FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x)
6135#define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\
6136 FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x)
6137
6138#define PTP_PHAD_CTRL_LOCK_ACC GENMASK(2, 0)
6139#define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\
6140 FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x)
6141#define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\
6142 FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x)
6143
6144/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */
6145#define PTP_PHAD_CYC_STAT(g) __REG(TARGET_PTP,\
6146 0, 1, 420, g, 5, 8, 4, 0, 1, 4)
6147
6148/* QFWD:SYSTEM:SWITCH_PORT_MODE */
6149#define QFWD_SWITCH_PORT_MODE(r) __REG(TARGET_QFWD,\
6150 0, 1, 0, 0, 1, 340, 0, r, 70, 4)
6151
6152#define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19)
6153#define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\
6154 FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
6155#define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\
6156 FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
6157
6158#define QFWD_SWITCH_PORT_MODE_FWD_URGENCY GENMASK(18, 10)
6159#define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\
6160 FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
6161#define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\
6162 FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
6163
6164#define QFWD_SWITCH_PORT_MODE_YEL_RSRVD GENMASK(9, 6)
6165#define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\
6166 FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
6167#define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\
6168 FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
6169
6170#define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(5)
6171#define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\
6172 FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
6173#define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\
6174 FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
6175
6176#define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING BIT(4)
6177#define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\
6178 FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
6179#define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\
6180 FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
6181
6182#define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING BIT(3)
6183#define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\
6184 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
6185#define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\
6186 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
6187
6188#define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE BIT(2)
6189#define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\
6190 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
6191#define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\
6192 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
6193
6194#define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS BIT(1)
6195#define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\
6196 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
6197#define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\
6198 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
6199
6200#define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE BIT(0)
6201#define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\
6202 FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
6203#define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\
6204 FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
6205
6206/* QRES:RES_CTRL:RES_CFG */
6207#define QRES_RES_CFG(g) __REG(TARGET_QRES,\
6208 0, 1, 0, g, 5120, 16, 0, 0, 1, 4)
6209
6210#define QRES_RES_CFG_WM_HIGH GENMASK(11, 0)
6211#define QRES_RES_CFG_WM_HIGH_SET(x)\
6212 FIELD_PREP(QRES_RES_CFG_WM_HIGH, x)
6213#define QRES_RES_CFG_WM_HIGH_GET(x)\
6214 FIELD_GET(QRES_RES_CFG_WM_HIGH, x)
6215
6216/* QRES:RES_CTRL:RES_STAT */
6217#define QRES_RES_STAT(g) __REG(TARGET_QRES,\
6218 0, 1, 0, g, 5120, 16, 4, 0, 1, 4)
6219
6220#define QRES_RES_STAT_MAXUSE GENMASK(20, 0)
6221#define QRES_RES_STAT_MAXUSE_SET(x)\
6222 FIELD_PREP(QRES_RES_STAT_MAXUSE, x)
6223#define QRES_RES_STAT_MAXUSE_GET(x)\
6224 FIELD_GET(QRES_RES_STAT_MAXUSE, x)
6225
6226/* QRES:RES_CTRL:RES_STAT_CUR */
6227#define QRES_RES_STAT_CUR(g) __REG(TARGET_QRES,\
6228 0, 1, 0, g, 5120, 16, 8, 0, 1, 4)
6229
6230#define QRES_RES_STAT_CUR_INUSE GENMASK(20, 0)
6231#define QRES_RES_STAT_CUR_INUSE_SET(x)\
6232 FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x)
6233#define QRES_RES_STAT_CUR_INUSE_GET(x)\
6234 FIELD_GET(QRES_RES_STAT_CUR_INUSE, x)
6235
6236/* DEVCPU_QS:XTR:XTR_GRP_CFG */
6237#define QS_XTR_GRP_CFG(r) __REG(TARGET_QS,\
6238 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
6239
6240#define QS_XTR_GRP_CFG_MODE GENMASK(3, 2)
6241#define QS_XTR_GRP_CFG_MODE_SET(x)\
6242 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
6243#define QS_XTR_GRP_CFG_MODE_GET(x)\
6244 FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
6245
6246#define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
6247#define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\
6248 FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
6249#define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\
6250 FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
6251
6252#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
6253#define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\
6254 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
6255#define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\
6256 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
6257
6258/* DEVCPU_QS:XTR:XTR_RD */
6259#define QS_XTR_RD(r) __REG(TARGET_QS,\
6260 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
6261
6262/* DEVCPU_QS:XTR:XTR_FLUSH */
6263#define QS_XTR_FLUSH __REG(TARGET_QS,\
6264 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
6265
6266#define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
6267#define QS_XTR_FLUSH_FLUSH_SET(x)\
6268 FIELD_PREP(QS_XTR_FLUSH_FLUSH, x)
6269#define QS_XTR_FLUSH_FLUSH_GET(x)\
6270 FIELD_GET(QS_XTR_FLUSH_FLUSH, x)
6271
6272/* DEVCPU_QS:XTR:XTR_DATA_PRESENT */
6273#define QS_XTR_DATA_PRESENT __REG(TARGET_QS,\
6274 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
6275
6276#define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0)
6277#define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\
6278 FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
6279#define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\
6280 FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
6281
6282/* DEVCPU_QS:INJ:INJ_GRP_CFG */
6283#define QS_INJ_GRP_CFG(r) __REG(TARGET_QS,\
6284 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
6285
6286#define QS_INJ_GRP_CFG_MODE GENMASK(3, 2)
6287#define QS_INJ_GRP_CFG_MODE_SET(x)\
6288 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
6289#define QS_INJ_GRP_CFG_MODE_GET(x)\
6290 FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
6291
6292#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
6293#define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\
6294 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
6295#define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\
6296 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
6297
6298/* DEVCPU_QS:INJ:INJ_WR */
6299#define QS_INJ_WR(r) __REG(TARGET_QS,\
6300 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
6301
6302/* DEVCPU_QS:INJ:INJ_CTRL */
6303#define QS_INJ_CTRL(r) __REG(TARGET_QS,\
6304 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
6305
6306#define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21)
6307#define QS_INJ_CTRL_GAP_SIZE_SET(x)\
6308 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
6309#define QS_INJ_CTRL_GAP_SIZE_GET(x)\
6310 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
6311
6312#define QS_INJ_CTRL_ABORT BIT(20)
6313#define QS_INJ_CTRL_ABORT_SET(x)\
6314 FIELD_PREP(QS_INJ_CTRL_ABORT, x)
6315#define QS_INJ_CTRL_ABORT_GET(x)\
6316 FIELD_GET(QS_INJ_CTRL_ABORT, x)
6317
6318#define QS_INJ_CTRL_EOF BIT(19)
6319#define QS_INJ_CTRL_EOF_SET(x)\
6320 FIELD_PREP(QS_INJ_CTRL_EOF, x)
6321#define QS_INJ_CTRL_EOF_GET(x)\
6322 FIELD_GET(QS_INJ_CTRL_EOF, x)
6323
6324#define QS_INJ_CTRL_SOF BIT(18)
6325#define QS_INJ_CTRL_SOF_SET(x)\
6326 FIELD_PREP(QS_INJ_CTRL_SOF, x)
6327#define QS_INJ_CTRL_SOF_GET(x)\
6328 FIELD_GET(QS_INJ_CTRL_SOF, x)
6329
6330#define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16)
6331#define QS_INJ_CTRL_VLD_BYTES_SET(x)\
6332 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
6333#define QS_INJ_CTRL_VLD_BYTES_GET(x)\
6334 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
6335
6336/* DEVCPU_QS:INJ:INJ_STATUS */
6337#define QS_INJ_STATUS __REG(TARGET_QS,\
6338 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
6339
6340#define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4)
6341#define QS_INJ_STATUS_WMARK_REACHED_SET(x)\
6342 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
6343#define QS_INJ_STATUS_WMARK_REACHED_GET(x)\
6344 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
6345
6346#define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2)
6347#define QS_INJ_STATUS_FIFO_RDY_SET(x)\
6348 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
6349#define QS_INJ_STATUS_FIFO_RDY_GET(x)\
6350 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
6351
6352#define QS_INJ_STATUS_INJ_IN_PROGRESS GENMASK(1, 0)
6353#define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\
6354 FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
6355#define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\
6356 FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
6357
6358/* QSYS:PAUSE_CFG:PAUSE_CFG */
6359#define QSYS_PAUSE_CFG(r) __REG(TARGET_QSYS,\
6360 0, 1, 544, 0, 1, 1128, 0, r, 70, 4)
6361
6362#define QSYS_PAUSE_CFG_PAUSE_START GENMASK(25, 14)
6363#define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\
6364 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x)
6365#define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\
6366 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x)
6367
6368#define QSYS_PAUSE_CFG_PAUSE_STOP GENMASK(13, 2)
6369#define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\
6370 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x)
6371#define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\
6372 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x)
6373
6374#define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1)
6375#define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\
6376 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x)
6377#define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\
6378 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x)
6379
6380#define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA BIT(0)
6381#define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\
6382 FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
6383#define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\
6384 FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
6385
6386/* QSYS:PAUSE_CFG:ATOP */
6387#define QSYS_ATOP(r) __REG(TARGET_QSYS,\
6388 0, 1, 544, 0, 1, 1128, 284, r, 70, 4)
6389
6390#define QSYS_ATOP_ATOP GENMASK(11, 0)
6391#define QSYS_ATOP_ATOP_SET(x)\
6392 FIELD_PREP(QSYS_ATOP_ATOP, x)
6393#define QSYS_ATOP_ATOP_GET(x)\
6394 FIELD_GET(QSYS_ATOP_ATOP, x)
6395
6396/* QSYS:PAUSE_CFG:FWD_PRESSURE */
6397#define QSYS_FWD_PRESSURE(r) __REG(TARGET_QSYS,\
6398 0, 1, 544, 0, 1, 1128, 564, r, 70, 4)
6399
6400#define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1)
6401#define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\
6402 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
6403#define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\
6404 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
6405
6406#define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS BIT(0)
6407#define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\
6408 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
6409#define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\
6410 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
6411
6412/* QSYS:PAUSE_CFG:ATOP_TOT_CFG */
6413#define QSYS_ATOP_TOT_CFG __REG(TARGET_QSYS,\
6414 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4)
6415
6416#define QSYS_ATOP_TOT_CFG_ATOP_TOT GENMASK(11, 0)
6417#define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\
6418 FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
6419#define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\
6420 FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
6421
6422/* QSYS:CALCFG:CAL_AUTO */
6423#define QSYS_CAL_AUTO(r) __REG(TARGET_QSYS,\
6424 0, 1, 2304, 0, 1, 40, 0, r, 7, 4)
6425
6426#define QSYS_CAL_AUTO_CAL_AUTO GENMASK(29, 0)
6427#define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\
6428 FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x)
6429#define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\
6430 FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x)
6431
6432/* QSYS:CALCFG:CAL_CTRL */
6433#define QSYS_CAL_CTRL __REG(TARGET_QSYS,\
6434 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4)
6435
6436#define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11)
6437#define QSYS_CAL_CTRL_CAL_MODE_SET(x)\
6438 FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x)
6439#define QSYS_CAL_CTRL_CAL_MODE_GET(x)\
6440 FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x)
6441
6442#define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE GENMASK(10, 1)
6443#define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\
6444 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
6445#define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\
6446 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
6447
6448#define QSYS_CAL_CTRL_CAL_AUTO_ERROR BIT(0)
6449#define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\
6450 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
6451#define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\
6452 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
6453
6454/* QSYS:RAM_CTRL:RAM_INIT */
6455#define QSYS_RAM_INIT __REG(TARGET_QSYS,\
6456 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4)
6457
6458#define QSYS_RAM_INIT_RAM_INIT BIT(1)
6459#define QSYS_RAM_INIT_RAM_INIT_SET(x)\
6460 FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x)
6461#define QSYS_RAM_INIT_RAM_INIT_GET(x)\
6462 FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x)
6463
6464#define QSYS_RAM_INIT_RAM_CFG_HOOK BIT(0)
6465#define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\
6466 FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
6467#define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\
6468 FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
6469
6470/* REW:COMMON:OWN_UPSID */
6471#define REW_OWN_UPSID(r) __REG(TARGET_REW,\
6472 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4)
6473
6474#define REW_OWN_UPSID_OWN_UPSID GENMASK(4, 0)
6475#define REW_OWN_UPSID_OWN_UPSID_SET(x)\
6476 FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x)
6477#define REW_OWN_UPSID_OWN_UPSID_GET(x)\
6478 FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x)
6479
6480/* REW:COMMON:RTAG_ETAG_CTRL */
6481#define REW_RTAG_ETAG_CTRL(r) __REG(TARGET_REW,\
6482 0, 1, 387264, 0, 1, 1232, 560, r, 70, 4)
6483
6484#define REW_RTAG_ETAG_CTRL_IPE_TBL GENMASK(9, 3)
6485#define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\
6486 FIELD_PREP(REW_RTAG_ETAG_CTRL_IPE_TBL, x)
6487#define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\
6488 FIELD_GET(REW_RTAG_ETAG_CTRL_IPE_TBL, x)
6489
6490#define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA GENMASK(2, 1)
6491#define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\
6492 FIELD_PREP(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x)
6493#define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_GET(x)\
6494 FIELD_GET(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x)
6495
6496#define REW_RTAG_ETAG_CTRL_KEEP_ETAG BIT(0)
6497#define REW_RTAG_ETAG_CTRL_KEEP_ETAG_SET(x)\
6498 FIELD_PREP(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x)
6499#define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\
6500 FIELD_GET(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x)
6501
6502/* REW:COMMON:ES0_CTRL */
6503#define REW_ES0_CTRL __REG(TARGET_REW,\
6504 0, 1, 387264, 0, 1, 1232, 852, 0, 1, 4)
6505
6506#define REW_ES0_CTRL_ES0_BY_RT_FWD BIT(5)
6507#define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\
6508 FIELD_PREP(REW_ES0_CTRL_ES0_BY_RT_FWD, x)
6509#define REW_ES0_CTRL_ES0_BY_RT_FWD_GET(x)\
6510 FIELD_GET(REW_ES0_CTRL_ES0_BY_RT_FWD, x)
6511
6512#define REW_ES0_CTRL_ES0_BY_RLEG BIT(4)
6513#define REW_ES0_CTRL_ES0_BY_RLEG_SET(x)\
6514 FIELD_PREP(REW_ES0_CTRL_ES0_BY_RLEG, x)
6515#define REW_ES0_CTRL_ES0_BY_RLEG_GET(x)\
6516 FIELD_GET(REW_ES0_CTRL_ES0_BY_RLEG, x)
6517
6518#define REW_ES0_CTRL_ES0_DPORT_ENA BIT(3)
6519#define REW_ES0_CTRL_ES0_DPORT_ENA_SET(x)\
6520 FIELD_PREP(REW_ES0_CTRL_ES0_DPORT_ENA, x)
6521#define REW_ES0_CTRL_ES0_DPORT_ENA_GET(x)\
6522 FIELD_GET(REW_ES0_CTRL_ES0_DPORT_ENA, x)
6523
6524#define REW_ES0_CTRL_ES0_FRM_LBK_CFG BIT(2)
6525#define REW_ES0_CTRL_ES0_FRM_LBK_CFG_SET(x)\
6526 FIELD_PREP(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x)
6527#define REW_ES0_CTRL_ES0_FRM_LBK_CFG_GET(x)\
6528 FIELD_GET(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x)
6529
6530#define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA BIT(1)
6531#define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_SET(x)\
6532 FIELD_PREP(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x)
6533#define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_GET(x)\
6534 FIELD_GET(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x)
6535
6536#define REW_ES0_CTRL_ES0_LU_ENA BIT(0)
6537#define REW_ES0_CTRL_ES0_LU_ENA_SET(x)\
6538 FIELD_PREP(REW_ES0_CTRL_ES0_LU_ENA, x)
6539#define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\
6540 FIELD_GET(REW_ES0_CTRL_ES0_LU_ENA, x)
6541
6542/* REW:PORT:PORT_VLAN_CFG */
6543#define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW,\
6544 0, 1, 360448, g, 70, 256, 0, 0, 1, 4)
6545
6546#define REW_PORT_VLAN_CFG_PORT_PCP GENMASK(15, 13)
6547#define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\
6548 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x)
6549#define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\
6550 FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x)
6551
6552#define REW_PORT_VLAN_CFG_PORT_DEI BIT(12)
6553#define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\
6554 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x)
6555#define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\
6556 FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x)
6557
6558#define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0)
6559#define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\
6560 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
6561#define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\
6562 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)
6563
6564/* REW:PORT:PCP_MAP_DE0 */
6565#define REW_PCP_MAP_DE0(g, r) __REG(TARGET_REW,\
6566 0, 1, 360448, g, 70, 256, 4, r, 8, 4)
6567
6568#define REW_PCP_MAP_DE0_PCP_DE0 GENMASK(2, 0)
6569#define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\
6570 FIELD_PREP(REW_PCP_MAP_DE0_PCP_DE0, x)
6571#define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\
6572 FIELD_GET(REW_PCP_MAP_DE0_PCP_DE0, x)
6573
6574/* REW:PORT:PCP_MAP_DE1 */
6575#define REW_PCP_MAP_DE1(g, r) __REG(TARGET_REW,\
6576 0, 1, 360448, g, 70, 256, 36, r, 8, 4)
6577
6578#define REW_PCP_MAP_DE1_PCP_DE1 GENMASK(2, 0)
6579#define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\
6580 FIELD_PREP(REW_PCP_MAP_DE1_PCP_DE1, x)
6581#define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\
6582 FIELD_GET(REW_PCP_MAP_DE1_PCP_DE1, x)
6583
6584/* REW:PORT:DEI_MAP_DE0 */
6585#define REW_DEI_MAP_DE0(g, r) __REG(TARGET_REW,\
6586 0, 1, 360448, g, 70, 256, 68, r, 8, 4)
6587
6588#define REW_DEI_MAP_DE0_DEI_DE0 BIT(0)
6589#define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\
6590 FIELD_PREP(REW_DEI_MAP_DE0_DEI_DE0, x)
6591#define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\
6592 FIELD_GET(REW_DEI_MAP_DE0_DEI_DE0, x)
6593
6594/* REW:PORT:DEI_MAP_DE1 */
6595#define REW_DEI_MAP_DE1(g, r) __REG(TARGET_REW,\
6596 0, 1, 360448, g, 70, 256, 100, r, 8, 4)
6597
6598#define REW_DEI_MAP_DE1_DEI_DE1 BIT(0)
6599#define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\
6600 FIELD_PREP(REW_DEI_MAP_DE1_DEI_DE1, x)
6601#define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\
6602 FIELD_GET(REW_DEI_MAP_DE1_DEI_DE1, x)
6603
6604/* REW:PORT:TAG_CTRL */
6605#define REW_TAG_CTRL(g) __REG(TARGET_REW,\
6606 0, 1, 360448, g, 70, 256, 132, 0, 1, 4)
6607
6608#define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED BIT(13)
6609#define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\
6610 FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
6611#define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\
6612 FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
6613
6614#define REW_TAG_CTRL_TAG_CFG GENMASK(12, 11)
6615#define REW_TAG_CTRL_TAG_CFG_SET(x)\
6616 FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x)
6617#define REW_TAG_CTRL_TAG_CFG_GET(x)\
6618 FIELD_GET(REW_TAG_CTRL_TAG_CFG, x)
6619
6620#define REW_TAG_CTRL_TAG_TPID_CFG GENMASK(10, 8)
6621#define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\
6622 FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x)
6623#define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\
6624 FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x)
6625
6626#define REW_TAG_CTRL_TAG_VID_CFG GENMASK(7, 6)
6627#define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\
6628 FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x)
6629#define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\
6630 FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x)
6631
6632#define REW_TAG_CTRL_TAG_PCP_CFG GENMASK(5, 3)
6633#define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\
6634 FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x)
6635#define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\
6636 FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x)
6637
6638#define REW_TAG_CTRL_TAG_DEI_CFG GENMASK(2, 0)
6639#define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\
6640 FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x)
6641#define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\
6642 FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x)
6643
6644/* REW:PORT:DSCP_MAP */
6645#define REW_DSCP_MAP(g) __REG(TARGET_REW,\
6646 0, 1, 360448, g, 70, 256, 136, 0, 1, 4)
6647
6648#define REW_DSCP_MAP_DSCP_UPDATE_ENA BIT(1)
6649#define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\
6650 FIELD_PREP(REW_DSCP_MAP_DSCP_UPDATE_ENA, x)
6651#define REW_DSCP_MAP_DSCP_UPDATE_ENA_GET(x)\
6652 FIELD_GET(REW_DSCP_MAP_DSCP_UPDATE_ENA, x)
6653
6654#define REW_DSCP_MAP_DSCP_REMAP_ENA BIT(0)
6655#define REW_DSCP_MAP_DSCP_REMAP_ENA_SET(x)\
6656 FIELD_PREP(REW_DSCP_MAP_DSCP_REMAP_ENA, x)
6657#define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\
6658 FIELD_GET(REW_DSCP_MAP_DSCP_REMAP_ENA, x)
6659
6660/* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */
6661#define REW_PTP_TWOSTEP_CTRL __REG(TARGET_REW,\
6662 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4)
6663
6664#define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12)
6665#define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\
6666 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
6667#define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\
6668 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
6669
6670#define REW_PTP_TWOSTEP_CTRL_PTP_NXT BIT(11)
6671#define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\
6672 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
6673#define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\
6674 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
6675
6676#define REW_PTP_TWOSTEP_CTRL_PTP_VLD BIT(10)
6677#define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\
6678 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
6679#define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\
6680 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
6681
6682#define REW_PTP_TWOSTEP_CTRL_STAMP_TX BIT(9)
6683#define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
6684 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
6685#define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
6686 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
6687
6688#define REW_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)
6689#define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
6690 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
6691#define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
6692 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
6693
6694#define REW_PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0)
6695#define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\
6696 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
6697#define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\
6698 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
6699
6700/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */
6701#define REW_PTP_TWOSTEP_STAMP __REG(TARGET_REW,\
6702 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4)
6703
6704#define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(29, 0)
6705#define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\
6706 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
6707#define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\
6708 FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
6709
6710/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */
6711#define REW_PTP_TWOSTEP_STAMP_SUBNS __REG(TARGET_REW,\
6712 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4)
6713
6714#define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0)
6715#define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\
6716 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
6717#define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\
6718 FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
6719
6720/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */
6721#define REW_PTP_RSRV_NOT_ZERO __REG(TARGET_REW,\
6722 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4)
6723
6724/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */
6725#define REW_PTP_RSRV_NOT_ZERO1 __REG(TARGET_REW,\
6726 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4)
6727
6728/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */
6729#define REW_PTP_RSRV_NOT_ZERO2 __REG(TARGET_REW,\
6730 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4)
6731
6732#define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0)
6733#define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\
6734 FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
6735#define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\
6736 FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
6737
6738/* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */
6739#define REW_PTP_GEN_STAMP_FMT(r) __REG(TARGET_REW,\
6740 0, 1, 378368, 0, 1, 40, 24, r, 4, 4)
6741
6742#define REW_PTP_GEN_STAMP_FMT_RT_OFS GENMASK(6, 2)
6743#define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\
6744 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
6745#define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\
6746 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
6747
6748#define REW_PTP_GEN_STAMP_FMT_RT_FMT GENMASK(1, 0)
6749#define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\
6750 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
6751#define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\
6752 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
6753
6754/* REW:RAM_CTRL:RAM_INIT */
6755#define REW_RAM_INIT __REG(TARGET_REW,\
6756 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4)
6757
6758#define REW_RAM_INIT_RAM_INIT BIT(1)
6759#define REW_RAM_INIT_RAM_INIT_SET(x)\
6760 FIELD_PREP(REW_RAM_INIT_RAM_INIT, x)
6761#define REW_RAM_INIT_RAM_INIT_GET(x)\
6762 FIELD_GET(REW_RAM_INIT_RAM_INIT, x)
6763
6764#define REW_RAM_INIT_RAM_CFG_HOOK BIT(0)
6765#define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\
6766 FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x)
6767#define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\
6768 FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x)
6769
6770/* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */
6771#define VCAP_ES0_CTRL __REG(TARGET_VCAP_ES0,\
6772 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
6773
6774#define VCAP_ES0_CTRL_UPDATE_CMD GENMASK(24, 22)
6775#define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\
6776 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CMD, x)
6777#define VCAP_ES0_CTRL_UPDATE_CMD_GET(x)\
6778 FIELD_GET(VCAP_ES0_CTRL_UPDATE_CMD, x)
6779
6780#define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS BIT(21)
6781#define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_SET(x)\
6782 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x)
6783#define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_GET(x)\
6784 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x)
6785
6786#define VCAP_ES0_CTRL_UPDATE_ACTION_DIS BIT(20)
6787#define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_SET(x)\
6788 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x)
6789#define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_GET(x)\
6790 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x)
6791
6792#define VCAP_ES0_CTRL_UPDATE_CNT_DIS BIT(19)
6793#define VCAP_ES0_CTRL_UPDATE_CNT_DIS_SET(x)\
6794 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x)
6795#define VCAP_ES0_CTRL_UPDATE_CNT_DIS_GET(x)\
6796 FIELD_GET(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x)
6797
6798#define VCAP_ES0_CTRL_UPDATE_ADDR GENMASK(18, 3)
6799#define VCAP_ES0_CTRL_UPDATE_ADDR_SET(x)\
6800 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ADDR, x)
6801#define VCAP_ES0_CTRL_UPDATE_ADDR_GET(x)\
6802 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ADDR, x)
6803
6804#define VCAP_ES0_CTRL_UPDATE_SHOT BIT(2)
6805#define VCAP_ES0_CTRL_UPDATE_SHOT_SET(x)\
6806 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_SHOT, x)
6807#define VCAP_ES0_CTRL_UPDATE_SHOT_GET(x)\
6808 FIELD_GET(VCAP_ES0_CTRL_UPDATE_SHOT, x)
6809
6810#define VCAP_ES0_CTRL_CLEAR_CACHE BIT(1)
6811#define VCAP_ES0_CTRL_CLEAR_CACHE_SET(x)\
6812 FIELD_PREP(VCAP_ES0_CTRL_CLEAR_CACHE, x)
6813#define VCAP_ES0_CTRL_CLEAR_CACHE_GET(x)\
6814 FIELD_GET(VCAP_ES0_CTRL_CLEAR_CACHE, x)
6815
6816#define VCAP_ES0_CTRL_MV_TRAFFIC_IGN BIT(0)
6817#define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_SET(x)\
6818 FIELD_PREP(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x)
6819#define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\
6820 FIELD_GET(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x)
6821
6822/* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */
6823#define VCAP_ES0_CFG __REG(TARGET_VCAP_ES0,\
6824 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
6825
6826#define VCAP_ES0_CFG_MV_NUM_POS GENMASK(31, 16)
6827#define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\
6828 FIELD_PREP(VCAP_ES0_CFG_MV_NUM_POS, x)
6829#define VCAP_ES0_CFG_MV_NUM_POS_GET(x)\
6830 FIELD_GET(VCAP_ES0_CFG_MV_NUM_POS, x)
6831
6832#define VCAP_ES0_CFG_MV_SIZE GENMASK(15, 0)
6833#define VCAP_ES0_CFG_MV_SIZE_SET(x)\
6834 FIELD_PREP(VCAP_ES0_CFG_MV_SIZE, x)
6835#define VCAP_ES0_CFG_MV_SIZE_GET(x)\
6836 FIELD_GET(VCAP_ES0_CFG_MV_SIZE, x)
6837
6838/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */
6839#define VCAP_ES0_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_ES0,\
6840 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
6841
6842/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */
6843#define VCAP_ES0_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_ES0,\
6844 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
6845
6846/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */
6847#define VCAP_ES0_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_ES0,\
6848 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
6849
6850/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */
6851#define VCAP_ES0_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_ES0,\
6852 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
6853
6854/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */
6855#define VCAP_ES0_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_ES0,\
6856 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
6857
6858/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */
6859#define VCAP_ES0_VCAP_TG_DAT __REG(TARGET_VCAP_ES0,\
6860 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
6861
6862/* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */
6863#define VCAP_ES0_IDX __REG(TARGET_VCAP_ES0,\
6864 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
6865
6866#define VCAP_ES0_IDX_CORE_IDX GENMASK(3, 0)
6867#define VCAP_ES0_IDX_CORE_IDX_SET(x)\
6868 FIELD_PREP(VCAP_ES0_IDX_CORE_IDX, x)
6869#define VCAP_ES0_IDX_CORE_IDX_GET(x)\
6870 FIELD_GET(VCAP_ES0_IDX_CORE_IDX, x)
6871
6872/* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */
6873#define VCAP_ES0_MAP __REG(TARGET_VCAP_ES0,\
6874 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
6875
6876#define VCAP_ES0_MAP_CORE_MAP GENMASK(2, 0)
6877#define VCAP_ES0_MAP_CORE_MAP_SET(x)\
6878 FIELD_PREP(VCAP_ES0_MAP_CORE_MAP, x)
6879#define VCAP_ES0_MAP_CORE_MAP_GET(x)\
6880 FIELD_GET(VCAP_ES0_MAP_CORE_MAP, x)
6881
6882/* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */
6883#define VCAP_ES0_VCAP_STICKY __REG(TARGET_VCAP_ES0,\
6884 0, 1, 920, 0, 1, 4, 0, 0, 1, 4)
6885
6886#define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0)
6887#define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\
6888 FIELD_PREP(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
6889#define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\
6890 FIELD_GET(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
6891
6892/* VCAP_ES0:VCAP_CONST:VCAP_VER */
6893#define VCAP_ES0_VCAP_VER __REG(TARGET_VCAP_ES0,\
6894 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
6895
6896/* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */
6897#define VCAP_ES0_ENTRY_WIDTH __REG(TARGET_VCAP_ES0,\
6898 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
6899
6900/* VCAP_ES0:VCAP_CONST:ENTRY_CNT */
6901#define VCAP_ES0_ENTRY_CNT __REG(TARGET_VCAP_ES0,\
6902 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
6903
6904/* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */
6905#define VCAP_ES0_ENTRY_SWCNT __REG(TARGET_VCAP_ES0,\
6906 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
6907
6908/* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */
6909#define VCAP_ES0_ENTRY_TG_WIDTH __REG(TARGET_VCAP_ES0,\
6910 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
6911
6912/* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */
6913#define VCAP_ES0_ACTION_DEF_CNT __REG(TARGET_VCAP_ES0,\
6914 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
6915
6916/* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */
6917#define VCAP_ES0_ACTION_WIDTH __REG(TARGET_VCAP_ES0,\
6918 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
6919
6920/* VCAP_ES0:VCAP_CONST:CNT_WIDTH */
6921#define VCAP_ES0_CNT_WIDTH __REG(TARGET_VCAP_ES0,\
6922 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
6923
6924/* VCAP_ES0:VCAP_CONST:CORE_CNT */
6925#define VCAP_ES0_CORE_CNT __REG(TARGET_VCAP_ES0,\
6926 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
6927
6928/* VCAP_ES0:VCAP_CONST:IF_CNT */
6929#define VCAP_ES0_IF_CNT __REG(TARGET_VCAP_ES0,\
6930 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
6931
6932/* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */
6933#define VCAP_ES2_CTRL __REG(TARGET_VCAP_ES2,\
6934 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
6935
6936#define VCAP_ES2_CTRL_UPDATE_CMD GENMASK(24, 22)
6937#define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\
6938 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CMD, x)
6939#define VCAP_ES2_CTRL_UPDATE_CMD_GET(x)\
6940 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CMD, x)
6941
6942#define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS BIT(21)
6943#define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_SET(x)\
6944 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x)
6945#define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_GET(x)\
6946 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x)
6947
6948#define VCAP_ES2_CTRL_UPDATE_ACTION_DIS BIT(20)
6949#define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_SET(x)\
6950 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x)
6951#define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_GET(x)\
6952 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x)
6953
6954#define VCAP_ES2_CTRL_UPDATE_CNT_DIS BIT(19)
6955#define VCAP_ES2_CTRL_UPDATE_CNT_DIS_SET(x)\
6956 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x)
6957#define VCAP_ES2_CTRL_UPDATE_CNT_DIS_GET(x)\
6958 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x)
6959
6960#define VCAP_ES2_CTRL_UPDATE_ADDR GENMASK(18, 3)
6961#define VCAP_ES2_CTRL_UPDATE_ADDR_SET(x)\
6962 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ADDR, x)
6963#define VCAP_ES2_CTRL_UPDATE_ADDR_GET(x)\
6964 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ADDR, x)
6965
6966#define VCAP_ES2_CTRL_UPDATE_SHOT BIT(2)
6967#define VCAP_ES2_CTRL_UPDATE_SHOT_SET(x)\
6968 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_SHOT, x)
6969#define VCAP_ES2_CTRL_UPDATE_SHOT_GET(x)\
6970 FIELD_GET(VCAP_ES2_CTRL_UPDATE_SHOT, x)
6971
6972#define VCAP_ES2_CTRL_CLEAR_CACHE BIT(1)
6973#define VCAP_ES2_CTRL_CLEAR_CACHE_SET(x)\
6974 FIELD_PREP(VCAP_ES2_CTRL_CLEAR_CACHE, x)
6975#define VCAP_ES2_CTRL_CLEAR_CACHE_GET(x)\
6976 FIELD_GET(VCAP_ES2_CTRL_CLEAR_CACHE, x)
6977
6978#define VCAP_ES2_CTRL_MV_TRAFFIC_IGN BIT(0)
6979#define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_SET(x)\
6980 FIELD_PREP(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x)
6981#define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\
6982 FIELD_GET(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x)
6983
6984/* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */
6985#define VCAP_ES2_CFG __REG(TARGET_VCAP_ES2,\
6986 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
6987
6988#define VCAP_ES2_CFG_MV_NUM_POS GENMASK(31, 16)
6989#define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\
6990 FIELD_PREP(VCAP_ES2_CFG_MV_NUM_POS, x)
6991#define VCAP_ES2_CFG_MV_NUM_POS_GET(x)\
6992 FIELD_GET(VCAP_ES2_CFG_MV_NUM_POS, x)
6993
6994#define VCAP_ES2_CFG_MV_SIZE GENMASK(15, 0)
6995#define VCAP_ES2_CFG_MV_SIZE_SET(x)\
6996 FIELD_PREP(VCAP_ES2_CFG_MV_SIZE, x)
6997#define VCAP_ES2_CFG_MV_SIZE_GET(x)\
6998 FIELD_GET(VCAP_ES2_CFG_MV_SIZE, x)
6999
7000/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */
7001#define VCAP_ES2_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_ES2,\
7002 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7003
7004/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */
7005#define VCAP_ES2_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_ES2,\
7006 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7007
7008/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */
7009#define VCAP_ES2_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_ES2,\
7010 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7011
7012/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */
7013#define VCAP_ES2_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_ES2,\
7014 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7015
7016/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */
7017#define VCAP_ES2_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_ES2,\
7018 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
7019
7020/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */
7021#define VCAP_ES2_VCAP_TG_DAT __REG(TARGET_VCAP_ES2,\
7022 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
7023
7024/* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */
7025#define VCAP_ES2_IDX __REG(TARGET_VCAP_ES2,\
7026 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
7027
7028#define VCAP_ES2_IDX_CORE_IDX GENMASK(3, 0)
7029#define VCAP_ES2_IDX_CORE_IDX_SET(x)\
7030 FIELD_PREP(VCAP_ES2_IDX_CORE_IDX, x)
7031#define VCAP_ES2_IDX_CORE_IDX_GET(x)\
7032 FIELD_GET(VCAP_ES2_IDX_CORE_IDX, x)
7033
7034/* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */
7035#define VCAP_ES2_MAP __REG(TARGET_VCAP_ES2,\
7036 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
7037
7038#define VCAP_ES2_MAP_CORE_MAP GENMASK(2, 0)
7039#define VCAP_ES2_MAP_CORE_MAP_SET(x)\
7040 FIELD_PREP(VCAP_ES2_MAP_CORE_MAP, x)
7041#define VCAP_ES2_MAP_CORE_MAP_GET(x)\
7042 FIELD_GET(VCAP_ES2_MAP_CORE_MAP, x)
7043
7044/* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */
7045#define VCAP_ES2_VCAP_STICKY __REG(TARGET_VCAP_ES2,\
7046 0, 1, 920, 0, 1, 4, 0, 0, 1, 4)
7047
7048#define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0)
7049#define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\
7050 FIELD_PREP(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7051#define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\
7052 FIELD_GET(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7053
7054/* VCAP_ES2:VCAP_CONST:VCAP_VER */
7055#define VCAP_ES2_VCAP_VER __REG(TARGET_VCAP_ES2,\
7056 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
7057
7058/* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */
7059#define VCAP_ES2_ENTRY_WIDTH __REG(TARGET_VCAP_ES2,\
7060 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
7061
7062/* VCAP_ES2:VCAP_CONST:ENTRY_CNT */
7063#define VCAP_ES2_ENTRY_CNT __REG(TARGET_VCAP_ES2,\
7064 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
7065
7066/* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */
7067#define VCAP_ES2_ENTRY_SWCNT __REG(TARGET_VCAP_ES2,\
7068 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
7069
7070/* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */
7071#define VCAP_ES2_ENTRY_TG_WIDTH __REG(TARGET_VCAP_ES2,\
7072 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
7073
7074/* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */
7075#define VCAP_ES2_ACTION_DEF_CNT __REG(TARGET_VCAP_ES2,\
7076 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
7077
7078/* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */
7079#define VCAP_ES2_ACTION_WIDTH __REG(TARGET_VCAP_ES2,\
7080 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
7081
7082/* VCAP_ES2:VCAP_CONST:CNT_WIDTH */
7083#define VCAP_ES2_CNT_WIDTH __REG(TARGET_VCAP_ES2,\
7084 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7085
7086/* VCAP_ES2:VCAP_CONST:CORE_CNT */
7087#define VCAP_ES2_CORE_CNT __REG(TARGET_VCAP_ES2,\
7088 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
7089
7090/* VCAP_ES2:VCAP_CONST:IF_CNT */
7091#define VCAP_ES2_IF_CNT __REG(TARGET_VCAP_ES2,\
7092 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7093
7094/* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */
7095#define VCAP_SUPER_CTRL __REG(TARGET_VCAP_SUPER,\
7096 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
7097
7098#define VCAP_SUPER_CTRL_UPDATE_CMD GENMASK(24, 22)
7099#define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\
7100 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CMD, x)
7101#define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x)\
7102 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CMD, x)
7103
7104#define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS BIT(21)
7105#define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x)\
7106 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x)
7107#define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x)\
7108 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x)
7109
7110#define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS BIT(20)
7111#define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x)\
7112 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x)
7113#define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x)\
7114 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x)
7115
7116#define VCAP_SUPER_CTRL_UPDATE_CNT_DIS BIT(19)
7117#define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x)\
7118 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x)
7119#define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x)\
7120 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x)
7121
7122#define VCAP_SUPER_CTRL_UPDATE_ADDR GENMASK(18, 3)
7123#define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x)\
7124 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ADDR, x)
7125#define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x)\
7126 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ADDR, x)
7127
7128#define VCAP_SUPER_CTRL_UPDATE_SHOT BIT(2)
7129#define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x)\
7130 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_SHOT, x)
7131#define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x)\
7132 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_SHOT, x)
7133
7134#define VCAP_SUPER_CTRL_CLEAR_CACHE BIT(1)
7135#define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x)\
7136 FIELD_PREP(VCAP_SUPER_CTRL_CLEAR_CACHE, x)
7137#define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x)\
7138 FIELD_GET(VCAP_SUPER_CTRL_CLEAR_CACHE, x)
7139
7140#define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN BIT(0)
7141#define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x)\
7142 FIELD_PREP(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x)
7143#define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\
7144 FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x)
7145
7146/* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */
7147#define VCAP_SUPER_CFG __REG(TARGET_VCAP_SUPER,\
7148 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
7149
7150#define VCAP_SUPER_CFG_MV_NUM_POS GENMASK(31, 16)
7151#define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\
7152 FIELD_PREP(VCAP_SUPER_CFG_MV_NUM_POS, x)
7153#define VCAP_SUPER_CFG_MV_NUM_POS_GET(x)\
7154 FIELD_GET(VCAP_SUPER_CFG_MV_NUM_POS, x)
7155
7156#define VCAP_SUPER_CFG_MV_SIZE GENMASK(15, 0)
7157#define VCAP_SUPER_CFG_MV_SIZE_SET(x)\
7158 FIELD_PREP(VCAP_SUPER_CFG_MV_SIZE, x)
7159#define VCAP_SUPER_CFG_MV_SIZE_GET(x)\
7160 FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x)
7161
7162/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */
7163#define VCAP_SUPER_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_SUPER,\
7164 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7165
7166/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */
7167#define VCAP_SUPER_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_SUPER,\
7168 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7169
7170/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */
7171#define VCAP_SUPER_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_SUPER,\
7172 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7173
7174/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */
7175#define VCAP_SUPER_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_SUPER,\
7176 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7177
7178/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */
7179#define VCAP_SUPER_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_SUPER,\
7180 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
7181
7182/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */
7183#define VCAP_SUPER_VCAP_TG_DAT __REG(TARGET_VCAP_SUPER,\
7184 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
7185
7186/* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */
7187#define VCAP_SUPER_IDX __REG(TARGET_VCAP_SUPER,\
7188 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
7189
7190#define VCAP_SUPER_IDX_CORE_IDX GENMASK(3, 0)
7191#define VCAP_SUPER_IDX_CORE_IDX_SET(x)\
7192 FIELD_PREP(VCAP_SUPER_IDX_CORE_IDX, x)
7193#define VCAP_SUPER_IDX_CORE_IDX_GET(x)\
7194 FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x)
7195
7196/* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */
7197#define VCAP_SUPER_MAP __REG(TARGET_VCAP_SUPER,\
7198 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
7199
7200#define VCAP_SUPER_MAP_CORE_MAP GENMASK(2, 0)
7201#define VCAP_SUPER_MAP_CORE_MAP_SET(x)\
7202 FIELD_PREP(VCAP_SUPER_MAP_CORE_MAP, x)
7203#define VCAP_SUPER_MAP_CORE_MAP_GET(x)\
7204 FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x)
7205
7206/* VCAP_SUPER:VCAP_CONST:VCAP_VER */
7207#define VCAP_SUPER_VCAP_VER __REG(TARGET_VCAP_SUPER,\
7208 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
7209
7210/* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */
7211#define VCAP_SUPER_ENTRY_WIDTH __REG(TARGET_VCAP_SUPER,\
7212 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
7213
7214/* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */
7215#define VCAP_SUPER_ENTRY_CNT __REG(TARGET_VCAP_SUPER,\
7216 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
7217
7218/* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */
7219#define VCAP_SUPER_ENTRY_SWCNT __REG(TARGET_VCAP_SUPER,\
7220 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
7221
7222/* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */
7223#define VCAP_SUPER_ENTRY_TG_WIDTH __REG(TARGET_VCAP_SUPER,\
7224 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
7225
7226/* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */
7227#define VCAP_SUPER_ACTION_DEF_CNT __REG(TARGET_VCAP_SUPER,\
7228 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
7229
7230/* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */
7231#define VCAP_SUPER_ACTION_WIDTH __REG(TARGET_VCAP_SUPER,\
7232 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
7233
7234/* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */
7235#define VCAP_SUPER_CNT_WIDTH __REG(TARGET_VCAP_SUPER,\
7236 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7237
7238/* VCAP_SUPER:VCAP_CONST:CORE_CNT */
7239#define VCAP_SUPER_CORE_CNT __REG(TARGET_VCAP_SUPER,\
7240 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
7241
7242/* VCAP_SUPER:VCAP_CONST:IF_CNT */
7243#define VCAP_SUPER_IF_CNT __REG(TARGET_VCAP_SUPER,\
7244 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7245
7246/* VCAP_SUPER:RAM_CTRL:RAM_INIT */
7247#define VCAP_SUPER_RAM_INIT __REG(TARGET_VCAP_SUPER,\
7248 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4)
7249
7250#define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1)
7251#define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\
7252 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
7253#define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\
7254 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
7255
7256#define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK BIT(0)
7257#define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\
7258 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
7259#define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\
7260 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
7261
7262/* VOP:RAM_CTRL:RAM_INIT */
7263#define VOP_RAM_INIT __REG(TARGET_VOP,\
7264 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4)
7265
7266#define VOP_RAM_INIT_RAM_INIT BIT(1)
7267#define VOP_RAM_INIT_RAM_INIT_SET(x)\
7268 FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x)
7269#define VOP_RAM_INIT_RAM_INIT_GET(x)\
7270 FIELD_GET(VOP_RAM_INIT_RAM_INIT, x)
7271
7272#define VOP_RAM_INIT_RAM_CFG_HOOK BIT(0)
7273#define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\
7274 FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x)
7275#define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\
7276 FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x)
7277
7278/* XQS:SYSTEM:STAT_CFG */
7279#define XQS_STAT_CFG __REG(TARGET_XQS,\
7280 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4)
7281
7282#define XQS_STAT_CFG_STAT_CLEAR_SHOT GENMASK(21, 18)
7283#define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\
7284 FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
7285#define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\
7286 FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
7287
7288#define XQS_STAT_CFG_STAT_VIEW GENMASK(17, 5)
7289#define XQS_STAT_CFG_STAT_VIEW_SET(x)\
7290 FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x)
7291#define XQS_STAT_CFG_STAT_VIEW_GET(x)\
7292 FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x)
7293
7294#define XQS_STAT_CFG_STAT_SRV_PKT_ONLY BIT(4)
7295#define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\
7296 FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
7297#define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\
7298 FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
7299
7300#define XQS_STAT_CFG_STAT_WRAP_DIS GENMASK(3, 0)
7301#define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\
7302 FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x)
7303#define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\
7304 FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x)
7305
7306/* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */
7307#define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS,\
7308 0, 1, 7936, g, 4, 48, 0, 0, 1, 4)
7309
7310#define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP GENMASK(14, 0)
7311#define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\
7312 FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
7313#define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\
7314 FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
7315
7316/* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */
7317#define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS,\
7318 0, 1, 7936, g, 4, 48, 4, 0, 1, 4)
7319
7320#define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP GENMASK(14, 0)
7321#define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\
7322 FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
7323#define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\
7324 FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
7325
7326/* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */
7327#define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS,\
7328 0, 1, 7936, g, 4, 48, 8, 0, 1, 4)
7329
7330#define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP GENMASK(14, 0)
7331#define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\
7332 FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
7333#define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\
7334 FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
7335
7336/* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */
7337#define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS,\
7338 0, 1, 7936, g, 4, 48, 12, 0, 1, 4)
7339
7340#define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM GENMASK(14, 0)
7341#define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\
7342 FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
7343#define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\
7344 FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
7345
7346/* XQS:STAT:CNT */
7347#define XQS_CNT(g) __REG(TARGET_XQS,\
7348 0, 1, 0, g, 1024, 4, 0, 0, 1, 4)
7349
7350#endif /* _SPARX5_MAIN_REGS_H_ */
7351

source code of linux/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h