1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
2 | /* |
3 | * Microsemi Ocelot Switch driver |
4 | * |
5 | * Copyright (c) 2017 Microsemi Corporation |
6 | * Copyright (c) 2021 Innovative Advantage |
7 | */ |
8 | #include <soc/mscc/ocelot_vcap.h> |
9 | #include <soc/mscc/vsc7514_regs.h> |
10 | #include "ocelot.h" |
11 | |
12 | const struct reg_field vsc7514_regfields[REGFIELD_MAX] = { |
13 | [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), |
14 | [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), |
15 | [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), |
16 | [ANA_ANEVENTS_ACLKILL] = REG_FIELD(ANA_ANEVENTS, 26, 26), |
17 | [ANA_ANEVENTS_ACLUSED] = REG_FIELD(ANA_ANEVENTS, 25, 25), |
18 | [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), |
19 | [ANA_ANEVENTS_VS2TTL1] = REG_FIELD(ANA_ANEVENTS, 23, 23), |
20 | [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), |
21 | [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), |
22 | [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), |
23 | [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), |
24 | [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), |
25 | [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), |
26 | [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), |
27 | [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), |
28 | [ANA_ANEVENTS_DROPPED] = REG_FIELD(ANA_ANEVENTS, 14, 14), |
29 | [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), |
30 | [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), |
31 | [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), |
32 | [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), |
33 | [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), |
34 | [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), |
35 | [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), |
36 | [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), |
37 | [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), |
38 | [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), |
39 | [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), |
40 | [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), |
41 | [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), |
42 | [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), |
43 | [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 18, 18), |
44 | [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 10, 11), |
45 | [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 9), |
46 | [QSYS_TIMED_FRAME_ENTRY_TFRM_VLD] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 20, 20), |
47 | [QSYS_TIMED_FRAME_ENTRY_TFRM_FP] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 8, 19), |
48 | [QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 4, 7), |
49 | [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 1, 3), |
50 | [QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T] = REG_FIELD(QSYS_TIMED_FRAME_ENTRY, 0, 0), |
51 | [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 2, 2), |
52 | [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 1, 1), |
53 | [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 0, 0), |
54 | /* Replicated per number of ports (12), register size 4 per port */ |
55 | [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 12, 4), |
56 | [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 12, 4), |
57 | [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 12, 4), |
58 | [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 12, 4), |
59 | [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 12, 4), |
60 | [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 12, 4), |
61 | [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 12, 4), |
62 | [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 12, 4), |
63 | [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 12, 4), |
64 | [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 12, 4), |
65 | [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 12, 4), |
66 | [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 12, 4), |
67 | [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 12, 4), |
68 | }; |
69 | EXPORT_SYMBOL(vsc7514_regfields); |
70 | |
71 | static const u32 vsc7514_ana_regmap[] = { |
72 | REG(ANA_ADVLEARN, 0x009000), |
73 | REG(ANA_VLANMASK, 0x009004), |
74 | REG(ANA_PORT_B_DOMAIN, 0x009008), |
75 | REG(ANA_ANAGEFIL, 0x00900c), |
76 | REG(ANA_ANEVENTS, 0x009010), |
77 | REG(ANA_STORMLIMIT_BURST, 0x009014), |
78 | REG(ANA_STORMLIMIT_CFG, 0x009018), |
79 | REG(ANA_ISOLATED_PORTS, 0x009028), |
80 | REG(ANA_COMMUNITY_PORTS, 0x00902c), |
81 | REG(ANA_AUTOAGE, 0x009030), |
82 | REG(ANA_MACTOPTIONS, 0x009034), |
83 | REG(ANA_LEARNDISC, 0x009038), |
84 | REG(ANA_AGENCTRL, 0x00903c), |
85 | REG(ANA_MIRRORPORTS, 0x009040), |
86 | REG(ANA_EMIRRORPORTS, 0x009044), |
87 | REG(ANA_FLOODING, 0x009048), |
88 | REG(ANA_FLOODING_IPMC, 0x00904c), |
89 | REG(ANA_SFLOW_CFG, 0x009050), |
90 | REG(ANA_PORT_MODE, 0x009080), |
91 | REG(ANA_PGID_PGID, 0x008c00), |
92 | REG(ANA_TABLES_ANMOVED, 0x008b30), |
93 | REG(ANA_TABLES_MACHDATA, 0x008b34), |
94 | REG(ANA_TABLES_MACLDATA, 0x008b38), |
95 | REG(ANA_TABLES_MACACCESS, 0x008b3c), |
96 | REG(ANA_TABLES_MACTINDX, 0x008b40), |
97 | REG(ANA_TABLES_VLANACCESS, 0x008b44), |
98 | REG(ANA_TABLES_VLANTIDX, 0x008b48), |
99 | REG(ANA_TABLES_ISDXACCESS, 0x008b4c), |
100 | REG(ANA_TABLES_ISDXTIDX, 0x008b50), |
101 | REG(ANA_TABLES_ENTRYLIM, 0x008b00), |
102 | REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54), |
103 | REG(ANA_TABLES_PTP_ID_LOW, 0x008b58), |
104 | REG(ANA_MSTI_STATE, 0x008e00), |
105 | REG(ANA_PORT_VLAN_CFG, 0x007000), |
106 | REG(ANA_PORT_DROP_CFG, 0x007004), |
107 | REG(ANA_PORT_QOS_CFG, 0x007008), |
108 | REG(ANA_PORT_VCAP_CFG, 0x00700c), |
109 | REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010), |
110 | REG(ANA_PORT_VCAP_S2_CFG, 0x00701c), |
111 | REG(ANA_PORT_PCP_DEI_MAP, 0x007020), |
112 | REG(ANA_PORT_CPU_FWD_CFG, 0x007060), |
113 | REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064), |
114 | REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068), |
115 | REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c), |
116 | REG(ANA_PORT_PORT_CFG, 0x007070), |
117 | REG(ANA_PORT_POL_CFG, 0x007074), |
118 | REG(ANA_PORT_PTP_CFG, 0x007078), |
119 | REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c), |
120 | REG(ANA_OAM_UPM_LM_CNT, 0x007c00), |
121 | REG(ANA_PORT_PTP_DLY2_CFG, 0x007080), |
122 | REG(ANA_PFC_PFC_CFG, 0x008800), |
123 | REG(ANA_PFC_PFC_TIMER, 0x008804), |
124 | REG(ANA_IPT_OAM_MEP_CFG, 0x008000), |
125 | REG(ANA_IPT_IPT, 0x008004), |
126 | REG(ANA_PPT_PPT, 0x008ac0), |
127 | REG(ANA_FID_MAP_FID_MAP, 0x000000), |
128 | REG(ANA_AGGR_CFG, 0x0090b4), |
129 | REG(ANA_CPUQ_CFG, 0x0090b8), |
130 | REG(ANA_CPUQ_CFG2, 0x0090bc), |
131 | REG(ANA_CPUQ_8021_CFG, 0x0090c0), |
132 | REG(ANA_DSCP_CFG, 0x009100), |
133 | REG(ANA_DSCP_REWR_CFG, 0x009200), |
134 | REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240), |
135 | REG(ANA_VCAP_RNG_VAL_CFG, 0x009260), |
136 | REG(ANA_VRAP_CFG, 0x009280), |
137 | REG(ANA_VRAP_HDR_DATA, 0x009284), |
138 | REG(ANA_VRAP_HDR_MASK, 0x009288), |
139 | REG(ANA_DISCARD_CFG, 0x00928c), |
140 | REG(ANA_FID_CFG, 0x009290), |
141 | REG(ANA_POL_PIR_CFG, 0x004000), |
142 | REG(ANA_POL_CIR_CFG, 0x004004), |
143 | REG(ANA_POL_MODE_CFG, 0x004008), |
144 | REG(ANA_POL_PIR_STATE, 0x00400c), |
145 | REG(ANA_POL_CIR_STATE, 0x004010), |
146 | REG(ANA_POL_STATE, 0x004014), |
147 | REG(ANA_POL_FLOWC, 0x008b80), |
148 | REG(ANA_POL_HYST, 0x008bec), |
149 | REG(ANA_POL_MISC_CFG, 0x008bf0), |
150 | }; |
151 | |
152 | static const u32 vsc7514_qs_regmap[] = { |
153 | REG(QS_XTR_GRP_CFG, 0x000000), |
154 | REG(QS_XTR_RD, 0x000008), |
155 | REG(QS_XTR_FRM_PRUNING, 0x000010), |
156 | REG(QS_XTR_FLUSH, 0x000018), |
157 | REG(QS_XTR_DATA_PRESENT, 0x00001c), |
158 | REG(QS_XTR_CFG, 0x000020), |
159 | REG(QS_INJ_GRP_CFG, 0x000024), |
160 | REG(QS_INJ_WR, 0x00002c), |
161 | REG(QS_INJ_CTRL, 0x000034), |
162 | REG(QS_INJ_STATUS, 0x00003c), |
163 | REG(QS_INJ_ERR, 0x000040), |
164 | REG(QS_INH_DBG, 0x000048), |
165 | }; |
166 | |
167 | static const u32 vsc7514_qsys_regmap[] = { |
168 | REG(QSYS_PORT_MODE, 0x011200), |
169 | REG(QSYS_SWITCH_PORT_MODE, 0x011234), |
170 | REG(QSYS_STAT_CNT_CFG, 0x011264), |
171 | REG(QSYS_EEE_CFG, 0x011268), |
172 | REG(QSYS_EEE_THRES, 0x011294), |
173 | REG(QSYS_IGR_NO_SHARING, 0x011298), |
174 | REG(QSYS_EGR_NO_SHARING, 0x01129c), |
175 | REG(QSYS_SW_STATUS, 0x0112a0), |
176 | REG(QSYS_EXT_CPU_CFG, 0x0112d0), |
177 | REG(QSYS_PAD_CFG, 0x0112d4), |
178 | REG(QSYS_CPU_GROUP_MAP, 0x0112d8), |
179 | REG(QSYS_QMAP, 0x0112dc), |
180 | REG(QSYS_ISDX_SGRP, 0x011400), |
181 | REG(QSYS_TIMED_FRAME_ENTRY, 0x014000), |
182 | REG(QSYS_TFRM_MISC, 0x011310), |
183 | REG(QSYS_TFRM_PORT_DLY, 0x011314), |
184 | REG(QSYS_TFRM_TIMER_CFG_1, 0x011318), |
185 | REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c), |
186 | REG(QSYS_TFRM_TIMER_CFG_3, 0x011320), |
187 | REG(QSYS_TFRM_TIMER_CFG_4, 0x011324), |
188 | REG(QSYS_TFRM_TIMER_CFG_5, 0x011328), |
189 | REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c), |
190 | REG(QSYS_TFRM_TIMER_CFG_7, 0x011330), |
191 | REG(QSYS_TFRM_TIMER_CFG_8, 0x011334), |
192 | REG(QSYS_RED_PROFILE, 0x011338), |
193 | REG(QSYS_RES_QOS_MODE, 0x011378), |
194 | REG(QSYS_RES_CFG, 0x012000), |
195 | REG(QSYS_RES_STAT, 0x012004), |
196 | REG(QSYS_EGR_DROP_MODE, 0x01137c), |
197 | REG(QSYS_EQ_CTRL, 0x011380), |
198 | REG(QSYS_EVENTS_CORE, 0x011384), |
199 | REG(QSYS_CIR_CFG, 0x000000), |
200 | REG(QSYS_EIR_CFG, 0x000004), |
201 | REG(QSYS_SE_CFG, 0x000008), |
202 | REG(QSYS_SE_DWRR_CFG, 0x00000c), |
203 | REG(QSYS_SE_CONNECT, 0x00003c), |
204 | REG(QSYS_SE_DLB_SENSE, 0x000040), |
205 | REG(QSYS_CIR_STATE, 0x000044), |
206 | REG(QSYS_EIR_STATE, 0x000048), |
207 | REG(QSYS_SE_STATE, 0x00004c), |
208 | REG(QSYS_HSCH_MISC_CFG, 0x011388), |
209 | }; |
210 | |
211 | static const u32 vsc7514_rew_regmap[] = { |
212 | REG(REW_PORT_VLAN_CFG, 0x000000), |
213 | REG(REW_TAG_CFG, 0x000004), |
214 | REG(REW_PORT_CFG, 0x000008), |
215 | REG(REW_DSCP_CFG, 0x00000c), |
216 | REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), |
217 | REG(REW_PTP_CFG, 0x000050), |
218 | REG(REW_PTP_DLY1_CFG, 0x000054), |
219 | REG(REW_DSCP_REMAP_DP1_CFG, 0x000690), |
220 | REG(REW_DSCP_REMAP_CFG, 0x000790), |
221 | REG(REW_STAT_CFG, 0x000890), |
222 | REG(REW_PPT, 0x000680), |
223 | }; |
224 | |
225 | static const u32 vsc7514_sys_regmap[] = { |
226 | REG(SYS_COUNT_RX_OCTETS, 0x000000), |
227 | REG(SYS_COUNT_RX_UNICAST, 0x000004), |
228 | REG(SYS_COUNT_RX_MULTICAST, 0x000008), |
229 | REG(SYS_COUNT_RX_BROADCAST, 0x00000c), |
230 | REG(SYS_COUNT_RX_SHORTS, 0x000010), |
231 | REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), |
232 | REG(SYS_COUNT_RX_JABBERS, 0x000018), |
233 | REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), |
234 | REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), |
235 | REG(SYS_COUNT_RX_64, 0x000024), |
236 | REG(SYS_COUNT_RX_65_127, 0x000028), |
237 | REG(SYS_COUNT_RX_128_255, 0x00002c), |
238 | REG(SYS_COUNT_RX_256_511, 0x000030), |
239 | REG(SYS_COUNT_RX_512_1023, 0x000034), |
240 | REG(SYS_COUNT_RX_1024_1526, 0x000038), |
241 | REG(SYS_COUNT_RX_1527_MAX, 0x00003c), |
242 | REG(SYS_COUNT_RX_PAUSE, 0x000040), |
243 | REG(SYS_COUNT_RX_CONTROL, 0x000044), |
244 | REG(SYS_COUNT_RX_LONGS, 0x000048), |
245 | REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), |
246 | REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), |
247 | REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), |
248 | REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), |
249 | REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), |
250 | REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), |
251 | REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), |
252 | REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), |
253 | REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), |
254 | REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), |
255 | REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), |
256 | REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), |
257 | REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), |
258 | REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), |
259 | REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), |
260 | REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), |
261 | REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), |
262 | REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), |
263 | REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), |
264 | REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), |
265 | REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), |
266 | REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), |
267 | REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), |
268 | REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), |
269 | REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), |
270 | REG(SYS_COUNT_TX_OCTETS, 0x000100), |
271 | REG(SYS_COUNT_TX_UNICAST, 0x000104), |
272 | REG(SYS_COUNT_TX_MULTICAST, 0x000108), |
273 | REG(SYS_COUNT_TX_BROADCAST, 0x00010c), |
274 | REG(SYS_COUNT_TX_COLLISION, 0x000110), |
275 | REG(SYS_COUNT_TX_DROPS, 0x000114), |
276 | REG(SYS_COUNT_TX_PAUSE, 0x000118), |
277 | REG(SYS_COUNT_TX_64, 0x00011c), |
278 | REG(SYS_COUNT_TX_65_127, 0x000120), |
279 | REG(SYS_COUNT_TX_128_255, 0x000124), |
280 | REG(SYS_COUNT_TX_256_511, 0x000128), |
281 | REG(SYS_COUNT_TX_512_1023, 0x00012c), |
282 | REG(SYS_COUNT_TX_1024_1526, 0x000130), |
283 | REG(SYS_COUNT_TX_1527_MAX, 0x000134), |
284 | REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000138), |
285 | REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00013c), |
286 | REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000140), |
287 | REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000144), |
288 | REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000148), |
289 | REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00014c), |
290 | REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000150), |
291 | REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000154), |
292 | REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000158), |
293 | REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00015c), |
294 | REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000160), |
295 | REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000164), |
296 | REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000168), |
297 | REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00016c), |
298 | REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000170), |
299 | REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000174), |
300 | REG(SYS_COUNT_TX_AGED, 0x000178), |
301 | REG(SYS_COUNT_DROP_LOCAL, 0x000200), |
302 | REG(SYS_COUNT_DROP_TAIL, 0x000204), |
303 | REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000208), |
304 | REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00020c), |
305 | REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000210), |
306 | REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000214), |
307 | REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000218), |
308 | REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00021c), |
309 | REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000220), |
310 | REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000224), |
311 | REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000228), |
312 | REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00022c), |
313 | REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000230), |
314 | REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000234), |
315 | REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000238), |
316 | REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00023c), |
317 | REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000240), |
318 | REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000244), |
319 | REG(SYS_RESET_CFG, 0x000508), |
320 | REG(SYS_CMID, 0x00050c), |
321 | REG(SYS_VLAN_ETYPE_CFG, 0x000510), |
322 | REG(SYS_PORT_MODE, 0x000514), |
323 | REG(SYS_FRONT_PORT_MODE, 0x000548), |
324 | REG(SYS_FRM_AGING, 0x000574), |
325 | REG(SYS_STAT_CFG, 0x000578), |
326 | REG(SYS_SW_STATUS, 0x00057c), |
327 | REG(SYS_MISC_CFG, 0x0005ac), |
328 | REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0), |
329 | REG(SYS_REW_MAC_LOW_CFG, 0x0005dc), |
330 | REG(SYS_CM_ADDR, 0x000500), |
331 | REG(SYS_CM_DATA, 0x000504), |
332 | REG(SYS_PAUSE_CFG, 0x000608), |
333 | REG(SYS_PAUSE_TOT_CFG, 0x000638), |
334 | REG(SYS_ATOP, 0x00063c), |
335 | REG(SYS_ATOP_TOT_CFG, 0x00066c), |
336 | REG(SYS_MAC_FC_CFG, 0x000670), |
337 | REG(SYS_MMGT, 0x00069c), |
338 | REG(SYS_MMGT_FAST, 0x0006a0), |
339 | REG(SYS_EVENTS_DIF, 0x0006a4), |
340 | REG(SYS_EVENTS_CORE, 0x0006b4), |
341 | REG(SYS_PTP_STATUS, 0x0006b8), |
342 | REG(SYS_PTP_TXSTAMP, 0x0006bc), |
343 | REG(SYS_PTP_NXT, 0x0006c0), |
344 | REG(SYS_PTP_CFG, 0x0006c4), |
345 | }; |
346 | |
347 | static const u32 vsc7514_vcap_regmap[] = { |
348 | /* VCAP_CORE_CFG */ |
349 | REG(VCAP_CORE_UPDATE_CTRL, 0x000000), |
350 | REG(VCAP_CORE_MV_CFG, 0x000004), |
351 | /* VCAP_CORE_CACHE */ |
352 | REG(VCAP_CACHE_ENTRY_DAT, 0x000008), |
353 | REG(VCAP_CACHE_MASK_DAT, 0x000108), |
354 | REG(VCAP_CACHE_ACTION_DAT, 0x000208), |
355 | REG(VCAP_CACHE_CNT_DAT, 0x000308), |
356 | REG(VCAP_CACHE_TG_DAT, 0x000388), |
357 | /* VCAP_CONST */ |
358 | REG(VCAP_CONST_VCAP_VER, 0x000398), |
359 | REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), |
360 | REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), |
361 | REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), |
362 | REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), |
363 | REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), |
364 | REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), |
365 | REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), |
366 | REG(VCAP_CONST_CORE_CNT, 0x0003b8), |
367 | REG(VCAP_CONST_IF_CNT, 0x0003bc), |
368 | }; |
369 | |
370 | static const u32 vsc7514_ptp_regmap[] = { |
371 | REG(PTP_PIN_CFG, 0x000000), |
372 | REG(PTP_PIN_TOD_SEC_MSB, 0x000004), |
373 | REG(PTP_PIN_TOD_SEC_LSB, 0x000008), |
374 | REG(PTP_PIN_TOD_NSEC, 0x00000c), |
375 | REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), |
376 | REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), |
377 | REG(PTP_CFG_MISC, 0x0000a0), |
378 | REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), |
379 | REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), |
380 | }; |
381 | |
382 | static const u32 vsc7514_dev_gmii_regmap[] = { |
383 | REG(DEV_CLOCK_CFG, 0x0), |
384 | REG(DEV_PORT_MISC, 0x4), |
385 | REG(DEV_EVENTS, 0x8), |
386 | REG(DEV_EEE_CFG, 0xc), |
387 | REG(DEV_RX_PATH_DELAY, 0x10), |
388 | REG(DEV_TX_PATH_DELAY, 0x14), |
389 | REG(DEV_PTP_PREDICT_CFG, 0x18), |
390 | REG(DEV_MAC_ENA_CFG, 0x1c), |
391 | REG(DEV_MAC_MODE_CFG, 0x20), |
392 | REG(DEV_MAC_MAXLEN_CFG, 0x24), |
393 | REG(DEV_MAC_TAGS_CFG, 0x28), |
394 | REG(DEV_MAC_ADV_CHK_CFG, 0x2c), |
395 | REG(DEV_MAC_IFG_CFG, 0x30), |
396 | REG(DEV_MAC_HDX_CFG, 0x34), |
397 | REG(DEV_MAC_DBG_CFG, 0x38), |
398 | REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), |
399 | REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), |
400 | REG(DEV_MAC_STICKY, 0x44), |
401 | REG(PCS1G_CFG, 0x48), |
402 | REG(PCS1G_MODE_CFG, 0x4c), |
403 | REG(PCS1G_SD_CFG, 0x50), |
404 | REG(PCS1G_ANEG_CFG, 0x54), |
405 | REG(PCS1G_ANEG_NP_CFG, 0x58), |
406 | REG(PCS1G_LB_CFG, 0x5c), |
407 | REG(PCS1G_DBG_CFG, 0x60), |
408 | REG(PCS1G_CDET_CFG, 0x64), |
409 | REG(PCS1G_ANEG_STATUS, 0x68), |
410 | REG(PCS1G_ANEG_NP_STATUS, 0x6c), |
411 | REG(PCS1G_LINK_STATUS, 0x70), |
412 | REG(PCS1G_LINK_DOWN_CNT, 0x74), |
413 | REG(PCS1G_STICKY, 0x78), |
414 | REG(PCS1G_DEBUG_STATUS, 0x7c), |
415 | REG(PCS1G_LPI_CFG, 0x80), |
416 | REG(PCS1G_LPI_WAKE_ERROR_CNT, 0x84), |
417 | REG(PCS1G_LPI_STATUS, 0x88), |
418 | REG(PCS1G_TSTPAT_MODE_CFG, 0x8c), |
419 | REG(PCS1G_TSTPAT_STATUS, 0x90), |
420 | REG(DEV_PCS_FX100_CFG, 0x94), |
421 | REG(DEV_PCS_FX100_STATUS, 0x98), |
422 | }; |
423 | |
424 | const u32 *vsc7514_regmap[TARGET_MAX] = { |
425 | [ANA] = vsc7514_ana_regmap, |
426 | [QS] = vsc7514_qs_regmap, |
427 | [QSYS] = vsc7514_qsys_regmap, |
428 | [REW] = vsc7514_rew_regmap, |
429 | [SYS] = vsc7514_sys_regmap, |
430 | [S0] = vsc7514_vcap_regmap, |
431 | [S1] = vsc7514_vcap_regmap, |
432 | [S2] = vsc7514_vcap_regmap, |
433 | [PTP] = vsc7514_ptp_regmap, |
434 | [DEV_GMII] = vsc7514_dev_gmii_regmap, |
435 | }; |
436 | EXPORT_SYMBOL(vsc7514_regmap); |
437 | |
438 | static const struct vcap_field vsc7514_vcap_es0_keys[] = { |
439 | [VCAP_ES0_EGR_PORT] = { 0, 4 }, |
440 | [VCAP_ES0_IGR_PORT] = { .offset: 4, .length: 4 }, |
441 | [VCAP_ES0_RSV] = { .offset: 8, .length: 2 }, |
442 | [VCAP_ES0_L2_MC] = { .offset: 10, .length: 1 }, |
443 | [VCAP_ES0_L2_BC] = { .offset: 11, .length: 1 }, |
444 | [VCAP_ES0_VID] = { .offset: 12, .length: 12 }, |
445 | [VCAP_ES0_DP] = { .offset: 24, .length: 1 }, |
446 | [VCAP_ES0_PCP] = { .offset: 25, .length: 3 }, |
447 | }; |
448 | |
449 | static const struct vcap_field vsc7514_vcap_es0_actions[] = { |
450 | [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { .offset: 0, .length: 2 }, |
451 | [VCAP_ES0_ACT_PUSH_INNER_TAG] = { .offset: 2, .length: 1 }, |
452 | [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { .offset: 3, .length: 2 }, |
453 | [VCAP_ES0_ACT_TAG_A_VID_SEL] = { .offset: 5, .length: 1 }, |
454 | [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { .offset: 6, .length: 2 }, |
455 | [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { .offset: 8, .length: 2 }, |
456 | [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { .offset: 10, .length: 2 }, |
457 | [VCAP_ES0_ACT_TAG_B_VID_SEL] = { .offset: 12, .length: 1 }, |
458 | [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { .offset: 13, .length: 2 }, |
459 | [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { .offset: 15, .length: 2 }, |
460 | [VCAP_ES0_ACT_VID_A_VAL] = { .offset: 17, .length: 12 }, |
461 | [VCAP_ES0_ACT_PCP_A_VAL] = { .offset: 29, .length: 3 }, |
462 | [VCAP_ES0_ACT_DEI_A_VAL] = { .offset: 32, .length: 1 }, |
463 | [VCAP_ES0_ACT_VID_B_VAL] = { .offset: 33, .length: 12 }, |
464 | [VCAP_ES0_ACT_PCP_B_VAL] = { .offset: 45, .length: 3 }, |
465 | [VCAP_ES0_ACT_DEI_B_VAL] = { .offset: 48, .length: 1 }, |
466 | [VCAP_ES0_ACT_RSV] = { .offset: 49, .length: 24 }, |
467 | [VCAP_ES0_ACT_HIT_STICKY] = { .offset: 73, .length: 1 }, |
468 | }; |
469 | |
470 | static const struct vcap_field vsc7514_vcap_is1_keys[] = { |
471 | [VCAP_IS1_HK_TYPE] = { .offset: 0, .length: 1 }, |
472 | [VCAP_IS1_HK_LOOKUP] = { .offset: 1, .length: 2 }, |
473 | [VCAP_IS1_HK_IGR_PORT_MASK] = { .offset: 3, .length: 12 }, |
474 | [VCAP_IS1_HK_RSV] = { .offset: 15, .length: 9 }, |
475 | [VCAP_IS1_HK_OAM_Y1731] = { .offset: 24, .length: 1 }, |
476 | [VCAP_IS1_HK_L2_MC] = { .offset: 25, .length: 1 }, |
477 | [VCAP_IS1_HK_L2_BC] = { .offset: 26, .length: 1 }, |
478 | [VCAP_IS1_HK_IP_MC] = { .offset: 27, .length: 1 }, |
479 | [VCAP_IS1_HK_VLAN_TAGGED] = { .offset: 28, .length: 1 }, |
480 | [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { .offset: 29, .length: 1 }, |
481 | [VCAP_IS1_HK_TPID] = { .offset: 30, .length: 1 }, |
482 | [VCAP_IS1_HK_VID] = { .offset: 31, .length: 12 }, |
483 | [VCAP_IS1_HK_DEI] = { .offset: 43, .length: 1 }, |
484 | [VCAP_IS1_HK_PCP] = { .offset: 44, .length: 3 }, |
485 | /* Specific Fields for IS1 Half Key S1_NORMAL */ |
486 | [VCAP_IS1_HK_L2_SMAC] = { .offset: 47, .length: 48 }, |
487 | [VCAP_IS1_HK_ETYPE_LEN] = { .offset: 95, .length: 1 }, |
488 | [VCAP_IS1_HK_ETYPE] = { .offset: 96, .length: 16 }, |
489 | [VCAP_IS1_HK_IP_SNAP] = { .offset: 112, .length: 1 }, |
490 | [VCAP_IS1_HK_IP4] = { .offset: 113, .length: 1 }, |
491 | /* Layer-3 Information */ |
492 | [VCAP_IS1_HK_L3_FRAGMENT] = { .offset: 114, .length: 1 }, |
493 | [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = { .offset: 115, .length: 1 }, |
494 | [VCAP_IS1_HK_L3_OPTIONS] = { .offset: 116, .length: 1 }, |
495 | [VCAP_IS1_HK_L3_DSCP] = { .offset: 117, .length: 6 }, |
496 | [VCAP_IS1_HK_L3_IP4_SIP] = { .offset: 123, .length: 32 }, |
497 | /* Layer-4 Information */ |
498 | [VCAP_IS1_HK_TCP_UDP] = { .offset: 155, .length: 1 }, |
499 | [VCAP_IS1_HK_TCP] = { .offset: 156, .length: 1 }, |
500 | [VCAP_IS1_HK_L4_SPORT] = { .offset: 157, .length: 16 }, |
501 | [VCAP_IS1_HK_L4_RNG] = { .offset: 173, .length: 8 }, |
502 | /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ |
503 | [VCAP_IS1_HK_IP4_INNER_TPID] = { .offset: 47, .length: 1 }, |
504 | [VCAP_IS1_HK_IP4_INNER_VID] = { .offset: 48, .length: 12 }, |
505 | [VCAP_IS1_HK_IP4_INNER_DEI] = { .offset: 60, .length: 1 }, |
506 | [VCAP_IS1_HK_IP4_INNER_PCP] = { .offset: 61, .length: 3 }, |
507 | [VCAP_IS1_HK_IP4_IP4] = { .offset: 64, .length: 1 }, |
508 | [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { .offset: 65, .length: 1 }, |
509 | [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { .offset: 66, .length: 1 }, |
510 | [VCAP_IS1_HK_IP4_L3_OPTIONS] = { .offset: 67, .length: 1 }, |
511 | [VCAP_IS1_HK_IP4_L3_DSCP] = { .offset: 68, .length: 6 }, |
512 | [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { .offset: 74, .length: 32 }, |
513 | [VCAP_IS1_HK_IP4_L3_IP4_SIP] = { .offset: 106, .length: 32 }, |
514 | [VCAP_IS1_HK_IP4_L3_PROTO] = { .offset: 138, .length: 8 }, |
515 | [VCAP_IS1_HK_IP4_TCP_UDP] = { .offset: 146, .length: 1 }, |
516 | [VCAP_IS1_HK_IP4_TCP] = { .offset: 147, .length: 1 }, |
517 | [VCAP_IS1_HK_IP4_L4_RNG] = { .offset: 148, .length: 8 }, |
518 | [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = { .offset: 156, .length: 32 }, |
519 | }; |
520 | |
521 | static const struct vcap_field vsc7514_vcap_is1_actions[] = { |
522 | [VCAP_IS1_ACT_DSCP_ENA] = { .offset: 0, .length: 1 }, |
523 | [VCAP_IS1_ACT_DSCP_VAL] = { .offset: 1, .length: 6 }, |
524 | [VCAP_IS1_ACT_QOS_ENA] = { .offset: 7, .length: 1 }, |
525 | [VCAP_IS1_ACT_QOS_VAL] = { .offset: 8, .length: 3 }, |
526 | [VCAP_IS1_ACT_DP_ENA] = { .offset: 11, .length: 1 }, |
527 | [VCAP_IS1_ACT_DP_VAL] = { .offset: 12, .length: 1 }, |
528 | [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { .offset: 13, .length: 8 }, |
529 | [VCAP_IS1_ACT_PAG_VAL] = { .offset: 21, .length: 8 }, |
530 | [VCAP_IS1_ACT_RSV] = { .offset: 29, .length: 9 }, |
531 | /* The fields below are incorrectly shifted by 2 in the manual */ |
532 | [VCAP_IS1_ACT_VID_REPLACE_ENA] = { .offset: 38, .length: 1 }, |
533 | [VCAP_IS1_ACT_VID_ADD_VAL] = { .offset: 39, .length: 12 }, |
534 | [VCAP_IS1_ACT_FID_SEL] = { .offset: 51, .length: 2 }, |
535 | [VCAP_IS1_ACT_FID_VAL] = { .offset: 53, .length: 13 }, |
536 | [VCAP_IS1_ACT_PCP_DEI_ENA] = { .offset: 66, .length: 1 }, |
537 | [VCAP_IS1_ACT_PCP_VAL] = { .offset: 67, .length: 3 }, |
538 | [VCAP_IS1_ACT_DEI_VAL] = { .offset: 70, .length: 1 }, |
539 | [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { .offset: 71, .length: 1 }, |
540 | [VCAP_IS1_ACT_VLAN_POP_CNT] = { .offset: 72, .length: 2 }, |
541 | [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { .offset: 74, .length: 4 }, |
542 | [VCAP_IS1_ACT_HIT_STICKY] = { .offset: 78, .length: 1 }, |
543 | }; |
544 | |
545 | static const struct vcap_field vsc7514_vcap_is2_keys[] = { |
546 | /* Common: 46 bits */ |
547 | [VCAP_IS2_TYPE] = { .offset: 0, .length: 4 }, |
548 | [VCAP_IS2_HK_FIRST] = { .offset: 4, .length: 1 }, |
549 | [VCAP_IS2_HK_PAG] = { .offset: 5, .length: 8 }, |
550 | [VCAP_IS2_HK_IGR_PORT_MASK] = { .offset: 13, .length: 12 }, |
551 | [VCAP_IS2_HK_RSV2] = { .offset: 25, .length: 1 }, |
552 | [VCAP_IS2_HK_HOST_MATCH] = { .offset: 26, .length: 1 }, |
553 | [VCAP_IS2_HK_L2_MC] = { .offset: 27, .length: 1 }, |
554 | [VCAP_IS2_HK_L2_BC] = { .offset: 28, .length: 1 }, |
555 | [VCAP_IS2_HK_VLAN_TAGGED] = { .offset: 29, .length: 1 }, |
556 | [VCAP_IS2_HK_VID] = { .offset: 30, .length: 12 }, |
557 | [VCAP_IS2_HK_DEI] = { .offset: 42, .length: 1 }, |
558 | [VCAP_IS2_HK_PCP] = { .offset: 43, .length: 3 }, |
559 | /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ |
560 | [VCAP_IS2_HK_L2_DMAC] = { .offset: 46, .length: 48 }, |
561 | [VCAP_IS2_HK_L2_SMAC] = { .offset: 94, .length: 48 }, |
562 | /* MAC_ETYPE (TYPE=000) */ |
563 | [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = { .offset: 142, .length: 16 }, |
564 | [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = { .offset: 158, .length: 16 }, |
565 | [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = { .offset: 174, .length: 8 }, |
566 | [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = { .offset: 182, .length: 3 }, |
567 | /* MAC_LLC (TYPE=001) */ |
568 | [VCAP_IS2_HK_MAC_LLC_L2_LLC] = { .offset: 142, .length: 40 }, |
569 | /* MAC_SNAP (TYPE=010) */ |
570 | [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = { .offset: 142, .length: 40 }, |
571 | /* MAC_ARP (TYPE=011) */ |
572 | [VCAP_IS2_HK_MAC_ARP_SMAC] = { .offset: 46, .length: 48 }, |
573 | [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { .offset: 94, .length: 1 }, |
574 | [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { .offset: 95, .length: 1 }, |
575 | [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { .offset: 96, .length: 1 }, |
576 | [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { .offset: 97, .length: 1 }, |
577 | [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { .offset: 98, .length: 1 }, |
578 | [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { .offset: 99, .length: 1 }, |
579 | [VCAP_IS2_HK_MAC_ARP_OPCODE] = { .offset: 100, .length: 2 }, |
580 | [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { .offset: 102, .length: 32 }, |
581 | [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = { .offset: 134, .length: 32 }, |
582 | [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = { .offset: 166, .length: 1 }, |
583 | /* IP4_TCP_UDP / IP4_OTHER common */ |
584 | [VCAP_IS2_HK_IP4] = { .offset: 46, .length: 1 }, |
585 | [VCAP_IS2_HK_L3_FRAGMENT] = { .offset: 47, .length: 1 }, |
586 | [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { .offset: 48, .length: 1 }, |
587 | [VCAP_IS2_HK_L3_OPTIONS] = { .offset: 49, .length: 1 }, |
588 | [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { .offset: 50, .length: 1 }, |
589 | [VCAP_IS2_HK_L3_TOS] = { .offset: 51, .length: 8 }, |
590 | [VCAP_IS2_HK_L3_IP4_DIP] = { .offset: 59, .length: 32 }, |
591 | [VCAP_IS2_HK_L3_IP4_SIP] = { .offset: 91, .length: 32 }, |
592 | [VCAP_IS2_HK_DIP_EQ_SIP] = { .offset: 123, .length: 1 }, |
593 | /* IP4_TCP_UDP (TYPE=100) */ |
594 | [VCAP_IS2_HK_TCP] = { .offset: 124, .length: 1 }, |
595 | [VCAP_IS2_HK_L4_DPORT] = { .offset: 125, .length: 16 }, |
596 | [VCAP_IS2_HK_L4_SPORT] = { .offset: 141, .length: 16 }, |
597 | [VCAP_IS2_HK_L4_RNG] = { .offset: 157, .length: 8 }, |
598 | [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = { .offset: 165, .length: 1 }, |
599 | [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = { .offset: 166, .length: 1 }, |
600 | [VCAP_IS2_HK_L4_FIN] = { .offset: 167, .length: 1 }, |
601 | [VCAP_IS2_HK_L4_SYN] = { .offset: 168, .length: 1 }, |
602 | [VCAP_IS2_HK_L4_RST] = { .offset: 169, .length: 1 }, |
603 | [VCAP_IS2_HK_L4_PSH] = { .offset: 170, .length: 1 }, |
604 | [VCAP_IS2_HK_L4_ACK] = { .offset: 171, .length: 1 }, |
605 | [VCAP_IS2_HK_L4_URG] = { .offset: 172, .length: 1 }, |
606 | [VCAP_IS2_HK_L4_1588_DOM] = { .offset: 173, .length: 8 }, |
607 | [VCAP_IS2_HK_L4_1588_VER] = { .offset: 181, .length: 4 }, |
608 | /* IP4_OTHER (TYPE=101) */ |
609 | [VCAP_IS2_HK_IP4_L3_PROTO] = { .offset: 124, .length: 8 }, |
610 | [VCAP_IS2_HK_L3_PAYLOAD] = { .offset: 132, .length: 56 }, |
611 | /* IP6_STD (TYPE=110) */ |
612 | [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { .offset: 46, .length: 1 }, |
613 | [VCAP_IS2_HK_L3_IP6_SIP] = { .offset: 47, .length: 128 }, |
614 | [VCAP_IS2_HK_IP6_L3_PROTO] = { .offset: 175, .length: 8 }, |
615 | /* OAM (TYPE=111) */ |
616 | [VCAP_IS2_HK_OAM_MEL_FLAGS] = { .offset: 142, .length: 7 }, |
617 | [VCAP_IS2_HK_OAM_VER] = { .offset: 149, .length: 5 }, |
618 | [VCAP_IS2_HK_OAM_OPCODE] = { .offset: 154, .length: 8 }, |
619 | [VCAP_IS2_HK_OAM_FLAGS] = { .offset: 162, .length: 8 }, |
620 | [VCAP_IS2_HK_OAM_MEPID] = { .offset: 170, .length: 16 }, |
621 | [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = { .offset: 186, .length: 1 }, |
622 | [VCAP_IS2_HK_OAM_IS_Y1731] = { .offset: 187, .length: 1 }, |
623 | }; |
624 | |
625 | static const struct vcap_field vsc7514_vcap_is2_actions[] = { |
626 | [VCAP_IS2_ACT_HIT_ME_ONCE] = { .offset: 0, .length: 1 }, |
627 | [VCAP_IS2_ACT_CPU_COPY_ENA] = { .offset: 1, .length: 1 }, |
628 | [VCAP_IS2_ACT_CPU_QU_NUM] = { .offset: 2, .length: 3 }, |
629 | [VCAP_IS2_ACT_MASK_MODE] = { .offset: 5, .length: 2 }, |
630 | [VCAP_IS2_ACT_MIRROR_ENA] = { .offset: 7, .length: 1 }, |
631 | [VCAP_IS2_ACT_LRN_DIS] = { .offset: 8, .length: 1 }, |
632 | [VCAP_IS2_ACT_POLICE_ENA] = { .offset: 9, .length: 1 }, |
633 | [VCAP_IS2_ACT_POLICE_IDX] = { .offset: 10, .length: 9 }, |
634 | [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { .offset: 19, .length: 1 }, |
635 | [VCAP_IS2_ACT_PORT_MASK] = { .offset: 20, .length: 11 }, |
636 | [VCAP_IS2_ACT_REW_OP] = { .offset: 31, .length: 9 }, |
637 | [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { .offset: 40, .length: 1 }, |
638 | [VCAP_IS2_ACT_RSV] = { .offset: 41, .length: 2 }, |
639 | [VCAP_IS2_ACT_ACL_ID] = { .offset: 43, .length: 6 }, |
640 | [VCAP_IS2_ACT_HIT_CNT] = { .offset: 49, .length: 32 }, |
641 | }; |
642 | |
643 | struct vcap_props vsc7514_vcap_props[] = { |
644 | [VCAP_ES0] = { |
645 | .action_type_width = 0, |
646 | .action_table = { |
647 | [ES0_ACTION_TYPE_NORMAL] = { |
648 | .width = 73, /* HIT_STICKY not included */ |
649 | .count = 1, |
650 | }, |
651 | }, |
652 | .target = S0, |
653 | .keys = vsc7514_vcap_es0_keys, |
654 | .actions = vsc7514_vcap_es0_actions, |
655 | }, |
656 | [VCAP_IS1] = { |
657 | .action_type_width = 0, |
658 | .action_table = { |
659 | [IS1_ACTION_TYPE_NORMAL] = { |
660 | .width = 78, /* HIT_STICKY not included */ |
661 | .count = 4, |
662 | }, |
663 | }, |
664 | .target = S1, |
665 | .keys = vsc7514_vcap_is1_keys, |
666 | .actions = vsc7514_vcap_is1_actions, |
667 | }, |
668 | [VCAP_IS2] = { |
669 | .action_type_width = 1, |
670 | .action_table = { |
671 | [IS2_ACTION_TYPE_NORMAL] = { |
672 | .width = 49, |
673 | .count = 2 |
674 | }, |
675 | [IS2_ACTION_TYPE_SMAC_SIP] = { |
676 | .width = 6, |
677 | .count = 4 |
678 | }, |
679 | }, |
680 | .target = S2, |
681 | .keys = vsc7514_vcap_is2_keys, |
682 | .actions = vsc7514_vcap_is2_actions, |
683 | }, |
684 | }; |
685 | EXPORT_SYMBOL(vsc7514_vcap_props); |
686 | |