1/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2/*
3 * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
4 * Copyright (c) 2014, I2SE GmbH
5 */
6
7/* Qualcomm Atheros SPI register definition.
8 *
9 * This module is designed to define the Qualcomm Atheros SPI
10 * register placeholders.
11 */
12
13#ifndef _QCA_7K_H
14#define _QCA_7K_H
15
16#include <linux/types.h>
17
18#include "qca_spi.h"
19
20#define QCA7K_SPI_READ (1 << 15)
21#define QCA7K_SPI_WRITE (0 << 15)
22#define QCA7K_SPI_INTERNAL (1 << 14)
23#define QCA7K_SPI_EXTERNAL (0 << 14)
24
25#define QCASPI_CMD_LEN 2
26#define QCASPI_HW_PKT_LEN 4
27#define QCASPI_HW_BUF_LEN 0xC5B
28
29/* SPI registers; */
30#define SPI_REG_BFR_SIZE 0x0100
31#define SPI_REG_WRBUF_SPC_AVA 0x0200
32#define SPI_REG_RDBUF_BYTE_AVA 0x0300
33#define SPI_REG_SPI_CONFIG 0x0400
34#define SPI_REG_SPI_STATUS 0x0500
35#define SPI_REG_INTR_CAUSE 0x0C00
36#define SPI_REG_INTR_ENABLE 0x0D00
37#define SPI_REG_RDBUF_WATERMARK 0x1200
38#define SPI_REG_WRBUF_WATERMARK 0x1300
39#define SPI_REG_SIGNATURE 0x1A00
40#define SPI_REG_ACTION_CTRL 0x1B00
41
42/* SPI_CONFIG register definition; */
43#define QCASPI_SLAVE_RESET_BIT BIT(6)
44
45/* INTR_CAUSE/ENABLE register definition. */
46#define SPI_INT_WRBUF_BELOW_WM BIT(10)
47#define SPI_INT_CPU_ON BIT(6)
48#define SPI_INT_ADDR_ERR BIT(3)
49#define SPI_INT_WRBUF_ERR BIT(2)
50#define SPI_INT_RDBUF_ERR BIT(1)
51#define SPI_INT_PKT_AVLBL BIT(0)
52
53void qcaspi_spi_error(struct qcaspi *qca);
54int qcaspi_read_register(struct qcaspi *qca, u16 reg, u16 *result);
55int qcaspi_write_register(struct qcaspi *qca, u16 reg, u16 value, int retry);
56
57#endif /* _QCA_7K_H */
58

source code of linux/drivers/net/ethernet/qualcomm/qca_7k.h