1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /**************************************************************************** |
3 | * Driver for Solarflare network controllers and boards |
4 | * Copyright 2018 Solarflare Communications Inc. |
5 | * Copyright 2019-2022 Xilinx Inc. |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify it |
8 | * under the terms of the GNU General Public License version 2 as published |
9 | * by the Free Software Foundation, incorporated herein by reference. |
10 | */ |
11 | |
12 | #ifndef EFX_EF100_REGS_H |
13 | #define EFX_EF100_REGS_H |
14 | |
15 | /* EF100 hardware architecture definitions have a name prefix following |
16 | * the format: |
17 | * |
18 | * E<type>_<min-rev><max-rev>_ |
19 | * |
20 | * The following <type> strings are used: |
21 | * |
22 | * MMIO register Host memory structure |
23 | * ------------------------------------------------------------- |
24 | * Address R |
25 | * Bitfield RF SF |
26 | * Enumerator FE SE |
27 | * |
28 | * <min-rev> is the first revision to which the definition applies: |
29 | * |
30 | * G: Riverhead |
31 | * |
32 | * If the definition has been changed or removed in later revisions |
33 | * then <max-rev> is the last revision to which the definition applies; |
34 | * otherwise it is "Z". |
35 | */ |
36 | |
37 | /************************************************************************** |
38 | * |
39 | * EF100 registers and descriptors |
40 | * |
41 | ************************************************************************** |
42 | */ |
43 | |
44 | /* HW_REV_ID_REG: Hardware revision info register */ |
45 | #define ER_GZ_HW_REV_ID 0x00000000 |
46 | |
47 | /* NIC_REV_ID: SoftNIC revision info register */ |
48 | #define ER_GZ_NIC_REV_ID 0x00000004 |
49 | |
50 | /* NIC_MAGIC: Signature register that should contain a well-known value */ |
51 | #define ER_GZ_NIC_MAGIC 0x00000008 |
52 | #define ERF_GZ_NIC_MAGIC_LBN 0 |
53 | #define ERF_GZ_NIC_MAGIC_WIDTH 32 |
54 | #define EFE_GZ_NIC_MAGIC_EXPECTED 0xEF100FCB |
55 | |
56 | /* MC_SFT_STATUS: MC soft status */ |
57 | #define ER_GZ_MC_SFT_STATUS 0x00000010 |
58 | #define ER_GZ_MC_SFT_STATUS_STEP 4 |
59 | #define ER_GZ_MC_SFT_STATUS_ROWS 2 |
60 | |
61 | /* MC_DB_LWRD_REG: MC doorbell register, low word */ |
62 | #define ER_GZ_MC_DB_LWRD 0x00000020 |
63 | |
64 | /* MC_DB_HWRD_REG: MC doorbell register, high word */ |
65 | #define ER_GZ_MC_DB_HWRD 0x00000024 |
66 | |
67 | /* EVQ_INT_PRIME: Prime EVQ */ |
68 | #define ER_GZ_EVQ_INT_PRIME 0x00000040 |
69 | #define ERF_GZ_IDX_LBN 16 |
70 | #define ERF_GZ_IDX_WIDTH 16 |
71 | #define ERF_GZ_EVQ_ID_LBN 0 |
72 | #define ERF_GZ_EVQ_ID_WIDTH 16 |
73 | |
74 | /* INT_AGG_RING_PRIME: Prime interrupt aggregation ring. */ |
75 | #define ER_GZ_INT_AGG_RING_PRIME 0x00000048 |
76 | /* defined as ERF_GZ_IDX_LBN 16; access=WO reset=0x0 */ |
77 | /* defined as ERF_GZ_IDX_WIDTH 16 */ |
78 | #define ERF_GZ_RING_ID_LBN 0 |
79 | #define ERF_GZ_RING_ID_WIDTH 16 |
80 | |
81 | /* EVQ_TMR: EVQ timer control */ |
82 | #define ER_GZ_EVQ_TMR 0x00000104 |
83 | #define ER_GZ_EVQ_TMR_STEP 65536 |
84 | #define ER_GZ_EVQ_TMR_ROWS 1024 |
85 | |
86 | /* EVQ_UNSOL_CREDIT_GRANT_SEQ: Grant credits for unsolicited events. */ |
87 | #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ 0x00000108 |
88 | #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_STEP 65536 |
89 | #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_ROWS 1024 |
90 | |
91 | /* EVQ_DESC_CREDIT_GRANT_SEQ: Grant credits for descriptor proxy events. */ |
92 | #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ 0x00000110 |
93 | #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_STEP 65536 |
94 | #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_ROWS 1024 |
95 | |
96 | /* RX_RING_DOORBELL: Ring Rx doorbell. */ |
97 | #define ER_GZ_RX_RING_DOORBELL 0x00000180 |
98 | #define ER_GZ_RX_RING_DOORBELL_STEP 65536 |
99 | #define ER_GZ_RX_RING_DOORBELL_ROWS 1024 |
100 | #define ERF_GZ_RX_RING_PIDX_LBN 16 |
101 | #define ERF_GZ_RX_RING_PIDX_WIDTH 16 |
102 | |
103 | /* TX_RING_DOORBELL: Ring Tx doorbell. */ |
104 | #define ER_GZ_TX_RING_DOORBELL 0x00000200 |
105 | #define ER_GZ_TX_RING_DOORBELL_STEP 65536 |
106 | #define ER_GZ_TX_RING_DOORBELL_ROWS 1024 |
107 | #define ERF_GZ_TX_RING_PIDX_LBN 16 |
108 | #define ERF_GZ_TX_RING_PIDX_WIDTH 16 |
109 | |
110 | /* TX_DESC_PUSH: Tx ring descriptor push. Reserved for future use. */ |
111 | #define ER_GZ_TX_DESC_PUSH 0x00000210 |
112 | #define ER_GZ_TX_DESC_PUSH_STEP 65536 |
113 | #define ER_GZ_TX_DESC_PUSH_ROWS 1024 |
114 | |
115 | /* THE_TIME: NIC hardware time */ |
116 | #define ER_GZ_THE_TIME 0x00000280 |
117 | #define ER_GZ_THE_TIME_STEP 65536 |
118 | #define ER_GZ_THE_TIME_ROWS 1024 |
119 | #define ERF_GZ_THE_TIME_SECS_LBN 32 |
120 | #define ERF_GZ_THE_TIME_SECS_WIDTH 32 |
121 | #define ERF_GZ_THE_TIME_NANOS_LBN 2 |
122 | #define ERF_GZ_THE_TIME_NANOS_WIDTH 30 |
123 | #define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_LBN 1 |
124 | #define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_WIDTH 1 |
125 | #define ERF_GZ_THE_TIME_CLOCK_IS_SET_LBN 0 |
126 | #define ERF_GZ_THE_TIME_CLOCK_IS_SET_WIDTH 1 |
127 | |
128 | /* PARAMS_TLV_LEN: Size of design parameters area in bytes */ |
129 | #define ER_GZ_PARAMS_TLV_LEN 0x00000c00 |
130 | #define ER_GZ_PARAMS_TLV_LEN_STEP 65536 |
131 | #define ER_GZ_PARAMS_TLV_LEN_ROWS 1024 |
132 | |
133 | /* PARAMS_TLV: Design parameters */ |
134 | #define ER_GZ_PARAMS_TLV 0x00000c04 |
135 | #define ER_GZ_PARAMS_TLV_STEP 65536 |
136 | #define ER_GZ_PARAMS_TLV_ROWS 1024 |
137 | |
138 | /* EW_EMBEDDED_EVENT */ |
139 | #define ESF_GZ_EV_256_EVENT_LBN 0 |
140 | #define ESF_GZ_EV_256_EVENT_WIDTH 64 |
141 | #define ESE_GZ_EW_EMBEDDED_EVENT_STRUCT_SIZE 64 |
142 | |
143 | /* NMMU_PAGESZ_2M_ADDR */ |
144 | #define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_LBN 59 |
145 | #define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_WIDTH 5 |
146 | #define ESE_GZ_NMMU_PAGE_SIZE_2M 9 |
147 | #define ESF_GZ_NMMU_2M_PAGE_ID_LBN 21 |
148 | #define ESF_GZ_NMMU_2M_PAGE_ID_WIDTH 38 |
149 | #define ESF_GZ_NMMU_2M_PAGE_OFFSET_LBN 0 |
150 | #define ESF_GZ_NMMU_2M_PAGE_OFFSET_WIDTH 21 |
151 | #define ESE_GZ_NMMU_PAGESZ_2M_ADDR_STRUCT_SIZE 64 |
152 | |
153 | /* PARAM_TLV */ |
154 | #define ESF_GZ_TLV_VALUE_LBN 16 |
155 | #define ESF_GZ_TLV_VALUE_WIDTH 8 |
156 | #define ESE_GZ_TLV_VALUE_LENMIN 8 |
157 | #define ESE_GZ_TLV_VALUE_LENMAX 2040 |
158 | #define ESF_GZ_TLV_LEN_LBN 8 |
159 | #define ESF_GZ_TLV_LEN_WIDTH 8 |
160 | #define ESF_GZ_TLV_TYPE_LBN 0 |
161 | #define ESF_GZ_TLV_TYPE_WIDTH 8 |
162 | #define ESE_GZ_DP_NMMU_GROUP_SIZE 5 |
163 | #define ESE_GZ_DP_EVQ_UNSOL_CREDIT_SEQ_BITS 4 |
164 | #define ESE_GZ_DP_TX_EV_NUM_DESCS_BITS 3 |
165 | #define ESE_GZ_DP_RX_EV_NUM_PACKETS_BITS 2 |
166 | #define ESE_GZ_DP_PARTIAL_TSTAMP_SUB_NANO_BITS 1 |
167 | #define ESE_GZ_DP_PAD 0 |
168 | #define ESE_GZ_PARAM_TLV_STRUCT_SIZE 24 |
169 | |
170 | /* PCI_EXPRESS_XCAP_HDR */ |
171 | #define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_LBN 20 |
172 | #define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_WIDTH 12 |
173 | #define ESF_GZ_PCI_EXPRESS_XCAP_VER_LBN 16 |
174 | #define ESF_GZ_PCI_EXPRESS_XCAP_VER_WIDTH 4 |
175 | #define ESE_GZ_PCI_EXPRESS_XCAP_VER_VSEC 1 |
176 | #define ESF_GZ_PCI_EXPRESS_XCAP_ID_LBN 0 |
177 | #define ESF_GZ_PCI_EXPRESS_XCAP_ID_WIDTH 16 |
178 | #define ESE_GZ_PCI_EXPRESS_XCAP_ID_VNDR 0xb |
179 | #define ESE_GZ_PCI_EXPRESS_XCAP_HDR_STRUCT_SIZE 32 |
180 | |
181 | /* RHEAD_BASE_EVENT */ |
182 | #define ESF_GZ_E_TYPE_LBN 60 |
183 | #define ESF_GZ_E_TYPE_WIDTH 4 |
184 | #define ESF_GZ_EV_EVQ_PHASE_LBN 59 |
185 | #define ESF_GZ_EV_EVQ_PHASE_WIDTH 1 |
186 | #define ESE_GZ_RHEAD_BASE_EVENT_STRUCT_SIZE 64 |
187 | |
188 | /* RHEAD_EW_EVENT */ |
189 | #define ESF_GZ_EV_256_EV32_PHASE_LBN 255 |
190 | #define ESF_GZ_EV_256_EV32_PHASE_WIDTH 1 |
191 | #define ESF_GZ_EV_256_EV32_TYPE_LBN 251 |
192 | #define ESF_GZ_EV_256_EV32_TYPE_WIDTH 4 |
193 | #define ESE_GZ_EF100_EVEW_VIRTQ_DESC 2 |
194 | #define ESE_GZ_EF100_EVEW_TXQ_DESC 1 |
195 | #define ESE_GZ_EF100_EVEW_64BIT 0 |
196 | #define ESE_GZ_RHEAD_EW_EVENT_STRUCT_SIZE 256 |
197 | |
198 | /* RX_DESC */ |
199 | #define ESF_GZ_RX_BUF_ADDR_LBN 0 |
200 | #define ESF_GZ_RX_BUF_ADDR_WIDTH 64 |
201 | #define ESE_GZ_RX_DESC_STRUCT_SIZE 64 |
202 | |
203 | /* TXQ_DESC_PROXY_EVENT */ |
204 | #define ESF_GZ_EV_TXQ_DP_VI_ID_LBN 128 |
205 | #define ESF_GZ_EV_TXQ_DP_VI_ID_WIDTH 16 |
206 | #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_LBN 0 |
207 | #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_WIDTH 128 |
208 | #define ESE_GZ_TXQ_DESC_PROXY_EVENT_STRUCT_SIZE 144 |
209 | |
210 | /* TX_DESC_TYPE */ |
211 | #define ESF_GZ_TX_DESC_TYPE_LBN 124 |
212 | #define ESF_GZ_TX_DESC_TYPE_WIDTH 4 |
213 | #define ESE_GZ_TX_DESC_TYPE_DESC2CMPT 7 |
214 | #define ESE_GZ_TX_DESC_TYPE_MEM2MEM 4 |
215 | #define ESE_GZ_TX_DESC_TYPE_SEG 3 |
216 | #define ESE_GZ_TX_DESC_TYPE_TSO 2 |
217 | #define ESE_GZ_TX_DESC_TYPE_PREFIX 1 |
218 | #define ESE_GZ_TX_DESC_TYPE_SEND 0 |
219 | #define ESE_GZ_TX_DESC_TYPE_STRUCT_SIZE 128 |
220 | |
221 | /* VIRTQ_DESC_PROXY_EVENT */ |
222 | #define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_LBN 144 |
223 | #define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_WIDTH 16 |
224 | #define ESF_GZ_EV_VQ_DP_VI_ID_LBN 128 |
225 | #define ESF_GZ_EV_VQ_DP_VI_ID_WIDTH 16 |
226 | #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_LBN 0 |
227 | #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_WIDTH 128 |
228 | #define ESE_GZ_VIRTQ_DESC_PROXY_EVENT_STRUCT_SIZE 160 |
229 | |
230 | /* XIL_CFGBAR_TBL_ENTRY */ |
231 | #define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_LBN 96 |
232 | #define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_WIDTH 32 |
233 | #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_LBN 68 |
234 | #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_WIDTH 60 |
235 | #define ESE_GZ_CONT_CAP_OFFSET_BYTES_SHIFT 4 |
236 | #define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_LBN 67 |
237 | #define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_WIDTH 29 |
238 | #define ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT 4 |
239 | #define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_LBN 68 |
240 | #define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_WIDTH 28 |
241 | #define ESF_GZ_CFGBAR_CONT_CAP_RSV_LBN 67 |
242 | #define ESF_GZ_CFGBAR_CONT_CAP_RSV_WIDTH 1 |
243 | #define ESF_GZ_CFGBAR_EF100_BAR_LBN 64 |
244 | #define ESF_GZ_CFGBAR_EF100_BAR_WIDTH 3 |
245 | #define ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID 7 |
246 | #define ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM 6 |
247 | #define ESF_GZ_CFGBAR_CONT_CAP_BAR_LBN 64 |
248 | #define ESF_GZ_CFGBAR_CONT_CAP_BAR_WIDTH 3 |
249 | #define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_INVALID 7 |
250 | #define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_EXPANSION_ROM 6 |
251 | #define ESF_GZ_CFGBAR_ENTRY_SIZE_LBN 32 |
252 | #define ESF_GZ_CFGBAR_ENTRY_SIZE_WIDTH 32 |
253 | #define ESE_GZ_CFGBAR_ENTRY_SIZE_EF100 12 |
254 | #define 8 |
255 | #define ESF_GZ_CFGBAR_ENTRY_LAST_LBN 28 |
256 | #define ESF_GZ_CFGBAR_ENTRY_LAST_WIDTH 1 |
257 | #define ESF_GZ_CFGBAR_ENTRY_REV_LBN 20 |
258 | #define ESF_GZ_CFGBAR_ENTRY_REV_WIDTH 8 |
259 | #define ESE_GZ_CFGBAR_ENTRY_REV_EF100 0 |
260 | #define ESF_GZ_CFGBAR_ENTRY_FORMAT_LBN 0 |
261 | #define ESF_GZ_CFGBAR_ENTRY_FORMAT_WIDTH 20 |
262 | #define ESE_GZ_CFGBAR_ENTRY_LAST 0xfffff |
263 | #define ESE_GZ_CFGBAR_ENTRY_CONT_CAP_ADDR 0xffffe |
264 | #define ESE_GZ_CFGBAR_ENTRY_EF100 0xef100 |
265 | #define ESE_GZ_XIL_CFGBAR_TBL_ENTRY_STRUCT_SIZE 128 |
266 | |
267 | /* XIL_CFGBAR_VSEC */ |
268 | #define ESF_GZ_VSEC_TBL_OFF_HI_LBN 64 |
269 | #define ESF_GZ_VSEC_TBL_OFF_HI_WIDTH 32 |
270 | #define ESE_GZ_VSEC_TBL_OFF_HI_BYTES_SHIFT 32 |
271 | #define ESF_GZ_VSEC_TBL_OFF_LO_LBN 36 |
272 | #define ESF_GZ_VSEC_TBL_OFF_LO_WIDTH 28 |
273 | #define ESE_GZ_VSEC_TBL_OFF_LO_BYTES_SHIFT 4 |
274 | #define ESF_GZ_VSEC_TBL_BAR_LBN 32 |
275 | #define ESF_GZ_VSEC_TBL_BAR_WIDTH 4 |
276 | #define ESE_GZ_VSEC_BAR_NUM_INVALID 7 |
277 | #define ESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM 6 |
278 | #define ESF_GZ_VSEC_LEN_LBN 20 |
279 | #define ESF_GZ_VSEC_LEN_WIDTH 12 |
280 | #define ESE_GZ_VSEC_LEN_HIGH_OFFT 16 |
281 | #define ESE_GZ_VSEC_LEN_MIN 12 |
282 | #define ESF_GZ_VSEC_VER_LBN 16 |
283 | #define ESF_GZ_VSEC_VER_WIDTH 4 |
284 | #define ESE_GZ_VSEC_VER_XIL_CFGBAR 0 |
285 | #define ESF_GZ_VSEC_ID_LBN 0 |
286 | #define ESF_GZ_VSEC_ID_WIDTH 16 |
287 | #define ESE_GZ_XILINX_VSEC_ID 0x20 |
288 | #define ESE_GZ_XIL_CFGBAR_VSEC_STRUCT_SIZE 96 |
289 | |
290 | /* rh_egres_hclass */ |
291 | #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_LBN 15 |
292 | #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_WIDTH 1 |
293 | #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_LBN 13 |
294 | #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_WIDTH 2 |
295 | #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_LBN 12 |
296 | #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_WIDTH 1 |
297 | #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_LBN 10 |
298 | #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_WIDTH 2 |
299 | #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_LBN 8 |
300 | #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_WIDTH 2 |
301 | #define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_LBN 5 |
302 | #define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_WIDTH 3 |
303 | #define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_LBN 3 |
304 | #define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_WIDTH 2 |
305 | #define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_LBN 2 |
306 | #define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_WIDTH 1 |
307 | #define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_LBN 0 |
308 | #define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_WIDTH 2 |
309 | #define ESE_GZ_RH_EGRES_HCLASS_STRUCT_SIZE 16 |
310 | |
311 | /* sf_driver */ |
312 | #define ESF_GZ_DRIVER_E_TYPE_LBN 60 |
313 | #define ESF_GZ_DRIVER_E_TYPE_WIDTH 4 |
314 | #define ESF_GZ_DRIVER_PHASE_LBN 59 |
315 | #define ESF_GZ_DRIVER_PHASE_WIDTH 1 |
316 | #define ESF_GZ_DRIVER_DATA_LBN 0 |
317 | #define ESF_GZ_DRIVER_DATA_WIDTH 59 |
318 | #define ESE_GZ_SF_DRIVER_STRUCT_SIZE 64 |
319 | |
320 | /* sf_ev_rsvd */ |
321 | #define ESF_GZ_EV_RSVD_TBD_NEXT_LBN 34 |
322 | #define ESF_GZ_EV_RSVD_TBD_NEXT_WIDTH 3 |
323 | #define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_LBN 30 |
324 | #define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_WIDTH 4 |
325 | #define ESF_GZ_EV_RSVD_SRC_QID_LBN 18 |
326 | #define ESF_GZ_EV_RSVD_SRC_QID_WIDTH 12 |
327 | #define ESF_GZ_EV_RSVD_SEQ_NUM_LBN 2 |
328 | #define ESF_GZ_EV_RSVD_SEQ_NUM_WIDTH 16 |
329 | #define ESF_GZ_EV_RSVD_TBD_LBN 0 |
330 | #define ESF_GZ_EV_RSVD_TBD_WIDTH 2 |
331 | #define ESE_GZ_SF_EV_RSVD_STRUCT_SIZE 37 |
332 | |
333 | /* sf_flush_evnt */ |
334 | #define ESF_GZ_EV_FLSH_E_TYPE_LBN 60 |
335 | #define ESF_GZ_EV_FLSH_E_TYPE_WIDTH 4 |
336 | #define ESF_GZ_EV_FLSH_PHASE_LBN 59 |
337 | #define ESF_GZ_EV_FLSH_PHASE_WIDTH 1 |
338 | #define ESF_GZ_EV_FLSH_SUB_TYPE_LBN 53 |
339 | #define ESF_GZ_EV_FLSH_SUB_TYPE_WIDTH 6 |
340 | #define ESF_GZ_EV_FLSH_RSVD_LBN 10 |
341 | #define ESF_GZ_EV_FLSH_RSVD_WIDTH 43 |
342 | #define ESF_GZ_EV_FLSH_LABEL_LBN 4 |
343 | #define ESF_GZ_EV_FLSH_LABEL_WIDTH 6 |
344 | #define ESF_GZ_EV_FLSH_FLUSH_TYPE_LBN 0 |
345 | #define ESF_GZ_EV_FLSH_FLUSH_TYPE_WIDTH 4 |
346 | #define ESE_GZ_SF_FLUSH_EVNT_STRUCT_SIZE 64 |
347 | |
348 | /* sf_rx_pkts */ |
349 | #define ESF_GZ_EV_RXPKTS_E_TYPE_LBN 60 |
350 | #define ESF_GZ_EV_RXPKTS_E_TYPE_WIDTH 4 |
351 | #define ESF_GZ_EV_RXPKTS_PHASE_LBN 59 |
352 | #define ESF_GZ_EV_RXPKTS_PHASE_WIDTH 1 |
353 | #define ESF_GZ_EV_RXPKTS_RSVD_LBN 22 |
354 | #define ESF_GZ_EV_RXPKTS_RSVD_WIDTH 37 |
355 | #define ESF_GZ_EV_RXPKTS_Q_LABEL_LBN 16 |
356 | #define ESF_GZ_EV_RXPKTS_Q_LABEL_WIDTH 6 |
357 | #define ESF_GZ_EV_RXPKTS_NUM_PKT_LBN 0 |
358 | #define ESF_GZ_EV_RXPKTS_NUM_PKT_WIDTH 16 |
359 | #define ESE_GZ_SF_RX_PKTS_STRUCT_SIZE 64 |
360 | |
361 | /* sf_rx_prefix */ |
362 | #define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_LBN 160 |
363 | #define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_WIDTH 16 |
364 | #define ESF_GZ_RX_PREFIX_CSUM_FRAME_LBN 144 |
365 | #define ESF_GZ_RX_PREFIX_CSUM_FRAME_WIDTH 16 |
366 | #define ESF_GZ_RX_PREFIX_INGRESS_MPORT_LBN 128 |
367 | #define ESF_GZ_RX_PREFIX_INGRESS_MPORT_WIDTH 16 |
368 | #define ESF_GZ_RX_PREFIX_USER_MARK_LBN 96 |
369 | #define ESF_GZ_RX_PREFIX_USER_MARK_WIDTH 32 |
370 | #define 64 |
371 | #define 32 |
372 | #define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN 34 |
373 | #define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_WIDTH 30 |
374 | #define ESF_GZ_RX_PREFIX_VSWITCH_STATUS_LBN 33 |
375 | #define ESF_GZ_RX_PREFIX_VSWITCH_STATUS_WIDTH 1 |
376 | #define ESF_GZ_RX_PREFIX_VLAN_STRIPPED_LBN 32 |
377 | #define ESF_GZ_RX_PREFIX_VLAN_STRIPPED_WIDTH 1 |
378 | #define ESF_GZ_RX_PREFIX_CLASS_LBN 16 |
379 | #define ESF_GZ_RX_PREFIX_CLASS_WIDTH 16 |
380 | #define ESF_GZ_RX_PREFIX_USER_FLAG_LBN 15 |
381 | #define ESF_GZ_RX_PREFIX_USER_FLAG_WIDTH 1 |
382 | #define 14 |
383 | #define 1 |
384 | #define ESF_GZ_RX_PREFIX_LENGTH_LBN 0 |
385 | #define ESF_GZ_RX_PREFIX_LENGTH_WIDTH 14 |
386 | #define ESE_GZ_SF_RX_PREFIX_STRUCT_SIZE 176 |
387 | |
388 | /* sf_rxtx_generic */ |
389 | #define ESF_GZ_EV_BARRIER_LBN 167 |
390 | #define ESF_GZ_EV_BARRIER_WIDTH 1 |
391 | #define ESF_GZ_EV_RSVD_LBN 130 |
392 | #define ESF_GZ_EV_RSVD_WIDTH 37 |
393 | #define ESF_GZ_EV_DPRXY_LBN 129 |
394 | #define ESF_GZ_EV_DPRXY_WIDTH 1 |
395 | #define ESF_GZ_EV_VIRTIO_LBN 128 |
396 | #define ESF_GZ_EV_VIRTIO_WIDTH 1 |
397 | #define ESF_GZ_EV_COUNT_LBN 0 |
398 | #define ESF_GZ_EV_COUNT_WIDTH 128 |
399 | #define ESE_GZ_SF_RXTX_GENERIC_STRUCT_SIZE 168 |
400 | |
401 | /* sf_ts_stamp */ |
402 | #define ESF_GZ_EV_TS_E_TYPE_LBN 60 |
403 | #define ESF_GZ_EV_TS_E_TYPE_WIDTH 4 |
404 | #define ESF_GZ_EV_TS_PHASE_LBN 59 |
405 | #define ESF_GZ_EV_TS_PHASE_WIDTH 1 |
406 | #define ESF_GZ_EV_TS_RSVD_LBN 56 |
407 | #define ESF_GZ_EV_TS_RSVD_WIDTH 3 |
408 | #define ESF_GZ_EV_TS_STATUS_LBN 54 |
409 | #define ESF_GZ_EV_TS_STATUS_WIDTH 2 |
410 | #define ESF_GZ_EV_TS_Q_LABEL_LBN 48 |
411 | #define ESF_GZ_EV_TS_Q_LABEL_WIDTH 6 |
412 | #define ESF_GZ_EV_TS_DESC_ID_LBN 32 |
413 | #define ESF_GZ_EV_TS_DESC_ID_WIDTH 16 |
414 | #define ESF_GZ_EV_TS_PARTIAL_STAMP_LBN 0 |
415 | #define ESF_GZ_EV_TS_PARTIAL_STAMP_WIDTH 32 |
416 | #define ESE_GZ_SF_TS_STAMP_STRUCT_SIZE 64 |
417 | |
418 | /* sf_tx_cmplt */ |
419 | #define ESF_GZ_EV_TXCMPL_E_TYPE_LBN 60 |
420 | #define ESF_GZ_EV_TXCMPL_E_TYPE_WIDTH 4 |
421 | #define ESF_GZ_EV_TXCMPL_PHASE_LBN 59 |
422 | #define ESF_GZ_EV_TXCMPL_PHASE_WIDTH 1 |
423 | #define ESF_GZ_EV_TXCMPL_RSVD_LBN 22 |
424 | #define ESF_GZ_EV_TXCMPL_RSVD_WIDTH 37 |
425 | #define ESF_GZ_EV_TXCMPL_Q_LABEL_LBN 16 |
426 | #define ESF_GZ_EV_TXCMPL_Q_LABEL_WIDTH 6 |
427 | #define ESF_GZ_EV_TXCMPL_NUM_DESC_LBN 0 |
428 | #define ESF_GZ_EV_TXCMPL_NUM_DESC_WIDTH 16 |
429 | #define ESE_GZ_SF_TX_CMPLT_STRUCT_SIZE 64 |
430 | |
431 | /* sf_tx_desc2cmpt_dsc_fmt */ |
432 | #define ESF_GZ_D2C_TGT_VI_ID_LBN 108 |
433 | #define ESF_GZ_D2C_TGT_VI_ID_WIDTH 16 |
434 | #define ESF_GZ_D2C_CMPT2_LBN 107 |
435 | #define ESF_GZ_D2C_CMPT2_WIDTH 1 |
436 | #define ESF_GZ_D2C_ABS_VI_ID_LBN 106 |
437 | #define ESF_GZ_D2C_ABS_VI_ID_WIDTH 1 |
438 | #define ESF_GZ_D2C_ORDERED_LBN 105 |
439 | #define ESF_GZ_D2C_ORDERED_WIDTH 1 |
440 | #define ESF_GZ_D2C_SKIP_N_LBN 97 |
441 | #define ESF_GZ_D2C_SKIP_N_WIDTH 8 |
442 | #define ESF_GZ_D2C_RSVD_LBN 64 |
443 | #define ESF_GZ_D2C_RSVD_WIDTH 33 |
444 | #define ESF_GZ_D2C_COMPLETION_LBN 0 |
445 | #define ESF_GZ_D2C_COMPLETION_WIDTH 64 |
446 | #define ESE_GZ_SF_TX_DESC2CMPT_DSC_FMT_STRUCT_SIZE 124 |
447 | |
448 | /* sf_tx_mem2mem_dsc_fmt */ |
449 | #define ESF_GZ_M2M_ADDR_SPC_EN_LBN 123 |
450 | #define ESF_GZ_M2M_ADDR_SPC_EN_WIDTH 1 |
451 | #define ESF_GZ_M2M_TRANSLATE_ADDR_LBN 122 |
452 | #define ESF_GZ_M2M_TRANSLATE_ADDR_WIDTH 1 |
453 | #define ESF_GZ_M2M_RSVD_LBN 120 |
454 | #define ESF_GZ_M2M_RSVD_WIDTH 2 |
455 | #define ESF_GZ_M2M_ADDR_SPC_ID_LBN 84 |
456 | #define ESF_GZ_M2M_ADDR_SPC_ID_WIDTH 36 |
457 | #define ESF_GZ_M2M_LEN_MINUS_1_LBN 64 |
458 | #define ESF_GZ_M2M_LEN_MINUS_1_WIDTH 20 |
459 | #define ESF_GZ_M2M_ADDR_LBN 0 |
460 | #define ESF_GZ_M2M_ADDR_WIDTH 64 |
461 | #define ESE_GZ_SF_TX_MEM2MEM_DSC_FMT_STRUCT_SIZE 124 |
462 | |
463 | /* sf_tx_ovr_dsc_fmt */ |
464 | #define ESF_GZ_TX_PREFIX_MARK_EN_LBN 123 |
465 | #define ESF_GZ_TX_PREFIX_MARK_EN_WIDTH 1 |
466 | #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_LBN 122 |
467 | #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_WIDTH 1 |
468 | #define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_LBN 121 |
469 | #define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_WIDTH 1 |
470 | #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_LBN 120 |
471 | #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_WIDTH 1 |
472 | #define ESF_GZ_TX_PREFIX_RSRVD_LBN 64 |
473 | #define ESF_GZ_TX_PREFIX_RSRVD_WIDTH 56 |
474 | #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_LBN 48 |
475 | #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_WIDTH 16 |
476 | #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_LBN 32 |
477 | #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_WIDTH 16 |
478 | #define ESF_GZ_TX_PREFIX_MARK_LBN 0 |
479 | #define ESF_GZ_TX_PREFIX_MARK_WIDTH 32 |
480 | #define ESE_GZ_SF_TX_OVR_DSC_FMT_STRUCT_SIZE 124 |
481 | |
482 | /* sf_tx_seg_dsc_fmt */ |
483 | #define ESF_GZ_TX_SEG_ADDR_SPC_EN_LBN 123 |
484 | #define ESF_GZ_TX_SEG_ADDR_SPC_EN_WIDTH 1 |
485 | #define ESF_GZ_TX_SEG_TRANSLATE_ADDR_LBN 122 |
486 | #define ESF_GZ_TX_SEG_TRANSLATE_ADDR_WIDTH 1 |
487 | #define ESF_GZ_TX_SEG_RSVD2_LBN 120 |
488 | #define ESF_GZ_TX_SEG_RSVD2_WIDTH 2 |
489 | #define ESF_GZ_TX_SEG_ADDR_SPC_ID_LBN 84 |
490 | #define ESF_GZ_TX_SEG_ADDR_SPC_ID_WIDTH 36 |
491 | #define ESF_GZ_TX_SEG_RSVD_LBN 80 |
492 | #define ESF_GZ_TX_SEG_RSVD_WIDTH 4 |
493 | #define ESF_GZ_TX_SEG_LEN_LBN 64 |
494 | #define ESF_GZ_TX_SEG_LEN_WIDTH 16 |
495 | #define ESF_GZ_TX_SEG_ADDR_LBN 0 |
496 | #define ESF_GZ_TX_SEG_ADDR_WIDTH 64 |
497 | #define ESE_GZ_SF_TX_SEG_DSC_FMT_STRUCT_SIZE 124 |
498 | |
499 | /* sf_tx_std_dsc_fmt */ |
500 | #define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_LBN 108 |
501 | #define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_WIDTH 16 |
502 | #define ESF_GZ_TX_SEND_VLAN_INSERT_EN_LBN 107 |
503 | #define ESF_GZ_TX_SEND_VLAN_INSERT_EN_WIDTH 1 |
504 | #define ESF_GZ_TX_SEND_TSTAMP_REQ_LBN 106 |
505 | #define ESF_GZ_TX_SEND_TSTAMP_REQ_WIDTH 1 |
506 | #define ESF_GZ_TX_SEND_CSO_OUTER_L4_LBN 105 |
507 | #define ESF_GZ_TX_SEND_CSO_OUTER_L4_WIDTH 1 |
508 | #define ESF_GZ_TX_SEND_CSO_OUTER_L3_LBN 104 |
509 | #define ESF_GZ_TX_SEND_CSO_OUTER_L3_WIDTH 1 |
510 | #define ESF_GZ_TX_SEND_CSO_INNER_L3_LBN 101 |
511 | #define ESF_GZ_TX_SEND_CSO_INNER_L3_WIDTH 3 |
512 | #define ESF_GZ_TX_SEND_RSVD_LBN 99 |
513 | #define ESF_GZ_TX_SEND_RSVD_WIDTH 2 |
514 | #define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_LBN 97 |
515 | #define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_WIDTH 2 |
516 | #define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_LBN 92 |
517 | #define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_WIDTH 5 |
518 | #define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_LBN 83 |
519 | #define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_WIDTH 9 |
520 | #define ESF_GZ_TX_SEND_NUM_SEGS_LBN 78 |
521 | #define ESF_GZ_TX_SEND_NUM_SEGS_WIDTH 5 |
522 | #define ESF_GZ_TX_SEND_LEN_LBN 64 |
523 | #define ESF_GZ_TX_SEND_LEN_WIDTH 14 |
524 | #define ESF_GZ_TX_SEND_ADDR_LBN 0 |
525 | #define ESF_GZ_TX_SEND_ADDR_WIDTH 64 |
526 | #define ESE_GZ_SF_TX_STD_DSC_FMT_STRUCT_SIZE 124 |
527 | |
528 | /* sf_tx_tso_dsc_fmt */ |
529 | #define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_LBN 108 |
530 | #define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_WIDTH 16 |
531 | #define ESF_GZ_TX_TSO_VLAN_INSERT_EN_LBN 107 |
532 | #define ESF_GZ_TX_TSO_VLAN_INSERT_EN_WIDTH 1 |
533 | #define ESF_GZ_TX_TSO_TSTAMP_REQ_LBN 106 |
534 | #define ESF_GZ_TX_TSO_TSTAMP_REQ_WIDTH 1 |
535 | #define ESF_GZ_TX_TSO_CSO_OUTER_L4_LBN 105 |
536 | #define ESF_GZ_TX_TSO_CSO_OUTER_L4_WIDTH 1 |
537 | #define ESF_GZ_TX_TSO_CSO_OUTER_L3_LBN 104 |
538 | #define ESF_GZ_TX_TSO_CSO_OUTER_L3_WIDTH 1 |
539 | #define ESF_GZ_TX_TSO_CSO_INNER_L3_LBN 101 |
540 | #define ESF_GZ_TX_TSO_CSO_INNER_L3_WIDTH 3 |
541 | #define ESF_GZ_TX_TSO_RSVD_LBN 94 |
542 | #define ESF_GZ_TX_TSO_RSVD_WIDTH 7 |
543 | #define ESF_GZ_TX_TSO_CSO_INNER_L4_LBN 93 |
544 | #define ESF_GZ_TX_TSO_CSO_INNER_L4_WIDTH 1 |
545 | #define ESF_GZ_TX_TSO_INNER_L4_OFF_W_LBN 85 |
546 | #define ESF_GZ_TX_TSO_INNER_L4_OFF_W_WIDTH 8 |
547 | #define ESF_GZ_TX_TSO_INNER_L3_OFF_W_LBN 77 |
548 | #define ESF_GZ_TX_TSO_INNER_L3_OFF_W_WIDTH 8 |
549 | #define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_LBN 69 |
550 | #define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_WIDTH 8 |
551 | #define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_LBN 64 |
552 | #define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_WIDTH 5 |
553 | #define ESF_GZ_TX_TSO_PAYLOAD_LEN_LBN 42 |
554 | #define ESF_GZ_TX_TSO_PAYLOAD_LEN_WIDTH 22 |
555 | #define ESF_GZ_TX_TSO_HDR_LEN_W_LBN 34 |
556 | #define ESF_GZ_TX_TSO_HDR_LEN_W_WIDTH 8 |
557 | #define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_LBN 33 |
558 | #define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_WIDTH 1 |
559 | #define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_LBN 32 |
560 | #define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_WIDTH 1 |
561 | #define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_LBN 31 |
562 | #define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_WIDTH 1 |
563 | #define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_LBN 29 |
564 | #define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_WIDTH 2 |
565 | #define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_LBN 27 |
566 | #define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_WIDTH 2 |
567 | #define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_LBN 17 |
568 | #define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_WIDTH 10 |
569 | #define ESF_GZ_TX_TSO_HDR_NUM_SEGS_LBN 14 |
570 | #define ESF_GZ_TX_TSO_HDR_NUM_SEGS_WIDTH 3 |
571 | #define ESF_GZ_TX_TSO_MSS_LBN 0 |
572 | #define ESF_GZ_TX_TSO_MSS_WIDTH 14 |
573 | #define ESE_GZ_SF_TX_TSO_DSC_FMT_STRUCT_SIZE 124 |
574 | |
575 | |
576 | /* Enum D2VIO_MSG_OP */ |
577 | #define ESE_GZ_QUE_JBDNE 3 |
578 | #define ESE_GZ_QUE_EVICT 2 |
579 | #define ESE_GZ_QUE_EMPTY 1 |
580 | #define ESE_GZ_NOP 0 |
581 | |
582 | /* Enum DESIGN_PARAMS */ |
583 | #define ESE_EF100_DP_GZ_RX_MAX_RUNT 17 |
584 | #define ESE_EF100_DP_GZ_VI_STRIDES 16 |
585 | #define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES 15 |
586 | #define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS 14 |
587 | #define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN 13 |
588 | #define ESE_EF100_DP_GZ_COMPAT 12 |
589 | #define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES 11 |
590 | #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS 10 |
591 | #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN 9 |
592 | #define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY 8 |
593 | #define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY 7 |
594 | #define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS 6 |
595 | #define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN 5 |
596 | #define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS 4 |
597 | #define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE 3 |
598 | #define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS 2 |
599 | #define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS 1 |
600 | #define ESE_EF100_DP_GZ_PAD 0 |
601 | |
602 | /* Enum DESIGN_PARAM_DEFAULTS */ |
603 | #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT 0x3fffff |
604 | #define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT 8192 |
605 | #define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN_DEFAULT 8192 |
606 | #define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS_DEFAULT 0x1106 |
607 | #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT 0x3ff |
608 | #define ESE_EF100_DP_GZ_RX_MAX_RUNT_DEFAULT 640 |
609 | #define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS_DEFAULT 512 |
610 | #define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES_DEFAULT 512 |
611 | #define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT 192 |
612 | #define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY_DEFAULT 64 |
613 | #define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY_DEFAULT 64 |
614 | #define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE_DEFAULT 32 |
615 | #define ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT 16 |
616 | #define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS_DEFAULT 7 |
617 | #define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT 4 |
618 | #define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS_DEFAULT 2 |
619 | #define ESE_EF100_DP_GZ_COMPAT_DEFAULT 0 |
620 | |
621 | /* Enum HOST_IF_CONSTANTS */ |
622 | #define ESE_GZ_FCW_LEN 0x4C |
623 | #define ESE_GZ_RX_PKT_PREFIX_LEN 22 |
624 | |
625 | /* Enum PCI_CONSTANTS */ |
626 | #define ESE_GZ_PCI_BASE_CONFIG_SPACE_SIZE 256 |
627 | #define ESE_GZ_PCI_EXPRESS_XCAP_HDR_SIZE 4 |
628 | |
629 | /* Enum RH_DSC_TYPE */ |
630 | #define ESE_GZ_TX_TOMB 0xF |
631 | #define ESE_GZ_TX_VIO 0xE |
632 | #define ESE_GZ_TX_TSO_OVRRD 0x8 |
633 | #define ESE_GZ_TX_D2CMP 0x7 |
634 | #define ESE_GZ_TX_DATA 0x6 |
635 | #define ESE_GZ_TX_D2M 0x5 |
636 | #define ESE_GZ_TX_M2M 0x4 |
637 | #define ESE_GZ_TX_SEG 0x3 |
638 | #define ESE_GZ_TX_TSO 0x2 |
639 | #define ESE_GZ_TX_OVRRD 0x1 |
640 | #define ESE_GZ_TX_SEND 0x0 |
641 | |
642 | /* Enum RH_HCLASS_L2_CLASS */ |
643 | #define ESE_GZ_RH_HCLASS_L2_CLASS_E2_0123VLAN 1 |
644 | #define ESE_GZ_RH_HCLASS_L2_CLASS_OTHER 0 |
645 | |
646 | /* Enum RH_HCLASS_L2_STATUS */ |
647 | #define ESE_GZ_RH_HCLASS_L2_STATUS_RESERVED 3 |
648 | #define ESE_GZ_RH_HCLASS_L2_STATUS_FCS_ERR 2 |
649 | #define ESE_GZ_RH_HCLASS_L2_STATUS_LEN_ERR 1 |
650 | #define ESE_GZ_RH_HCLASS_L2_STATUS_OK 0 |
651 | |
652 | /* Enum RH_HCLASS_L3_CLASS */ |
653 | #define ESE_GZ_RH_HCLASS_L3_CLASS_OTHER 3 |
654 | #define ESE_GZ_RH_HCLASS_L3_CLASS_IP6 2 |
655 | #define ESE_GZ_RH_HCLASS_L3_CLASS_IP4BAD 1 |
656 | #define ESE_GZ_RH_HCLASS_L3_CLASS_IP4GOOD 0 |
657 | |
658 | /* Enum RH_HCLASS_L4_CLASS */ |
659 | #define ESE_GZ_RH_HCLASS_L4_CLASS_OTHER 3 |
660 | #define ESE_GZ_RH_HCLASS_L4_CLASS_FRAG 2 |
661 | #define ESE_GZ_RH_HCLASS_L4_CLASS_UDP 1 |
662 | #define ESE_GZ_RH_HCLASS_L4_CLASS_TCP 0 |
663 | |
664 | /* Enum RH_HCLASS_L4_CSUM */ |
665 | #define ESE_GZ_RH_HCLASS_L4_CSUM_GOOD 1 |
666 | #define ESE_GZ_RH_HCLASS_L4_CSUM_BAD_OR_UNKNOWN 0 |
667 | |
668 | /* Enum RH_HCLASS_TUNNEL_CLASS */ |
669 | #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_7 7 |
670 | #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_6 6 |
671 | #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_5 5 |
672 | #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_4 4 |
673 | #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_GENEVE 3 |
674 | #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NVGRE 2 |
675 | #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_VXLAN 1 |
676 | #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NONE 0 |
677 | |
678 | /* Enum SF_CTL_EVENT_SUBTYPE */ |
679 | #define ESE_GZ_EF100_CTL_EV_EVQ_TIMEOUT 0x3 |
680 | #define ESE_GZ_EF100_CTL_EV_FLUSH 0x2 |
681 | #define ESE_GZ_EF100_CTL_EV_TIME_SYNC 0x1 |
682 | #define ESE_GZ_EF100_CTL_EV_UNSOL_OVERFLOW 0x0 |
683 | |
684 | /* Enum SF_EVENT_TYPE */ |
685 | #define ESE_GZ_EF100_EV_DRIVER 0x5 |
686 | #define ESE_GZ_EF100_EV_MCDI 0x4 |
687 | #define ESE_GZ_EF100_EV_CONTROL 0x3 |
688 | #define ESE_GZ_EF100_EV_TX_TIMESTAMP 0x2 |
689 | #define ESE_GZ_EF100_EV_TX_COMPLETION 0x1 |
690 | #define ESE_GZ_EF100_EV_RX_PKTS 0x0 |
691 | |
692 | /* Enum SF_EW_EVENT_TYPE */ |
693 | #define ESE_GZ_EF100_EWEV_VIRTQ_DESC 0x2 |
694 | #define ESE_GZ_EF100_EWEV_TXQ_DESC 0x1 |
695 | #define ESE_GZ_EF100_EWEV_64BIT 0x0 |
696 | |
697 | /* Enum TX_DESC_CSO_PARTIAL_EN */ |
698 | #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_TCP 2 |
699 | #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_UDP 1 |
700 | #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_OFF 0 |
701 | |
702 | /* Enum TX_DESC_CS_INNER_L3 */ |
703 | #define ESE_GZ_TX_DESC_CS_INNER_L3_GENEVE 3 |
704 | #define ESE_GZ_TX_DESC_CS_INNER_L3_NVGRE 2 |
705 | #define ESE_GZ_TX_DESC_CS_INNER_L3_VXLAN 1 |
706 | #define ESE_GZ_TX_DESC_CS_INNER_L3_OFF 0 |
707 | |
708 | /* Enum TX_DESC_IP4_ID */ |
709 | #define ESE_GZ_TX_DESC_IP4_ID_INC_MOD16 2 |
710 | #define ESE_GZ_TX_DESC_IP4_ID_INC_MOD15 1 |
711 | #define ESE_GZ_TX_DESC_IP4_ID_NO_OP 0 |
712 | |
713 | /* Enum VIRTIO_NET_HDR_F */ |
714 | #define ESE_GZ_NEEDS_CSUM 0x1 |
715 | |
716 | /* Enum VIRTIO_NET_HDR_GSO */ |
717 | #define ESE_GZ_TCPV6 0x4 |
718 | #define ESE_GZ_UDP 0x3 |
719 | #define ESE_GZ_TCPV4 0x1 |
720 | #define ESE_GZ_NONE 0x0 |
721 | /**************************************************************************/ |
722 | |
723 | #define ESF_GZ_EV_DEBUG_EVENT_GEN_FLAGS_LBN 44 |
724 | #define ESF_GZ_EV_DEBUG_EVENT_GEN_FLAGS_WIDTH 4 |
725 | #define ESF_GZ_EV_DEBUG_SRC_QID_LBN 32 |
726 | #define ESF_GZ_EV_DEBUG_SRC_QID_WIDTH 12 |
727 | #define ESF_GZ_EV_DEBUG_SEQ_NUM_LBN 16 |
728 | #define ESF_GZ_EV_DEBUG_SEQ_NUM_WIDTH 16 |
729 | |
730 | #endif /* EFX_EF100_REGS_H */ |
731 | |