1/* SPDX-License-Identifier: GPL-2.0-only */
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
6 */
7
8
9#ifndef MCDI_PCOL_H
10#define MCDI_PCOL_H
11
12/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
13/* Power-on reset state */
14#define MC_FW_STATE_POR (1)
15/* If this is set in MC_RESET_STATE_REG then it should be
16 * possible to jump into IMEM without loading code from flash. */
17#define MC_FW_WARM_BOOT_OK (2)
18/* The MC main image has started to boot. */
19#define MC_FW_STATE_BOOTING (4)
20/* The Scheduler has started. */
21#define MC_FW_STATE_SCHED (8)
22/* If this is set in MC_RESET_STATE_REG then it should be
23 * possible to jump into IMEM without loading code from flash.
24 * Unlike a warm boot, assume DMEM has been reloaded, so that
25 * the MC persistent data must be reinitialised. */
26#define MC_FW_TEPID_BOOT_OK (16)
27/* We have entered the main firmware via recovery mode. This
28 * means that MC persistent data must be reinitialised, but that
29 * we shouldn't touch PCIe config. */
30#define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)
31/* BIST state has been initialized */
32#define MC_FW_BIST_INIT_OK (128)
33
34/* Siena MC shared memmory offsets */
35/* The 'doorbell' addresses are hard-wired to alert the MC when written */
36#define MC_SMEM_P0_DOORBELL_OFST 0x000
37#define MC_SMEM_P1_DOORBELL_OFST 0x004
38/* The rest of these are firmware-defined */
39#define MC_SMEM_P0_PDU_OFST 0x008
40#define MC_SMEM_P1_PDU_OFST 0x108
41#define MC_SMEM_PDU_LEN 0x100
42#define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
43#define MC_SMEM_P0_STATUS_OFST 0x7f8
44#define MC_SMEM_P1_STATUS_OFST 0x7fc
45
46/* Values to be written to the per-port status dword in shared
47 * memory on reboot and assert */
48#define MC_STATUS_DWORD_REBOOT (0xb007b007)
49#define MC_STATUS_DWORD_ASSERT (0xdeaddead)
50
51/* Check whether an mcfw version (in host order) belongs to a bootloader */
52#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
53
54/* The current version of the MCDI protocol.
55 *
56 * Note that the ROM burnt into the card only talks V0, so at the very
57 * least every driver must support version 0 and MCDI_PCOL_VERSION
58 */
59#define MCDI_PCOL_VERSION 2
60
61/* Unused commands: 0x23, 0x27, 0x30, 0x31 */
62
63/* MCDI version 1
64 *
65 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
66 * structure, filled in by the client.
67 *
68 * 0 7 8 16 20 22 23 24 31
69 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
70 * | | |
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
74 *
75 * The client writes its request into MC shared memory, and rings the
76 * doorbell. Each request is completed either by the MC writing
77 * back into shared memory, or by writing out an event.
78 *
79 * All MCDI commands support completion by shared memory response. Each
80 * request may also contain additional data (accounted for by HEADER.LEN),
81 * and some responses may also contain additional data (again, accounted
82 * for by HEADER.LEN).
83 *
84 * Some MCDI commands support completion by event, in which any associated
85 * response data is included in the event.
86 *
87 * The protocol requires one response to be delivered for every request; a
88 * request should not be sent unless the response for the previous request
89 * has been received (either by polling shared memory, or by receiving
90 * an event).
91 */
92
93/** Request/Response structure */
94#define MCDI_HEADER_OFST 0
95#define MCDI_HEADER_CODE_LBN 0
96#define MCDI_HEADER_CODE_WIDTH 7
97#define MCDI_HEADER_RESYNC_LBN 7
98#define MCDI_HEADER_RESYNC_WIDTH 1
99#define MCDI_HEADER_DATALEN_LBN 8
100#define MCDI_HEADER_DATALEN_WIDTH 8
101#define MCDI_HEADER_SEQ_LBN 16
102#define MCDI_HEADER_SEQ_WIDTH 4
103#define MCDI_HEADER_RSVD_LBN 20
104#define MCDI_HEADER_RSVD_WIDTH 1
105#define MCDI_HEADER_NOT_EPOCH_LBN 21
106#define MCDI_HEADER_NOT_EPOCH_WIDTH 1
107#define MCDI_HEADER_ERROR_LBN 22
108#define MCDI_HEADER_ERROR_WIDTH 1
109#define MCDI_HEADER_RESPONSE_LBN 23
110#define MCDI_HEADER_RESPONSE_WIDTH 1
111#define MCDI_HEADER_XFLAGS_LBN 24
112#define MCDI_HEADER_XFLAGS_WIDTH 8
113/* Request response using event */
114#define MCDI_HEADER_XFLAGS_EVREQ 0x01
115/* Request (and signal) early doorbell return */
116#define MCDI_HEADER_XFLAGS_DBRET 0x02
117
118/* Maximum number of payload bytes */
119#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
120#define MCDI_CTL_SDU_LEN_MAX_V2 0x400
121
122#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
123
124
125/* The MC can generate events for two reasons:
126 * - To advance a shared memory request if XFLAGS_EVREQ was set
127 * - As a notification (link state, i2c event), controlled
128 * via MC_CMD_LOG_CTRL
129 *
130 * Both events share a common structure:
131 *
132 * 0 32 33 36 44 52 60
133 * | Data | Cont | Level | Src | Code | Rsvd |
134 * |
135 * \ There is another event pending in this notification
136 *
137 * If Code==CMDDONE, then the fields are further interpreted as:
138 *
139 * - LEVEL==INFO Command succeeded
140 * - LEVEL==ERR Command failed
141 *
142 * 0 8 16 24 32
143 * | Seq | Datalen | Errno | Rsvd |
144 *
145 * These fields are taken directly out of the standard MCDI header, i.e.,
146 * LEVEL==ERR, Datalen == 0 => Reboot
147 *
148 * Events can be squirted out of the UART (using LOG_CTRL) without a
149 * MCDI header. An event can be distinguished from a MCDI response by
150 * examining the first byte which is 0xc0. This corresponds to the
151 * non-existent MCDI command MC_CMD_DEBUG_LOG.
152 *
153 * 0 7 8
154 * | command | Resync | = 0xc0
155 *
156 * Since the event is written in big-endian byte order, this works
157 * providing bits 56-63 of the event are 0xc0.
158 *
159 * 56 60 63
160 * | Rsvd | Code | = 0xc0
161 *
162 * Which means for convenience the event code is 0xc for all MC
163 * generated events.
164 */
165#define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
166
167
168
169#define MC_CMD_ERR_CODE_OFST 0
170#define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
171
172/* We define 8 "escape" commands to allow
173 for command number space extension */
174
175#define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
176#define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
177#define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
178#define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
179#define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
180#define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
181#define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
182#define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
183
184/* Vectors in the boot ROM */
185/* Point to the copycode entry point. */
186#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
187#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
188#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
189/* Points to the recovery mode entry point. Misnamed but kept for compatibility. */
190#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
191#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
192#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
193/* Points to the recovery mode entry point. Same as above, but the right name. */
194#define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
195#define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
196#define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
197
198/* Points to noflash mode entry point. */
199#define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
200
201/* The command set exported by the boot ROM (MCDI v0) */
202#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \
203 (1 << MC_CMD_READ32) | \
204 (1 << MC_CMD_WRITE32) | \
205 (1 << MC_CMD_COPYCODE) | \
206 (1 << MC_CMD_GET_VERSION), \
207 0, 0, 0 }
208
209#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
210 (MC_CMD_SENSOR_ENTRY_OFST + (_x))
211
212#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \
213 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
214 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \
215 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
216
217#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \
218 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
219 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \
220 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
221
222#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \
223 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
224 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \
225 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
226
227/* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
228 * stack ID (which must be in the range 1-255) along with an EVB port ID.
229 */
230#define EVB_STACK_ID(n) (((n) & 0xff) << 16)
231
232
233/* Version 2 adds an optional argument to error returns: the errno value
234 * may be followed by the (0-based) number of the first argument that
235 * could not be processed.
236 */
237#define MC_CMD_ERR_ARG_OFST 4
238
239/* MC_CMD_ERR enum: Public MCDI error codes. Error codes that correspond to
240 * POSIX errnos should use the same numeric values that linux does. Error codes
241 * specific to Solarflare firmware should use values in the range 0x1000 -
242 * 0x10ff. The range 0x2000 - 0x20ff is reserved for private error codes (see
243 * MC_CMD_ERR_PRIV below).
244 */
245/* enum: Operation not permitted. */
246#define MC_CMD_ERR_EPERM 0x1
247/* enum: Non-existent command target */
248#define MC_CMD_ERR_ENOENT 0x2
249/* enum: assert() has killed the MC */
250#define MC_CMD_ERR_EINTR 0x4
251/* enum: I/O failure */
252#define MC_CMD_ERR_EIO 0x5
253/* enum: Already exists */
254#define MC_CMD_ERR_EEXIST 0x6
255/* enum: Try again */
256#define MC_CMD_ERR_EAGAIN 0xb
257/* enum: Out of memory */
258#define MC_CMD_ERR_ENOMEM 0xc
259/* enum: Caller does not hold required locks */
260#define MC_CMD_ERR_EACCES 0xd
261/* enum: Resource is currently unavailable (e.g. lock contention) */
262#define MC_CMD_ERR_EBUSY 0x10
263/* enum: No such device */
264#define MC_CMD_ERR_ENODEV 0x13
265/* enum: Invalid argument to target */
266#define MC_CMD_ERR_EINVAL 0x16
267/* enum: No space */
268#define MC_CMD_ERR_ENOSPC 0x1c
269/* enum: Read-only */
270#define MC_CMD_ERR_EROFS 0x1e
271/* enum: Broken pipe */
272#define MC_CMD_ERR_EPIPE 0x20
273/* enum: Out of range */
274#define MC_CMD_ERR_ERANGE 0x22
275/* enum: Non-recursive resource is already acquired */
276#define MC_CMD_ERR_EDEADLK 0x23
277/* enum: Operation not implemented */
278#define MC_CMD_ERR_ENOSYS 0x26
279/* enum: Operation timed out */
280#define MC_CMD_ERR_ETIME 0x3e
281/* enum: Link has been severed */
282#define MC_CMD_ERR_ENOLINK 0x43
283/* enum: Protocol error */
284#define MC_CMD_ERR_EPROTO 0x47
285/* enum: Bad message */
286#define MC_CMD_ERR_EBADMSG 0x4a
287/* enum: Operation not supported */
288#define MC_CMD_ERR_ENOTSUP 0x5f
289/* enum: Address not available */
290#define MC_CMD_ERR_EADDRNOTAVAIL 0x63
291/* enum: Not connected */
292#define MC_CMD_ERR_ENOTCONN 0x6b
293/* enum: Operation already in progress */
294#define MC_CMD_ERR_EALREADY 0x72
295/* enum: Stale handle. The handle references a resource that no longer exists.
296 */
297#define MC_CMD_ERR_ESTALE 0x74
298/* enum: Resource allocation failed. */
299#define MC_CMD_ERR_ALLOC_FAIL 0x1000
300/* enum: V-adaptor not found. */
301#define MC_CMD_ERR_NO_VADAPTOR 0x1001
302/* enum: EVB port not found. */
303#define MC_CMD_ERR_NO_EVB_PORT 0x1002
304/* enum: V-switch not found. */
305#define MC_CMD_ERR_NO_VSWITCH 0x1003
306/* enum: Too many VLAN tags. */
307#define MC_CMD_ERR_VLAN_LIMIT 0x1004
308/* enum: Bad PCI function number. */
309#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
310/* enum: Invalid VLAN mode. */
311#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
312/* enum: Invalid v-switch type. */
313#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
314/* enum: Invalid v-port type. */
315#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
316/* enum: MAC address exists. */
317#define MC_CMD_ERR_MAC_EXIST 0x1009
318/* enum: Slave core not present */
319#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
320/* enum: The datapath is disabled. */
321#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
322/* enum: The requesting client is not a function */
323#define MC_CMD_ERR_CLIENT_NOT_FN 0x100c
324/* enum: The requested operation might require the command to be passed between
325 * MCs, and the transport doesn't support that. Should only ever been seen over
326 * the UART.
327 */
328#define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
329/* enum: VLAN tag(s) exists */
330#define MC_CMD_ERR_VLAN_EXIST 0x100e
331/* enum: No MAC address assigned to an EVB port */
332#define MC_CMD_ERR_NO_MAC_ADDR 0x100f
333/* enum: Notifies the driver that the request has been relayed to an admin
334 * function for authorization. The driver should wait for a PROXY_RESPONSE
335 * event and then resend its request. This error code is followed by a 32-bit
336 * handle that helps matching it with the respective PROXY_RESPONSE event.
337 */
338#define MC_CMD_ERR_PROXY_PENDING 0x1010
339/* enum: The request cannot be passed for authorization because another request
340 * from the same function is currently being authorized. The drvier should try
341 * again later.
342 */
343#define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
344/* enum: Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function
345 * that has enabled proxying or BLOCK_INDEX points to a function that doesn't
346 * await an authorization.
347 */
348#define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
349/* enum: This code is currently only used internally in FW. Its meaning is that
350 * an operation failed due to lack of SR-IOV privilege. Normally it is
351 * translated to EPERM by send_cmd_err(), but it may also be used to trigger
352 * some special mechanism for handling such case, e.g. to relay the failed
353 * request to a designated admin function for authorization.
354 */
355#define MC_CMD_ERR_NO_PRIVILEGE 0x1013
356/* enum: Workaround 26807 could not be turned on/off because some functions
357 * have already installed filters. See the comment at
358 * MC_CMD_WORKAROUND_BUG26807. May also returned for other operations such as
359 * sub-variant switching.
360 */
361#define MC_CMD_ERR_FILTERS_PRESENT 0x1014
362/* enum: The clock whose frequency you've attempted to set doesn't exist on
363 * this NIC
364 */
365#define MC_CMD_ERR_NO_CLOCK 0x1015
366/* enum: Returned by MC_CMD_TESTASSERT if the action that should have caused an
367 * assertion failed to do so.
368 */
369#define MC_CMD_ERR_UNREACHABLE 0x1016
370/* enum: This command needs to be processed in the background but there were no
371 * resources to do so. Send it again after a command has completed.
372 */
373#define MC_CMD_ERR_QUEUE_FULL 0x1017
374/* enum: The operation could not be completed because the PCIe link has gone
375 * away. This error code is never expected to be returned over the TLP
376 * transport.
377 */
378#define MC_CMD_ERR_NO_PCIE 0x1018
379/* enum: The operation could not be completed because the datapath has gone
380 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
381 * datapath absence may be temporary
382 */
383#define MC_CMD_ERR_NO_DATAPATH 0x1019
384/* enum: The operation could not complete because some VIs are allocated */
385#define MC_CMD_ERR_VIS_PRESENT 0x101a
386/* enum: The operation could not complete because some PIO buffers are
387 * allocated
388 */
389#define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
390
391/* PCIE_INTERFACE enum: From EF100 onwards, SFC products can have multiple PCIe
392 * interfaces. There is a need to refer to interfaces explicitly from drivers
393 * (for example, a management driver on one interface administering a function
394 * on another interface). This enumeration provides stable identifiers to all
395 * interfaces present on a product. Product documentation will specify which
396 * interfaces exist and their associated identifier. In general, drivers,
397 * should not assign special meanings to specific values. Instead, behaviour
398 * should be determined by NIC configuration, which will identify interfaces
399 * where appropriate.
400 */
401/* enum: Primary host interfaces. Typically (i.e. for all known SFC products)
402 * the interface exposed on the edge connector (or form factor equivalent).
403 */
404#define PCIE_INTERFACE_HOST_PRIMARY 0x0
405/* enum: Riverhead and keystone products have a second PCIe interface to which
406 * an on-NIC ARM module is expected to be connected.
407 */
408#define PCIE_INTERFACE_NIC_EMBEDDED 0x1
409/* enum: The PCIe logical interface 0. It is an alias for HOST_PRIMARY. */
410#define PCIE_INTERFACE_PCIE_HOST_INTF_0 0x0
411/* enum: The PCIe logical interface 1. */
412#define PCIE_INTERFACE_PCIE_HOST_INTF_1 0x2
413/* enum: The PCIe logical interface 2. */
414#define PCIE_INTERFACE_PCIE_HOST_INTF_2 0x3
415/* enum: The PCIe logical interface 3. */
416#define PCIE_INTERFACE_PCIE_HOST_INTF_3 0x4
417/* enum: For MCDI commands issued over a PCIe interface, this value is
418 * translated into the interface over which the command was issued. Not
419 * meaningful for other MCDI transports.
420 */
421#define PCIE_INTERFACE_CALLER 0xffffffff
422
423/* MC_CLIENT_ID_SPECIFIER enum */
424/* enum: Equivalent to the caller's client ID */
425#define MC_CMD_CLIENT_ID_SELF 0xffffffff
426
427/* MAE_FIELD_SUPPORT_STATUS enum */
428/* enum: The NIC does not support this field. The driver must ensure that any
429 * mask associated with this field in a match rule is zeroed. The NIC may
430 * either reject requests with an invalid mask for such a field, or may assume
431 * that the mask is zero. (This category only exists to describe behaviour for
432 * fields that a newer driver might know about but that older firmware does
433 * not. It is recommended that firmware report MAE_FIELD_FIELD_MATCH_NEVER for
434 * all match fields defined at the time of its compilation. If a driver see a
435 * field support status value that it does not recognise, it must treat that
436 * field as thought the field was reported as MAE_FIELD_SUPPORTED_MATCH_NEVER,
437 * and must never set a non-zero mask value for this field.
438 */
439#define MAE_FIELD_UNSUPPORTED 0x0
440/* enum: The NIC supports this field, but cannot use it in a match rule. The
441 * driver must ensure that any mask for such a field in a match rule is zeroed.
442 * The NIC will reject requests with an invalid mask for such a field.
443 */
444#define MAE_FIELD_SUPPORTED_MATCH_NEVER 0x1
445/* enum: The NIC supports this field, and must use it in all match rules. The
446 * driver must ensure that any mask for such a field is all ones. The NIC will
447 * reject requests with an invalid mask for such a field.
448 */
449#define MAE_FIELD_SUPPORTED_MATCH_ALWAYS 0x2
450/* enum: The NIC supports this field, and may optionally use it in match rules.
451 * The driver must ensure that any mask for such a field is either all zeroes
452 * or all ones. The NIC will reject requests with an invalid mask for such a
453 * field.
454 */
455#define MAE_FIELD_SUPPORTED_MATCH_OPTIONAL 0x3
456/* enum: The NIC supports this field, and may optionally use it in match rules.
457 * The driver must ensure that any mask for such a field is either all zeroes
458 * or a consecutive set of ones following by all zeroes (starting from MSB).
459 * The NIC will reject requests with an invalid mask for such a field.
460 */
461#define MAE_FIELD_SUPPORTED_MATCH_PREFIX 0x4
462/* enum: The NIC supports this field, and may optionally use it in match rules.
463 * The driver may provide an arbitrary mask for such a field.
464 */
465#define MAE_FIELD_SUPPORTED_MATCH_MASK 0x5
466
467/* MAE_CT_VNI_MODE enum: Controls the layout of the VNI input to the conntrack
468 * lookup. (Values are not arbitrary - constrained by table access ABI.)
469 */
470/* enum: The VNI input to the conntrack lookup will be zero. */
471#define MAE_CT_VNI_MODE_ZERO 0x0
472/* enum: The VNI input to the conntrack lookup will be the VNI (VXLAN/Geneve)
473 * or VSID (NVGRE) field from the packet.
474 */
475#define MAE_CT_VNI_MODE_VNI 0x1
476/* enum: The VNI input to the conntrack lookup will be the VLAN ID from the
477 * outermost VLAN tag (in bottom 12 bits; top 12 bits zero).
478 */
479#define MAE_CT_VNI_MODE_1VLAN 0x2
480/* enum: The VNI input to the conntrack lookup will be the VLAN IDs from both
481 * VLAN tags (outermost in bottom 12 bits, innermost in top 12 bits).
482 */
483#define MAE_CT_VNI_MODE_2VLAN 0x3
484
485/* MAE_FIELD enum: NB: this enum shares namespace with the support status enum.
486 */
487/* enum: Source mport upon entering the MAE. */
488#define MAE_FIELD_INGRESS_PORT 0x0
489#define MAE_FIELD_MARK 0x1 /* enum */
490/* enum: Table ID used in action rule. Initially zero, can be changed in action
491 * rule response.
492 */
493#define MAE_FIELD_RECIRC_ID 0x2
494#define MAE_FIELD_IS_IP_FRAG 0x3 /* enum */
495#define MAE_FIELD_DO_CT 0x4 /* enum */
496#define MAE_FIELD_CT_HIT 0x5 /* enum */
497/* enum: Undefined unless CT_HIT=1. */
498#define MAE_FIELD_CT_MARK 0x6
499/* enum: Undefined unless DO_CT=1. */
500#define MAE_FIELD_CT_DOMAIN 0x7
501/* enum: Undefined unless CT_HIT=1. */
502#define MAE_FIELD_CT_PRIVATE_FLAGS 0x8
503/* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */
504#define MAE_FIELD_IS_FROM_NETWORK 0x9
505/* enum: 1 if the packet has 1 or more VLAN tags, else 0. */
506#define MAE_FIELD_HAS_OVLAN 0xa
507/* enum: 1 if the packet has 2 or more VLAN tags, else 0. */
508#define MAE_FIELD_HAS_IVLAN 0xb
509/* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present
510 * when encap
511 */
512#define MAE_FIELD_ENC_HAS_OVLAN 0xc
513/* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present
514 * when encap
515 */
516#define MAE_FIELD_ENC_HAS_IVLAN 0xd
517/* enum: Packet is IP fragment */
518#define MAE_FIELD_ENC_IP_FRAG 0xe
519#define MAE_FIELD_ETHER_TYPE 0x21 /* enum */
520#define MAE_FIELD_VLAN0_TCI 0x22 /* enum */
521#define MAE_FIELD_VLAN0_PROTO 0x23 /* enum */
522#define MAE_FIELD_VLAN1_TCI 0x24 /* enum */
523#define MAE_FIELD_VLAN1_PROTO 0x25 /* enum */
524/* enum: Inner when encap */
525#define MAE_FIELD_ETH_SADDR 0x28
526/* enum: Inner when encap */
527#define MAE_FIELD_ETH_DADDR 0x29
528/* enum: Inner when encap. NB: IPv4 and IPv6 fields are mutually exclusive. */
529#define MAE_FIELD_SRC_IP4 0x2a
530/* enum: Inner when encap */
531#define MAE_FIELD_SRC_IP6 0x2b
532/* enum: Inner when encap */
533#define MAE_FIELD_DST_IP4 0x2c
534/* enum: Inner when encap */
535#define MAE_FIELD_DST_IP6 0x2d
536/* enum: Inner when encap */
537#define MAE_FIELD_IP_PROTO 0x2e
538/* enum: Inner when encap */
539#define MAE_FIELD_IP_TOS 0x2f
540/* enum: Inner when encap */
541#define MAE_FIELD_IP_TTL 0x30
542/* enum: Inner when encap TODO: how this is defined? The raw flags +
543 * frag_offset from the packet, or some derived value more amenable to ternary
544 * matching? TODO: there was a proposal for driver-allocation fields. The
545 * driver would provide some instruction for how to extract given field values,
546 * and would be given a field id in return. It could then use that field id in
547 * its matches. This feels like it would be extremely hard to implement in
548 * hardware, but I mention it for completeness.
549 */
550#define MAE_FIELD_IP_FLAGS 0x31
551/* enum: Ports (UDP, TCP) Inner when encap */
552#define MAE_FIELD_L4_SPORT 0x32
553/* enum: Ports (UDP, TCP) Inner when encap */
554#define MAE_FIELD_L4_DPORT 0x33
555/* enum: Inner when encap */
556#define MAE_FIELD_TCP_FLAGS 0x34
557/* enum: TCP packet with any of SYN, FIN or RST flag set */
558#define MAE_FIELD_TCP_SYN_FIN_RST 0x35
559/* enum: Packet is IP fragment with fragment offset 0 */
560#define MAE_FIELD_IP_FIRST_FRAG 0x36
561/* enum: The type of encapsulated used for this packet. Value as per
562 * ENCAP_TYPE_*.
563 */
564#define MAE_FIELD_ENCAP_TYPE 0x3f
565/* enum: The ID of the outer rule that marked this packet as encapsulated.
566 * Useful for implicitly matching on outer fields.
567 */
568#define MAE_FIELD_OUTER_RULE_ID 0x40
569/* enum: Outer; only present when encap */
570#define MAE_FIELD_ENC_ETHER_TYPE 0x41
571/* enum: Outer; only present when encap */
572#define MAE_FIELD_ENC_VLAN0_TCI 0x42
573/* enum: Outer; only present when encap */
574#define MAE_FIELD_ENC_VLAN0_PROTO 0x43
575/* enum: Outer; only present when encap */
576#define MAE_FIELD_ENC_VLAN1_TCI 0x44
577/* enum: Outer; only present when encap */
578#define MAE_FIELD_ENC_VLAN1_PROTO 0x45
579/* enum: Outer; only present when encap */
580#define MAE_FIELD_ENC_ETH_SADDR 0x48
581/* enum: Outer; only present when encap */
582#define MAE_FIELD_ENC_ETH_DADDR 0x49
583/* enum: Outer; only present when encap */
584#define MAE_FIELD_ENC_SRC_IP4 0x4a
585/* enum: Outer; only present when encap */
586#define MAE_FIELD_ENC_SRC_IP6 0x4b
587/* enum: Outer; only present when encap */
588#define MAE_FIELD_ENC_DST_IP4 0x4c
589/* enum: Outer; only present when encap */
590#define MAE_FIELD_ENC_DST_IP6 0x4d
591/* enum: Outer; only present when encap */
592#define MAE_FIELD_ENC_IP_PROTO 0x4e
593/* enum: Outer; only present when encap */
594#define MAE_FIELD_ENC_IP_TOS 0x4f
595/* enum: Outer; only present when encap */
596#define MAE_FIELD_ENC_IP_TTL 0x50
597/* enum: Outer; only present when encap */
598#define MAE_FIELD_ENC_IP_FLAGS 0x51
599/* enum: Outer; only present when encap */
600#define MAE_FIELD_ENC_L4_SPORT 0x52
601/* enum: Outer; only present when encap */
602#define MAE_FIELD_ENC_L4_DPORT 0x53
603/* enum: VNI (when VXLAN or GENEVE) VSID (when NVGRE) Bottom 24 bits of Key
604 * (when L2GRE) Outer; only present when encap
605 */
606#define MAE_FIELD_ENC_VNET_ID 0x54
607
608/* MAE_MCDI_ENCAP_TYPE enum: Encapsulation type. Defines how the payload will
609 * be parsed to an inner frame. Other values are reserved. Unknown values
610 * should be treated same as NONE. (Values are not arbitrary - constrained by
611 * table access ABI.)
612 */
613#define MAE_MCDI_ENCAP_TYPE_NONE 0x0 /* enum */
614/* enum: Don't assume enum aligns with support bitmask... */
615#define MAE_MCDI_ENCAP_TYPE_VXLAN 0x1
616#define MAE_MCDI_ENCAP_TYPE_NVGRE 0x2 /* enum */
617#define MAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */
618#define MAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */
619
620/* MAE_MPORT_END enum: Selects which end of the logical link identified by an
621 * MPORT_SELECTOR is targeted by an operation.
622 */
623/* enum: Selects the port on the MAE virtual switch */
624#define MAE_MPORT_END_MAE 0x1
625/* enum: Selects the virtual NIC plugged into the MAE switch */
626#define MAE_MPORT_END_VNIC 0x2
627
628/* MAE_COUNTER_TYPE enum: The datapath maintains several sets of counters, each
629 * being associated with a different table. Note that the same counter ID may
630 * be allocated by different counter blocks, so e.g. AR counter 42 is different
631 * from CT counter 42. Generation counts are also type-specific. This value is
632 * also present in the header of streaming counter packets, in the IDENTIFIER
633 * field (see packetiser packet format definitions). Also note that LACP
634 * counter IDs are not allocated individually, instead the counter IDs are
635 * directly tied to the LACP balance table indices. These in turn are allocated
636 * in large contiguous blocks as a LAG config. Calling MAE_COUNTER_ALLOC/FREE
637 * with an LACP counter type will return EPERM.
638 */
639/* enum: Action Rule counters - can be referenced in AR response. */
640#define MAE_COUNTER_TYPE_AR 0x0
641/* enum: Conntrack counters - can be referenced in CT response. */
642#define MAE_COUNTER_TYPE_CT 0x1
643/* enum: Outer Rule counters - can be referenced in OR response. */
644#define MAE_COUNTER_TYPE_OR 0x2
645/* enum: LACP counters - linked to LACP balance table entries. */
646#define MAE_COUNTER_TYPE_LACP 0x3
647
648/* MAE_COUNTER_ID enum: ID of allocated counter or counter list. */
649/* enum: A counter ID that is guaranteed never to represent a real counter or
650 * counter list.
651 */
652#define MAE_COUNTER_ID_NULL 0xffffffff
653
654/* TABLE_ID enum: Unique IDs for tables. The 32-bit ID values have been
655 * structured with bits [31:24] reserved (0), [23:16] indicating which major
656 * block the tables belongs to (0=VNIC TX, none currently; 1=MAE; 2=VNIC RX),
657 * [15:8] a unique ID within the block, and [7:0] reserved for future
658 * variations of the same table. (All of the tables currently defined within
659 * the streaming engines are listed here, but this does not imply that they are
660 * all supported - MC_CMD_TABLE_LIST returns the list of actually supported
661 * tables.) The DPU offload engines' enumerators follow a deliberate pattern:
662 * 0x01010000 + is_dpu_net * 0x10000 + is_wr_or_tx * 0x8000 + is_lite_pipe *
663 * 0x1000 + oe_engine_type * 0x100 + oe_instance_within_pipe * 0x10
664 */
665/* enum: Outer_Rule_Table in the MAE - refer to SF-123102-TC. */
666#define TABLE_ID_OUTER_RULE_TABLE 0x10000
667/* enum: Outer_Rule_No_CT_Table in the MAE - refer to SF-123102-TC. */
668#define TABLE_ID_OUTER_RULE_NO_CT_TABLE 0x10100
669/* enum: Mgmt_Filter_Table in the MAE - refer to SF-123102-TC. */
670#define TABLE_ID_MGMT_FILTER_TABLE 0x10200
671/* enum: Conntrack_Table in the MAE - refer to SF-123102-TC. */
672#define TABLE_ID_CONNTRACK_TABLE 0x10300
673/* enum: Action_Rule_Table in the MAE - refer to SF-123102-TC. */
674#define TABLE_ID_ACTION_RULE_TABLE 0x10400
675/* enum: Mgroup_Default_Action_Set_Table in the MAE - refer to SF-123102-TC. */
676#define TABLE_ID_MGROUP_DEFAULT_ACTION_SET_TABLE 0x10500
677/* enum: Encap_Hdr_Part1_Table in the MAE - refer to SF-123102-TC. */
678#define TABLE_ID_ENCAP_HDR_PART1_TABLE 0x10600
679/* enum: Encap_Hdr_Part2_Table in the MAE - refer to SF-123102-TC. */
680#define TABLE_ID_ENCAP_HDR_PART2_TABLE 0x10700
681/* enum: Replace_Src_MAC_Table in the MAE - refer to SF-123102-TC. */
682#define TABLE_ID_REPLACE_SRC_MAC_TABLE 0x10800
683/* enum: Replace_Dst_MAC_Table in the MAE - refer to SF-123102-TC. */
684#define TABLE_ID_REPLACE_DST_MAC_TABLE 0x10900
685/* enum: Dst_Mport_VC_Table in the MAE - refer to SF-123102-TC. */
686#define TABLE_ID_DST_MPORT_VC_TABLE 0x10a00
687/* enum: LACP_LAG_Config_Table in the MAE - refer to SF-123102-TC. */
688#define TABLE_ID_LACP_LAG_CONFIG_TABLE 0x10b00
689/* enum: LACP_Balance_Table in the MAE - refer to SF-123102-TC. */
690#define TABLE_ID_LACP_BALANCE_TABLE 0x10c00
691/* enum: Dst_Mport_Host_Chan_Table in the MAE - refer to SF-123102-TC. */
692#define TABLE_ID_DST_MPORT_HOST_CHAN_TABLE 0x10d00
693/* enum: VNIC_Rx_Encap_Table in VNIC Rx - refer to SF-123102-TC. */
694#define TABLE_ID_VNIC_RX_ENCAP_TABLE 0x20000
695/* enum: Steering_Table in VNIC Rx - refer to SF-123102-TC. */
696#define TABLE_ID_STEERING_TABLE 0x20100
697/* enum: RSS_Context_Table in VNIC Rx - refer to SF-123102-TC. */
698#define TABLE_ID_RSS_CONTEXT_TABLE 0x20200
699/* enum: Indirection_Table in VNIC Rx - refer to SF-123102-TC. */
700#define TABLE_ID_INDIRECTION_TABLE 0x20300
701/* enum: DPU.host read pipe first CRC offload engine profiles - refer to
702 * XN-200147-AN.
703 */
704#define TABLE_ID_DPU_HOST_RD_CRC0_OE_PROFILE 0x1010000
705/* enum: DPU.host read pipe second CRC offload engine profiles - refer to
706 * XN-200147-AN.
707 */
708#define TABLE_ID_DPU_HOST_RD_CRC1_OE_PROFILE 0x1010010
709/* enum: DPU.host write pipe first CRC offload engine profiles - refer to
710 * XN-200147-AN.
711 */
712#define TABLE_ID_DPU_HOST_WR_CRC0_OE_PROFILE 0x1018000
713/* enum: DPU.host write pipe second CRC offload engine profiles - refer to
714 * XN-200147-AN.
715 */
716#define TABLE_ID_DPU_HOST_WR_CRC1_OE_PROFILE 0x1018010
717/* enum: DPU.net 'full' receive pipe CRC offload engine profiles - refer to
718 * XN-200147-AN.
719 */
720#define TABLE_ID_DPU_NET_RX_CRC0_OE_PROFILE 0x1020000
721/* enum: DPU.net 'full' receive pipe first checksum offload engine profiles -
722 * refer to XN-200147-AN.
723 */
724#define TABLE_ID_DPU_NET_RX_CSUM0_OE_PROFILE 0x1020100
725/* enum: DPU.net 'full' receive pipe second checksum offload engine profiles -
726 * refer to XN-200147-AN.
727 */
728#define TABLE_ID_DPU_NET_RX_CSUM1_OE_PROFILE 0x1020110
729/* enum: DPU.net 'full' receive pipe AES-GCM offload engine profiles - refer to
730 * XN-200147-AN.
731 */
732#define TABLE_ID_DPU_NET_RX_AES_GCM0_OE_PROFILE 0x1020200
733/* enum: DPU.net 'lite' receive pipe CRC offload engine profiles - refer to
734 * XN-200147-AN.
735 */
736#define TABLE_ID_DPU_NET_RXLITE_CRC0_OE_PROFILE 0x1021000
737/* enum: DPU.net 'lite' receive pipe checksum offload engine profiles - refer
738 * to XN-200147-AN.
739 */
740#define TABLE_ID_DPU_NET_RXLITE_CSUM0_OE_PROFILE 0x1021100
741/* enum: DPU.net 'full' transmit pipe CRC offload engine profiles - refer to
742 * XN-200147-AN.
743 */
744#define TABLE_ID_DPU_NET_TX_CRC0_OE_PROFILE 0x1028000
745/* enum: DPU.net 'full' transmit pipe first checksum offload engine profiles -
746 * refer to XN-200147-AN.
747 */
748#define TABLE_ID_DPU_NET_TX_CSUM0_OE_PROFILE 0x1028100
749/* enum: DPU.net 'full' transmit pipe second checksum offload engine profiles -
750 * refer to XN-200147-AN.
751 */
752#define TABLE_ID_DPU_NET_TX_CSUM1_OE_PROFILE 0x1028110
753/* enum: DPU.net 'full' transmit pipe AES-GCM offload engine profiles - refer
754 * to XN-200147-AN.
755 */
756#define TABLE_ID_DPU_NET_TX_AES_GCM0_OE_PROFILE 0x1028200
757/* enum: DPU.net 'lite' transmit pipe CRC offload engine profiles - refer to
758 * XN-200147-AN.
759 */
760#define TABLE_ID_DPU_NET_TXLITE_CRC0_OE_PROFILE 0x1029000
761/* enum: DPU.net 'lite' transmit pipe checksum offload engine profiles - refer
762 * to XN-200147-AN.
763 */
764#define TABLE_ID_DPU_NET_TXLITE_CSUM0_OE_PROFILE 0x1029100
765
766/* TABLE_FIELD_ID enum: Unique IDs for fields. Related concepts have been
767 * loosely grouped together into blocks with gaps for expansion, but the values
768 * are arbitrary. Field IDs are not specific to particular tables, and in some
769 * cases this sharing means that they are not used with the exact names of the
770 * corresponding table definitions in SF-123102-TC; however, the mapping should
771 * still be clear. The intent is that a list of fields, with their associated
772 * bit widths and semantics version code, unambiguously defines the semantics
773 * of the fields in a key or response. (Again, this list includes all of the
774 * fields currently defined within the streaming engines, but only a subset may
775 * actually be used by the supported list of tables.)
776 */
777/* enum: May appear multiple times within a key or response, and indicates that
778 * the field is unused and should be set to 0 (or masked out if permitted by
779 * the MASK_VALUE for this field).
780 */
781#define TABLE_FIELD_ID_UNUSED 0x0
782/* enum: Source m-port (a full m-port label). */
783#define TABLE_FIELD_ID_SRC_MPORT 0x1
784/* enum: Destination m-port (a full m-port label). */
785#define TABLE_FIELD_ID_DST_MPORT 0x2
786/* enum: Source m-group ID. */
787#define TABLE_FIELD_ID_SRC_MGROUP_ID 0x3
788/* enum: Physical network port ID (or m-port ID; same thing, for physical
789 * network ports).
790 */
791#define TABLE_FIELD_ID_NETWORK_PORT_ID 0x4
792/* enum: True if packet arrived via network port, false if it arrived via host.
793 */
794#define TABLE_FIELD_ID_IS_FROM_NETWORK 0x5
795/* enum: Full virtual channel from capsule header. */
796#define TABLE_FIELD_ID_CH_VC 0x6
797/* enum: Low bits of virtual channel from capsule header. */
798#define TABLE_FIELD_ID_CH_VC_LOW 0x7
799/* enum: User mark value in metadata and packet prefix. */
800#define TABLE_FIELD_ID_USER_MARK 0x8
801/* enum: User flag value in metadata and packet prefix. */
802#define TABLE_FIELD_ID_USER_FLAG 0x9
803/* enum: Counter ID associated with a response. All-bits-1 is a null value to
804 * suppress counting.
805 */
806#define TABLE_FIELD_ID_COUNTER_ID 0xa
807/* enum: Discriminator which may be set by plugins in some lookup keys; this
808 * allows plugins to make a reinterpretation of packet fields in these keys
809 * without clashing with the normal interpretation.
810 */
811#define TABLE_FIELD_ID_DISCRIM 0xb
812/* enum: Destination MAC address. The mapping from bytes in a frame to the
813 * 48-bit value for this field is in network order, i.e. a MAC address of
814 * AA:BB:CC:DD:EE:FF becomes a 48-bit value of 0xAABBCCDDEEFF.
815 */
816#define TABLE_FIELD_ID_DST_MAC 0x14
817/* enum: Source MAC address (see notes for DST_MAC). */
818#define TABLE_FIELD_ID_SRC_MAC 0x15
819/* enum: Outer VLAN tag TPID, compressed to an enumeration. */
820#define TABLE_FIELD_ID_OVLAN_TPID_COMPRESSED 0x16
821/* enum: Full outer VLAN tag TCI (16 bits). */
822#define TABLE_FIELD_ID_OVLAN 0x17
823/* enum: Outer VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
824#define TABLE_FIELD_ID_OVLAN_VID 0x18
825/* enum: Inner VLAN tag TPID, compressed to an enumeration. */
826#define TABLE_FIELD_ID_IVLAN_TPID_COMPRESSED 0x19
827/* enum: Full inner VLAN tag TCI (16 bits). */
828#define TABLE_FIELD_ID_IVLAN 0x1a
829/* enum: Inner VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
830#define TABLE_FIELD_ID_IVLAN_VID 0x1b
831/* enum: Ethertype. */
832#define TABLE_FIELD_ID_ETHER_TYPE 0x1c
833/* enum: Source IP address, either IPv4 or IPv6. The mapping from bytes in a
834 * frame to the 128-bit value for this field is in network order, with IPv4
835 * addresses assumed to have 12 bytes of trailing zeroes. i.e. the IPv6 address
836 * [2345::6789:ABCD] is 0x2345000000000000000000006789ABCD; the IPv4 address
837 * 192.168.1.2 is 0xC0A80102000000000000000000000000.
838 */
839#define TABLE_FIELD_ID_SRC_IP 0x1d
840/* enum: Destination IP address (see notes for SRC_IP). */
841#define TABLE_FIELD_ID_DST_IP 0x1e
842/* enum: IPv4 Type-of-Service or IPv6 Traffic Class field. */
843#define TABLE_FIELD_ID_IP_TOS 0x1f
844/* enum: IP Protocol. */
845#define TABLE_FIELD_ID_IP_PROTO 0x20
846/* enum: Layer 4 source port. */
847#define TABLE_FIELD_ID_SRC_PORT 0x21
848/* enum: Layer 4 destination port. */
849#define TABLE_FIELD_ID_DST_PORT 0x22
850/* enum: TCP flags. */
851#define TABLE_FIELD_ID_TCP_FLAGS 0x23
852/* enum: Virtual Network Identifier (VXLAN) or Virtual Session ID (NVGRE). */
853#define TABLE_FIELD_ID_VNI 0x24
854/* enum: True if packet has any tunnel encapsulation header. */
855#define TABLE_FIELD_ID_HAS_ENCAP 0x32
856/* enum: True if encap header has an outer VLAN tag. */
857#define TABLE_FIELD_ID_HAS_ENC_OVLAN 0x33
858/* enum: True if encap header has an inner VLAN tag. */
859#define TABLE_FIELD_ID_HAS_ENC_IVLAN 0x34
860/* enum: True if encap header is some sort of IP. */
861#define TABLE_FIELD_ID_HAS_ENC_IP 0x35
862/* enum: True if encap header is specifically IPv4. */
863#define TABLE_FIELD_ID_HAS_ENC_IP4 0x36
864/* enum: True if encap header is UDP. */
865#define TABLE_FIELD_ID_HAS_ENC_UDP 0x37
866/* enum: True if only/inner frame has an outer VLAN tag. */
867#define TABLE_FIELD_ID_HAS_OVLAN 0x38
868/* enum: True if only/inner frame has an inner VLAN tag. */
869#define TABLE_FIELD_ID_HAS_IVLAN 0x39
870/* enum: True if only/inner frame is some sort of IP. */
871#define TABLE_FIELD_ID_HAS_IP 0x3a
872/* enum: True if only/inner frame has a recognised L4 IP protocol (TCP or UDP).
873 */
874#define TABLE_FIELD_ID_HAS_L4 0x3b
875/* enum: True if only/inner frame is an IP fragment. */
876#define TABLE_FIELD_ID_IP_FRAG 0x3c
877/* enum: True if only/inner frame is the first IP fragment (fragment offset 0).
878 */
879#define TABLE_FIELD_ID_IP_FIRST_FRAG 0x3d
880/* enum: True if only/inner frame has an IP Time-To-Live of <= 1. (Note: the
881 * implementation calls this "ip_ttl_is_one" but does in fact match packets
882 * with TTL=0 - which we shouldn't be seeing! - as well.)
883 */
884#define TABLE_FIELD_ID_IP_TTL_LE_ONE 0x3e
885/* enum: True if only/inner frame has any of TCP SYN, FIN or RST flags set. */
886#define TABLE_FIELD_ID_TCP_INTERESTING_FLAGS 0x3f
887/* enum: Plugin channel selection. */
888#define TABLE_FIELD_ID_RDP_PL_CHAN 0x50
889/* enum: Enable update of CH_ROUTE_RDP_C_PL route bit. */
890#define TABLE_FIELD_ID_RDP_C_PL_EN 0x51
891/* enum: New value of CH_ROUTE_RDP_C_PL route bit. */
892#define TABLE_FIELD_ID_RDP_C_PL 0x52
893/* enum: Enable update of CH_ROUTE_RDP_D_PL route bit. */
894#define TABLE_FIELD_ID_RDP_D_PL_EN 0x53
895/* enum: New value of CH_ROUTE_RDP_D_PL route bit. */
896#define TABLE_FIELD_ID_RDP_D_PL 0x54
897/* enum: Enable update of CH_ROUTE_RDP_OUT_HOST_CHAN route bit. */
898#define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN_EN 0x55
899/* enum: New value of CH_ROUTE_RDP_OUT_HOST_CHAN route bit. */
900#define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN 0x56
901/* enum: Recirculation ID for lookup sequences with two action rule lookups. */
902#define TABLE_FIELD_ID_RECIRC_ID 0x64
903/* enum: Domain ID passed to conntrack and action rule lookups. */
904#define TABLE_FIELD_ID_DOMAIN 0x65
905/* enum: Construction mode for encap_tunnel_id - see MAE_CT_VNI_MODE enum. */
906#define TABLE_FIELD_ID_CT_VNI_MODE 0x66
907/* enum: True to inhibit conntrack lookup if TCP SYN, FIN or RST flag is set.
908 */
909#define TABLE_FIELD_ID_CT_TCP_FLAGS_INHIBIT 0x67
910/* enum: True to do conntrack lookups for IPv4 TCP packets. */
911#define TABLE_FIELD_ID_DO_CT_IP4_TCP 0x68
912/* enum: True to do conntrack lookups for IPv4 UDP packets. */
913#define TABLE_FIELD_ID_DO_CT_IP4_UDP 0x69
914/* enum: True to do conntrack lookups for IPv6 TCP packets. */
915#define TABLE_FIELD_ID_DO_CT_IP6_TCP 0x6a
916/* enum: True to do conntrack lookups for IPv6 UDP packets. */
917#define TABLE_FIELD_ID_DO_CT_IP6_UDP 0x6b
918/* enum: Outer rule identifier. */
919#define TABLE_FIELD_ID_OUTER_RULE_ID 0x6c
920/* enum: Encapsulation type - see MAE_MCDI_ENCAP_TYPE enum. */
921#define TABLE_FIELD_ID_ENCAP_TYPE 0x6d
922/* enum: Encap tunnel ID for conntrack lookups from VNI, VLAN tag(s), or 0,
923 * depending on CT_VNI_MODE.
924 */
925#define TABLE_FIELD_ID_ENCAP_TUNNEL_ID 0x78
926/* enum: A conntrack entry identifier, passed to plugins. */
927#define TABLE_FIELD_ID_CT_ENTRY_ID 0x79
928/* enum: Either source or destination NAT replacement port. */
929#define TABLE_FIELD_ID_NAT_PORT 0x7a
930/* enum: Either source or destination NAT replacement IPv4 address. Note that
931 * this is specifically an IPv4 address (IPv6 is not supported for NAT), with
932 * byte mapped to a 32-bit value in network order, i.e. the IPv4 address
933 * 192.168.1.2 is the value 0xC0A80102.
934 */
935#define TABLE_FIELD_ID_NAT_IP 0x7b
936/* enum: NAT direction: 0=>source, 1=>destination. */
937#define TABLE_FIELD_ID_NAT_DIR 0x7c
938/* enum: Conntrack mark value, passed to action rule lookup. Note that this is
939 * not related to the "user mark" in the metadata / packet prefix.
940 */
941#define TABLE_FIELD_ID_CT_MARK 0x7d
942/* enum: Private flags for conntrack, passed to action rule lookup. */
943#define TABLE_FIELD_ID_CT_PRIV_FLAGS 0x7e
944/* enum: True if the conntrack lookup resulted in a hit. */
945#define TABLE_FIELD_ID_CT_HIT 0x7f
946/* enum: True to suppress delivery when source and destination m-ports match.
947 */
948#define TABLE_FIELD_ID_SUPPRESS_SELF_DELIVERY 0x8c
949/* enum: True to perform tunnel decapsulation. */
950#define TABLE_FIELD_ID_DO_DECAP 0x8d
951/* enum: True to copy outer frame DSCP to inner on decap. */
952#define TABLE_FIELD_ID_DECAP_DSCP_COPY 0x8e
953/* enum: True to map outer frame ECN to inner on decap, by RFC 6040 rules. */
954#define TABLE_FIELD_ID_DECAP_ECN_RFC6040 0x8f
955/* enum: True to replace DSCP field. */
956#define TABLE_FIELD_ID_DO_REPLACE_DSCP 0x90
957/* enum: True to replace ECN field. */
958#define TABLE_FIELD_ID_DO_REPLACE_ECN 0x91
959/* enum: True to decrement IP Time-To-Live. */
960#define TABLE_FIELD_ID_DO_DECR_IP_TTL 0x92
961/* enum: True to replace source MAC address. */
962#define TABLE_FIELD_ID_DO_SRC_MAC 0x93
963/* enum: True to replace destination MAC address. */
964#define TABLE_FIELD_ID_DO_DST_MAC 0x94
965/* enum: Number of VLAN tags to pop. Valid values are 0, 1, or 2. */
966#define TABLE_FIELD_ID_DO_VLAN_POP 0x95
967/* enum: Number of VLANs tags to push. Valid values are 0, 1, or 2. */
968#define TABLE_FIELD_ID_DO_VLAN_PUSH 0x96
969/* enum: True to count this packet. */
970#define TABLE_FIELD_ID_DO_COUNT 0x97
971/* enum: True to perform tunnel encapsulation. */
972#define TABLE_FIELD_ID_DO_ENCAP 0x98
973/* enum: True to copy inner frame DSCP to outer on encap. */
974#define TABLE_FIELD_ID_ENCAP_DSCP_COPY 0x99
975/* enum: True to copy inner frame ECN to outer on encap. */
976#define TABLE_FIELD_ID_ENCAP_ECN_COPY 0x9a
977/* enum: True to deliver the packet (otherwise it is dropped). */
978#define TABLE_FIELD_ID_DO_DELIVER 0x9b
979/* enum: True to set the user flag in the metadata. */
980#define TABLE_FIELD_ID_DO_FLAG 0x9c
981/* enum: True to update the user mark in the metadata. */
982#define TABLE_FIELD_ID_DO_MARK 0x9d
983/* enum: True to override the capsule virtual channel for network deliveries.
984 */
985#define TABLE_FIELD_ID_DO_SET_NET_CHAN 0x9e
986/* enum: True to override the reported source m-port for host deliveries. */
987#define TABLE_FIELD_ID_DO_SET_SRC_MPORT 0x9f
988/* enum: Encap header ID for DO_ENCAP, indexing Encap_Hdr_Part1/2_Table. */
989#define TABLE_FIELD_ID_ENCAP_HDR_ID 0xaa
990/* enum: New DSCP value for DO_REPLACE_DSCP. */
991#define TABLE_FIELD_ID_DSCP_VALUE 0xab
992/* enum: If DO_REPLACE_ECN is set, the new value for the ECN field. If
993 * DO_REPLACE_ECN is not set, ECN_CONTROL[0] and ECN_CONTROL[1] are set to
994 * request remapping of ECT0 and ECT1 ECN codepoints respectively to CE.
995 */
996#define TABLE_FIELD_ID_ECN_CONTROL 0xac
997/* enum: Source MAC ID for DO_SRC_MAC, indexing Replace_Src_MAC_Table. */
998#define TABLE_FIELD_ID_SRC_MAC_ID 0xad
999/* enum: Destination MAC ID for DO_DST_MAC, indexing Replace_Dst_MAC_Table. */
1000#define TABLE_FIELD_ID_DST_MAC_ID 0xae
1001/* enum: Parameter for either DO_SET_NET_CHAN (only bottom 6 bits used in this
1002 * case) or DO_SET_SRC_MPORT.
1003 */
1004#define TABLE_FIELD_ID_REPORTED_SRC_MPORT_OR_NET_CHAN 0xaf
1005/* enum: 64-byte chunk of added encapsulation header. */
1006#define TABLE_FIELD_ID_CHUNK64 0xb4
1007/* enum: 32-byte chunk of added encapsulation header. */
1008#define TABLE_FIELD_ID_CHUNK32 0xb5
1009/* enum: 16-byte chunk of added encapsulation header. */
1010#define TABLE_FIELD_ID_CHUNK16 0xb6
1011/* enum: 8-byte chunk of added encapsulation header. */
1012#define TABLE_FIELD_ID_CHUNK8 0xb7
1013/* enum: 4-byte chunk of added encapsulation header. */
1014#define TABLE_FIELD_ID_CHUNK4 0xb8
1015/* enum: 2-byte chunk of added encapsulation header. */
1016#define TABLE_FIELD_ID_CHUNK2 0xb9
1017/* enum: Added encapsulation header length in words. */
1018#define TABLE_FIELD_ID_HDR_LEN_W 0xba
1019/* enum: Static value for layer 2/3 LACP hash of the encapsulation header. */
1020#define TABLE_FIELD_ID_ENC_LACP_HASH_L23 0xbb
1021/* enum: Static value for layer 4 LACP hash of the encapsulation header. */
1022#define TABLE_FIELD_ID_ENC_LACP_HASH_L4 0xbc
1023/* enum: True to use the static ENC_LACP_HASH values for the encap header
1024 * instead of the calculated values for the inner frame when delivering a newly
1025 * encapsulated packet to a LAG m-port.
1026 */
1027#define TABLE_FIELD_ID_USE_ENC_LACP_HASHES 0xbd
1028/* enum: True to trigger conntrack from first action rule lookup (AR=>CT=>AR
1029 * sequence).
1030 */
1031#define TABLE_FIELD_ID_DO_CT 0xc8
1032/* enum: True to perform NAT using parameters from conntrack lookup response.
1033 */
1034#define TABLE_FIELD_ID_DO_NAT 0xc9
1035/* enum: True to trigger recirculated action rule lookup (AR=>AR sequence). */
1036#define TABLE_FIELD_ID_DO_RECIRC 0xca
1037/* enum: Next action set payload ID for replay. The null value is all-1-bits.
1038 */
1039#define TABLE_FIELD_ID_NEXT_ACTION_SET_PAYLOAD 0xcb
1040/* enum: Next action set row ID for replay. The null value is all-1-bits. */
1041#define TABLE_FIELD_ID_NEXT_ACTION_SET_ROW 0xcc
1042/* enum: Action set payload ID for additional delivery to management CPU. The
1043 * null value is all-1-bits.
1044 */
1045#define TABLE_FIELD_ID_MC_ACTION_SET_PAYLOAD 0xcd
1046/* enum: Action set row ID for additional delivery to management CPU. The null
1047 * value is all-1-bits.
1048 */
1049#define TABLE_FIELD_ID_MC_ACTION_SET_ROW 0xce
1050/* enum: True to include layer 4 in LACP hash on delivery to a LAG m-port. */
1051#define TABLE_FIELD_ID_LACP_INC_L4 0xdc
1052/* enum: True to request that LACP is performed by a plugin. */
1053#define TABLE_FIELD_ID_LACP_PLUGIN 0xdd
1054/* enum: LACP_Balance_Table base address divided by 64. */
1055#define TABLE_FIELD_ID_BAL_TBL_BASE_DIV64 0xde
1056/* enum: Length of balance table region: 0=>64, 1=>128, 2=>256. */
1057#define TABLE_FIELD_ID_BAL_TBL_LEN_ID 0xdf
1058/* enum: LACP LAG ID (i.e. the low 3 bits of LACP LAG mport ID), indexing
1059 * LACP_LAG_Config_Table. Refer to SF-123102-TC.
1060 */
1061#define TABLE_FIELD_ID_LACP_LAG_ID 0xe0
1062/* enum: Address in LACP_Balance_Table. The balance table is partitioned
1063 * between LAGs according to the settings in LACP_LAG_Config_Table and then
1064 * indexed by the LACP hash, providing the mapping to destination mports. Refer
1065 * to SF-123102-TC.
1066 */
1067#define TABLE_FIELD_ID_BAL_TBL_ADDR 0xe1
1068/* enum: UDP port to match for UDP-based encapsulations; required to be 0 for
1069 * other encapsulation types.
1070 */
1071#define TABLE_FIELD_ID_UDP_PORT 0xe6
1072/* enum: True to perform RSS based on outer fields rather than inner fields. */
1073#define TABLE_FIELD_ID_RSS_ON_OUTER 0xe7
1074/* enum: True to perform steering table lookup on outer fields rather than
1075 * inner fields.
1076 */
1077#define TABLE_FIELD_ID_STEER_ON_OUTER 0xe8
1078/* enum: Destination queue ID for host delivery. */
1079#define TABLE_FIELD_ID_DST_QID 0xf0
1080/* enum: True to drop this packet. */
1081#define TABLE_FIELD_ID_DROP 0xf1
1082/* enum: True to strip outer VLAN tag from this packet. */
1083#define TABLE_FIELD_ID_VLAN_STRIP 0xf2
1084/* enum: True to override the user mark field with the supplied USER_MARK, or
1085 * false to bitwise-OR the USER_MARK into it.
1086 */
1087#define TABLE_FIELD_ID_MARK_OVERRIDE 0xf3
1088/* enum: True to override the user flag field with the supplied USER_FLAG, or
1089 * false to bitwise-OR the USER_FLAG into it.
1090 */
1091#define TABLE_FIELD_ID_FLAG_OVERRIDE 0xf4
1092/* enum: RSS context ID, indexing the RSS_Context_Table. */
1093#define TABLE_FIELD_ID_RSS_CTX_ID 0xfa
1094/* enum: True to enable RSS. */
1095#define TABLE_FIELD_ID_RSS_EN 0xfb
1096/* enum: Toeplitz hash key. */
1097#define TABLE_FIELD_ID_KEY 0xfc
1098/* enum: Key mode for IPv4 TCP packets - see TABLE_RSS_KEY_MODE enum. */
1099#define TABLE_FIELD_ID_TCP_V4_KEY_MODE 0xfd
1100/* enum: Key mode for IPv6 TCP packets - see TABLE_RSS_KEY_MODE enum. */
1101#define TABLE_FIELD_ID_TCP_V6_KEY_MODE 0xfe
1102/* enum: Key mode for IPv4 UDP packets - see TABLE_RSS_KEY_MODE enum. */
1103#define TABLE_FIELD_ID_UDP_V4_KEY_MODE 0xff
1104/* enum: Key mode for IPv6 UDP packets - see TABLE_RSS_KEY_MODE enum. */
1105#define TABLE_FIELD_ID_UDP_V6_KEY_MODE 0x100
1106/* enum: Key mode for other IPv4 packets - see TABLE_RSS_KEY_MODE enum. */
1107#define TABLE_FIELD_ID_OTHER_V4_KEY_MODE 0x101
1108/* enum: Key mode for other IPv6 packets - see TABLE_RSS_KEY_MODE enum. */
1109#define TABLE_FIELD_ID_OTHER_V6_KEY_MODE 0x102
1110/* enum: Spreading mode - 0=>indirection; 1=>even. */
1111#define TABLE_FIELD_ID_SPREAD_MODE 0x103
1112/* enum: For indirection spreading mode, the base address of a region within
1113 * the Indirection_Table. For even spreading mode, the number of queues to
1114 * spread across (only values 1-255 are valid for this mode).
1115 */
1116#define TABLE_FIELD_ID_INDIR_TBL_BASE 0x104
1117/* enum: For indirection spreading mode, identifies the length of a region
1118 * within the Indirection_Table, where length = 32 << len_id. Must be set to 0
1119 * for even spreading mode.
1120 */
1121#define TABLE_FIELD_ID_INDIR_TBL_LEN_ID 0x105
1122/* enum: An offset to be applied to the base destination queue ID. */
1123#define TABLE_FIELD_ID_INDIR_OFFSET 0x106
1124/* enum: DPU offload engine profile ID to address. */
1125#define TABLE_FIELD_ID_OE_PROFILE 0x3e8
1126/* enum: Width of the CRC to calculate - see CRC_VARIANT enum. */
1127#define TABLE_FIELD_ID_CRC_VARIANT 0x3f2
1128/* enum: If set, reflect the bits of each input byte, bit 7 is LSB, bit 0 is
1129 * MSB. If clear, bit 7 is MSB, bit 0 is LSB.
1130 */
1131#define TABLE_FIELD_ID_CRC_REFIN 0x3f3
1132/* enum: If set, reflect the bits of each output byte, bit 7 is LSB, bit 0 is
1133 * MSB. If clear, bit 7 is MSB, bit 0 is LSB.
1134 */
1135#define TABLE_FIELD_ID_CRC_REFOUT 0x3f4
1136/* enum: If set, invert every bit of the output value. */
1137#define TABLE_FIELD_ID_CRC_INVOUT 0x3f5
1138/* enum: The CRC polynomial to use for checksumming, in normal form. */
1139#define TABLE_FIELD_ID_CRC_POLY 0x3f6
1140/* enum: Operation for the checksum engine to perform - see DPU_CSUM_OP enum.
1141 */
1142#define TABLE_FIELD_ID_CSUM_OP 0x410
1143/* enum: Byte offset of checksum relative to region_start (for VALIDATE_*
1144 * operations only).
1145 */
1146#define TABLE_FIELD_ID_CSUM_OFFSET 0x411
1147/* enum: Indicates there is additional data on OPR bus that needs to be
1148 * incorporated into the payload checksum.
1149 */
1150#define TABLE_FIELD_ID_CSUM_OPR_ADDITIONAL_DATA 0x412
1151/* enum: Log2 data size of additional data on OPR bus. */
1152#define TABLE_FIELD_ID_CSUM_OPR_DATA_SIZE_LOG2 0x413
1153/* enum: 4 byte offset of where to find the additional data on the OPR bus. */
1154#define TABLE_FIELD_ID_CSUM_OPR_4B_OFF 0x414
1155/* enum: Operation type for the AES-GCM core - see GCM_OP_CODE enum. */
1156#define TABLE_FIELD_ID_GCM_OP_CODE 0x41a
1157/* enum: Key length - AES_KEY_LEN enum. */
1158#define TABLE_FIELD_ID_GCM_KEY_LEN 0x41b
1159/* enum: OPR 4 byte offset for ICV or GHASH output (only in BULK_* mode) or
1160 * IPSEC descrypt output.
1161 */
1162#define TABLE_FIELD_ID_GCM_OPR_4B_OFFSET 0x41c
1163/* enum: If OP_CODE is BULK_*, indicates Emit GHASH (Fragment mode). Else,
1164 * indicates IPSEC-ESN mode.
1165 */
1166#define TABLE_FIELD_ID_GCM_EMIT_GHASH_ISESN 0x41d
1167/* enum: Replay Protection Enable. */
1168#define TABLE_FIELD_ID_GCM_REPLAY_PROTECT_EN 0x41e
1169/* enum: IPSEC Encrypt ESP trailer NEXT_HEADER byte. */
1170#define TABLE_FIELD_ID_GCM_NEXT_HDR 0x41f
1171/* enum: Replay Window Size. */
1172#define TABLE_FIELD_ID_GCM_REPLAY_WIN_SIZE 0x420
1173
1174/* MCDI_EVENT structuredef: The structure of an MCDI_EVENT on Siena/EF10/EF100
1175 * platforms
1176 */
1177#define MCDI_EVENT_LEN 8
1178#define MCDI_EVENT_CONT_LBN 32
1179#define MCDI_EVENT_CONT_WIDTH 1
1180#define MCDI_EVENT_LEVEL_LBN 33
1181#define MCDI_EVENT_LEVEL_WIDTH 3
1182/* enum: Info. */
1183#define MCDI_EVENT_LEVEL_INFO 0x0
1184/* enum: Warning. */
1185#define MCDI_EVENT_LEVEL_WARN 0x1
1186/* enum: Error. */
1187#define MCDI_EVENT_LEVEL_ERR 0x2
1188/* enum: Fatal. */
1189#define MCDI_EVENT_LEVEL_FATAL 0x3
1190#define MCDI_EVENT_DATA_OFST 0
1191#define MCDI_EVENT_DATA_LEN 4
1192#define MCDI_EVENT_CMDDONE_SEQ_OFST 0
1193#define MCDI_EVENT_CMDDONE_SEQ_LBN 0
1194#define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
1195#define MCDI_EVENT_CMDDONE_DATALEN_OFST 0
1196#define MCDI_EVENT_CMDDONE_DATALEN_LBN 8
1197#define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
1198#define MCDI_EVENT_CMDDONE_ERRNO_OFST 0
1199#define MCDI_EVENT_CMDDONE_ERRNO_LBN 16
1200#define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
1201#define MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0
1202#define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
1203#define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
1204#define MCDI_EVENT_LINKCHANGE_SPEED_OFST 0
1205#define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
1206#define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
1207/* enum: Link is down or link speed could not be determined */
1208#define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
1209/* enum: 100Mbs */
1210#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
1211/* enum: 1Gbs */
1212#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
1213/* enum: 10Gbs */
1214#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
1215/* enum: 40Gbs */
1216#define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
1217/* enum: 25Gbs */
1218#define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
1219/* enum: 50Gbs */
1220#define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
1221/* enum: 100Gbs */
1222#define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
1223#define MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0
1224#define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
1225#define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
1226#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0
1227#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
1228#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
1229#define MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_OFST 0
1230#define MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_LBN 0
1231#define MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_WIDTH 24
1232#define MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_OFST 0
1233#define MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_LBN 24
1234#define MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_WIDTH 7
1235#define MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_OFST 0
1236#define MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_LBN 31
1237#define MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_WIDTH 1
1238#define MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_OFST 0
1239#define MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_LBN 0
1240#define MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_WIDTH 24
1241#define MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_OFST 0
1242#define MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_LBN 24
1243#define MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_WIDTH 7
1244#define MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_OFST 0
1245#define MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_LBN 31
1246#define MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_WIDTH 1
1247#define MCDI_EVENT_SENSOREVT_MONITOR_OFST 0
1248#define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
1249#define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
1250#define MCDI_EVENT_SENSOREVT_STATE_OFST 0
1251#define MCDI_EVENT_SENSOREVT_STATE_LBN 8
1252#define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
1253#define MCDI_EVENT_SENSOREVT_VALUE_OFST 0
1254#define MCDI_EVENT_SENSOREVT_VALUE_LBN 16
1255#define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
1256#define MCDI_EVENT_FWALERT_DATA_OFST 0
1257#define MCDI_EVENT_FWALERT_DATA_LBN 8
1258#define MCDI_EVENT_FWALERT_DATA_WIDTH 24
1259#define MCDI_EVENT_FWALERT_REASON_OFST 0
1260#define MCDI_EVENT_FWALERT_REASON_LBN 0
1261#define MCDI_EVENT_FWALERT_REASON_WIDTH 8
1262/* enum: SRAM Access. */
1263#define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
1264#define MCDI_EVENT_FLR_VF_OFST 0
1265#define MCDI_EVENT_FLR_VF_LBN 0
1266#define MCDI_EVENT_FLR_VF_WIDTH 8
1267#define MCDI_EVENT_TX_ERR_TXQ_OFST 0
1268#define MCDI_EVENT_TX_ERR_TXQ_LBN 0
1269#define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
1270#define MCDI_EVENT_TX_ERR_TYPE_OFST 0
1271#define MCDI_EVENT_TX_ERR_TYPE_LBN 12
1272#define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
1273/* enum: Descriptor loader reported failure. Specific to EF10-family NICs. */
1274#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
1275/* enum: Descriptor ring empty and no EOP seen for packet. Specific to
1276 * EF10-family NICs
1277 */
1278#define MCDI_EVENT_TX_ERR_NO_EOP 0x2
1279/* enum: Overlength packet. Specific to EF10-family NICs. */
1280#define MCDI_EVENT_TX_ERR_2BIG 0x3
1281/* enum: Malformed option descriptor. Specific to EF10-family NICs. */
1282#define MCDI_EVENT_TX_BAD_OPTDESC 0x5
1283/* enum: Option descriptor part way through a packet. Specific to EF10-family
1284 * NICs.
1285 */
1286#define MCDI_EVENT_TX_OPT_IN_PKT 0x8
1287/* enum: DMA or PIO data access error. Specific to EF10-family NICs */
1288#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
1289#define MCDI_EVENT_TX_ERR_INFO_OFST 0
1290#define MCDI_EVENT_TX_ERR_INFO_LBN 16
1291#define MCDI_EVENT_TX_ERR_INFO_WIDTH 16
1292#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0
1293#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
1294#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
1295#define MCDI_EVENT_TX_FLUSH_TXQ_OFST 0
1296#define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
1297#define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
1298#define MCDI_EVENT_PTP_ERR_TYPE_OFST 0
1299#define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
1300#define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
1301/* enum: PLL lost lock */
1302#define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
1303/* enum: Filter overflow (PDMA) */
1304#define MCDI_EVENT_PTP_ERR_FILTER 0x2
1305/* enum: FIFO overflow (FPGA) */
1306#define MCDI_EVENT_PTP_ERR_FIFO 0x3
1307/* enum: Merge queue overflow */
1308#define MCDI_EVENT_PTP_ERR_QUEUE 0x4
1309#define MCDI_EVENT_AOE_ERR_TYPE_OFST 0
1310#define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
1311#define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
1312/* enum: AOE failed to load - no valid image? */
1313#define MCDI_EVENT_AOE_NO_LOAD 0x1
1314/* enum: AOE FC reported an exception */
1315#define MCDI_EVENT_AOE_FC_ASSERT 0x2
1316/* enum: AOE FC watchdogged */
1317#define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
1318/* enum: AOE FC failed to start */
1319#define MCDI_EVENT_AOE_FC_NO_START 0x4
1320/* enum: Generic AOE fault - likely to have been reported via other means too
1321 * but intended for use by aoex driver.
1322 */
1323#define MCDI_EVENT_AOE_FAULT 0x5
1324/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
1325#define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
1326/* enum: AOE loaded successfully */
1327#define MCDI_EVENT_AOE_LOAD 0x7
1328/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
1329#define MCDI_EVENT_AOE_DMA 0x8
1330/* enum: AOE byteblaster connected/disconnected (Connection status in
1331 * AOE_ERR_DATA)
1332 */
1333#define MCDI_EVENT_AOE_BYTEBLASTER 0x9
1334/* enum: DDR ECC status update */
1335#define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
1336/* enum: PTP status update */
1337#define MCDI_EVENT_AOE_PTP_STATUS 0xb
1338/* enum: FPGA header incorrect */
1339#define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
1340/* enum: FPGA Powered Off due to error in powering up FPGA */
1341#define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
1342/* enum: AOE FPGA load failed due to MC to MUM communication failure */
1343#define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
1344/* enum: Notify that invalid flash type detected */
1345#define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
1346/* enum: Notify that the attempt to run FPGA Controller firmware timed out */
1347#define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
1348/* enum: Failure to probe one or more FPGA boot flash chips */
1349#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
1350/* enum: FPGA boot-flash contains an invalid image header */
1351#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
1352/* enum: Failed to program clocks required by the FPGA */
1353#define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
1354/* enum: Notify that FPGA Controller is alive to serve MCDI requests */
1355#define MCDI_EVENT_AOE_FC_RUNNING 0x14
1356#define MCDI_EVENT_AOE_ERR_DATA_OFST 0
1357#define MCDI_EVENT_AOE_ERR_DATA_LBN 8
1358#define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
1359#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0
1360#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8
1361#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8
1362/* enum: FC Assert happened, but the register information is not available */
1363#define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
1364/* enum: The register information for FC Assert is ready for reading by driver
1365 */
1366#define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
1367#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0
1368#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8
1369#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8
1370/* enum: Reading from NV failed */
1371#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
1372/* enum: Invalid Magic Number if FPGA header */
1373#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
1374/* enum: Invalid Silicon type detected in header */
1375#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
1376/* enum: Unsupported VRatio */
1377#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
1378/* enum: Unsupported DDR Type */
1379#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
1380/* enum: DDR Voltage out of supported range */
1381#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
1382/* enum: Unsupported DDR speed */
1383#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
1384/* enum: Unsupported DDR size */
1385#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
1386/* enum: Unsupported DDR rank */
1387#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
1388#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0
1389#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8
1390#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8
1391/* enum: Primary boot flash */
1392#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
1393/* enum: Secondary boot flash */
1394#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
1395#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0
1396#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8
1397#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8
1398#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0
1399#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8
1400#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8
1401#define MCDI_EVENT_RX_ERR_RXQ_OFST 0
1402#define MCDI_EVENT_RX_ERR_RXQ_LBN 0
1403#define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
1404#define MCDI_EVENT_RX_ERR_TYPE_OFST 0
1405#define MCDI_EVENT_RX_ERR_TYPE_LBN 12
1406#define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
1407#define MCDI_EVENT_RX_ERR_INFO_OFST 0
1408#define MCDI_EVENT_RX_ERR_INFO_LBN 16
1409#define MCDI_EVENT_RX_ERR_INFO_WIDTH 16
1410#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0
1411#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
1412#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
1413#define MCDI_EVENT_RX_FLUSH_RXQ_OFST 0
1414#define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
1415#define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
1416#define MCDI_EVENT_MC_REBOOT_COUNT_OFST 0
1417#define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
1418#define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
1419#define MCDI_EVENT_MUM_ERR_TYPE_OFST 0
1420#define MCDI_EVENT_MUM_ERR_TYPE_LBN 0
1421#define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8
1422/* enum: MUM failed to load - no valid image? */
1423#define MCDI_EVENT_MUM_NO_LOAD 0x1
1424/* enum: MUM f/w reported an exception */
1425#define MCDI_EVENT_MUM_ASSERT 0x2
1426/* enum: MUM not kicking watchdog */
1427#define MCDI_EVENT_MUM_WATCHDOG 0x3
1428#define MCDI_EVENT_MUM_ERR_DATA_OFST 0
1429#define MCDI_EVENT_MUM_ERR_DATA_LBN 8
1430#define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8
1431#define MCDI_EVENT_DBRET_SEQ_OFST 0
1432#define MCDI_EVENT_DBRET_SEQ_LBN 0
1433#define MCDI_EVENT_DBRET_SEQ_WIDTH 8
1434#define MCDI_EVENT_SUC_ERR_TYPE_OFST 0
1435#define MCDI_EVENT_SUC_ERR_TYPE_LBN 0
1436#define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8
1437/* enum: Corrupted or bad SUC application. */
1438#define MCDI_EVENT_SUC_BAD_APP 0x1
1439/* enum: SUC application reported an assert. */
1440#define MCDI_EVENT_SUC_ASSERT 0x2
1441/* enum: SUC application reported an exception. */
1442#define MCDI_EVENT_SUC_EXCEPTION 0x3
1443/* enum: SUC watchdog timer expired. */
1444#define MCDI_EVENT_SUC_WATCHDOG 0x4
1445#define MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0
1446#define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8
1447#define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24
1448#define MCDI_EVENT_SUC_ERR_DATA_OFST 0
1449#define MCDI_EVENT_SUC_ERR_DATA_LBN 8
1450#define MCDI_EVENT_SUC_ERR_DATA_WIDTH 24
1451#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0
1452#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0
1453#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_WIDTH 24
1454#define MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0
1455#define MCDI_EVENT_LINKCHANGE_V2_SPEED_LBN 24
1456#define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4
1457/* Enum values, see field(s): */
1458/* MCDI_EVENT/LINKCHANGE_SPEED */
1459#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0
1460#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_LBN 28
1461#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 1
1462#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0
1463#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_LBN 29
1464#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_WIDTH 3
1465/* Enum values, see field(s): */
1466/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
1467#define MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0
1468#define MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0
1469#define MCDI_EVENT_MODULECHANGE_LD_CAP_WIDTH 30
1470#define MCDI_EVENT_MODULECHANGE_SEQ_OFST 0
1471#define MCDI_EVENT_MODULECHANGE_SEQ_LBN 30
1472#define MCDI_EVENT_MODULECHANGE_SEQ_WIDTH 2
1473#define MCDI_EVENT_DESC_PROXY_VIRTQ_VI_ID_OFST 0
1474#define MCDI_EVENT_DESC_PROXY_VIRTQ_VI_ID_LBN 0
1475#define MCDI_EVENT_DESC_PROXY_VIRTQ_VI_ID_WIDTH 16
1476#define MCDI_EVENT_DESC_PROXY_VIRTQ_ID_OFST 0
1477#define MCDI_EVENT_DESC_PROXY_VIRTQ_ID_LBN 16
1478#define MCDI_EVENT_DESC_PROXY_VIRTQ_ID_WIDTH 16
1479#define MCDI_EVENT_DATA_LBN 0
1480#define MCDI_EVENT_DATA_WIDTH 32
1481/* Alias for PTP_DATA. */
1482#define MCDI_EVENT_SRC_LBN 36
1483#define MCDI_EVENT_SRC_WIDTH 8
1484/* Data associated with PTP events which doesn't fit into the main DATA field
1485 */
1486#define MCDI_EVENT_PTP_DATA_LBN 36
1487#define MCDI_EVENT_PTP_DATA_WIDTH 8
1488/* EF100 specific. Defined by QDMA. The phase bit, changes each time round the
1489 * event ring
1490 */
1491#define MCDI_EVENT_EV_EVQ_PHASE_LBN 59
1492#define MCDI_EVENT_EV_EVQ_PHASE_WIDTH 1
1493#define MCDI_EVENT_EV_CODE_LBN 60
1494#define MCDI_EVENT_EV_CODE_WIDTH 4
1495#define MCDI_EVENT_CODE_LBN 44
1496#define MCDI_EVENT_CODE_WIDTH 8
1497/* enum: Event generated by host software */
1498#define MCDI_EVENT_SW_EVENT 0x0
1499/* enum: Bad assert. */
1500#define MCDI_EVENT_CODE_BADSSERT 0x1
1501/* enum: PM Notice. */
1502#define MCDI_EVENT_CODE_PMNOTICE 0x2
1503/* enum: Command done. */
1504#define MCDI_EVENT_CODE_CMDDONE 0x3
1505/* enum: Link change. */
1506#define MCDI_EVENT_CODE_LINKCHANGE 0x4
1507/* enum: Sensor Event. */
1508#define MCDI_EVENT_CODE_SENSOREVT 0x5
1509/* enum: Schedule error. */
1510#define MCDI_EVENT_CODE_SCHEDERR 0x6
1511/* enum: Reboot. */
1512#define MCDI_EVENT_CODE_REBOOT 0x7
1513/* enum: Mac stats DMA. */
1514#define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
1515/* enum: Firmware alert. */
1516#define MCDI_EVENT_CODE_FWALERT 0x9
1517/* enum: Function level reset. */
1518#define MCDI_EVENT_CODE_FLR 0xa
1519/* enum: Transmit error */
1520#define MCDI_EVENT_CODE_TX_ERR 0xb
1521/* enum: Tx flush has completed */
1522#define MCDI_EVENT_CODE_TX_FLUSH 0xc
1523/* enum: PTP packet received timestamp */
1524#define MCDI_EVENT_CODE_PTP_RX 0xd
1525/* enum: PTP NIC failure */
1526#define MCDI_EVENT_CODE_PTP_FAULT 0xe
1527/* enum: PTP PPS event */
1528#define MCDI_EVENT_CODE_PTP_PPS 0xf
1529/* enum: Rx flush has completed */
1530#define MCDI_EVENT_CODE_RX_FLUSH 0x10
1531/* enum: Receive error */
1532#define MCDI_EVENT_CODE_RX_ERR 0x11
1533/* enum: AOE fault */
1534#define MCDI_EVENT_CODE_AOE 0x12
1535/* enum: Network port calibration failed (VCAL). */
1536#define MCDI_EVENT_CODE_VCAL_FAIL 0x13
1537/* enum: HW PPS event */
1538#define MCDI_EVENT_CODE_HW_PPS 0x14
1539/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
1540 * a different format)
1541 */
1542#define MCDI_EVENT_CODE_MC_REBOOT 0x15
1543/* enum: the MC has detected a parity error */
1544#define MCDI_EVENT_CODE_PAR_ERR 0x16
1545/* enum: the MC has detected a correctable error */
1546#define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
1547/* enum: the MC has detected an uncorrectable error */
1548#define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
1549/* enum: The MC has entered offline BIST mode */
1550#define MCDI_EVENT_CODE_MC_BIST 0x19
1551/* enum: PTP tick event providing current NIC time */
1552#define MCDI_EVENT_CODE_PTP_TIME 0x1a
1553/* enum: MUM fault */
1554#define MCDI_EVENT_CODE_MUM 0x1b
1555/* enum: notify the designated PF of a new authorization request */
1556#define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
1557/* enum: notify a function that awaits an authorization that its request has
1558 * been processed and it may now resend the command
1559 */
1560#define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
1561/* enum: MCDI command accepted. New commands can be issued but this command is
1562 * not done yet.
1563 */
1564#define MCDI_EVENT_CODE_DBRET 0x1e
1565/* enum: The MC has detected a fault on the SUC */
1566#define MCDI_EVENT_CODE_SUC 0x1f
1567/* enum: Link change. This event is sent instead of LINKCHANGE if
1568 * WANT_V2_LINKCHANGES was set on driver attach.
1569 */
1570#define MCDI_EVENT_CODE_LINKCHANGE_V2 0x20
1571/* enum: This event is sent if WANT_V2_LINKCHANGES was set on driver attach
1572 * when the local device capabilities changes. This will usually correspond to
1573 * a module change.
1574 */
1575#define MCDI_EVENT_CODE_MODULECHANGE 0x21
1576/* enum: Notification that the sensors have been added and/or removed from the
1577 * sensor table. This event includes the new sensor table generation count, if
1578 * this does not match the driver's local copy it is expected to call
1579 * DYNAMIC_SENSORS_LIST to refresh it.
1580 */
1581#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22
1582/* enum: Notification that a sensor has changed state as a result of a reading
1583 * crossing a threshold. This is sent as two events, the first event contains
1584 * the handle and the sensor's state (in the SRC field), and the second
1585 * contains the value.
1586 */
1587#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23
1588/* enum: Notification that a descriptor proxy function configuration has been
1589 * pushed to "live" status (visible to host). SRC field contains the handle of
1590 * the affected descriptor proxy function. DATA field contains the generation
1591 * count of configuration set applied. See MC_CMD_DESC_PROXY_FUNC_CONFIG_SET /
1592 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.
1593 */
1594#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24
1595/* enum: Notification that a descriptor proxy function has been reset. SRC
1596 * field contains the handle of the affected descriptor proxy function. See
1597 * SF-122927-TC for details.
1598 */
1599#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25
1600/* enum: Notification that a driver attached to a descriptor proxy function.
1601 * SRC field contains the handle of the affected descriptor proxy function. For
1602 * Virtio proxy functions this message consists of two MCDI events, where the
1603 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0
1604 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy
1605 * functions event length and meaning of DATA field is not yet defined. See
1606 * SF-122927-TC for details.
1607 */
1608#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26
1609/* enum: Notification that the mport journal has changed since it was last read
1610 * and updates can be read using the MC_CMD_MAE_MPORT_READ_JOURNAL command. The
1611 * firmware may moderate the events so that an event is not sent for every
1612 * change to the journal.
1613 */
1614#define MCDI_EVENT_CODE_MPORT_JOURNAL_CHANGE 0x27
1615/* enum: Notification that a source queue is enabled and attached to its proxy
1616 * sink queue. SRC field contains the handle of the affected descriptor proxy
1617 * function. DATA field contains the relative source queue number and absolute
1618 * VI ID.
1619 */
1620#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_QUEUE_START 0x28
1621/* enum: Notification of a change in link state and/or link speed of a network
1622 * port link. This event applies to a network port identified by a handle,
1623 * PORT_HANDLE, which is discovered by the driver using the MC_CMD_ENUM_PORTS
1624 * command.
1625 */
1626#define MCDI_EVENT_CODE_PORT_LINKCHANGE 0x29
1627/* enum: Notification of a change in the state of an MDI (external connector)
1628 * of a network port. This typically corresponds to module plug/unplug for
1629 * modular interfaces (e.g., SFP/QSFP and similar) or cable connect/disconnect.
1630 * This event applies to a network port identified by a handle, PORT_HANDLE,
1631 * which is discovered by the driver using the MC_CMD_ENUM_PORTS command.
1632 */
1633#define MCDI_EVENT_CODE_PORT_MODULECHANGE 0x2a
1634/* enum: Notification that the port enumeration journal has changed since it
1635 * was last read and updates can be read using the MC_CMD_ENUM_PORTS command.
1636 * The firmware may moderate the events so that an event is not sent for every
1637 * change to the journal.
1638 */
1639#define MCDI_EVENT_CODE_ENUM_PORTS_CHANGE 0x2b
1640/* enum: Artificial event generated by host and posted via MC for test
1641 * purposes.
1642 */
1643#define MCDI_EVENT_CODE_TESTGEN 0xfa
1644#define MCDI_EVENT_CMDDONE_DATA_OFST 0
1645#define MCDI_EVENT_CMDDONE_DATA_LEN 4
1646#define MCDI_EVENT_CMDDONE_DATA_LBN 0
1647#define MCDI_EVENT_CMDDONE_DATA_WIDTH 32
1648#define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
1649#define MCDI_EVENT_LINKCHANGE_DATA_LEN 4
1650#define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
1651#define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
1652#define MCDI_EVENT_PORT_LINKCHANGE_DATA_OFST 0
1653#define MCDI_EVENT_PORT_LINKCHANGE_DATA_LEN 4
1654#define MCDI_EVENT_PORT_LINKCHANGE_DATA_LBN 0
1655#define MCDI_EVENT_PORT_LINKCHANGE_DATA_WIDTH 32
1656#define MCDI_EVENT_PORT_MODULECHANGE_DATA_OFST 0
1657#define MCDI_EVENT_PORT_MODULECHANGE_DATA_LEN 4
1658#define MCDI_EVENT_PORT_MODULECHANGE_DATA_LBN 0
1659#define MCDI_EVENT_PORT_MODULECHANGE_DATA_WIDTH 32
1660#define MCDI_EVENT_SENSOREVT_DATA_OFST 0
1661#define MCDI_EVENT_SENSOREVT_DATA_LEN 4
1662#define MCDI_EVENT_SENSOREVT_DATA_LBN 0
1663#define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
1664#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
1665#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
1666#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
1667#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
1668#define MCDI_EVENT_TX_ERR_DATA_OFST 0
1669#define MCDI_EVENT_TX_ERR_DATA_LEN 4
1670#define MCDI_EVENT_TX_ERR_DATA_LBN 0
1671#define MCDI_EVENT_TX_ERR_DATA_WIDTH 32
1672/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of
1673 * timestamp
1674 */
1675#define MCDI_EVENT_PTP_SECONDS_OFST 0
1676#define MCDI_EVENT_PTP_SECONDS_LEN 4
1677#define MCDI_EVENT_PTP_SECONDS_LBN 0
1678#define MCDI_EVENT_PTP_SECONDS_WIDTH 32
1679/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of
1680 * timestamp
1681 */
1682#define MCDI_EVENT_PTP_MAJOR_OFST 0
1683#define MCDI_EVENT_PTP_MAJOR_LEN 4
1684#define MCDI_EVENT_PTP_MAJOR_LBN 0
1685#define MCDI_EVENT_PTP_MAJOR_WIDTH 32
1686/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field
1687 * of timestamp
1688 */
1689#define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
1690#define MCDI_EVENT_PTP_NANOSECONDS_LEN 4
1691#define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
1692#define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
1693/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of
1694 * timestamp
1695 */
1696#define MCDI_EVENT_PTP_MINOR_OFST 0
1697#define MCDI_EVENT_PTP_MINOR_LEN 4
1698#define MCDI_EVENT_PTP_MINOR_LBN 0
1699#define MCDI_EVENT_PTP_MINOR_WIDTH 32
1700/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
1701 */
1702#define MCDI_EVENT_PTP_UUID_OFST 0
1703#define MCDI_EVENT_PTP_UUID_LEN 4
1704#define MCDI_EVENT_PTP_UUID_LBN 0
1705#define MCDI_EVENT_PTP_UUID_WIDTH 32
1706#define MCDI_EVENT_RX_ERR_DATA_OFST 0
1707#define MCDI_EVENT_RX_ERR_DATA_LEN 4
1708#define MCDI_EVENT_RX_ERR_DATA_LBN 0
1709#define MCDI_EVENT_RX_ERR_DATA_WIDTH 32
1710#define MCDI_EVENT_PAR_ERR_DATA_OFST 0
1711#define MCDI_EVENT_PAR_ERR_DATA_LEN 4
1712#define MCDI_EVENT_PAR_ERR_DATA_LBN 0
1713#define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
1714#define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
1715#define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
1716#define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
1717#define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
1718#define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
1719#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
1720#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
1721#define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
1722/* For CODE_PTP_TIME events, the major value of the PTP clock */
1723#define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
1724#define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
1725#define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
1726#define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32
1727/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
1728#define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36
1729#define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8
1730/* For CODE_PTP_TIME events, most significant bits of the minor value of the
1731 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19.
1732 */
1733#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36
1734#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8
1735/* For CODE_PTP_TIME events where report sync status is enabled, indicates
1736 * whether the NIC clock has ever been set
1737 */
1738#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36
1739#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
1740/* For CODE_PTP_TIME events where report sync status is enabled, indicates
1741 * whether the NIC and System clocks are in sync
1742 */
1743#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37
1744#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
1745/* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
1746 * the minor value of the PTP clock
1747 */
1748#define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38
1749#define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6
1750/* For CODE_PTP_TIME events, most significant bits of the minor value of the
1751 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21.
1752 */
1753#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38
1754#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6
1755#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
1756#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
1757#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
1758#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32
1759#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
1760#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
1761#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
1762#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32
1763/* Zero means that the request has been completed or authorized, and the driver
1764 * should resend it. A non-zero value means that the authorization has been
1765 * denied, and gives the reason. Typically it will be EPERM.
1766 */
1767#define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36
1768#define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8
1769#define MCDI_EVENT_DBRET_DATA_OFST 0
1770#define MCDI_EVENT_DBRET_DATA_LEN 4
1771#define MCDI_EVENT_DBRET_DATA_LBN 0
1772#define MCDI_EVENT_DBRET_DATA_WIDTH 32
1773#define MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0
1774#define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4
1775#define MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0
1776#define MCDI_EVENT_LINKCHANGE_V2_DATA_WIDTH 32
1777#define MCDI_EVENT_MODULECHANGE_DATA_OFST 0
1778#define MCDI_EVENT_MODULECHANGE_DATA_LEN 4
1779#define MCDI_EVENT_MODULECHANGE_DATA_LBN 0
1780#define MCDI_EVENT_MODULECHANGE_DATA_WIDTH 32
1781/* The new generation count after a sensor has been added or deleted. */
1782#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0
1783#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4
1784#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0
1785#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_WIDTH 32
1786/* The handle of a dynamic sensor. */
1787#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0
1788#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4
1789#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0
1790#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_WIDTH 32
1791/* The current values of a sensor. */
1792#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0
1793#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4
1794#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0
1795#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_WIDTH 32
1796/* The current state of a sensor. */
1797#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_LBN 36
1798#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_WIDTH 8
1799#define MCDI_EVENT_DESC_PROXY_DATA_OFST 0
1800#define MCDI_EVENT_DESC_PROXY_DATA_LEN 4
1801#define MCDI_EVENT_DESC_PROXY_DATA_LBN 0
1802#define MCDI_EVENT_DESC_PROXY_DATA_WIDTH 32
1803/* Generation count of applied configuration set */
1804#define MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0
1805#define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4
1806#define MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0
1807#define MCDI_EVENT_DESC_PROXY_GENERATION_WIDTH 32
1808/* Virtio features negotiated with the host driver. First event (CONT=1)
1809 * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.
1810 */
1811#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0
1812#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4
1813#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0
1814#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_WIDTH 32
1815
1816
1817/***********************************/
1818/* MC_CMD_READ32
1819 * Read multiple 32byte words from MC memory. Note - this command really
1820 * belongs to INSECURE category but is required by shmboot. The command handler
1821 * has additional checks to reject insecure calls.
1822 */
1823#define MC_CMD_READ32 0x1
1824#undef MC_CMD_0x1_PRIVILEGE_CTG
1825
1826#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1827
1828/* MC_CMD_READ32_IN msgrequest */
1829#define MC_CMD_READ32_IN_LEN 8
1830#define MC_CMD_READ32_IN_ADDR_OFST 0
1831#define MC_CMD_READ32_IN_ADDR_LEN 4
1832#define MC_CMD_READ32_IN_NUMWORDS_OFST 4
1833#define MC_CMD_READ32_IN_NUMWORDS_LEN 4
1834
1835/* MC_CMD_READ32_OUT msgresponse */
1836#define MC_CMD_READ32_OUT_LENMIN 4
1837#define MC_CMD_READ32_OUT_LENMAX 252
1838#define MC_CMD_READ32_OUT_LENMAX_MCDI2 1020
1839#define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1840#define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
1841#define MC_CMD_READ32_OUT_BUFFER_OFST 0
1842#define MC_CMD_READ32_OUT_BUFFER_LEN 4
1843#define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
1844#define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
1845#define MC_CMD_READ32_OUT_BUFFER_MAXNUM_MCDI2 255
1846
1847
1848/***********************************/
1849/* MC_CMD_WRITE32
1850 * Write multiple 32byte words to MC memory.
1851 */
1852#define MC_CMD_WRITE32 0x2
1853#undef MC_CMD_0x2_PRIVILEGE_CTG
1854
1855#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1856
1857/* MC_CMD_WRITE32_IN msgrequest */
1858#define MC_CMD_WRITE32_IN_LENMIN 8
1859#define MC_CMD_WRITE32_IN_LENMAX 252
1860#define MC_CMD_WRITE32_IN_LENMAX_MCDI2 1020
1861#define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1862#define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)
1863#define MC_CMD_WRITE32_IN_ADDR_OFST 0
1864#define MC_CMD_WRITE32_IN_ADDR_LEN 4
1865#define MC_CMD_WRITE32_IN_BUFFER_OFST 4
1866#define MC_CMD_WRITE32_IN_BUFFER_LEN 4
1867#define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
1868#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
1869#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM_MCDI2 254
1870
1871/* MC_CMD_WRITE32_OUT msgresponse */
1872#define MC_CMD_WRITE32_OUT_LEN 0
1873
1874
1875/***********************************/
1876/* MC_CMD_GET_BOOT_STATUS
1877 * Get the instruction address from which the MC booted.
1878 */
1879#define MC_CMD_GET_BOOT_STATUS 0x5
1880#undef MC_CMD_0x5_PRIVILEGE_CTG
1881
1882#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1883
1884/* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
1885#define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
1886
1887/* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
1888#define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
1889/* ?? */
1890#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
1891#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
1892/* enum: indicates that the MC wasn't flash booted */
1893#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
1894#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
1895#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
1896#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4
1897#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
1898#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
1899#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4
1900#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
1901#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
1902#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4
1903#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
1904#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
1905
1906
1907/***********************************/
1908/* MC_CMD_GET_ASSERTS
1909 * Get (and optionally clear) the current assertion status. Only
1910 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other
1911 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
1912 */
1913#define MC_CMD_GET_ASSERTS 0x6
1914#undef MC_CMD_0x6_PRIVILEGE_CTG
1915
1916#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1917
1918/* MC_CMD_GET_ASSERTS_IN msgrequest */
1919#define MC_CMD_GET_ASSERTS_IN_LEN 4
1920/* Set to clear assertion */
1921#define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
1922#define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
1923
1924/* MC_CMD_GET_ASSERTS_OUT msgresponse */
1925#define MC_CMD_GET_ASSERTS_OUT_LEN 140
1926/* Assertion status flag. */
1927#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
1928#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
1929/* enum: No assertions have failed. */
1930#define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
1931/* enum: A system-level assertion has failed. */
1932#define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
1933/* enum: A thread-level assertion has failed. */
1934#define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
1935/* enum: The system was reset by the watchdog. */
1936#define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
1937/* enum: An illegal address trap stopped the system (huntington and later) */
1938#define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
1939/* Failing PC value */
1940#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
1941#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
1942/* Saved GP regs */
1943#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
1944#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
1945#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
1946/* enum: A magic value hinting that the value in this register at the time of
1947 * the failure has likely been lost.
1948 */
1949#define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
1950/* Failing thread address */
1951#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
1952#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
1953#define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
1954#define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
1955
1956/* MC_CMD_GET_ASSERTS_OUT_V2 msgresponse: Extended response for MicroBlaze CPUs
1957 * found on Riverhead designs
1958 */
1959#define MC_CMD_GET_ASSERTS_OUT_V2_LEN 240
1960/* Assertion status flag. */
1961#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0
1962#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4
1963/* enum: No assertions have failed. */
1964/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
1965/* enum: A system-level assertion has failed. */
1966/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
1967/* enum: A thread-level assertion has failed. */
1968/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
1969/* enum: The system was reset by the watchdog. */
1970/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
1971/* enum: An illegal address trap stopped the system (huntington and later) */
1972/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
1973/* Failing PC value */
1974#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4
1975#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4
1976/* Saved GP regs */
1977#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_OFST 8
1978#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4
1979#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_NUM 31
1980/* enum: A magic value hinting that the value in this register at the time of
1981 * the failure has likely been lost.
1982 */
1983/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
1984/* Failing thread address */
1985#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_OFST 132
1986#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4
1987#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_OFST 136
1988#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4
1989/* Saved Special Function Registers */
1990#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_OFST 136
1991#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4
1992#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_NUM 26
1993
1994/* MC_CMD_GET_ASSERTS_OUT_V3 msgresponse: Extended response with asserted
1995 * firmware version information
1996 */
1997#define MC_CMD_GET_ASSERTS_OUT_V3_LEN 360
1998/* Assertion status flag. */
1999#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0
2000#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4
2001/* enum: No assertions have failed. */
2002/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
2003/* enum: A system-level assertion has failed. */
2004/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
2005/* enum: A thread-level assertion has failed. */
2006/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
2007/* enum: The system was reset by the watchdog. */
2008/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
2009/* enum: An illegal address trap stopped the system (huntington and later) */
2010/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
2011/* Failing PC value */
2012#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4
2013#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4
2014/* Saved GP regs */
2015#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_OFST 8
2016#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4
2017#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_NUM 31
2018/* enum: A magic value hinting that the value in this register at the time of
2019 * the failure has likely been lost.
2020 */
2021/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
2022/* Failing thread address */
2023#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_OFST 132
2024#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4
2025#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_OFST 136
2026#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4
2027/* Saved Special Function Registers */
2028#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_OFST 136
2029#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4
2030#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_NUM 26
2031/* MC firmware unique build ID (as binary SHA-1 value) */
2032#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_OFST 240
2033#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_LEN 20
2034/* MC firmware build date (as Unix timestamp) */
2035#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260
2036#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8
2037#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260
2038#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LEN 4
2039#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LBN 2080
2040#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_WIDTH 32
2041#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264
2042#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LEN 4
2043#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LBN 2112
2044#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_WIDTH 32
2045/* MC firmware version number */
2046#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268
2047#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8
2048#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268
2049#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LEN 4
2050#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LBN 2144
2051#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_WIDTH 32
2052#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272
2053#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LEN 4
2054#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LBN 2176
2055#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_WIDTH 32
2056/* MC firmware security level */
2057#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276
2058#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
2059/* MC firmware extra version info (as null-terminated US-ASCII string) */
2060#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_OFST 280
2061#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_LEN 16
2062/* MC firmware build name (as null-terminated US-ASCII string) */
2063#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_OFST 296
2064#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_LEN 64
2065
2066
2067/***********************************/
2068/* MC_CMD_LOG_CTRL
2069 * Configure the output stream for log events such as link state changes,
2070 * sensor notifications and MCDI completions
2071 */
2072#define MC_CMD_LOG_CTRL 0x7
2073#undef MC_CMD_0x7_PRIVILEGE_CTG
2074
2075#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2076
2077/* MC_CMD_LOG_CTRL_IN msgrequest */
2078#define MC_CMD_LOG_CTRL_IN_LEN 8
2079/* Log destination */
2080#define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
2081#define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
2082/* enum property: bitmask */
2083/* enum: UART. */
2084#define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
2085/* enum: Event queue. */
2086#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
2087/* Legacy argument. Must be zero. */
2088#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
2089#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4
2090
2091/* MC_CMD_LOG_CTRL_OUT msgresponse */
2092#define MC_CMD_LOG_CTRL_OUT_LEN 0
2093
2094
2095/***********************************/
2096/* MC_CMD_GET_VERSION
2097 * Get version information about adapter components.
2098 */
2099#define MC_CMD_GET_VERSION 0x8
2100#undef MC_CMD_0x8_PRIVILEGE_CTG
2101
2102#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2103
2104/* MC_CMD_GET_VERSION_IN msgrequest */
2105#define MC_CMD_GET_VERSION_IN_LEN 0
2106
2107/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */
2108#define MC_CMD_GET_VERSION_EXT_IN_LEN 4
2109/* placeholder, set to 0 */
2110#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
2111#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
2112
2113/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */
2114#define MC_CMD_GET_VERSION_V0_OUT_LEN 4
2115#define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
2116#define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
2117/* enum: Reserved version number to indicate "any" version. */
2118#define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
2119/* enum: Bootrom version value for Siena. */
2120#define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
2121/* enum: Bootrom version value for Huntington. */
2122#define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
2123/* enum: Bootrom version value for Medford2. */
2124#define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
2125
2126/* MC_CMD_GET_VERSION_OUT msgresponse */
2127#define MC_CMD_GET_VERSION_OUT_LEN 32
2128/* This is normally the UTC build time in seconds since epoch or one of the
2129 * special values listed
2130 */
2131/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2132/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2133/* Enum values, see field(s): */
2134/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2135#define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
2136#define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
2137/* 128bit mask of functions supported by the current firmware */
2138#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
2139#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
2140#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
2141#define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
2142#define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
2143#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LEN 4
2144#define MC_CMD_GET_VERSION_OUT_VERSION_LO_LBN 192
2145#define MC_CMD_GET_VERSION_OUT_VERSION_LO_WIDTH 32
2146#define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
2147#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LEN 4
2148#define MC_CMD_GET_VERSION_OUT_VERSION_HI_LBN 224
2149#define MC_CMD_GET_VERSION_OUT_VERSION_HI_WIDTH 32
2150
2151/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
2152#define MC_CMD_GET_VERSION_EXT_OUT_LEN 48
2153/* This is normally the UTC build time in seconds since epoch or one of the
2154 * special values listed
2155 */
2156/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2157/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2158/* Enum values, see field(s): */
2159/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2160#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
2161#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
2162/* 128bit mask of functions supported by the current firmware */
2163#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8
2164#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16
2165#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
2166#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
2167#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
2168#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LEN 4
2169#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LBN 192
2170#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_WIDTH 32
2171#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
2172#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LEN 4
2173#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LBN 224
2174#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_WIDTH 32
2175/* extra info */
2176#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
2177#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
2178
2179/* MC_CMD_GET_VERSION_V2_OUT msgresponse: Extended response providing version
2180 * information for all adapter components. For Riverhead based designs, base MC
2181 * firmware version fields refer to NMC firmware, while CMC firmware data is in
2182 * dedicated CMC fields. Flags indicate which data is present in the response
2183 * (depending on which components exist on a particular adapter)
2184 */
2185#define MC_CMD_GET_VERSION_V2_OUT_LEN 304
2186/* This is normally the UTC build time in seconds since epoch or one of the
2187 * special values listed
2188 */
2189/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2190/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2191/* Enum values, see field(s): */
2192/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2193#define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4
2194#define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4
2195/* 128bit mask of functions supported by the current firmware */
2196#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_OFST 8
2197#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_LEN 16
2198#define MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 24
2199#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 8
2200#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 24
2201#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LEN 4
2202#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LBN 192
2203#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_WIDTH 32
2204#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 28
2205#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LEN 4
2206#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LBN 224
2207#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_WIDTH 32
2208/* extra info */
2209#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 32
2210#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 16
2211/* Flags indicating which extended fields are valid */
2212#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_OFST 48
2213#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4
2214#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
2215#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2216#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2217#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
2218#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2219#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2220#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_OFST 48
2221#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_LBN 2
2222#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2223#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
2224#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
2225#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2226#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
2227#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2228#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2229#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
2230#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
2231#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2232#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
2233#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
2234#define MC_CMD_GET_VERSION_V2_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2235#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
2236#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
2237#define MC_CMD_GET_VERSION_V2_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2238#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
2239#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
2240#define MC_CMD_GET_VERSION_V2_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2241#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
2242#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
2243#define MC_CMD_GET_VERSION_V2_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2244#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
2245#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
2246#define MC_CMD_GET_VERSION_V2_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2247#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_OFST 48
2248#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_LBN 11
2249#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2250#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_OFST 48
2251#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_LBN 12
2252#define MC_CMD_GET_VERSION_V2_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2253#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_OFST 48
2254#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_LBN 13
2255#define MC_CMD_GET_VERSION_V2_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2256/* MC firmware unique build ID (as binary SHA-1 value) */
2257#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 52
2258#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 20
2259/* MC firmware security level */
2260#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_OFST 72
2261#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4
2262/* MC firmware build name (as null-terminated US-ASCII string) */
2263#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_OFST 76
2264#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_LEN 64
2265/* The SUC firmware version as four numbers - a.b.c.d */
2266#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_OFST 140
2267#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4
2268#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4
2269/* SUC firmware build date (as 64-bit Unix timestamp) */
2270#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 156
2271#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 8
2272#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 156
2273#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2274#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
2275#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
2276#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 160
2277#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2278#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
2279#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
2280/* The ID of the SUC chip. This is specific to the platform but typically
2281 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2282 */
2283#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_OFST 164
2284#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4
2285/* The CMC firmware version as four numbers - a.b.c.d */
2286#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_OFST 168
2287#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4
2288#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4
2289/* CMC firmware build date (as 64-bit Unix timestamp) */
2290#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 184
2291#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 8
2292#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 184
2293#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2294#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
2295#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
2296#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 188
2297#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2298#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
2299#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
2300/* FPGA version as three numbers. On Riverhead based systems this field uses
2301 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
2302 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2303 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2304 */
2305#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_OFST 192
2306#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4
2307#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_NUM 3
2308/* Extra FPGA revision information (as null-terminated US-ASCII string) */
2309#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_OFST 204
2310#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_LEN 16
2311/* Board name / adapter model (as null-terminated US-ASCII string) */
2312#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_OFST 220
2313#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_LEN 16
2314/* Board revision number */
2315#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_OFST 236
2316#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4
2317/* Board serial number (as null-terminated US-ASCII string) */
2318#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 240
2319#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 64
2320
2321/* MC_CMD_GET_VERSION_V3_OUT msgresponse: Extended response providing version
2322 * information for all adapter components. For Riverhead based designs, base MC
2323 * firmware version fields refer to NMC firmware, while CMC firmware data is in
2324 * dedicated CMC fields. Flags indicate which data is present in the response
2325 * (depending on which components exist on a particular adapter)
2326 */
2327#define MC_CMD_GET_VERSION_V3_OUT_LEN 328
2328/* This is normally the UTC build time in seconds since epoch or one of the
2329 * special values listed
2330 */
2331/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2332/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2333/* Enum values, see field(s): */
2334/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2335#define MC_CMD_GET_VERSION_V3_OUT_PCOL_OFST 4
2336#define MC_CMD_GET_VERSION_V3_OUT_PCOL_LEN 4
2337/* 128bit mask of functions supported by the current firmware */
2338#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_OFST 8
2339#define MC_CMD_GET_VERSION_V3_OUT_SUPPORTED_FUNCS_LEN 16
2340#define MC_CMD_GET_VERSION_V3_OUT_VERSION_OFST 24
2341#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LEN 8
2342#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_OFST 24
2343#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LEN 4
2344#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LBN 192
2345#define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_WIDTH 32
2346#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_OFST 28
2347#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LEN 4
2348#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LBN 224
2349#define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_WIDTH 32
2350/* extra info */
2351#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_OFST 32
2352#define MC_CMD_GET_VERSION_V3_OUT_EXTRA_LEN 16
2353/* Flags indicating which extended fields are valid */
2354#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_OFST 48
2355#define MC_CMD_GET_VERSION_V3_OUT_FLAGS_LEN 4
2356#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
2357#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2358#define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2359#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
2360#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2361#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2362#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_OFST 48
2363#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_LBN 2
2364#define MC_CMD_GET_VERSION_V3_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2365#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
2366#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
2367#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2368#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
2369#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2370#define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2371#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
2372#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
2373#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2374#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
2375#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
2376#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2377#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
2378#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
2379#define MC_CMD_GET_VERSION_V3_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2380#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
2381#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
2382#define MC_CMD_GET_VERSION_V3_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2383#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
2384#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
2385#define MC_CMD_GET_VERSION_V3_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2386#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
2387#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
2388#define MC_CMD_GET_VERSION_V3_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2389#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_OFST 48
2390#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_LBN 11
2391#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2392#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_OFST 48
2393#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_LBN 12
2394#define MC_CMD_GET_VERSION_V3_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2395#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_OFST 48
2396#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_LBN 13
2397#define MC_CMD_GET_VERSION_V3_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2398/* MC firmware unique build ID (as binary SHA-1 value) */
2399#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_OFST 52
2400#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_ID_LEN 20
2401/* MC firmware security level */
2402#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_OFST 72
2403#define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_LEN 4
2404/* MC firmware build name (as null-terminated US-ASCII string) */
2405#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_OFST 76
2406#define MC_CMD_GET_VERSION_V3_OUT_MCFW_BUILD_NAME_LEN 64
2407/* The SUC firmware version as four numbers - a.b.c.d */
2408#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_OFST 140
2409#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_LEN 4
2410#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_NUM 4
2411/* SUC firmware build date (as 64-bit Unix timestamp) */
2412#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_OFST 156
2413#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LEN 8
2414#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_OFST 156
2415#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2416#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
2417#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
2418#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_OFST 160
2419#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2420#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
2421#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
2422/* The ID of the SUC chip. This is specific to the platform but typically
2423 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2424 */
2425#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_OFST 164
2426#define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_LEN 4
2427/* The CMC firmware version as four numbers - a.b.c.d */
2428#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_OFST 168
2429#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_LEN 4
2430#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_NUM 4
2431/* CMC firmware build date (as 64-bit Unix timestamp) */
2432#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_OFST 184
2433#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LEN 8
2434#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_OFST 184
2435#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2436#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
2437#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
2438#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_OFST 188
2439#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2440#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
2441#define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
2442/* FPGA version as three numbers. On Riverhead based systems this field uses
2443 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
2444 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2445 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2446 */
2447#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_OFST 192
2448#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_LEN 4
2449#define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_NUM 3
2450/* Extra FPGA revision information (as null-terminated US-ASCII string) */
2451#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_OFST 204
2452#define MC_CMD_GET_VERSION_V3_OUT_FPGA_EXTRA_LEN 16
2453/* Board name / adapter model (as null-terminated US-ASCII string) */
2454#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_OFST 220
2455#define MC_CMD_GET_VERSION_V3_OUT_BOARD_NAME_LEN 16
2456/* Board revision number */
2457#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_OFST 236
2458#define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_LEN 4
2459/* Board serial number (as null-terminated US-ASCII string) */
2460#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_OFST 240
2461#define MC_CMD_GET_VERSION_V3_OUT_BOARD_SERIAL_LEN 64
2462/* The version of the datapath hardware design as three number - a.b.c */
2463#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_OFST 304
2464#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_LEN 4
2465#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_NUM 3
2466/* The version of the firmware library used to control the datapath as three
2467 * number - a.b.c
2468 */
2469#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_OFST 316
2470#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_LEN 4
2471#define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_NUM 3
2472
2473/* MC_CMD_GET_VERSION_V4_OUT msgresponse: Extended response providing SoC
2474 * version information
2475 */
2476#define MC_CMD_GET_VERSION_V4_OUT_LEN 392
2477/* This is normally the UTC build time in seconds since epoch or one of the
2478 * special values listed
2479 */
2480/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2481/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2482/* Enum values, see field(s): */
2483/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2484#define MC_CMD_GET_VERSION_V4_OUT_PCOL_OFST 4
2485#define MC_CMD_GET_VERSION_V4_OUT_PCOL_LEN 4
2486/* 128bit mask of functions supported by the current firmware */
2487#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_OFST 8
2488#define MC_CMD_GET_VERSION_V4_OUT_SUPPORTED_FUNCS_LEN 16
2489#define MC_CMD_GET_VERSION_V4_OUT_VERSION_OFST 24
2490#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LEN 8
2491#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_OFST 24
2492#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LEN 4
2493#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LBN 192
2494#define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_WIDTH 32
2495#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_OFST 28
2496#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LEN 4
2497#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LBN 224
2498#define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_WIDTH 32
2499/* extra info */
2500#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_OFST 32
2501#define MC_CMD_GET_VERSION_V4_OUT_EXTRA_LEN 16
2502/* Flags indicating which extended fields are valid */
2503#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_OFST 48
2504#define MC_CMD_GET_VERSION_V4_OUT_FLAGS_LEN 4
2505#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
2506#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2507#define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2508#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
2509#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2510#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2511#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_OFST 48
2512#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_LBN 2
2513#define MC_CMD_GET_VERSION_V4_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2514#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
2515#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
2516#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2517#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
2518#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2519#define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2520#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
2521#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
2522#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2523#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
2524#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
2525#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2526#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
2527#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
2528#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2529#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
2530#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
2531#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2532#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
2533#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
2534#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2535#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
2536#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
2537#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2538#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_OFST 48
2539#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_LBN 11
2540#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2541#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_OFST 48
2542#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_LBN 12
2543#define MC_CMD_GET_VERSION_V4_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2544#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_OFST 48
2545#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_LBN 13
2546#define MC_CMD_GET_VERSION_V4_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2547/* MC firmware unique build ID (as binary SHA-1 value) */
2548#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_OFST 52
2549#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_ID_LEN 20
2550/* MC firmware security level */
2551#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_OFST 72
2552#define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_LEN 4
2553/* MC firmware build name (as null-terminated US-ASCII string) */
2554#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_OFST 76
2555#define MC_CMD_GET_VERSION_V4_OUT_MCFW_BUILD_NAME_LEN 64
2556/* The SUC firmware version as four numbers - a.b.c.d */
2557#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_OFST 140
2558#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_LEN 4
2559#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_NUM 4
2560/* SUC firmware build date (as 64-bit Unix timestamp) */
2561#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_OFST 156
2562#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LEN 8
2563#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_OFST 156
2564#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2565#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
2566#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
2567#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_OFST 160
2568#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2569#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
2570#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
2571/* The ID of the SUC chip. This is specific to the platform but typically
2572 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2573 */
2574#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_OFST 164
2575#define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_LEN 4
2576/* The CMC firmware version as four numbers - a.b.c.d */
2577#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_OFST 168
2578#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_LEN 4
2579#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_NUM 4
2580/* CMC firmware build date (as 64-bit Unix timestamp) */
2581#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_OFST 184
2582#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LEN 8
2583#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_OFST 184
2584#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2585#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
2586#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
2587#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_OFST 188
2588#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2589#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
2590#define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
2591/* FPGA version as three numbers. On Riverhead based systems this field uses
2592 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
2593 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2594 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2595 */
2596#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_OFST 192
2597#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_LEN 4
2598#define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_NUM 3
2599/* Extra FPGA revision information (as null-terminated US-ASCII string) */
2600#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_OFST 204
2601#define MC_CMD_GET_VERSION_V4_OUT_FPGA_EXTRA_LEN 16
2602/* Board name / adapter model (as null-terminated US-ASCII string) */
2603#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_OFST 220
2604#define MC_CMD_GET_VERSION_V4_OUT_BOARD_NAME_LEN 16
2605/* Board revision number */
2606#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_OFST 236
2607#define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_LEN 4
2608/* Board serial number (as null-terminated US-ASCII string) */
2609#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_OFST 240
2610#define MC_CMD_GET_VERSION_V4_OUT_BOARD_SERIAL_LEN 64
2611/* The version of the datapath hardware design as three number - a.b.c */
2612#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_OFST 304
2613#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_LEN 4
2614#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_NUM 3
2615/* The version of the firmware library used to control the datapath as three
2616 * number - a.b.c
2617 */
2618#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_OFST 316
2619#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_LEN 4
2620#define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_NUM 3
2621/* The SOC boot version as four numbers - a.b.c.d */
2622#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_OFST 328
2623#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_LEN 4
2624#define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_NUM 4
2625/* The SOC uboot version as four numbers - a.b.c.d */
2626#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_OFST 344
2627#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_LEN 4
2628#define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_NUM 4
2629/* The SOC main rootfs version as four numbers - a.b.c.d */
2630#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
2631#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
2632#define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
2633/* The SOC recovery buildroot version as four numbers - a.b.c.d */
2634#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
2635#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
2636#define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
2637
2638/* MC_CMD_GET_VERSION_V5_OUT msgresponse: Extended response providing bundle
2639 * and board version information
2640 */
2641#define MC_CMD_GET_VERSION_V5_OUT_LEN 424
2642/* This is normally the UTC build time in seconds since epoch or one of the
2643 * special values listed
2644 */
2645/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2646/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2647/* Enum values, see field(s): */
2648/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
2649#define MC_CMD_GET_VERSION_V5_OUT_PCOL_OFST 4
2650#define MC_CMD_GET_VERSION_V5_OUT_PCOL_LEN 4
2651/* 128bit mask of functions supported by the current firmware */
2652#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_OFST 8
2653#define MC_CMD_GET_VERSION_V5_OUT_SUPPORTED_FUNCS_LEN 16
2654#define MC_CMD_GET_VERSION_V5_OUT_VERSION_OFST 24
2655#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LEN 8
2656#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_OFST 24
2657#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LEN 4
2658#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LBN 192
2659#define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_WIDTH 32
2660#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_OFST 28
2661#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LEN 4
2662#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LBN 224
2663#define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_WIDTH 32
2664/* extra info */
2665#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_OFST 32
2666#define MC_CMD_GET_VERSION_V5_OUT_EXTRA_LEN 16
2667/* Flags indicating which extended fields are valid */
2668#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_OFST 48
2669#define MC_CMD_GET_VERSION_V5_OUT_FLAGS_LEN 4
2670#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
2671#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2672#define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
2673#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
2674#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
2675#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
2676#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_OFST 48
2677#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_LBN 2
2678#define MC_CMD_GET_VERSION_V5_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
2679#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
2680#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
2681#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
2682#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
2683#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2684#define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
2685#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_OFST 48
2686#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_LBN 5
2687#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_PRESENT_WIDTH 1
2688#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_OFST 48
2689#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_LBN 6
2690#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_PRESENT_WIDTH 1
2691#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_OFST 48
2692#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_LBN 7
2693#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_PRESENT_WIDTH 1
2694#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_OFST 48
2695#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_LBN 8
2696#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_PRESENT_WIDTH 1
2697#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_OFST 48
2698#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_LBN 9
2699#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_PRESENT_WIDTH 1
2700#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_OFST 48
2701#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_LBN 10
2702#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_PRESENT_WIDTH 1
2703#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_OFST 48
2704#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_LBN 11
2705#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_PRESENT_WIDTH 1
2706#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_OFST 48
2707#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_LBN 12
2708#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_PRESENT_WIDTH 1
2709#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_OFST 48
2710#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_LBN 13
2711#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_PRESENT_WIDTH 1
2712/* MC firmware unique build ID (as binary SHA-1 value) */
2713#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_OFST 52
2714#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_ID_LEN 20
2715/* MC firmware security level */
2716#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_OFST 72
2717#define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_LEN 4
2718/* MC firmware build name (as null-terminated US-ASCII string) */
2719#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_OFST 76
2720#define MC_CMD_GET_VERSION_V5_OUT_MCFW_BUILD_NAME_LEN 64
2721/* The SUC firmware version as four numbers - a.b.c.d */
2722#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_OFST 140
2723#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_LEN 4
2724#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_NUM 4
2725/* SUC firmware build date (as 64-bit Unix timestamp) */
2726#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_OFST 156
2727#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LEN 8
2728#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_OFST 156
2729#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2730#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LBN 1248
2731#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_WIDTH 32
2732#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_OFST 160
2733#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2734#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LBN 1280
2735#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_WIDTH 32
2736/* The ID of the SUC chip. This is specific to the platform but typically
2737 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2738 */
2739#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_OFST 164
2740#define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_LEN 4
2741/* The CMC firmware version as four numbers - a.b.c.d */
2742#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_OFST 168
2743#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_LEN 4
2744#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_NUM 4
2745/* CMC firmware build date (as 64-bit Unix timestamp) */
2746#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_OFST 184
2747#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LEN 8
2748#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_OFST 184
2749#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2750#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LBN 1472
2751#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_WIDTH 32
2752#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_OFST 188
2753#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2754#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LBN 1504
2755#define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_WIDTH 32
2756/* FPGA version as three numbers. On Riverhead based systems this field uses
2757 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
2758 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2759 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2760 */
2761#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_OFST 192
2762#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_LEN 4
2763#define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_NUM 3
2764/* Extra FPGA revision information (as null-terminated US-ASCII string) */
2765#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_OFST 204
2766#define MC_CMD_GET_VERSION_V5_OUT_FPGA_EXTRA_LEN 16
2767/* Board name / adapter model (as null-terminated US-ASCII string) */
2768#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_OFST 220
2769#define MC_CMD_GET_VERSION_V5_OUT_BOARD_NAME_LEN 16
2770/* Board revision number */
2771#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_OFST 236
2772#define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_LEN 4
2773/* Board serial number (as null-terminated US-ASCII string) */
2774#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_OFST 240
2775#define MC_CMD_GET_VERSION_V5_OUT_BOARD_SERIAL_LEN 64
2776/* The version of the datapath hardware design as three number - a.b.c */
2777#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_OFST 304
2778#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_LEN 4
2779#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_NUM 3
2780/* The version of the firmware library used to control the datapath as three
2781 * number - a.b.c
2782 */
2783#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_OFST 316
2784#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_LEN 4
2785#define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_NUM 3
2786/* The SOC boot version as four numbers - a.b.c.d */
2787#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_OFST 328
2788#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_LEN 4
2789#define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_NUM 4
2790/* The SOC uboot version as four numbers - a.b.c.d */
2791#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_OFST 344
2792#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_LEN 4
2793#define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_NUM 4
2794/* The SOC main rootfs version as four numbers - a.b.c.d */
2795#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_OFST 360
2796#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
2797#define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
2798/* The SOC recovery buildroot version as four numbers - a.b.c.d */
2799#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_OFST 376
2800#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
2801#define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
2802/* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the
2803 * BOARD_REVISION field
2804 */
2805#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_OFST 392
2806#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_LEN 4
2807#define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_NUM 4
2808/* Bundle version as four numbers - a.b.c.d */
2809#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_OFST 408
2810#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_LEN 4
2811#define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_NUM 4
2812
2813
2814/***********************************/
2815/* MC_CMD_PTP
2816 * Perform PTP operation
2817 */
2818#define MC_CMD_PTP 0xb
2819#undef MC_CMD_0xb_PRIVILEGE_CTG
2820
2821#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2822
2823/* MC_CMD_PTP_IN msgrequest */
2824#define MC_CMD_PTP_IN_LEN 1
2825/* PTP operation code */
2826#define MC_CMD_PTP_IN_OP_OFST 0
2827#define MC_CMD_PTP_IN_OP_LEN 1
2828/* enum: Enable PTP packet timestamping operation. */
2829#define MC_CMD_PTP_OP_ENABLE 0x1
2830/* enum: Disable PTP packet timestamping operation. */
2831#define MC_CMD_PTP_OP_DISABLE 0x2
2832/* enum: Send a PTP packet. This operation is used on Siena and Huntington.
2833 * From Medford onwards it is not supported: on those platforms PTP transmit
2834 * timestamping is done using the fast path.
2835 */
2836#define MC_CMD_PTP_OP_TRANSMIT 0x3
2837/* enum: Read the current NIC time. */
2838#define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
2839/* enum: Get the current PTP status. Note that the clock frequency returned (in
2840 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666).
2841 */
2842#define MC_CMD_PTP_OP_STATUS 0x5
2843/* enum: Adjust the PTP NIC's time. */
2844#define MC_CMD_PTP_OP_ADJUST 0x6
2845/* enum: Synchronize host and NIC time. */
2846#define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
2847/* enum: Basic manufacturing tests. Siena PTP adapters only. */
2848#define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
2849/* enum: Packet based manufacturing tests. Siena PTP adapters only. */
2850#define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
2851/* enum: Reset some of the PTP related statistics */
2852#define MC_CMD_PTP_OP_RESET_STATS 0xa
2853/* enum: Debug operations to MC. */
2854#define MC_CMD_PTP_OP_DEBUG 0xb
2855/* enum: Read an FPGA register. Siena PTP adapters only. */
2856#define MC_CMD_PTP_OP_FPGAREAD 0xc
2857/* enum: Write an FPGA register. Siena PTP adapters only. */
2858#define MC_CMD_PTP_OP_FPGAWRITE 0xd
2859/* enum: Apply an offset to the NIC clock */
2860#define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
2861/* enum: Change the frequency correction applied to the NIC clock */
2862#define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
2863/* enum: Set the MC packet filter VLAN tags for received PTP packets.
2864 * Deprecated for Huntington onwards.
2865 */
2866#define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
2867/* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for
2868 * Huntington onwards.
2869 */
2870#define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
2871/* enum: Set the MC packet filter Domain for received PTP packets. Deprecated
2872 * for Huntington onwards.
2873 */
2874#define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
2875/* enum: Set the clock source. Required for snapper tests on Huntington and
2876 * Medford. Not implemented for Siena or Medford2.
2877 */
2878#define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
2879/* enum: Reset value of Timer Reg. Not implemented. */
2880#define MC_CMD_PTP_OP_RST_CLK 0x14
2881/* enum: Enable the forwarding of PPS events to the host */
2882#define MC_CMD_PTP_OP_PPS_ENABLE 0x15
2883/* enum: Get the time format used by this NIC for PTP operations */
2884#define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
2885/* enum: Get the clock attributes. NOTE- extended version of
2886 * MC_CMD_PTP_OP_GET_TIME_FORMAT
2887 */
2888#define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
2889/* enum: Get corrections that should be applied to the various different
2890 * timestamps
2891 */
2892#define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
2893/* enum: Subscribe to receive periodic time events indicating the current NIC
2894 * time
2895 */
2896#define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
2897/* enum: Unsubscribe to stop receiving time events */
2898#define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
2899/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS
2900 * input on the same NIC. Siena PTP adapters only.
2901 */
2902#define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
2903/* enum: Set the PTP sync status. Status is used by firmware to report to event
2904 * subscribers.
2905 */
2906#define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
2907/* enum: X4 and later adapters should use this instead of
2908 * PTP_OP_TIME_EVENT_SUBSCRIBE. Subscribe to receive periodic time events
2909 * indicating the current NIC time
2910 */
2911#define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE_V2 0x1c
2912/* enum: For X4 and later NICs. Packet timestamps and time sync events have
2913 * IS_SET and IN_SYNC flags, that indicates whether time is updated and if it
2914 * is in sync with host. Once set, IN_SYNC flag is cleared by hardware after a
2915 * software configurable time out. Host driver need to query what is set and
2916 * what is maximum supported interval, this MCDI can be used to query these.
2917 */
2918#define MC_CMD_PTP_OP_GET_SYNC_TIMEOUT 0x1d
2919
2920/* MC_CMD_PTP_IN_ENABLE msgrequest */
2921#define MC_CMD_PTP_IN_ENABLE_LEN 16
2922#define MC_CMD_PTP_IN_CMD_OFST 0
2923#define MC_CMD_PTP_IN_CMD_LEN 4
2924#define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
2925#define MC_CMD_PTP_IN_PERIPH_ID_LEN 4
2926/* Not used, initialize to 0. Events are always sent to function relative queue
2927 * 0.
2928 */
2929#define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
2930#define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
2931/* PTP timestamping mode. Not used from Huntington onwards. */
2932#define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
2933#define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
2934/* enum: PTP, version 1 */
2935#define MC_CMD_PTP_MODE_V1 0x0
2936/* enum: PTP, version 1, with VLAN headers - deprecated */
2937#define MC_CMD_PTP_MODE_V1_VLAN 0x1
2938/* enum: PTP, version 2 */
2939#define MC_CMD_PTP_MODE_V2 0x2
2940/* enum: PTP, version 2, with VLAN headers - deprecated */
2941#define MC_CMD_PTP_MODE_V2_VLAN 0x3
2942/* enum: PTP, version 2, with improved UUID filtering */
2943#define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
2944/* enum: FCoE (seconds and microseconds) */
2945#define MC_CMD_PTP_MODE_FCOE 0x5
2946
2947/* MC_CMD_PTP_IN_DISABLE msgrequest */
2948#define MC_CMD_PTP_IN_DISABLE_LEN 8
2949/* MC_CMD_PTP_IN_CMD_OFST 0 */
2950/* MC_CMD_PTP_IN_CMD_LEN 4 */
2951/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2952/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2953
2954/* MC_CMD_PTP_IN_TRANSMIT msgrequest */
2955#define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
2956#define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
2957#define MC_CMD_PTP_IN_TRANSMIT_LENMAX_MCDI2 1020
2958#define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
2959#define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)
2960/* MC_CMD_PTP_IN_CMD_OFST 0 */
2961/* MC_CMD_PTP_IN_CMD_LEN 4 */
2962/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2963/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2964/* Transmit packet length */
2965#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
2966#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
2967/* Transmit packet data */
2968#define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
2969#define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
2970#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
2971#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
2972#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM_MCDI2 1008
2973
2974/* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
2975#define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
2976/* MC_CMD_PTP_IN_CMD_OFST 0 */
2977/* MC_CMD_PTP_IN_CMD_LEN 4 */
2978/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2979/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2980
2981/* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */
2982#define MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8
2983/* MC_CMD_PTP_IN_CMD_OFST 0 */
2984/* MC_CMD_PTP_IN_CMD_LEN 4 */
2985/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2986/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2987
2988/* MC_CMD_PTP_IN_STATUS msgrequest */
2989#define MC_CMD_PTP_IN_STATUS_LEN 8
2990/* MC_CMD_PTP_IN_CMD_OFST 0 */
2991/* MC_CMD_PTP_IN_CMD_LEN 4 */
2992/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2993/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2994
2995/* MC_CMD_PTP_IN_ADJUST msgrequest */
2996#define MC_CMD_PTP_IN_ADJUST_LEN 24
2997/* MC_CMD_PTP_IN_CMD_OFST 0 */
2998/* MC_CMD_PTP_IN_CMD_LEN 4 */
2999/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3000/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3001/* Frequency adjustment 40 bit fixed point ns */
3002#define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
3003#define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
3004#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
3005#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LEN 4
3006#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LBN 64
3007#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_WIDTH 32
3008#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
3009#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LEN 4
3010#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LBN 96
3011#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_WIDTH 32
3012/* enum: Number of fractional bits in frequency adjustment */
3013#define MC_CMD_PTP_IN_ADJUST_BITS 0x28
3014/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
3015 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
3016 * field.
3017 */
3018#define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
3019/* Time adjustment in seconds */
3020#define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
3021#define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
3022/* Time adjustment major value */
3023#define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16
3024#define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
3025/* Time adjustment in nanoseconds */
3026#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
3027#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
3028/* Time adjustment minor value */
3029#define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20
3030#define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4
3031
3032/* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */
3033#define MC_CMD_PTP_IN_ADJUST_V2_LEN 28
3034/* MC_CMD_PTP_IN_CMD_OFST 0 */
3035/* MC_CMD_PTP_IN_CMD_LEN 4 */
3036/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3037/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3038/* Frequency adjustment 40 bit fixed point ns */
3039#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8
3040#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8
3041#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8
3042#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LEN 4
3043#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LBN 64
3044#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_WIDTH 32
3045#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12
3046#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LEN 4
3047#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LBN 96
3048#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_WIDTH 32
3049/* enum: Number of fractional bits in frequency adjustment */
3050/* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
3051/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
3052 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
3053 * field.
3054 */
3055/* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
3056/* Time adjustment in seconds */
3057#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16
3058#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
3059/* Time adjustment major value */
3060#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16
3061#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
3062/* Time adjustment in nanoseconds */
3063#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20
3064#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
3065/* Time adjustment minor value */
3066#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20
3067#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
3068/* Upper 32bits of major time offset adjustment */
3069#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24
3070#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4
3071
3072/* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
3073#define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
3074/* MC_CMD_PTP_IN_CMD_OFST 0 */
3075/* MC_CMD_PTP_IN_CMD_LEN 4 */
3076/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3077/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3078/* Number of time readings to capture */
3079#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
3080#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
3081/* Host address in which to write "synchronization started" indication (64
3082 * bits)
3083 */
3084#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
3085#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
3086#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
3087#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LEN 4
3088#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LBN 96
3089#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_WIDTH 32
3090#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
3091#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LEN 4
3092#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LBN 128
3093#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_WIDTH 32
3094
3095/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
3096#define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
3097/* MC_CMD_PTP_IN_CMD_OFST 0 */
3098/* MC_CMD_PTP_IN_CMD_LEN 4 */
3099/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3100/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3101
3102/* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
3103#define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
3104/* MC_CMD_PTP_IN_CMD_OFST 0 */
3105/* MC_CMD_PTP_IN_CMD_LEN 4 */
3106/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3107/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3108/* Enable or disable packet testing */
3109#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
3110#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
3111
3112/* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */
3113#define MC_CMD_PTP_IN_RESET_STATS_LEN 8
3114/* MC_CMD_PTP_IN_CMD_OFST 0 */
3115/* MC_CMD_PTP_IN_CMD_LEN 4 */
3116/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3117/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3118
3119/* MC_CMD_PTP_IN_DEBUG msgrequest */
3120#define MC_CMD_PTP_IN_DEBUG_LEN 12
3121/* MC_CMD_PTP_IN_CMD_OFST 0 */
3122/* MC_CMD_PTP_IN_CMD_LEN 4 */
3123/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3124/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3125/* Debug operations */
3126#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
3127#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4
3128
3129/* MC_CMD_PTP_IN_FPGAREAD msgrequest */
3130#define MC_CMD_PTP_IN_FPGAREAD_LEN 16
3131/* MC_CMD_PTP_IN_CMD_OFST 0 */
3132/* MC_CMD_PTP_IN_CMD_LEN 4 */
3133/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3134/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3135#define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8
3136#define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
3137#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12
3138#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4
3139
3140/* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
3141#define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
3142#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
3143#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX_MCDI2 1020
3144#define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
3145#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)
3146/* MC_CMD_PTP_IN_CMD_OFST 0 */
3147/* MC_CMD_PTP_IN_CMD_LEN 4 */
3148/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3149/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3150#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8
3151#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
3152#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12
3153#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
3154#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
3155#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
3156#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM_MCDI2 1008
3157
3158/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
3159#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
3160/* MC_CMD_PTP_IN_CMD_OFST 0 */
3161/* MC_CMD_PTP_IN_CMD_LEN 4 */
3162/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3163/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3164/* Time adjustment in seconds */
3165#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
3166#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
3167/* Time adjustment major value */
3168#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8
3169#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
3170/* Time adjustment in nanoseconds */
3171#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
3172#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
3173/* Time adjustment minor value */
3174#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12
3175#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4
3176
3177/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */
3178#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20
3179/* MC_CMD_PTP_IN_CMD_OFST 0 */
3180/* MC_CMD_PTP_IN_CMD_LEN 4 */
3181/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3182/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3183/* Time adjustment in seconds */
3184#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8
3185#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
3186/* Time adjustment major value */
3187#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8
3188#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
3189/* Time adjustment in nanoseconds */
3190#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12
3191#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
3192/* Time adjustment minor value */
3193#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12
3194#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
3195/* Upper 32bits of major time offset adjustment */
3196#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16
3197#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4
3198
3199/* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
3200#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
3201/* MC_CMD_PTP_IN_CMD_OFST 0 */
3202/* MC_CMD_PTP_IN_CMD_LEN 4 */
3203/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3204/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3205/* Frequency adjustment 40 bit fixed point ns */
3206#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
3207#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
3208#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
3209#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LEN 4
3210#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LBN 64
3211#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_WIDTH 32
3212#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
3213#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LEN 4
3214#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LBN 96
3215#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_WIDTH 32
3216/* Enum values, see field(s): */
3217/* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */
3218
3219/* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
3220#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
3221/* MC_CMD_PTP_IN_CMD_OFST 0 */
3222/* MC_CMD_PTP_IN_CMD_LEN 4 */
3223/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3224/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3225/* Number of VLAN tags, 0 if not VLAN */
3226#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
3227#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
3228/* Set of VLAN tags to filter against */
3229#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
3230#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
3231#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3
3232
3233/* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */
3234#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
3235/* MC_CMD_PTP_IN_CMD_OFST 0 */
3236/* MC_CMD_PTP_IN_CMD_LEN 4 */
3237/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3238/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3239/* 1 to enable UUID filtering, 0 to disable */
3240#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
3241#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
3242/* UUID to filter against */
3243#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
3244#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
3245#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
3246#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LEN 4
3247#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LBN 96
3248#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_WIDTH 32
3249#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
3250#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LEN 4
3251#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LBN 128
3252#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_WIDTH 32
3253
3254/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
3255#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
3256/* MC_CMD_PTP_IN_CMD_OFST 0 */
3257/* MC_CMD_PTP_IN_CMD_LEN 4 */
3258/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3259/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3260/* 1 to enable Domain filtering, 0 to disable */
3261#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
3262#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
3263/* Domain number to filter against */
3264#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
3265#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4
3266
3267/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */
3268#define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12
3269/* MC_CMD_PTP_IN_CMD_OFST 0 */
3270/* MC_CMD_PTP_IN_CMD_LEN 4 */
3271/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3272/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3273/* Set the clock source. */
3274#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8
3275#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
3276/* enum: Internal. */
3277#define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
3278/* enum: External. */
3279#define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
3280
3281/* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */
3282#define MC_CMD_PTP_IN_RST_CLK_LEN 8
3283/* MC_CMD_PTP_IN_CMD_OFST 0 */
3284/* MC_CMD_PTP_IN_CMD_LEN 4 */
3285/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3286/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3287
3288/* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
3289#define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
3290/* MC_CMD_PTP_IN_CMD_OFST 0 */
3291/* MC_CMD_PTP_IN_CMD_LEN 4 */
3292/* Enable or disable */
3293#define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
3294#define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
3295/* enum: Enable */
3296#define MC_CMD_PTP_ENABLE_PPS 0x0
3297/* enum: Disable */
3298#define MC_CMD_PTP_DISABLE_PPS 0x1
3299/* Not used, initialize to 0. Events are always sent to function relative queue
3300 * 0.
3301 */
3302#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
3303#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4
3304
3305/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */
3306#define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8
3307/* MC_CMD_PTP_IN_CMD_OFST 0 */
3308/* MC_CMD_PTP_IN_CMD_LEN 4 */
3309/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3310/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3311
3312/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */
3313#define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8
3314/* MC_CMD_PTP_IN_CMD_OFST 0 */
3315/* MC_CMD_PTP_IN_CMD_LEN 4 */
3316/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3317/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3318
3319/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */
3320#define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8
3321/* MC_CMD_PTP_IN_CMD_OFST 0 */
3322/* MC_CMD_PTP_IN_CMD_LEN 4 */
3323/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3324/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3325
3326/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */
3327#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12
3328/* MC_CMD_PTP_IN_CMD_OFST 0 */
3329/* MC_CMD_PTP_IN_CMD_LEN 4 */
3330/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3331/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3332/* Original field containing queue ID. Now extended to include flags. */
3333#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8
3334#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
3335#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_OFST 8
3336#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
3337#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16
3338#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_OFST 8
3339#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31
3340#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1
3341
3342/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */
3343#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16
3344/* MC_CMD_PTP_IN_CMD_OFST 0 */
3345/* MC_CMD_PTP_IN_CMD_LEN 4 */
3346/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3347/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3348/* Unsubscribe options */
3349#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8
3350#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
3351/* enum: Unsubscribe a single queue */
3352#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
3353/* enum: Unsubscribe all queues */
3354#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
3355/* Event queue ID */
3356#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
3357#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
3358
3359/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2 msgrequest */
3360#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_LEN 16
3361/* MC_CMD_PTP_IN_CMD_OFST 0 */
3362/* MC_CMD_PTP_IN_CMD_LEN 4 */
3363/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3364/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3365/* Event queue ID */
3366#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_QUEUE_ID_OFST 8
3367#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_QUEUE_ID_LEN 4
3368/* Space for flags. */
3369#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_FLAGS_OFST 12
3370#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_FLAGS_LEN 4
3371#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_OFST 12
3372#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_LBN 31
3373#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_REPORT_SYNC_STATUS_WIDTH 1
3374
3375/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
3376#define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
3377/* MC_CMD_PTP_IN_CMD_OFST 0 */
3378/* MC_CMD_PTP_IN_CMD_LEN 4 */
3379/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3380/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3381/* 1 to enable PPS test mode, 0 to disable and return result. */
3382#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8
3383#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4
3384
3385/* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */
3386#define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24
3387/* MC_CMD_PTP_IN_CMD_OFST 0 */
3388/* MC_CMD_PTP_IN_CMD_LEN 4 */
3389/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3390/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3391/* NIC - Host System Clock Synchronization status */
3392#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8
3393#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
3394/* enum: Host System clock and NIC clock are not in sync */
3395#define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
3396/* enum: Host System clock and NIC clock are synchronized */
3397#define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
3398/* If synchronized, number of seconds until clocks should be considered to be
3399 * no longer in sync.
3400 */
3401#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12
3402#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
3403#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16
3404#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
3405#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20
3406#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
3407
3408/* MC_CMD_PTP_IN_GET_SYNC_TIMEOUT msgrequest */
3409#define MC_CMD_PTP_IN_GET_SYNC_TIMEOUT_LEN 8
3410/* MC_CMD_PTP_IN_CMD_OFST 0 */
3411/* MC_CMD_PTP_IN_CMD_LEN 4 */
3412/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3413/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3414
3415/* MC_CMD_PTP_OUT msgresponse */
3416#define MC_CMD_PTP_OUT_LEN 0
3417
3418/* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
3419#define MC_CMD_PTP_OUT_TRANSMIT_LEN 8
3420/* Value of seconds timestamp */
3421#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
3422#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
3423/* Timestamp major value */
3424#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
3425#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
3426/* Value of nanoseconds timestamp */
3427#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
3428#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
3429/* Timestamp minor value */
3430#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
3431#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4
3432
3433/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */
3434#define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
3435
3436/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */
3437#define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
3438
3439/* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
3440#define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
3441/* Value of seconds timestamp */
3442#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
3443#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
3444/* Timestamp major value */
3445#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
3446#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
3447/* Value of nanoseconds timestamp */
3448#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
3449#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
3450/* Timestamp minor value */
3451#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
3452#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
3453
3454/* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */
3455#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12
3456/* Value of seconds timestamp */
3457#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
3458#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
3459/* Timestamp major value */
3460#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
3461#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
3462/* Value of nanoseconds timestamp */
3463#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
3464#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
3465/* Timestamp minor value */
3466#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
3467#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
3468/* Upper 32bits of major timestamp value */
3469#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8
3470#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
3471
3472/* MC_CMD_PTP_OUT_STATUS msgresponse */
3473#define MC_CMD_PTP_OUT_STATUS_LEN 64
3474/* Frequency of NIC's hardware clock */
3475#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
3476#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
3477/* Number of packets transmitted and timestamped */
3478#define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
3479#define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
3480/* Number of packets received and timestamped */
3481#define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
3482#define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
3483/* Number of packets timestamped by the FPGA */
3484#define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
3485#define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
3486/* Number of packets filter matched */
3487#define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
3488#define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
3489/* Number of packets not filter matched */
3490#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
3491#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
3492/* Number of PPS overflows (noise on input?) */
3493#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
3494#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
3495/* Number of PPS bad periods */
3496#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
3497#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
3498/* Minimum period of PPS pulse in nanoseconds */
3499#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
3500#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
3501/* Maximum period of PPS pulse in nanoseconds */
3502#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
3503#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
3504/* Last period of PPS pulse in nanoseconds */
3505#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
3506#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
3507/* Mean period of PPS pulse in nanoseconds */
3508#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
3509#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
3510/* Minimum offset of PPS pulse in nanoseconds (signed) */
3511#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
3512#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
3513/* Maximum offset of PPS pulse in nanoseconds (signed) */
3514#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
3515#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
3516/* Last offset of PPS pulse in nanoseconds (signed) */
3517#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
3518#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
3519/* Mean offset of PPS pulse in nanoseconds (signed) */
3520#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
3521#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
3522
3523/* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
3524#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
3525#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
3526#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX_MCDI2 1020
3527#define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
3528#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
3529/* A set of host and NIC times */
3530#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
3531#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
3532#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
3533#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
3534#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM_MCDI2 51
3535/* Host time immediately before NIC's hardware clock read */
3536#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
3537#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
3538/* Value of seconds timestamp */
3539#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
3540#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
3541/* Timestamp major value */
3542#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
3543#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
3544/* Value of nanoseconds timestamp */
3545#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
3546#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
3547/* Timestamp minor value */
3548#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8
3549#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
3550/* Host time immediately after NIC's hardware clock read */
3551#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
3552#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
3553/* Number of nanoseconds waited after reading NIC's hardware clock */
3554#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
3555#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
3556
3557/* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
3558#define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
3559/* Results of testing */
3560#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
3561#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
3562/* enum: Successful test */
3563#define MC_CMD_PTP_MANF_SUCCESS 0x0
3564/* enum: FPGA load failed */
3565#define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
3566/* enum: FPGA version invalid */
3567#define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
3568/* enum: FPGA registers incorrect */
3569#define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
3570/* enum: Oscillator possibly not working? */
3571#define MC_CMD_PTP_MANF_OSCILLATOR 0x4
3572/* enum: Timestamps not increasing */
3573#define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
3574/* enum: Mismatched packet count */
3575#define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
3576/* enum: Mismatched packet count (Siena filter and FPGA) */
3577#define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
3578/* enum: Not enough packets to perform timestamp check */
3579#define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
3580/* enum: Timestamp trigger GPIO not working */
3581#define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
3582/* enum: Insufficient PPS events to perform checks */
3583#define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
3584/* enum: PPS time event period not sufficiently close to 1s. */
3585#define MC_CMD_PTP_MANF_PPS_PERIOD 0xb
3586/* enum: PPS time event nS reading not sufficiently close to zero. */
3587#define MC_CMD_PTP_MANF_PPS_NS 0xc
3588/* enum: PTP peripheral registers incorrect */
3589#define MC_CMD_PTP_MANF_REGISTERS 0xd
3590/* enum: Failed to read time from PTP peripheral */
3591#define MC_CMD_PTP_MANF_CLOCK_READ 0xe
3592/* Presence of external oscillator */
3593#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
3594#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
3595
3596/* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
3597#define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
3598/* Results of testing */
3599#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
3600#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
3601/* Number of packets received by FPGA */
3602#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
3603#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
3604/* Number of packets received by Siena filters */
3605#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
3606#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
3607
3608/* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
3609#define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
3610#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
3611#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX_MCDI2 1020
3612#define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
3613#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
3614#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
3615#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
3616#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
3617#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
3618#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM_MCDI2 1020
3619
3620/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */
3621#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
3622/* Time format required/used by for this NIC. Applies to all PTP MCDI
3623 * operations that pass times between the host and firmware. If this operation
3624 * is not supported (older firmware) a format of seconds and nanoseconds should
3625 * be assumed. Note this enum is deprecated. Do not add to it- use the
3626 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead.
3627 */
3628#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
3629#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
3630/* enum: Times are in seconds and nanoseconds */
3631#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
3632/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
3633#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
3634/* enum: Major register has units of seconds, minor 2^-27s per tick */
3635#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
3636
3637/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */
3638#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24
3639/* Time format required/used by for this NIC. Applies to all PTP MCDI
3640 * operations that pass times between the host and firmware. If this operation
3641 * is not supported (older firmware) a format of seconds and nanoseconds should
3642 * be assumed.
3643 */
3644#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
3645#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
3646/* enum: Times are in seconds and nanoseconds */
3647#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
3648/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
3649#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
3650/* enum: Major register has units of seconds, minor 2^-27s per tick */
3651#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
3652/* enum: Major register units are seconds, minor units are quarter nanoseconds
3653 */
3654#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
3655/* Minimum acceptable value for a corrected synchronization timeset. When
3656 * comparing host and NIC clock times, the MC returns a set of samples that
3657 * contain the host start and end time, the MC time when the host start was
3658 * detected and the time the MC waited between reading the time and detecting
3659 * the host end. The corrected sync window is the difference between the host
3660 * end and start times minus the time that the MC waited for host end.
3661 */
3662#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
3663#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
3664/* Various PTP capabilities */
3665#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8
3666#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
3667#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_OFST 8
3668#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
3669#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
3670#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_OFST 8
3671#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1
3672#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1
3673#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_OFST 8
3674#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2
3675#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1
3676#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_OFST 8
3677#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3
3678#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1
3679#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12
3680#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
3681#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16
3682#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
3683#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20
3684#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
3685
3686/* MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2 msgresponse */
3687#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_LEN 40
3688/* Time format required/used by for this NIC. Applies to all PTP MCDI
3689 * operations that pass times between the host and firmware. If this operation
3690 * is not supported (older firmware) a format of seconds and nanoseconds should
3691 * be assumed.
3692 */
3693#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_OFST 0
3694#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_LEN 4
3695/* enum: Times are in seconds and nanoseconds */
3696#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_NANOSECONDS 0x0
3697/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
3698#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_16SECONDS_8NANOSECONDS 0x1
3699/* enum: Major register has units of seconds, minor 2^-27s per tick */
3700#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_27FRACTION 0x2
3701/* enum: Major register units are seconds, minor units are quarter nanoseconds
3702 */
3703#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_QTR_NANOSECONDS 0x3
3704/* Minimum acceptable value for a corrected synchronization timeset. When
3705 * comparing host and NIC clock times, the MC returns a set of samples that
3706 * contain the host start and end time, the MC time when the host start was
3707 * detected and the time the MC waited between reading the time and detecting
3708 * the host end. The corrected sync window is the difference between the host
3709 * end and start times minus the time that the MC waited for host end.
3710 */
3711#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_OFST 4
3712#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_LEN 4
3713/* Various PTP capabilities */
3714#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_CAPABILITIES_OFST 8
3715#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_CAPABILITIES_LEN 4
3716#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_OFST 8
3717#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_LBN 0
3718#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_WIDTH 1
3719#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_OFST 8
3720#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_LBN 1
3721#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RX_TSTAMP_OOB_WIDTH 1
3722#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_OFST 8
3723#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_LBN 2
3724#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_64BIT_SECONDS_WIDTH 1
3725#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_OFST 8
3726#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_LBN 3
3727#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FP44_FREQ_ADJ_WIDTH 1
3728#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED0_OFST 12
3729#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED0_LEN 4
3730#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED1_OFST 16
3731#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED1_LEN 4
3732#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED2_OFST 20
3733#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED2_LEN 4
3734/* Minimum supported value for the FREQ field in
3735 * MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST and
3736 * MC_CMD_PTP/MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST message requests. If this message
3737 * response is not supported a value of -0.1 ns should be assumed, which is
3738 * equivalent to a -10% adjustment.
3739 */
3740#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_OFST 24
3741#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LEN 8
3742#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_OFST 24
3743#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_LEN 4
3744#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_LBN 192
3745#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_WIDTH 32
3746#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_OFST 28
3747#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_LEN 4
3748#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_LBN 224
3749#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_WIDTH 32
3750/* Maximum supported value for the FREQ field in
3751 * MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST and
3752 * MC_CMD_PTP/MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST message requests. If this message
3753 * response is not supported a value of 0.1 ns should be assumed, which is
3754 * equivalent to a +10% adjustment.
3755 */
3756#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_OFST 32
3757#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LEN 8
3758#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_OFST 32
3759#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_LEN 4
3760#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_LBN 256
3761#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_WIDTH 32
3762#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_OFST 36
3763#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_LEN 4
3764#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_LBN 288
3765#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_WIDTH 32
3766
3767/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */
3768#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16
3769/* Uncorrected error on PTP transmit timestamps in NIC clock format */
3770#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
3771#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
3772/* Uncorrected error on PTP receive timestamps in NIC clock format */
3773#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
3774#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
3775/* Uncorrected error on PPS output in NIC clock format */
3776#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8
3777#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
3778/* Uncorrected error on PPS input in NIC clock format */
3779#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12
3780#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
3781
3782/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */
3783#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24
3784/* Uncorrected error on PTP transmit timestamps in NIC clock format */
3785#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
3786#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
3787/* Uncorrected error on PTP receive timestamps in NIC clock format */
3788#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
3789#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
3790/* Uncorrected error on PPS output in NIC clock format */
3791#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8
3792#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
3793/* Uncorrected error on PPS input in NIC clock format */
3794#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12
3795#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
3796/* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
3797#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16
3798#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
3799/* Uncorrected error on non-PTP receive timestamps in NIC clock format */
3800#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20
3801#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
3802
3803/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */
3804#define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
3805/* Results of testing */
3806#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
3807#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
3808/* Enum values, see field(s): */
3809/* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */
3810
3811/* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */
3812#define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
3813
3814/* MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT msgresponse */
3815#define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_LEN 8
3816/* Current value set in NIC, in seconds */
3817#define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_CURRENT_OFST 0
3818#define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_CURRENT_LEN 4
3819/* Maximum supported by NIC, in seconds */
3820#define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_MAXIMUM_OFST 4
3821#define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_MAXIMUM_LEN 4
3822
3823
3824/***********************************/
3825/* MC_CMD_GET_BOARD_CFG
3826 * Returns the MC firmware configuration structure.
3827 */
3828#define MC_CMD_GET_BOARD_CFG 0x18
3829#undef MC_CMD_0x18_PRIVILEGE_CTG
3830
3831#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3832
3833/* MC_CMD_GET_BOARD_CFG_IN msgrequest */
3834#define MC_CMD_GET_BOARD_CFG_IN_LEN 0
3835
3836/* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
3837#define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
3838#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
3839#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX_MCDI2 136
3840#define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
3841#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)
3842#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
3843#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
3844#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
3845#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
3846/* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on
3847 * EF10 and later (use MC_CMD_GET_CAPABILITIES).
3848 */
3849#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
3850#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
3851/* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on
3852 * EF10 and later (use MC_CMD_GET_CAPABILITIES).
3853 */
3854#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
3855#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
3856/* Base MAC address for Siena Port0. Unused on EF10 and later (use
3857 * MC_CMD_GET_MAC_ADDRESSES).
3858 */
3859#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
3860#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
3861/* Base MAC address for Siena Port1. Unused on EF10 and later (use
3862 * MC_CMD_GET_MAC_ADDRESSES).
3863 */
3864#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
3865#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
3866/* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use
3867 * MC_CMD_GET_MAC_ADDRESSES).
3868 */
3869#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
3870#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
3871/* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use
3872 * MC_CMD_GET_MAC_ADDRESSES).
3873 */
3874#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
3875#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
3876/* Increment between addresses in MAC address pool for Siena Port0. Unused on
3877 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
3878 */
3879#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
3880#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
3881/* Increment between addresses in MAC address pool for Siena Port1. Unused on
3882 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
3883 */
3884#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
3885#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
3886/* Siena only. This field contains a 16-bit value for each of the types of
3887 * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a
3888 * specific board type, but otherwise have no meaning to the MC; they are used
3889 * by the driver to manage selection of appropriate firmware updates. Unused on
3890 * EF10 and later (use MC_CMD_NVRAM_METADATA).
3891 */
3892#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
3893#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
3894#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
3895#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
3896#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM_MCDI2 32
3897
3898
3899/***********************************/
3900/* MC_CMD_DRV_ATTACH
3901 * Inform MCPU that this port is managed on the host (i.e. driver active). For
3902 * Huntington, also request the preferred datapath firmware to use if possible
3903 * (it may not be possible for this request to be fulfilled; the driver must
3904 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which
3905 * features are actually available). The FIRMWARE_ID field is ignored by older
3906 * platforms.
3907 */
3908#define MC_CMD_DRV_ATTACH 0x1c
3909#undef MC_CMD_0x1c_PRIVILEGE_CTG
3910
3911#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3912
3913/* MC_CMD_DRV_ATTACH_IN msgrequest */
3914#define MC_CMD_DRV_ATTACH_IN_LEN 12
3915/* new state to set if UPDATE=1 */
3916#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
3917#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
3918#define MC_CMD_DRV_ATTACH_OFST 0
3919#define MC_CMD_DRV_ATTACH_LBN 0
3920#define MC_CMD_DRV_ATTACH_WIDTH 1
3921#define MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0
3922#define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
3923#define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
3924#define MC_CMD_DRV_PREBOOT_OFST 0
3925#define MC_CMD_DRV_PREBOOT_LBN 1
3926#define MC_CMD_DRV_PREBOOT_WIDTH 1
3927#define MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0
3928#define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
3929#define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
3930#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0
3931#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2
3932#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
3933#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0
3934#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3
3935#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1
3936#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0
3937#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4
3938#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 1
3939#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
3940#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
3941#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
3942#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0
3943#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_LBN 5
3944#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 1
3945/* 1 to set new state, or 0 to just report the existing state */
3946#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
3947#define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
3948/* preferred datapath firmware (for Huntington; ignored for Siena) */
3949#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8
3950#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
3951/* enum: Prefer to use full featured firmware */
3952#define MC_CMD_FW_FULL_FEATURED 0x0
3953/* enum: Prefer to use firmware with fewer features but lower latency */
3954#define MC_CMD_FW_LOW_LATENCY 0x1
3955/* enum: Prefer to use firmware for SolarCapture packed stream mode */
3956#define MC_CMD_FW_PACKED_STREAM 0x2
3957/* enum: Prefer to use firmware with fewer features and simpler TX event
3958 * batching but higher TX packet rate
3959 */
3960#define MC_CMD_FW_HIGH_TX_RATE 0x3
3961/* enum: Reserved value */
3962#define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
3963/* enum: Prefer to use firmware with additional "rules engine" filtering
3964 * support
3965 */
3966#define MC_CMD_FW_RULES_ENGINE 0x5
3967/* enum: Prefer to use firmware with additional DPDK support */
3968#define MC_CMD_FW_DPDK 0x6
3969/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
3970 * bug69716)
3971 */
3972#define MC_CMD_FW_L3XUDP 0x7
3973/* enum: Requests that the MC keep whatever datapath firmware is currently
3974 * running. It's used for test purposes, where we want to be able to shmboot
3975 * special test firmware variants. This option is only recognised in eftest
3976 * (i.e. non-production) builds.
3977 */
3978#define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe
3979/* enum: Only this option is allowed for non-admin functions */
3980#define MC_CMD_FW_DONT_CARE 0xffffffff
3981
3982/* MC_CMD_DRV_ATTACH_IN_V2 msgrequest: Updated DRV_ATTACH to include driver
3983 * version
3984 */
3985#define MC_CMD_DRV_ATTACH_IN_V2_LEN 32
3986/* new state to set if UPDATE=1 */
3987#define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0
3988#define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4
3989/* MC_CMD_DRV_ATTACH_OFST 0 */
3990/* MC_CMD_DRV_ATTACH_LBN 0 */
3991/* MC_CMD_DRV_ATTACH_WIDTH 1 */
3992#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0
3993#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0
3994#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 1
3995/* MC_CMD_DRV_PREBOOT_OFST 0 */
3996/* MC_CMD_DRV_PREBOOT_LBN 1 */
3997/* MC_CMD_DRV_PREBOOT_WIDTH 1 */
3998#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0
3999#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 1
4000#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 1
4001#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0
4002#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_LBN 2
4003#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 1
4004#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0
4005#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_LBN 3
4006#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 1
4007#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0
4008#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4
4009#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 1
4010#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
4011#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
4012#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
4013#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0
4014#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_LBN 5
4015#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 1
4016/* 1 to set new state, or 0 to just report the existing state */
4017#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4
4018#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4
4019/* preferred datapath firmware (for Huntington; ignored for Siena) */
4020#define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_OFST 8
4021#define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4
4022/* enum: Prefer to use full featured firmware */
4023/* MC_CMD_FW_FULL_FEATURED 0x0 */
4024/* enum: Prefer to use firmware with fewer features but lower latency */
4025/* MC_CMD_FW_LOW_LATENCY 0x1 */
4026/* enum: Prefer to use firmware for SolarCapture packed stream mode */
4027/* MC_CMD_FW_PACKED_STREAM 0x2 */
4028/* enum: Prefer to use firmware with fewer features and simpler TX event
4029 * batching but higher TX packet rate
4030 */
4031/* MC_CMD_FW_HIGH_TX_RATE 0x3 */
4032/* enum: Reserved value */
4033/* MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */
4034/* enum: Prefer to use firmware with additional "rules engine" filtering
4035 * support
4036 */
4037/* MC_CMD_FW_RULES_ENGINE 0x5 */
4038/* enum: Prefer to use firmware with additional DPDK support */
4039/* MC_CMD_FW_DPDK 0x6 */
4040/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
4041 * bug69716)
4042 */
4043/* MC_CMD_FW_L3XUDP 0x7 */
4044/* enum: Requests that the MC keep whatever datapath firmware is currently
4045 * running. It's used for test purposes, where we want to be able to shmboot
4046 * special test firmware variants. This option is only recognised in eftest
4047 * (i.e. non-production) builds.
4048 */
4049/* MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */
4050/* enum: Only this option is allowed for non-admin functions */
4051/* MC_CMD_FW_DONT_CARE 0xffffffff */
4052/* Version of the driver to be reported by management protocols (e.g. NC-SI)
4053 * handled by the NIC. This is a zero-terminated ASCII string.
4054 */
4055#define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_OFST 12
4056#define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN 20
4057
4058/* MC_CMD_DRV_ATTACH_OUT msgresponse */
4059#define MC_CMD_DRV_ATTACH_OUT_LEN 4
4060/* previous or existing state, see the bitmask at NEW_STATE */
4061#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
4062#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
4063
4064/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */
4065#define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8
4066/* previous or existing state, see the bitmask at NEW_STATE */
4067#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
4068#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
4069/* Flags associated with this function */
4070#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
4071#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
4072/* enum property: bitshift */
4073/* enum: Labels the lowest-numbered function visible to the OS */
4074#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
4075/* enum: The function can control the link state of the physical port it is
4076 * bound to.
4077 */
4078#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
4079/* enum: The function can perform privileged operations */
4080#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
4081/* enum: The function does not have an active port associated with it. The port
4082 * refers to the Sorrento external FPGA port.
4083 */
4084#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
4085/* enum: If set, indicates that VI spreading is currently enabled. Will always
4086 * indicate the current state, regardless of the value in the WANT_VI_SPREADING
4087 * input.
4088 */
4089#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
4090/* enum: Used during development only. Should no longer be used. */
4091#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5
4092/* enum: If set, indicates that TX only spreading is enabled. Even-numbered
4093 * TXQs will use one engine, and odd-numbered TXQs will use the other. This
4094 * also has the effect that only even-numbered RXQs will receive traffic.
4095 */
4096#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5
4097
4098
4099/***********************************/
4100/* MC_CMD_PORT_RESET
4101 * Generic per-port reset. There is no equivalent for per-board reset. Locks
4102 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
4103 * use MC_CMD_ENTITY_RESET instead.
4104 */
4105#define MC_CMD_PORT_RESET 0x20
4106#undef MC_CMD_0x20_PRIVILEGE_CTG
4107
4108#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4109
4110/* MC_CMD_PORT_RESET_IN msgrequest */
4111#define MC_CMD_PORT_RESET_IN_LEN 0
4112
4113/* MC_CMD_PORT_RESET_OUT msgresponse */
4114#define MC_CMD_PORT_RESET_OUT_LEN 0
4115
4116
4117/***********************************/
4118/* MC_CMD_ENTITY_RESET
4119 * Generic per-resource reset. There is no equivalent for per-board reset.
4120 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
4121 * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
4122 */
4123#define MC_CMD_ENTITY_RESET 0x20
4124/* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
4125
4126/* MC_CMD_ENTITY_RESET_IN msgrequest */
4127#define MC_CMD_ENTITY_RESET_IN_LEN 4
4128/* Optional flags field. Omitting this will perform a "legacy" reset action
4129 * (TBD).
4130 */
4131#define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
4132#define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
4133#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 0
4134#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
4135#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
4136
4137/* MC_CMD_ENTITY_RESET_OUT msgresponse */
4138#define MC_CMD_ENTITY_RESET_OUT_LEN 0
4139
4140
4141/***********************************/
4142/* MC_CMD_PUTS
4143 * Copy the given ASCII string out onto UART and/or out of the network port.
4144 */
4145#define MC_CMD_PUTS 0x23
4146#undef MC_CMD_0x23_PRIVILEGE_CTG
4147
4148#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE
4149
4150/* MC_CMD_PUTS_IN msgrequest */
4151#define MC_CMD_PUTS_IN_LENMIN 13
4152#define MC_CMD_PUTS_IN_LENMAX 252
4153#define MC_CMD_PUTS_IN_LENMAX_MCDI2 1020
4154#define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
4155#define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)
4156#define MC_CMD_PUTS_IN_DEST_OFST 0
4157#define MC_CMD_PUTS_IN_DEST_LEN 4
4158#define MC_CMD_PUTS_IN_UART_OFST 0
4159#define MC_CMD_PUTS_IN_UART_LBN 0
4160#define MC_CMD_PUTS_IN_UART_WIDTH 1
4161#define MC_CMD_PUTS_IN_PORT_OFST 0
4162#define MC_CMD_PUTS_IN_PORT_LBN 1
4163#define MC_CMD_PUTS_IN_PORT_WIDTH 1
4164#define MC_CMD_PUTS_IN_DHOST_OFST 4
4165#define MC_CMD_PUTS_IN_DHOST_LEN 6
4166#define MC_CMD_PUTS_IN_STRING_OFST 12
4167#define MC_CMD_PUTS_IN_STRING_LEN 1
4168#define MC_CMD_PUTS_IN_STRING_MINNUM 1
4169#define MC_CMD_PUTS_IN_STRING_MAXNUM 240
4170#define MC_CMD_PUTS_IN_STRING_MAXNUM_MCDI2 1008
4171
4172/* MC_CMD_PUTS_OUT msgresponse */
4173#define MC_CMD_PUTS_OUT_LEN 0
4174
4175
4176/***********************************/
4177/* MC_CMD_GET_PHY_CFG
4178 * Report PHY configuration. This guarantees to succeed even if the PHY is in a
4179 * 'zombie' state. Locks required: None
4180 */
4181#define MC_CMD_GET_PHY_CFG 0x24
4182#undef MC_CMD_0x24_PRIVILEGE_CTG
4183
4184#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4185
4186/* MC_CMD_GET_PHY_CFG_IN msgrequest */
4187#define MC_CMD_GET_PHY_CFG_IN_LEN 0
4188
4189/* MC_CMD_GET_PHY_CFG_IN_V2 msgrequest */
4190#define MC_CMD_GET_PHY_CFG_IN_V2_LEN 8
4191/* Target port to request PHY state for. Uses MAE_LINK_ENDPOINT_SELECTOR which
4192 * identifies a real or virtual network port by MAE port and link end. See the
4193 * structure definition for more details
4194 */
4195#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_OFST 0
4196#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LEN 8
4197#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LO_OFST 0
4198#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LO_LEN 4
4199#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LO_LBN 0
4200#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LO_WIDTH 32
4201#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_HI_OFST 4
4202#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_HI_LEN 4
4203#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_HI_LBN 32
4204#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_HI_WIDTH 32
4205/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
4206#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_OFST 0
4207#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_LEN 4
4208#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0
4209#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4
4210#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_TYPE_OFST 3
4211#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_TYPE_LEN 1
4212#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
4213#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
4214#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
4215#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
4216#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
4217#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
4218#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
4219#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
4220#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
4221#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
4222#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
4223#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
4224#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LINK_END_OFST 4
4225#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LINK_END_LEN 4
4226#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_OFST 0
4227#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LEN 8
4228#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LO_OFST 0
4229#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LO_LEN 4
4230#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LO_LBN 0
4231#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LO_WIDTH 32
4232#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_HI_OFST 4
4233#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_HI_LEN 4
4234#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_HI_LBN 32
4235#define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_HI_WIDTH 32
4236
4237/* MC_CMD_GET_PHY_CFG_OUT msgresponse */
4238#define MC_CMD_GET_PHY_CFG_OUT_LEN 72
4239/* flags */
4240#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
4241#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
4242#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 0
4243#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
4244#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
4245#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 0
4246#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
4247#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
4248#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 0
4249#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
4250#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
4251#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 0
4252#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
4253#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
4254#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 0
4255#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
4256#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
4257#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 0
4258#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
4259#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
4260#define MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 0
4261#define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
4262#define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
4263/* ?? */
4264#define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
4265#define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
4266/* Bitmask of supported capabilities */
4267#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
4268#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
4269#define MC_CMD_PHY_CAP_10HDX_OFST 8
4270#define MC_CMD_PHY_CAP_10HDX_LBN 1
4271#define MC_CMD_PHY_CAP_10HDX_WIDTH 1
4272#define MC_CMD_PHY_CAP_10FDX_OFST 8
4273#define MC_CMD_PHY_CAP_10FDX_LBN 2
4274#define MC_CMD_PHY_CAP_10FDX_WIDTH 1
4275#define MC_CMD_PHY_CAP_100HDX_OFST 8
4276#define MC_CMD_PHY_CAP_100HDX_LBN 3
4277#define MC_CMD_PHY_CAP_100HDX_WIDTH 1
4278#define MC_CMD_PHY_CAP_100FDX_OFST 8
4279#define MC_CMD_PHY_CAP_100FDX_LBN 4
4280#define MC_CMD_PHY_CAP_100FDX_WIDTH 1
4281#define MC_CMD_PHY_CAP_1000HDX_OFST 8
4282#define MC_CMD_PHY_CAP_1000HDX_LBN 5
4283#define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
4284#define MC_CMD_PHY_CAP_1000FDX_OFST 8
4285#define MC_CMD_PHY_CAP_1000FDX_LBN 6
4286#define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
4287#define MC_CMD_PHY_CAP_10000FDX_OFST 8
4288#define MC_CMD_PHY_CAP_10000FDX_LBN 7
4289#define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
4290#define MC_CMD_PHY_CAP_PAUSE_OFST 8
4291#define MC_CMD_PHY_CAP_PAUSE_LBN 8
4292#define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
4293#define MC_CMD_PHY_CAP_ASYM_OFST 8
4294#define MC_CMD_PHY_CAP_ASYM_LBN 9
4295#define MC_CMD_PHY_CAP_ASYM_WIDTH 1
4296#define MC_CMD_PHY_CAP_AN_OFST 8
4297#define MC_CMD_PHY_CAP_AN_LBN 10
4298#define MC_CMD_PHY_CAP_AN_WIDTH 1
4299#define MC_CMD_PHY_CAP_40000FDX_OFST 8
4300#define MC_CMD_PHY_CAP_40000FDX_LBN 11
4301#define MC_CMD_PHY_CAP_40000FDX_WIDTH 1
4302#define MC_CMD_PHY_CAP_DDM_OFST 8
4303#define MC_CMD_PHY_CAP_DDM_LBN 12
4304#define MC_CMD_PHY_CAP_DDM_WIDTH 1
4305#define MC_CMD_PHY_CAP_100000FDX_OFST 8
4306#define MC_CMD_PHY_CAP_100000FDX_LBN 13
4307#define MC_CMD_PHY_CAP_100000FDX_WIDTH 1
4308#define MC_CMD_PHY_CAP_25000FDX_OFST 8
4309#define MC_CMD_PHY_CAP_25000FDX_LBN 14
4310#define MC_CMD_PHY_CAP_25000FDX_WIDTH 1
4311#define MC_CMD_PHY_CAP_50000FDX_OFST 8
4312#define MC_CMD_PHY_CAP_50000FDX_LBN 15
4313#define MC_CMD_PHY_CAP_50000FDX_WIDTH 1
4314#define MC_CMD_PHY_CAP_BASER_FEC_OFST 8
4315#define MC_CMD_PHY_CAP_BASER_FEC_LBN 16
4316#define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1
4317#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_OFST 8
4318#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17
4319#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1
4320#define MC_CMD_PHY_CAP_RS_FEC_OFST 8
4321#define MC_CMD_PHY_CAP_RS_FEC_LBN 18
4322#define MC_CMD_PHY_CAP_RS_FEC_WIDTH 1
4323#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_OFST 8
4324#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19
4325#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1
4326#define MC_CMD_PHY_CAP_25G_BASER_FEC_OFST 8
4327#define MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20
4328#define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1
4329#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_OFST 8
4330#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21
4331#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1
4332#define MC_CMD_PHY_CAP_200000FDX_OFST 8
4333#define MC_CMD_PHY_CAP_200000FDX_LBN 22
4334#define MC_CMD_PHY_CAP_200000FDX_WIDTH 1
4335/* ?? */
4336#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
4337#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
4338/* ?? */
4339#define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
4340#define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
4341/* ?? */
4342#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
4343#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
4344/* ?? */
4345#define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
4346#define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
4347/* ?? */
4348#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
4349#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
4350/* enum: Xaui. */
4351#define MC_CMD_MEDIA_XAUI 0x1
4352/* enum: CX4. */
4353#define MC_CMD_MEDIA_CX4 0x2
4354/* enum: KX4. */
4355#define MC_CMD_MEDIA_KX4 0x3
4356/* enum: XFP Far. */
4357#define MC_CMD_MEDIA_XFP 0x4
4358/* enum: SFP+. */
4359#define MC_CMD_MEDIA_SFP_PLUS 0x5
4360/* enum: 10GBaseT. */
4361#define MC_CMD_MEDIA_BASE_T 0x6
4362/* enum: QSFP+. */
4363#define MC_CMD_MEDIA_QSFP_PLUS 0x7
4364/* enum: DSFP. */
4365#define MC_CMD_MEDIA_DSFP 0x8
4366#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
4367#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
4368/* enum property: bitshift */
4369/* enum: Native clause 22 */
4370#define MC_CMD_MMD_CLAUSE22 0x0
4371#define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
4372#define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
4373#define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
4374#define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
4375#define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
4376#define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
4377#define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
4378/* enum: Clause22 proxied over clause45 by PHY. */
4379#define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
4380#define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
4381#define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
4382#define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
4383#define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
4384
4385
4386/***********************************/
4387/* MC_CMD_START_BIST
4388 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST
4389 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
4390 */
4391#define MC_CMD_START_BIST 0x25
4392#undef MC_CMD_0x25_PRIVILEGE_CTG
4393
4394#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
4395
4396/* MC_CMD_START_BIST_IN msgrequest */
4397#define MC_CMD_START_BIST_IN_LEN 4
4398/* Type of test. */
4399#define MC_CMD_START_BIST_IN_TYPE_OFST 0
4400#define MC_CMD_START_BIST_IN_TYPE_LEN 4
4401/* enum: Run the PHY's short cable BIST. */
4402#define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
4403/* enum: Run the PHY's long cable BIST. */
4404#define MC_CMD_PHY_BIST_CABLE_LONG 0x2
4405/* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */
4406#define MC_CMD_BPX_SERDES_BIST 0x3
4407/* enum: Run the MC loopback tests. */
4408#define MC_CMD_MC_LOOPBACK_BIST 0x4
4409/* enum: Run the PHY's standard BIST. */
4410#define MC_CMD_PHY_BIST 0x5
4411/* enum: Run MC RAM test. */
4412#define MC_CMD_MC_MEM_BIST 0x6
4413/* enum: Run Port RAM test. */
4414#define MC_CMD_PORT_MEM_BIST 0x7
4415/* enum: Run register test. */
4416#define MC_CMD_REG_BIST 0x8
4417
4418/* MC_CMD_START_BIST_OUT msgresponse */
4419#define MC_CMD_START_BIST_OUT_LEN 0
4420
4421
4422/***********************************/
4423/* MC_CMD_POLL_BIST
4424 * Poll for BIST completion. Returns a single status code, and optionally some
4425 * PHY specific bist output. The driver should only consume the BIST output
4426 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't
4427 * successfully parse the BIST output, it should still respect the pass/Fail in
4428 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
4429 * EACCES (if PHY_LOCK is not held).
4430 */
4431#define MC_CMD_POLL_BIST 0x26
4432#undef MC_CMD_0x26_PRIVILEGE_CTG
4433
4434#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
4435
4436/* MC_CMD_POLL_BIST_IN msgrequest */
4437#define MC_CMD_POLL_BIST_IN_LEN 0
4438
4439/* MC_CMD_POLL_BIST_OUT msgresponse */
4440#define MC_CMD_POLL_BIST_OUT_LEN 8
4441/* result */
4442#define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
4443#define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
4444/* enum: Running. */
4445#define MC_CMD_POLL_BIST_RUNNING 0x1
4446/* enum: Passed. */
4447#define MC_CMD_POLL_BIST_PASSED 0x2
4448/* enum: Failed. */
4449#define MC_CMD_POLL_BIST_FAILED 0x3
4450/* enum: Timed-out. */
4451#define MC_CMD_POLL_BIST_TIMEOUT 0x4
4452#define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
4453#define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4
4454
4455/* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
4456#define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
4457/* result */
4458/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
4459/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
4460/* Enum values, see field(s): */
4461/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
4462#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
4463#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
4464#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
4465#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
4466#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
4467#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
4468#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
4469#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
4470/* Status of each channel A */
4471#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
4472#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
4473/* enum: Ok. */
4474#define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
4475/* enum: Open. */
4476#define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
4477/* enum: Intra-pair short. */
4478#define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
4479/* enum: Inter-pair short. */
4480#define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
4481/* enum: Busy. */
4482#define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
4483/* Status of each channel B */
4484#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
4485#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
4486/* Enum values, see field(s): */
4487/* CABLE_STATUS_A */
4488/* Status of each channel C */
4489#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
4490#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
4491/* Enum values, see field(s): */
4492/* CABLE_STATUS_A */
4493/* Status of each channel D */
4494#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
4495#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
4496/* Enum values, see field(s): */
4497/* CABLE_STATUS_A */
4498
4499/* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
4500#define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
4501/* result */
4502/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
4503/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
4504/* Enum values, see field(s): */
4505/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
4506#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
4507#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
4508/* enum: Complete. */
4509#define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
4510/* enum: Bus switch off I2C write. */
4511#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
4512/* enum: Bus switch off I2C no access IO exp. */
4513#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
4514/* enum: Bus switch off I2C no access module. */
4515#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
4516/* enum: IO exp I2C configure. */
4517#define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
4518/* enum: Bus switch I2C no cross talk. */
4519#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
4520/* enum: Module presence. */
4521#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
4522/* enum: Module ID I2C access. */
4523#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
4524/* enum: Module ID sane value. */
4525#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
4526
4527/* MC_CMD_POLL_BIST_OUT_MEM msgresponse */
4528#define MC_CMD_POLL_BIST_OUT_MEM_LEN 36
4529/* result */
4530/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
4531/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
4532/* Enum values, see field(s): */
4533/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
4534#define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
4535#define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
4536/* enum: Test has completed. */
4537#define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
4538/* enum: RAM test - walk ones. */
4539#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
4540/* enum: RAM test - walk zeros. */
4541#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
4542/* enum: RAM test - walking inversions zeros/ones. */
4543#define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
4544/* enum: RAM test - walking inversions checkerboard. */
4545#define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
4546/* enum: Register test - set / clear individual bits. */
4547#define MC_CMD_POLL_BIST_MEM_REG 0x5
4548/* enum: ECC error detected. */
4549#define MC_CMD_POLL_BIST_MEM_ECC 0x6
4550/* Failure address, only valid if result is POLL_BIST_FAILED */
4551#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8
4552#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
4553/* Bus or address space to which the failure address corresponds */
4554#define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12
4555#define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
4556/* enum: MC MIPS bus. */
4557#define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
4558/* enum: CSR IREG bus. */
4559#define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
4560/* enum: RX0 DPCPU bus. */
4561#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
4562/* enum: TX0 DPCPU bus. */
4563#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
4564/* enum: TX1 DPCPU bus. */
4565#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
4566/* enum: RX0 DICPU bus. */
4567#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
4568/* enum: TX DICPU bus. */
4569#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
4570/* enum: RX1 DPCPU bus. */
4571#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
4572/* enum: RX1 DICPU bus. */
4573#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
4574/* Pattern written to RAM / register */
4575#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16
4576#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
4577/* Actual value read from RAM / register */
4578#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20
4579#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
4580/* ECC error mask */
4581#define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24
4582#define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
4583/* ECC parity error mask */
4584#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28
4585#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
4586/* ECC fatal error mask */
4587#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32
4588#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4
4589
4590
4591/***********************************/
4592/* MC_CMD_GET_LOOPBACK_MODES
4593 * Returns a bitmask of loopback modes available at each speed.
4594 */
4595#define MC_CMD_GET_LOOPBACK_MODES 0x28
4596#undef MC_CMD_0x28_PRIVILEGE_CTG
4597
4598#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4599
4600/* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
4601#define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
4602
4603/* MC_CMD_GET_LOOPBACK_MODES_IN_V2 msgrequest */
4604#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_LEN 8
4605/* Target port to request loopback modes for. Uses MAE_LINK_ENDPOINT_SELECTOR
4606 * which identifies a real or virtual network port by MAE port and link end.
4607 * See the structure definition for more details
4608 */
4609#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_OFST 0
4610#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LEN 8
4611#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LO_OFST 0
4612#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LO_LEN 4
4613#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LO_LBN 0
4614#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LO_WIDTH 32
4615#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_HI_OFST 4
4616#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_HI_LEN 4
4617#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_HI_LBN 32
4618#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_HI_WIDTH 32
4619/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
4620#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_OFST 0
4621#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_LEN 4
4622#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0
4623#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4
4624#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_TYPE_OFST 3
4625#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_TYPE_LEN 1
4626#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
4627#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
4628#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
4629#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
4630#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
4631#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
4632#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
4633#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
4634#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
4635#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
4636#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
4637#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
4638#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LINK_END_OFST 4
4639#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LINK_END_LEN 4
4640#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_OFST 0
4641#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LEN 8
4642#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LO_OFST 0
4643#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LO_LEN 4
4644#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LO_LBN 0
4645#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LO_WIDTH 32
4646#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_HI_OFST 4
4647#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_HI_LEN 4
4648#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_HI_LBN 32
4649#define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_HI_WIDTH 32
4650
4651/* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
4652#define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40
4653/* Supported loopbacks. */
4654#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
4655#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
4656#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
4657#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LEN 4
4658#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LBN 0
4659#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_WIDTH 32
4660#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
4661#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 4
4662#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LBN 32
4663#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_WIDTH 32
4664/* enum property: bitshift */
4665/* enum: None. */
4666#define MC_CMD_LOOPBACK_NONE 0x0
4667/* enum: Data. */
4668#define MC_CMD_LOOPBACK_DATA 0x1
4669/* enum: GMAC. */
4670#define MC_CMD_LOOPBACK_GMAC 0x2
4671/* enum: XGMII. */
4672#define MC_CMD_LOOPBACK_XGMII 0x3
4673/* enum: XGXS. */
4674#define MC_CMD_LOOPBACK_XGXS 0x4
4675/* enum: XAUI. */
4676#define MC_CMD_LOOPBACK_XAUI 0x5
4677/* enum: GMII. */
4678#define MC_CMD_LOOPBACK_GMII 0x6
4679/* enum: SGMII. */
4680#define MC_CMD_LOOPBACK_SGMII 0x7
4681/* enum: XGBR. */
4682#define MC_CMD_LOOPBACK_XGBR 0x8
4683/* enum: XFI. */
4684#define MC_CMD_LOOPBACK_XFI 0x9
4685/* enum: XAUI Far. */
4686#define MC_CMD_LOOPBACK_XAUI_FAR 0xa
4687/* enum: GMII Far. */
4688#define MC_CMD_LOOPBACK_GMII_FAR 0xb
4689/* enum: SGMII Far. */
4690#define MC_CMD_LOOPBACK_SGMII_FAR 0xc
4691/* enum: XFI Far. */
4692#define MC_CMD_LOOPBACK_XFI_FAR 0xd
4693/* enum: GPhy. */
4694#define MC_CMD_LOOPBACK_GPHY 0xe
4695/* enum: PhyXS. */
4696#define MC_CMD_LOOPBACK_PHYXS 0xf
4697/* enum: PCS. */
4698#define MC_CMD_LOOPBACK_PCS 0x10
4699/* enum: PMA-PMD. */
4700#define MC_CMD_LOOPBACK_PMAPMD 0x11
4701/* enum: Cross-Port. */
4702#define MC_CMD_LOOPBACK_XPORT 0x12
4703/* enum: XGMII-Wireside. */
4704#define MC_CMD_LOOPBACK_XGMII_WS 0x13
4705/* enum: XAUI Wireside. */
4706#define MC_CMD_LOOPBACK_XAUI_WS 0x14
4707/* enum: XAUI Wireside Far. */
4708#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
4709/* enum: XAUI Wireside near. */
4710#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
4711/* enum: GMII Wireside. */
4712#define MC_CMD_LOOPBACK_GMII_WS 0x17
4713/* enum: XFI Wireside. */
4714#define MC_CMD_LOOPBACK_XFI_WS 0x18
4715/* enum: XFI Wireside Far. */
4716#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
4717/* enum: PhyXS Wireside. */
4718#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
4719/* enum: PMA lanes MAC-Serdes. */
4720#define MC_CMD_LOOPBACK_PMA_INT 0x1b
4721/* enum: KR Serdes Parallel (Encoder). */
4722#define MC_CMD_LOOPBACK_SD_NEAR 0x1c
4723/* enum: KR Serdes Serial. */
4724#define MC_CMD_LOOPBACK_SD_FAR 0x1d
4725/* enum: PMA lanes MAC-Serdes Wireside. */
4726#define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
4727/* enum: KR Serdes Parallel Wireside (Full PCS). */
4728#define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
4729/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
4730#define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
4731/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
4732#define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
4733/* enum: KR Serdes Serial Wireside. */
4734#define MC_CMD_LOOPBACK_SD_FES_WS 0x22
4735/* enum: Near side of AOE Siena side port */
4736#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
4737/* enum: Medford Wireside datapath loopback */
4738#define MC_CMD_LOOPBACK_DATA_WS 0x24
4739/* enum: Force link up without setting up any physical loopback (snapper use
4740 * only)
4741 */
4742#define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
4743/* Supported loopbacks. */
4744#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
4745#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
4746#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
4747#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LEN 4
4748#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LBN 64
4749#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_WIDTH 32
4750#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
4751#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 4
4752#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LBN 96
4753#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_WIDTH 32
4754/* enum property: bitshift */
4755/* Enum values, see field(s): */
4756/* 100M */
4757/* Supported loopbacks. */
4758#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
4759#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
4760#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
4761#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LEN 4
4762#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LBN 128
4763#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_WIDTH 32
4764#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
4765#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 4
4766#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LBN 160
4767#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_WIDTH 32
4768/* enum property: bitshift */
4769/* Enum values, see field(s): */
4770/* 100M */
4771/* Supported loopbacks. */
4772#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
4773#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
4774#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
4775#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LEN 4
4776#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LBN 192
4777#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_WIDTH 32
4778#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
4779#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 4
4780#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LBN 224
4781#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_WIDTH 32
4782/* enum property: bitshift */
4783/* Enum values, see field(s): */
4784/* 100M */
4785/* Supported loopbacks. */
4786#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
4787#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
4788#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
4789#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LEN 4
4790#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LBN 256
4791#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_WIDTH 32
4792#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
4793#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 4
4794#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LBN 288
4795#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_WIDTH 32
4796/* enum property: bitshift */
4797/* Enum values, see field(s): */
4798/* 100M */
4799
4800/* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for
4801 * newer NICs with 25G/50G/100G support
4802 */
4803#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64
4804/* Supported loopbacks. */
4805#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
4806#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8
4807#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
4808#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LEN 4
4809#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LBN 0
4810#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_WIDTH 32
4811#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
4812#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 4
4813#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LBN 32
4814#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_WIDTH 32
4815/* enum property: bitshift */
4816/* enum: None. */
4817/* MC_CMD_LOOPBACK_NONE 0x0 */
4818/* enum: Data. */
4819/* MC_CMD_LOOPBACK_DATA 0x1 */
4820/* enum: GMAC. */
4821/* MC_CMD_LOOPBACK_GMAC 0x2 */
4822/* enum: XGMII. */
4823/* MC_CMD_LOOPBACK_XGMII 0x3 */
4824/* enum: XGXS. */
4825/* MC_CMD_LOOPBACK_XGXS 0x4 */
4826/* enum: XAUI. */
4827/* MC_CMD_LOOPBACK_XAUI 0x5 */
4828/* enum: GMII. */
4829/* MC_CMD_LOOPBACK_GMII 0x6 */
4830/* enum: SGMII. */
4831/* MC_CMD_LOOPBACK_SGMII 0x7 */
4832/* enum: XGBR. */
4833/* MC_CMD_LOOPBACK_XGBR 0x8 */
4834/* enum: XFI. */
4835/* MC_CMD_LOOPBACK_XFI 0x9 */
4836/* enum: XAUI Far. */
4837/* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
4838/* enum: GMII Far. */
4839/* MC_CMD_LOOPBACK_GMII_FAR 0xb */
4840/* enum: SGMII Far. */
4841/* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
4842/* enum: XFI Far. */
4843/* MC_CMD_LOOPBACK_XFI_FAR 0xd */
4844/* enum: GPhy. */
4845/* MC_CMD_LOOPBACK_GPHY 0xe */
4846/* enum: PhyXS. */
4847/* MC_CMD_LOOPBACK_PHYXS 0xf */
4848/* enum: PCS. */
4849/* MC_CMD_LOOPBACK_PCS 0x10 */
4850/* enum: PMA-PMD. */
4851/* MC_CMD_LOOPBACK_PMAPMD 0x11 */
4852/* enum: Cross-Port. */
4853/* MC_CMD_LOOPBACK_XPORT 0x12 */
4854/* enum: XGMII-Wireside. */
4855/* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
4856/* enum: XAUI Wireside. */
4857/* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
4858/* enum: XAUI Wireside Far. */
4859/* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
4860/* enum: XAUI Wireside near. */
4861/* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
4862/* enum: GMII Wireside. */
4863/* MC_CMD_LOOPBACK_GMII_WS 0x17 */
4864/* enum: XFI Wireside. */
4865/* MC_CMD_LOOPBACK_XFI_WS 0x18 */
4866/* enum: XFI Wireside Far. */
4867/* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
4868/* enum: PhyXS Wireside. */
4869/* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
4870/* enum: PMA lanes MAC-Serdes. */
4871/* MC_CMD_LOOPBACK_PMA_INT 0x1b */
4872/* enum: KR Serdes Parallel (Encoder). */
4873/* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
4874/* enum: KR Serdes Serial. */
4875/* MC_CMD_LOOPBACK_SD_FAR 0x1d */
4876/* enum: PMA lanes MAC-Serdes Wireside. */
4877/* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
4878/* enum: KR Serdes Parallel Wireside (Full PCS). */
4879/* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
4880/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
4881/* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
4882/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
4883/* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
4884/* enum: KR Serdes Serial Wireside. */
4885/* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
4886/* enum: Near side of AOE Siena side port */
4887/* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
4888/* enum: Medford Wireside datapath loopback */
4889/* MC_CMD_LOOPBACK_DATA_WS 0x24 */
4890/* enum: Force link up without setting up any physical loopback (snapper use
4891 * only)
4892 */
4893/* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
4894/* Supported loopbacks. */
4895#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
4896#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
4897#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8
4898#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LEN 4
4899#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LBN 64
4900#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_WIDTH 32
4901#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12
4902#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 4
4903#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LBN 96
4904#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_WIDTH 32
4905/* enum property: bitshift */
4906/* Enum values, see field(s): */
4907/* 100M */
4908/* Supported loopbacks. */
4909#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16
4910#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8
4911#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16
4912#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LEN 4
4913#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LBN 128
4914#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_WIDTH 32
4915#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20
4916#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 4
4917#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LBN 160
4918#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_WIDTH 32
4919/* enum property: bitshift */
4920/* Enum values, see field(s): */
4921/* 100M */
4922/* Supported loopbacks. */
4923#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24
4924#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8
4925#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24
4926#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LEN 4
4927#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LBN 192
4928#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_WIDTH 32
4929#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28
4930#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 4
4931#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LBN 224
4932#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_WIDTH 32
4933/* enum property: bitshift */
4934/* Enum values, see field(s): */
4935/* 100M */
4936/* Supported loopbacks. */
4937#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32
4938#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8
4939#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32
4940#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LEN 4
4941#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LBN 256
4942#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_WIDTH 32
4943#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36
4944#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 4
4945#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LBN 288
4946#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_WIDTH 32
4947/* enum property: bitshift */
4948/* Enum values, see field(s): */
4949/* 100M */
4950/* Supported 25G loopbacks. */
4951#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40
4952#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8
4953#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40
4954#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LEN 4
4955#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LBN 320
4956#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_WIDTH 32
4957#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44
4958#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 4
4959#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LBN 352
4960#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_WIDTH 32
4961/* enum property: bitshift */
4962/* Enum values, see field(s): */
4963/* 100M */
4964/* Supported 50 loopbacks. */
4965#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48
4966#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8
4967#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48
4968#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LEN 4
4969#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LBN 384
4970#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_WIDTH 32
4971#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52
4972#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 4
4973#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LBN 416
4974#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_WIDTH 32
4975/* enum property: bitshift */
4976/* Enum values, see field(s): */
4977/* 100M */
4978/* Supported 100G loopbacks. */
4979#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56
4980#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8
4981#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56
4982#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LEN 4
4983#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LBN 448
4984#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_WIDTH 32
4985#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60
4986#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 4
4987#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LBN 480
4988#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_WIDTH 32
4989/* enum property: bitshift */
4990/* Enum values, see field(s): */
4991/* 100M */
4992
4993/* MC_CMD_GET_LOOPBACK_MODES_OUT_V3 msgresponse: Supported loopback modes for
4994 * newer NICs with 200G support
4995 */
4996#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_LEN 72
4997/* Supported loopbacks. */
4998#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_OFST 0
4999#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LEN 8
5000#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LO_OFST 0
5001#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LO_LEN 4
5002#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LO_LBN 0
5003#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LO_WIDTH 32
5004#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_HI_OFST 4
5005#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_HI_LEN 4
5006#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_HI_LBN 32
5007#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_HI_WIDTH 32
5008/* enum property: bitshift */
5009/* enum: None. */
5010/* MC_CMD_LOOPBACK_NONE 0x0 */
5011/* enum: Data. */
5012/* MC_CMD_LOOPBACK_DATA 0x1 */
5013/* enum: GMAC. */
5014/* MC_CMD_LOOPBACK_GMAC 0x2 */
5015/* enum: XGMII. */
5016/* MC_CMD_LOOPBACK_XGMII 0x3 */
5017/* enum: XGXS. */
5018/* MC_CMD_LOOPBACK_XGXS 0x4 */
5019/* enum: XAUI. */
5020/* MC_CMD_LOOPBACK_XAUI 0x5 */
5021/* enum: GMII. */
5022/* MC_CMD_LOOPBACK_GMII 0x6 */
5023/* enum: SGMII. */
5024/* MC_CMD_LOOPBACK_SGMII 0x7 */
5025/* enum: XGBR. */
5026/* MC_CMD_LOOPBACK_XGBR 0x8 */
5027/* enum: XFI. */
5028/* MC_CMD_LOOPBACK_XFI 0x9 */
5029/* enum: XAUI Far. */
5030/* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
5031/* enum: GMII Far. */
5032/* MC_CMD_LOOPBACK_GMII_FAR 0xb */
5033/* enum: SGMII Far. */
5034/* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
5035/* enum: XFI Far. */
5036/* MC_CMD_LOOPBACK_XFI_FAR 0xd */
5037/* enum: GPhy. */
5038/* MC_CMD_LOOPBACK_GPHY 0xe */
5039/* enum: PhyXS. */
5040/* MC_CMD_LOOPBACK_PHYXS 0xf */
5041/* enum: PCS. */
5042/* MC_CMD_LOOPBACK_PCS 0x10 */
5043/* enum: PMA-PMD. */
5044/* MC_CMD_LOOPBACK_PMAPMD 0x11 */
5045/* enum: Cross-Port. */
5046/* MC_CMD_LOOPBACK_XPORT 0x12 */
5047/* enum: XGMII-Wireside. */
5048/* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
5049/* enum: XAUI Wireside. */
5050/* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
5051/* enum: XAUI Wireside Far. */
5052/* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
5053/* enum: XAUI Wireside near. */
5054/* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
5055/* enum: GMII Wireside. */
5056/* MC_CMD_LOOPBACK_GMII_WS 0x17 */
5057/* enum: XFI Wireside. */
5058/* MC_CMD_LOOPBACK_XFI_WS 0x18 */
5059/* enum: XFI Wireside Far. */
5060/* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
5061/* enum: PhyXS Wireside. */
5062/* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
5063/* enum: PMA lanes MAC-Serdes. */
5064/* MC_CMD_LOOPBACK_PMA_INT 0x1b */
5065/* enum: KR Serdes Parallel (Encoder). */
5066/* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
5067/* enum: KR Serdes Serial. */
5068/* MC_CMD_LOOPBACK_SD_FAR 0x1d */
5069/* enum: PMA lanes MAC-Serdes Wireside. */
5070/* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
5071/* enum: KR Serdes Parallel Wireside (Full PCS). */
5072/* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
5073/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
5074/* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
5075/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
5076/* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
5077/* enum: KR Serdes Serial Wireside. */
5078/* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
5079/* enum: Near side of AOE Siena side port */
5080/* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
5081/* enum: Medford Wireside datapath loopback */
5082/* MC_CMD_LOOPBACK_DATA_WS 0x24 */
5083/* enum: Force link up without setting up any physical loopback (snapper use
5084 * only)
5085 */
5086/* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
5087/* Supported loopbacks. */
5088#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_OFST 8
5089#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_LEN 8
5090#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_LO_OFST 8
5091#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_LO_LEN 4
5092#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_LO_LBN 64
5093#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_LO_WIDTH 32
5094#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_HI_OFST 12
5095#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_HI_LEN 4
5096#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_HI_LBN 96
5097#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_HI_WIDTH 32
5098/* enum property: bitshift */
5099/* Enum values, see field(s): */
5100/* 100M */
5101/* Supported loopbacks. */
5102#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_OFST 16
5103#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_LEN 8
5104#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_LO_OFST 16
5105#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_LO_LEN 4
5106#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_LO_LBN 128
5107#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_LO_WIDTH 32
5108#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_HI_OFST 20
5109#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_HI_LEN 4
5110#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_HI_LBN 160
5111#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_HI_WIDTH 32
5112/* enum property: bitshift */
5113/* Enum values, see field(s): */
5114/* 100M */
5115/* Supported loopbacks. */
5116#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_OFST 24
5117#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_LEN 8
5118#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_LO_OFST 24
5119#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_LO_LEN 4
5120#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_LO_LBN 192
5121#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_LO_WIDTH 32
5122#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_HI_OFST 28
5123#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_HI_LEN 4
5124#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_HI_LBN 224
5125#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_HI_WIDTH 32
5126/* enum property: bitshift */
5127/* Enum values, see field(s): */
5128/* 100M */
5129/* Supported loopbacks. */
5130#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_OFST 32
5131#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_LEN 8
5132#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_LO_OFST 32
5133#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_LO_LEN 4
5134#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_LO_LBN 256
5135#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_LO_WIDTH 32
5136#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_HI_OFST 36
5137#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_HI_LEN 4
5138#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_HI_LBN 288
5139#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_HI_WIDTH 32
5140/* enum property: bitshift */
5141/* Enum values, see field(s): */
5142/* 100M */
5143/* Supported 25G loopbacks. */
5144#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_OFST 40
5145#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_LEN 8
5146#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_LO_OFST 40
5147#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_LO_LEN 4
5148#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_LO_LBN 320
5149#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_LO_WIDTH 32
5150#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_HI_OFST 44
5151#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_HI_LEN 4
5152#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_HI_LBN 352
5153#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_HI_WIDTH 32
5154/* enum property: bitshift */
5155/* Enum values, see field(s): */
5156/* 100M */
5157/* Supported 50 loopbacks. */
5158#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_OFST 48
5159#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_LEN 8
5160#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_LO_OFST 48
5161#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_LO_LEN 4
5162#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_LO_LBN 384
5163#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_LO_WIDTH 32
5164#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_HI_OFST 52
5165#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_HI_LEN 4
5166#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_HI_LBN 416
5167#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_HI_WIDTH 32
5168/* enum property: bitshift */
5169/* Enum values, see field(s): */
5170/* 100M */
5171/* Supported 100G loopbacks. */
5172#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_OFST 56
5173#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_LEN 8
5174#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_LO_OFST 56
5175#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_LO_LEN 4
5176#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_LO_LBN 448
5177#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_LO_WIDTH 32
5178#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_HI_OFST 60
5179#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_HI_LEN 4
5180#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_HI_LBN 480
5181#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_HI_WIDTH 32
5182/* enum property: bitshift */
5183/* Enum values, see field(s): */
5184/* 100M */
5185/* Supported 200G loopbacks. */
5186#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_OFST 64
5187#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_LEN 8
5188#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_LO_OFST 64
5189#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_LO_LEN 4
5190#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_LO_LBN 512
5191#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_LO_WIDTH 32
5192#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_HI_OFST 68
5193#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_HI_LEN 4
5194#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_HI_LBN 544
5195#define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_HI_WIDTH 32
5196/* enum property: bitshift */
5197/* Enum values, see field(s): */
5198/* 100M */
5199
5200/* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
5201#define AN_TYPE_LEN 4
5202#define AN_TYPE_TYPE_OFST 0
5203#define AN_TYPE_TYPE_LEN 4
5204/* enum: None, AN disabled or not supported */
5205#define MC_CMD_AN_NONE 0x0
5206/* enum: Clause 28 - BASE-T */
5207#define MC_CMD_AN_CLAUSE28 0x1
5208/* enum: Clause 37 - BASE-X */
5209#define MC_CMD_AN_CLAUSE37 0x2
5210/* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
5211 * assemblies. Includes Clause 72/Clause 92 link-training.
5212 */
5213#define MC_CMD_AN_CLAUSE73 0x3
5214#define AN_TYPE_TYPE_LBN 0
5215#define AN_TYPE_TYPE_WIDTH 32
5216
5217/* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.3
5218 */
5219#define FEC_TYPE_LEN 4
5220#define FEC_TYPE_TYPE_OFST 0
5221#define FEC_TYPE_TYPE_LEN 4
5222/* enum: No FEC */
5223#define MC_CMD_FEC_NONE 0x0
5224/* enum: IEEE 802.3, Clause 74 BASE-R FEC (a.k.a Firecode) */
5225#define MC_CMD_FEC_BASER 0x1
5226/* enum: IEEE 802.3, Clause 91/Clause 108 Reed-Solomon FEC */
5227#define MC_CMD_FEC_RS 0x2
5228/* enum: IEEE 802.3, Clause 161, interleaved RS-FEC sublayer for 100GBASE-R
5229 * PHYs
5230 */
5231#define MC_CMD_FEC_IEEE_RS_INT 0x3
5232/* enum: Ethernet Consortium, Low Latency RS-FEC. RS(272, 258). Replaces FEC
5233 * specified in Clause 119 for 100/200G PHY. Replaces FEC specified in Clause
5234 * 134 for 50G PHY.
5235 */
5236#define MC_CMD_FEC_ETCS_RS_LL 0x4
5237/* enum: FEC mode selected automatically */
5238#define MC_CMD_FEC_AUTO 0x5
5239#define FEC_TYPE_TYPE_LBN 0
5240#define FEC_TYPE_TYPE_WIDTH 32
5241
5242/* MC_CMD_ETH_TECH structuredef: Ethernet technology as defined by IEEE802.3,
5243 * Ethernet Technology Consortium, proprietary technologies. The driver must
5244 * not use technologies labelled NONE and AUTO.
5245 */
5246#define MC_CMD_ETH_TECH_LEN 16
5247/* The enums in this field can be used either as bitwise indices into a tech
5248 * mask (e.g. see MC_CMD_ETH_AN_FIELDS/TECH_MASK for example) or as regular
5249 * enums (e.g. see MC_CMD_LINK_CTRL_IN/ADVERTISED_TECH_ABILITIES_MASK). This
5250 * structure must be updated to add new technologies when projects that need
5251 * them arise. An incomplete list of possible expansion in the future include:
5252 * 100GBASE_KP4, 800GBASE_CR8, 800GBASE_KR8, 800GBASE_DR8, 800GBASE_SR8
5253 * 800GBASE_VR8
5254 */
5255#define MC_CMD_ETH_TECH_TECH_OFST 0
5256#define MC_CMD_ETH_TECH_TECH_LEN 16
5257/* enum: 1000BASE-KX - 1000BASE-X PCS/PMA over an electrical backplane PMD. See
5258 * IEEE 802.3 Clause 70
5259 */
5260#define MC_CMD_ETH_TECH_1000BASEKX 0x0
5261/* enum: 10GBASE-R - PCS/PMA over an electrical backplane PMD. Refer to IEEE
5262 * 802.3 Clause 72
5263 */
5264#define MC_CMD_ETH_TECH_10GBASE_KR 0x1
5265/* enum: 40GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5266 * Clause 84.
5267 */
5268#define MC_CMD_ETH_TECH_40GBASE_KR4 0x2
5269/* enum: 40GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD. See
5270 * IEEE 802.3 Clause 85
5271 */
5272#define MC_CMD_ETH_TECH_40GBASE_CR4 0x3
5273/* enum: 40GBASE-R PCS/PMA over 4 lane multimode fiber PMD as specified in
5274 * Clause 86
5275 */
5276#define MC_CMD_ETH_TECH_40GBASE_SR4 0x4
5277/* enum: 40GBASE-R PCS/PMA over 4 WDM lane single mode fiber PMD with long
5278 * reach. See IEEE 802.3 Clause 87
5279 */
5280#define MC_CMD_ETH_TECH_40GBASE_LR4 0x5
5281/* enum: 25GBASE-R PCS/PMA over shielded balanced copper cable PMD. See IEEE
5282 * 802.3 Clause 110
5283 */
5284#define MC_CMD_ETH_TECH_25GBASE_CR 0x6
5285/* enum: 25GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5286 * Clause 111
5287 */
5288#define MC_CMD_ETH_TECH_25GBASE_KR 0x7
5289/* enum: 25GBASE-R PCS/PMA over multimode fiber PMD. Refer to IEEE 802.3 Clause
5290 * 112
5291 */
5292#define MC_CMD_ETH_TECH_25GBASE_SR 0x8
5293/* enum: An Ethernet Physical layer operating at 50 Gb/s on twin-axial copper
5294 * cable. Refer to Ethernet Technology Consortium 25/50G Ethernet Spec.
5295 */
5296#define MC_CMD_ETH_TECH_50GBASE_CR2 0x9
5297/* enum: An Ethernet Physical layer operating at 50 Gb/s on copper backplane.
5298 * Refer to Ethernet Technology Consortium 25/50G Ethernet Spec.
5299 */
5300#define MC_CMD_ETH_TECH_50GBASE_KR2 0xa
5301/* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5302 * Clause 93
5303 */
5304#define MC_CMD_ETH_TECH_100GBASE_KR4 0xb
5305/* enum: 100GBASE-R PCS/PMA over 4 lane multimode fiber PMD. See IEEE 802.3
5306 * Clause 95
5307 */
5308#define MC_CMD_ETH_TECH_100GBASE_SR4 0xc
5309/* enum: 100GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD. See
5310 * IEEE 802.3 Clause 92
5311 */
5312#define MC_CMD_ETH_TECH_100GBASE_CR4 0xd
5313/* enum: 100GBASE-R PCS/PMA over 4 WDM lane single mode fiber PMD, with
5314 * long/extended reach,. See IEEE 802.3 Clause 88
5315 */
5316#define MC_CMD_ETH_TECH_100GBASE_LR4_ER4 0xe
5317/* enum: An Ethernet Physical layer operating at 50 Gb/s on short reach fiber.
5318 * Refer to Ethernet Technology Consortium 25/50G Ethernet Spec.
5319 */
5320#define MC_CMD_ETH_TECH_50GBASE_SR2 0xf
5321/* enum: 1000BASEX PCS/PMA. See IEEE 802.3 Clause 36 over undefined PMD, duplex
5322 * mode unknown
5323 */
5324#define MC_CMD_ETH_TECH_1000BASEX 0x10
5325/* enum: Non-standardised. 10G direct attach */
5326#define MC_CMD_ETH_TECH_10GBASE_CR 0x11
5327/* enum: 10GBASE-SR fiber over 850nm optics. See IEEE 802.3 Clause 52 */
5328#define MC_CMD_ETH_TECH_10GBASE_SR 0x12
5329/* enum: 10GBASE-LR fiber over 1310nm optics. See IEEE 802.3 Clause 52 */
5330#define MC_CMD_ETH_TECH_10GBASE_LR 0x13
5331/* enum: 10GBASE-LRM fiber over 1310 nm optics. See IEEE 802.3 Clause 68 */
5332#define MC_CMD_ETH_TECH_10GBASE_LRM 0x14
5333/* enum: 10GBASE-ER fiber over 1550nm optics. See IEEE 802.3 Clause 52 */
5334#define MC_CMD_ETH_TECH_10GBASE_ER 0x15
5335/* enum: 50GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5336 * Clause 137
5337 */
5338#define MC_CMD_ETH_TECH_50GBASE_KR 0x16
5339/* enum: 50GBASE-SR PCS/PMA over multimode fiber PMD as specified in Clause 138
5340 */
5341#define MC_CMD_ETH_TECH_50GBASE_SR 0x17
5342/* enum: 50GBASE-CR PCS/PMA over shielded copper balanced cable PMD. See IEEE
5343 * 802.3 Clause 136
5344 */
5345#define MC_CMD_ETH_TECH_50GBASE_CR 0x18
5346/* enum: 50GBASE-R PCS/PMA over single mode fiber PMD as specified in Clause
5347 * 139.
5348 */
5349#define MC_CMD_ETH_TECH_50GBASE_LR_ER_FR 0x19
5350/* enum: 100 Gb/s PHY using 100GBASE-R encoding over single-mode fiber with
5351 * reach up to at least 500 m (see IEEE 802.3 Clause 140)
5352 */
5353#define MC_CMD_ETH_TECH_50GBASE_DR 0x1a
5354/* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5355 * Clause 137
5356 */
5357#define MC_CMD_ETH_TECH_100GBASE_KR2 0x1b
5358/* enum: 100GBASE-R PCS/PMA over 2 lane multimode fiber PMD. See IEEE 802.3
5359 * Clause 138
5360 */
5361#define MC_CMD_ETH_TECH_100GBASE_SR2 0x1c
5362/* enum: 100GBASE-R PCS/PMA over 2 lane shielded copper balanced cable PMD. See
5363 * IEEE 802.3 Clause 136
5364 */
5365#define MC_CMD_ETH_TECH_100GBASE_CR2 0x1d
5366/* enum: Unknown source */
5367#define MC_CMD_ETH_TECH_100GBASE_LR2_ER2_FR2 0x1e
5368/* enum: Unknown source */
5369#define MC_CMD_ETH_TECH_100GBASE_DR2 0x1f
5370/* enum: 200GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5371 * Clause 137
5372 */
5373#define MC_CMD_ETH_TECH_200GBASE_KR4 0x20
5374/* enum: 200GBASE-R PCS/PMA over 4 lane multimode fiber PMD. See IEEE 802.3
5375 * Clause 138
5376 */
5377#define MC_CMD_ETH_TECH_200GBASE_SR4 0x21
5378/* enum: 200GBASE-R PCS/PMA over 4 WDM lane single-mode fiber PMD as specified
5379 * in Clause 122
5380 */
5381#define MC_CMD_ETH_TECH_200GBASE_LR4_ER4_FR4 0x22
5382/* enum: 200GBASE-R PCS/PMA over 4-lane single-mode fiber PMD. See IEEE 802.3
5383 * Clause 121
5384 */
5385#define MC_CMD_ETH_TECH_200GBASE_DR4 0x23
5386/* enum: 200GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD as
5387 * specified in Clause 136
5388 */
5389#define MC_CMD_ETH_TECH_200GBASE_CR4 0x24
5390/* enum: Ethernet Technology Consortium 400G AN Spec. 400GBASE-KR8 PMD uses
5391 * 802.3 Clause 137, but the number PMD lanes is 8.
5392 */
5393#define MC_CMD_ETH_TECH_400GBASE_KR8 0x25
5394/* enum: 400GBASE-R PCS/PMA over 8-lane multimode fiber PMD. See IEEE 802.3
5395 * Clause 138
5396 */
5397#define MC_CMD_ETH_TECH_400GBASE_SR8 0x26
5398/* enum: 400GBASE-R PCS/PMA over 8 WDM lane single-mode fiber PMD. See IEEE
5399 * 802.3 Clause 122
5400 */
5401#define MC_CMD_ETH_TECH_400GBASE_LR8_ER8_FR8 0x27
5402/* enum: Unknown source */
5403#define MC_CMD_ETH_TECH_400GBASE_DR8 0x28
5404/* enum: Ethernet Technology Consortium 400G AN Spec. 400GBASE-CR8 PMD uses
5405 * IEEE 802.3 Clause 136, but the number PMD lanes is 8.
5406 */
5407#define MC_CMD_ETH_TECH_400GBASE_CR8 0x29
5408/* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3ck
5409 * Clause 163.
5410 */
5411#define MC_CMD_ETH_TECH_100GBASE_KR 0x2a
5412/* enum: IEEE 802.3ck. 100G PHY with PMD as specified in Clause 167 over short
5413 * reach fiber
5414 */
5415#define MC_CMD_ETH_TECH_100GBASE_SR 0x2b
5416/* enum: 100G PMD together with single-mode fiber medium. See IEEE 802.3 Clause
5417 * 140
5418 */
5419#define MC_CMD_ETH_TECH_100GBASE_LR_ER_FR 0x2c
5420/* enum: 100GBASE-R PCS/PMA over shielded balanced copper cable PMD. See IEEE
5421 * 802.3 in Clause 162 IEEE 802.3ck.
5422 */
5423#define MC_CMD_ETH_TECH_100GBASE_CR 0x2d
5424/* enum: 100G PMD together with single-mode fiber medium. See IEEE 802.3 Clause
5425 * 140
5426 */
5427#define MC_CMD_ETH_TECH_100GBASE_DR 0x2e
5428/* enum: 200GBASE-R PCS/PMA over an electrical backplane PMD as specified in
5429 * Clause 163 IEEE 802.3ck
5430 */
5431#define MC_CMD_ETH_TECH_200GBASE_KR2 0x2f
5432/* enum: 200G PHY with PMD as specified in Clause 167 over short reach fiber
5433 * IEEE 802.3ck
5434 */
5435#define MC_CMD_ETH_TECH_200GBASE_SR2 0x30
5436/* enum: Unknown source */
5437#define MC_CMD_ETH_TECH_200GBASE_LR2_ER2_FR2 0x31
5438/* enum: Unknown source */
5439#define MC_CMD_ETH_TECH_200GBASE_DR2 0x32
5440/* enum: 200GBASE-R PCS/PMA over 2 lane shielded balanced copper cable PMD as
5441 * specified in Clause 162 IEEE 802.3ck.
5442 */
5443#define MC_CMD_ETH_TECH_200GBASE_CR2 0x33
5444/* enum: 400GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5445 * Clause 163 IEEE 802.3ck.
5446 */
5447#define MC_CMD_ETH_TECH_400GBASE_KR4 0x34
5448/* enum: 400G PHY with PMD over short reach fiber. See Clause 167 of IEEE
5449 * 802.3ck.
5450 */
5451#define MC_CMD_ETH_TECH_400GBASE_SR4 0x35
5452/* enum: 400GBASE-R PCS/PMA over 4 WDM lane single-mode fiber PMD. See IEEE
5453 * 802.3 Clause 151
5454 */
5455#define MC_CMD_ETH_TECH_400GBASE_LR4_ER4_FR4 0x36
5456/* enum: 400GBASE-R PCS/PMA over 4-lane single-mode fiber PMD as specified in
5457 * Clause 124
5458 */
5459#define MC_CMD_ETH_TECH_400GBASE_DR4 0x37
5460/* enum: 400GBASE-R PCS/PMA over 4 lane shielded balanced copper cable PMD as
5461 * specified in Clause 162 of IEEE 802.3ck.
5462 */
5463#define MC_CMD_ETH_TECH_400GBASE_CR4 0x38
5464/* enum: Automatic tech mode. The driver must not use this. */
5465#define MC_CMD_ETH_TECH_AUTO 0x39
5466/* enum: See IEEE 802.3cc-2017 Clause 114 */
5467#define MC_CMD_ETH_TECH_25GBASE_LR_ER 0x3a
5468/* enum: Up to 7 m over twinaxial copper cable assembly (10 lanes, 10 Gbit/s
5469 * each) See IEEE 802.3ba-2010 Clause 85
5470 */
5471#define MC_CMD_ETH_TECH_100GBASE_CR10 0x3b
5472/* enum: Invalid tech mode. The driver must not use this. */
5473#define MC_CMD_ETH_TECH_NONE 0x7f
5474#define MC_CMD_ETH_TECH_TECH_LBN 0
5475#define MC_CMD_ETH_TECH_TECH_WIDTH 128
5476
5477/* MC_CMD_LINK_STATUS_FLAGS structuredef */
5478#define MC_CMD_LINK_STATUS_FLAGS_LEN 8
5479/* Flags used to report the current configuration/state of the link. */
5480#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_OFST 0
5481#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LEN 8
5482#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_OFST 0
5483#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_LEN 4
5484#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_LBN 0
5485#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_WIDTH 32
5486#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_OFST 4
5487#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_LEN 4
5488#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_LBN 32
5489#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_WIDTH 32
5490/* enum property: bitshift */
5491/* enum: Whether we have overall link up */
5492#define MC_CMD_LINK_STATUS_FLAGS_LINK_UP 0x0
5493/* enum: If set, the PHY has no external RX link synchronisation */
5494#define MC_CMD_LINK_STATUS_FLAGS_NO_PHY_LINK 0x1
5495/* enum: If set, PMD/MDI is not connected (e.g. cable disconnected, module cage
5496 * empty)
5497 */
5498#define MC_CMD_LINK_STATUS_FLAGS_PMD_MDI_DISCONNECTED 0x2
5499/* enum: Set on error while decoding module data (e.g. module EEPROM does not
5500 * contain valid values, has checksum errors, etc.)
5501 */
5502#define MC_CMD_LINK_STATUS_FLAGS_PMD_BAD 0x3
5503/* enum: Set when module unsupported (e.g. unsupported link rate or link
5504 * technology)
5505 */
5506#define MC_CMD_LINK_STATUS_FLAGS_PMD_UNSUPPORTED 0x4
5507/* enum: Set on error while communicating with the module (e.g. I2C errors
5508 * while reading EEPROM)
5509 */
5510#define MC_CMD_LINK_STATUS_FLAGS_PMD_COMMS_FAULT 0x5
5511/* enum: Set on module overcurrent/overvoltage condition */
5512#define MC_CMD_LINK_STATUS_FLAGS_PMD_POWER_FAULT 0x6
5513/* enum: Set on module overtemperature condition */
5514#define MC_CMD_LINK_STATUS_FLAGS_PMD_THERMAL_FAULT 0x7
5515/* enum: If set, the module is indicating Loss of Signal */
5516#define MC_CMD_LINK_STATUS_FLAGS_PMD_LOS 0x8
5517/* enum: If set, PMA is indicating loss of CDR lock (clock sync) */
5518#define MC_CMD_LINK_STATUS_FLAGS_PMA_NO_CDR_LOCK 0x9
5519/* enum: If set, PMA is indicating loss of analog signal */
5520#define MC_CMD_LINK_STATUS_FLAGS_PMA_LOS 0xa
5521/* enum: If set, PCS is indicating loss of block lock */
5522#define MC_CMD_LINK_STATUS_FLAGS_PCS_NO_BLOCK_LOCK 0xb
5523/* enum: If set, PCS is indicating loss of alignment marker lock on one or more
5524 * lanes
5525 */
5526#define MC_CMD_LINK_STATUS_FLAGS_PCS_NO_AM_LOCK 0xc
5527/* enum: If set, PCS is indicating loss of overall alignment lock */
5528#define MC_CMD_LINK_STATUS_FLAGS_PCS_NO_ALIGN_LOCK 0xd
5529/* enum: If set, PCS is indicating high bit error rate condition. */
5530#define MC_CMD_LINK_STATUS_FLAGS_PCS_HI_BER 0xe
5531/* enum: If set, FEC is indicating loss of FEC lock */
5532#define MC_CMD_LINK_STATUS_FLAGS_FEC_NO_LOCK 0xf
5533/* enum: If set, indicates that the number of symbol errors in a 8192-codeword
5534 * window has exceeded the threshold K (417).
5535 */
5536#define MC_CMD_LINK_STATUS_FLAGS_FEC_HI_SER 0x10
5537/* enum: If set, the receiver has detected the local FEC has degraded. */
5538#define MC_CMD_LINK_STATUS_FLAGS_FEC_LOCAL_DEGRADED 0x11
5539/* enum: If set, the receiver has detected the remote FEC has degraded. */
5540#define MC_CMD_LINK_STATUS_FLAGS_FEC_RM_DEGRADED 0x12
5541/* enum: If set, the number of symbol errors is over an internal threshold. */
5542#define MC_CMD_LINK_STATUS_FLAGS_FEC_DEGRADED_SER 0x13
5543/* enum: If set, autonegotiation has detected an auto-negotiation capable link
5544 * partner
5545 */
5546#define MC_CMD_LINK_STATUS_FLAGS_AN_ABLE 0x14
5547/* enum: If set, autonegotiation base page exchange has failed */
5548#define MC_CMD_LINK_STATUS_FLAGS_AN_BP_FAILED 0x15
5549/* enum: If set, autonegotiation next page exchange has failed */
5550#define MC_CMD_LINK_STATUS_FLAGS_AN_NP_FAILED 0x16
5551/* enum: If set, autonegotiation has failed to negotiate a common set of
5552 * capabilities
5553 */
5554#define MC_CMD_LINK_STATUS_FLAGS_AN_NO_HCD 0x17
5555/* enum: If set, local end link training has failed to establish link training
5556 * frame lock on one or more lanes
5557 */
5558#define MC_CMD_LINK_STATUS_FLAGS_LT_NO_LOCAL_FRAME_LOCK 0x18
5559/* enum: If set, remote end link training has failed to establish link training
5560 * frame lock on one or more lanes
5561 */
5562#define MC_CMD_LINK_STATUS_FLAGS_LT_NO_RM_FRAME_LOCK 0x19
5563/* enum: If set, remote end has failed to assert Receiver Ready (link training
5564 * success) within the designated timeout
5565 */
5566#define MC_CMD_LINK_STATUS_FLAGS_LT_NO_RX_READY 0x1a
5567#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LBN 0
5568#define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_WIDTH 64
5569
5570/* MC_CMD_PAUSE_MODE structuredef */
5571#define MC_CMD_PAUSE_MODE_LEN 1
5572#define MC_CMD_PAUSE_MODE_TYPE_OFST 0
5573#define MC_CMD_PAUSE_MODE_TYPE_LEN 1
5574/* enum: See IEEE 802.3 Clause 73.6.6 */
5575#define MC_CMD_PAUSE_MODE_AN_PAUSE 0x0
5576/* enum: See IEEE 802.3 Clause 73.6.6 */
5577#define MC_CMD_PAUSE_MODE_AN_ASYM_DIR 0x1
5578#define MC_CMD_PAUSE_MODE_TYPE_LBN 0
5579#define MC_CMD_PAUSE_MODE_TYPE_WIDTH 8
5580
5581/* MC_CMD_ETH_AN_FIELDS structuredef: Fields used for IEEE 802.3 Clause 73
5582 * Auto-Negotiation. Warning - This is fixed size and cannot be extended. This
5583 * structure is used to define autonegotiable abilities (advertised, link
5584 * partner and supported abilities).
5585 */
5586#define MC_CMD_ETH_AN_FIELDS_LEN 25
5587/* Mask of Ethernet technologies. The bit indices in this mask are taken from
5588 * the TECH field in the MC_CMD_ETH_TECH structure.
5589 */
5590#define MC_CMD_ETH_AN_FIELDS_TECH_MASK_OFST 0
5591#define MC_CMD_ETH_AN_FIELDS_TECH_MASK_LEN 16
5592/* enum property: bitshift */
5593/* Enum values, see field(s): */
5594/* MC_CMD_ETH_TECH/TECH */
5595#define MC_CMD_ETH_AN_FIELDS_TECH_MASK_LBN 0
5596#define MC_CMD_ETH_AN_FIELDS_TECH_MASK_WIDTH 128
5597/* Mask of supported FEC modes */
5598#define MC_CMD_ETH_AN_FIELDS_FEC_MASK_OFST 16
5599#define MC_CMD_ETH_AN_FIELDS_FEC_MASK_LEN 4
5600/* enum property: bitshift */
5601/* Enum values, see field(s): */
5602/* FEC_TYPE/TYPE */
5603#define MC_CMD_ETH_AN_FIELDS_FEC_MASK_LBN 128
5604#define MC_CMD_ETH_AN_FIELDS_FEC_MASK_WIDTH 32
5605/* Mask of requested FEC modes */
5606#define MC_CMD_ETH_AN_FIELDS_FEC_REQ_OFST 20
5607#define MC_CMD_ETH_AN_FIELDS_FEC_REQ_LEN 4
5608/* enum property: bitshift */
5609/* Enum values, see field(s): */
5610/* FEC_TYPE/TYPE */
5611#define MC_CMD_ETH_AN_FIELDS_FEC_REQ_LBN 160
5612#define MC_CMD_ETH_AN_FIELDS_FEC_REQ_WIDTH 32
5613/* Bitmask of negotiated pause modes */
5614#define MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_OFST 24
5615#define MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_LEN 1
5616/* enum property: bitshift */
5617/* Enum values, see field(s): */
5618/* MC_CMD_PAUSE_MODE/TYPE */
5619#define MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_LBN 192
5620#define MC_CMD_ETH_AN_FIELDS_PAUSE_MASK_WIDTH 8
5621
5622/* MC_CMD_LOOPBACK_V2 structuredef: Loopback modes for use with the new
5623 * MC_CMD_LINK_CTRL and MC_CMD_LINK_STATE. These loopback modes are not
5624 * supported in other getlink/setlink commands.
5625 */
5626#define MC_CMD_LOOPBACK_V2_LEN 4
5627#define MC_CMD_LOOPBACK_V2_MODE_OFST 0
5628#define MC_CMD_LOOPBACK_V2_MODE_LEN 4
5629/* enum: No loopback */
5630#define MC_CMD_LOOPBACK_V2_NONE 0x0
5631/* enum: Let firmware choose a supported loopback mode */
5632#define MC_CMD_LOOPBACK_V2_AUTO 0x1
5633/* enum: Loopback after the MAC */
5634#define MC_CMD_LOOPBACK_V2_POST_MAC 0x2
5635/* enum: Loopback after the PCS */
5636#define MC_CMD_LOOPBACK_V2_POST_PCS 0x3
5637/* enum: Loopback after the PMA */
5638#define MC_CMD_LOOPBACK_V2_POST_PMA 0x4
5639/* enum: Loopback after the MDI Wireside */
5640#define MC_CMD_LOOPBACK_V2_POST_MDI_WS 0x5
5641/* enum: Loopback after the PMA Wireside */
5642#define MC_CMD_LOOPBACK_V2_POST_PMA_WS 0x6
5643/* enum: Loopback after the PCS Wireside */
5644#define MC_CMD_LOOPBACK_V2_POST_PCS_WS 0x7
5645/* enum: Loopback after the MAC Wireside */
5646#define MC_CMD_LOOPBACK_V2_POST_MAC_WS 0x8
5647/* enum: Loopback after the MAC FIFOs (before the MAC) */
5648#define MC_CMD_LOOPBACK_V2_PRE_MAC 0x9
5649#define MC_CMD_LOOPBACK_V2_MODE_LBN 0
5650#define MC_CMD_LOOPBACK_V2_MODE_WIDTH 32
5651
5652/* MC_CMD_FCNTL structuredef */
5653#define MC_CMD_FCNTL_LEN 4
5654#define MC_CMD_FCNTL_MASK_OFST 0
5655#define MC_CMD_FCNTL_MASK_LEN 4
5656/* enum: Flow control is off. */
5657#define MC_CMD_FCNTL_OFF 0x0
5658/* enum: Respond to flow control. */
5659#define MC_CMD_FCNTL_RESPOND 0x1
5660/* enum: Respond to and Issue flow control. */
5661#define MC_CMD_FCNTL_BIDIR 0x2
5662/* enum: Auto negotiate flow control. */
5663#define MC_CMD_FCNTL_AUTO 0x3
5664/* enum: Priority flow control. This is only supported on KSB. */
5665#define MC_CMD_FCNTL_QBB 0x4
5666/* enum: Issue flow control. */
5667#define MC_CMD_FCNTL_GENERATE 0x5
5668#define MC_CMD_FCNTL_MASK_LBN 0
5669#define MC_CMD_FCNTL_MASK_WIDTH 32
5670
5671/* MC_CMD_LINK_FLAGS structuredef */
5672#define MC_CMD_LINK_FLAGS_LEN 4
5673/* The enums defined in this field are used as indices into the
5674 * MC_CMD_LINK_FLAGS bitmask.
5675 */
5676#define MC_CMD_LINK_FLAGS_MASK_OFST 0
5677#define MC_CMD_LINK_FLAGS_MASK_LEN 4
5678/* enum property: bitshift */
5679/* enum: Enable auto-negotiation. If AN is enabled, link technology and FEC
5680 * mode are determined by advertised capabilities and requested FEC modes,
5681 * combined with link partner capabilities. If AN is disabled, link technology
5682 * is forced to LINK_TECHNOLOGY and FEC mode is forced to FEC_MODE. Not valid
5683 * if loopback is enabled
5684 */
5685#define MC_CMD_LINK_FLAGS_AUTONEG_EN 0x0
5686/* enum: Enable parallel detect. In addition to AN, try to sense partner forced
5687 * speed/FEC mode (when partner AN disabled). Only valid if AN is enabled.
5688 */
5689#define MC_CMD_LINK_FLAGS_PARALLEL_DETECT_EN 0x1
5690/* enum: Force link down, in electrical idle. */
5691#define MC_CMD_LINK_FLAGS_LINK_DISABLE 0x2
5692/* enum: Ignore the sequence number and always apply. */
5693#define MC_CMD_LINK_FLAGS_IGNORE_MODULE_SEQ 0x3
5694#define MC_CMD_LINK_FLAGS_MASK_LBN 0
5695#define MC_CMD_LINK_FLAGS_MASK_WIDTH 32
5696
5697
5698/***********************************/
5699/* MC_CMD_LINK_CTRL
5700 * Write the unified MAC/PHY link configuration. Locks required: None. Return
5701 * code: 0, EINVAL, ETIME, EAGAIN
5702 */
5703#define MC_CMD_LINK_CTRL 0x6b
5704#undef MC_CMD_0x6b_PRIVILEGE_CTG
5705
5706#define MC_CMD_0x6b_PRIVILEGE_CTG SRIOV_CTG_LINK
5707
5708/* MC_CMD_LINK_CTRL_IN msgrequest */
5709#define MC_CMD_LINK_CTRL_IN_LEN 40
5710/* Handle to the port to set link state for. */
5711#define MC_CMD_LINK_CTRL_IN_PORT_HANDLE_OFST 0
5712#define MC_CMD_LINK_CTRL_IN_PORT_HANDLE_LEN 4
5713/* Control flags */
5714#define MC_CMD_LINK_CTRL_IN_CONTROL_FLAGS_OFST 4
5715#define MC_CMD_LINK_CTRL_IN_CONTROL_FLAGS_LEN 4
5716/* enum property: bitshift */
5717/* Enum values, see field(s): */
5718/* MC_CMD_LINK_FLAGS/MASK */
5719/* Reserved for future expansion, and included to provide padding for alignment
5720 * purposes.
5721 */
5722#define MC_CMD_LINK_CTRL_IN_RESERVED_OFST 8
5723#define MC_CMD_LINK_CTRL_IN_RESERVED_LEN 8
5724#define MC_CMD_LINK_CTRL_IN_RESERVED_LO_OFST 8
5725#define MC_CMD_LINK_CTRL_IN_RESERVED_LO_LEN 4
5726#define MC_CMD_LINK_CTRL_IN_RESERVED_LO_LBN 64
5727#define MC_CMD_LINK_CTRL_IN_RESERVED_LO_WIDTH 32
5728#define MC_CMD_LINK_CTRL_IN_RESERVED_HI_OFST 12
5729#define MC_CMD_LINK_CTRL_IN_RESERVED_HI_LEN 4
5730#define MC_CMD_LINK_CTRL_IN_RESERVED_HI_LBN 96
5731#define MC_CMD_LINK_CTRL_IN_RESERVED_HI_WIDTH 32
5732/* Technology abilities to advertise during auto-negotiation */
5733#define MC_CMD_LINK_CTRL_IN_ADVERTISED_TECH_ABILITIES_MASK_OFST 16
5734#define MC_CMD_LINK_CTRL_IN_ADVERTISED_TECH_ABILITIES_MASK_LEN 16
5735/* enum property: bitshift */
5736/* Enum values, see field(s): */
5737/* MC_CMD_ETH_TECH/TECH */
5738/* Pause abilities to advertise during auto-negotiation. Valid when auto-
5739 * negotation is enabled and MC_CMD_SET_MAC_IN/FCTL is set to
5740 * MC_CMD_FCNTL_AUTO. If auto-negotiation is disabled the driver must
5741 * explicitly configure pause mode with MC_CMD_SET_MAC.
5742 */
5743#define MC_CMD_LINK_CTRL_IN_ADVERTISED_PAUSE_ABILITIES_MASK_OFST 32
5744#define MC_CMD_LINK_CTRL_IN_ADVERTISED_PAUSE_ABILITIES_MASK_LEN 1
5745/* enum property: bitshift */
5746/* Enum values, see field(s): */
5747/* MC_CMD_PAUSE_MODE/TYPE */
5748/* When auto-negotiation is enabled, this is the FEC mode to request. Note that
5749 * a weaker FEC mode may get negotiated, depending on what the link partner
5750 * supports. The driver should subsequently use MC_CMD_GET_LINK to check the
5751 * actual negotiated FEC mode. When auto-negotiation is disabled, this is the
5752 * forced FEC mode.
5753 */
5754#define MC_CMD_LINK_CTRL_IN_FEC_MODE_OFST 33
5755#define MC_CMD_LINK_CTRL_IN_FEC_MODE_LEN 1
5756/* enum property: value */
5757/* Enum values, see field(s): */
5758/* FEC_TYPE/TYPE */
5759/* This is only to be used when auto-negotiation is disabled (forced speed or
5760 * loopback mode). If the specified value does not align with the values
5761 * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
5762 */
5763#define MC_CMD_LINK_CTRL_IN_LINK_TECHNOLOGY_OFST 36
5764#define MC_CMD_LINK_CTRL_IN_LINK_TECHNOLOGY_LEN 2
5765/* enum property: value */
5766/* Enum values, see field(s): */
5767/* MC_CMD_ETH_TECH/TECH */
5768/* The sequence number of the last MODULECHANGE event. If this doesn't match,
5769 * fail with EAGAIN.
5770 */
5771#define MC_CMD_LINK_CTRL_IN_MODULE_SEQ_OFST 38
5772#define MC_CMD_LINK_CTRL_IN_MODULE_SEQ_LEN 1
5773/* Loopback Mode. Only valid when auto-negotiation is disabled. */
5774#define MC_CMD_LINK_CTRL_IN_LOOPBACK_OFST 39
5775#define MC_CMD_LINK_CTRL_IN_LOOPBACK_LEN 1
5776/* enum property: value */
5777/* Enum values, see field(s): */
5778/* MC_CMD_LOOPBACK_V2/MODE */
5779
5780/* MC_CMD_LINK_CTRL_OUT msgresponse */
5781#define MC_CMD_LINK_CTRL_OUT_LEN 0
5782
5783
5784/***********************************/
5785/* MC_CMD_LINK_STATE
5786 */
5787#define MC_CMD_LINK_STATE 0x6c
5788#undef MC_CMD_0x6c_PRIVILEGE_CTG
5789
5790#define MC_CMD_0x6c_PRIVILEGE_CTG SRIOV_CTG_LINK
5791
5792/* MC_CMD_LINK_STATE_IN msgrequest */
5793#define MC_CMD_LINK_STATE_IN_LEN 4
5794/* Handle to the port to get link state for. */
5795#define MC_CMD_LINK_STATE_IN_PORT_HANDLE_OFST 0
5796#define MC_CMD_LINK_STATE_IN_PORT_HANDLE_LEN 4
5797
5798/* MC_CMD_LINK_STATE_OUT msgresponse */
5799#define MC_CMD_LINK_STATE_OUT_LEN 114
5800/* Flags used to report the current configuration/state of the link. */
5801#define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_OFST 0
5802#define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LEN 8
5803#define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_OFST 0
5804#define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_LEN 4
5805#define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_LBN 0
5806#define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_WIDTH 32
5807#define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_OFST 4
5808#define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_LEN 4
5809#define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_LBN 32
5810#define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_WIDTH 32
5811/* enum property: value */
5812/* Enum values, see field(s): */
5813/* MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */
5814/* Configured technology. If the specified value does not align with the values
5815 * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
5816 */
5817#define MC_CMD_LINK_STATE_OUT_LINK_TECHNOLOGY_OFST 8
5818#define MC_CMD_LINK_STATE_OUT_LINK_TECHNOLOGY_LEN 2
5819/* enum property: value */
5820/* Enum values, see field(s): */
5821/* MC_CMD_ETH_TECH/TECH */
5822/* Configured FEC mode */
5823#define MC_CMD_LINK_STATE_OUT_FEC_MODE_OFST 10
5824#define MC_CMD_LINK_STATE_OUT_FEC_MODE_LEN 1
5825/* enum property: value */
5826/* Enum values, see field(s): */
5827/* FEC_TYPE/TYPE */
5828/* Bitmask of auto-negotiated pause modes */
5829#define MC_CMD_LINK_STATE_OUT_PAUSE_MASK_OFST 11
5830#define MC_CMD_LINK_STATE_OUT_PAUSE_MASK_LEN 1
5831/* enum property: bitshift */
5832/* Enum values, see field(s): */
5833/* MC_CMD_PAUSE_MODE/TYPE */
5834/* Configured loopback mode */
5835#define MC_CMD_LINK_STATE_OUT_LOOPBACK_OFST 12
5836#define MC_CMD_LINK_STATE_OUT_LOOPBACK_LEN 1
5837/* enum property: value */
5838/* Enum values, see field(s): */
5839/* MC_CMD_LOOPBACK_V2/MODE */
5840/* Abilities requested by the driver to advertise during auto-negotiation */
5841#define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_OFST 16
5842#define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_LEN 32
5843/* See structuredef: MC_CMD_ETH_AN_FIELDS */
5844#define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_TECH_MASK_OFST 16
5845#define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_TECH_MASK_LEN 16
5846#define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_MASK_OFST 32
5847#define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_MASK_LEN 4
5848#define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_REQ_OFST 36
5849#define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_REQ_LEN 4
5850#define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_PAUSE_MASK_OFST 40
5851#define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_PAUSE_MASK_LEN 1
5852/* Abilities advertised by the link partner during auto-negotiation */
5853#define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_OFST 48
5854#define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_LEN 32
5855/* See structuredef: MC_CMD_ETH_AN_FIELDS */
5856#define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_TECH_MASK_OFST 48
5857#define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_TECH_MASK_LEN 16
5858#define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_MASK_OFST 64
5859#define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_MASK_LEN 4
5860#define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_REQ_OFST 68
5861#define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_REQ_LEN 4
5862#define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_PAUSE_MASK_OFST 72
5863#define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_PAUSE_MASK_LEN 1
5864/* Abilities supported by the local device (including cable abilities) For
5865 * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO
5866 */
5867#define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_OFST 80
5868#define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_LEN 28
5869/* See structuredef: MC_CMD_ETH_AN_FIELDS */
5870#define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_TECH_MASK_OFST 80
5871#define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_TECH_MASK_LEN 16
5872#define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_MASK_OFST 96
5873#define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_MASK_LEN 4
5874#define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_REQ_OFST 100
5875#define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_REQ_LEN 4
5876#define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_PAUSE_MASK_OFST 104
5877#define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_PAUSE_MASK_LEN 1
5878/* Control flags */
5879#define MC_CMD_LINK_STATE_OUT_CONTROL_FLAGS_OFST 108
5880#define MC_CMD_LINK_STATE_OUT_CONTROL_FLAGS_LEN 4
5881/* enum property: bitshift */
5882/* Enum values, see field(s): */
5883/* MC_CMD_LINK_FLAGS/MASK */
5884/* Sequence number to synchronize link change events */
5885#define MC_CMD_LINK_STATE_OUT_PORT_LINKCHANGE_SEQ_NUM_OFST 112
5886#define MC_CMD_LINK_STATE_OUT_PORT_LINKCHANGE_SEQ_NUM_LEN 1
5887/* Sequence number to synchronize module change events */
5888#define MC_CMD_LINK_STATE_OUT_PORT_MODULECHANGE_SEQ_NUM_OFST 113
5889#define MC_CMD_LINK_STATE_OUT_PORT_MODULECHANGE_SEQ_NUM_LEN 1
5890
5891/* MC_CMD_LINK_STATE_OUT_V2 msgresponse: Updated LINK_STATE_OUT with
5892 * LOCAL_AN_SUPPORT
5893 */
5894#define MC_CMD_LINK_STATE_OUT_V2_LEN 120
5895/* Flags used to report the current configuration/state of the link. */
5896#define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_OFST 0
5897#define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LEN 8
5898#define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_OFST 0
5899#define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_LEN 4
5900#define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_LBN 0
5901#define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_WIDTH 32
5902#define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_OFST 4
5903#define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_LEN 4
5904#define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_LBN 32
5905#define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_WIDTH 32
5906/* enum property: value */
5907/* Enum values, see field(s): */
5908/* MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */
5909/* Configured technology. If the specified value does not align with the values
5910 * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
5911 */
5912#define MC_CMD_LINK_STATE_OUT_V2_LINK_TECHNOLOGY_OFST 8
5913#define MC_CMD_LINK_STATE_OUT_V2_LINK_TECHNOLOGY_LEN 2
5914/* enum property: value */
5915/* Enum values, see field(s): */
5916/* MC_CMD_ETH_TECH/TECH */
5917/* Configured FEC mode */
5918#define MC_CMD_LINK_STATE_OUT_V2_FEC_MODE_OFST 10
5919#define MC_CMD_LINK_STATE_OUT_V2_FEC_MODE_LEN 1
5920/* enum property: value */
5921/* Enum values, see field(s): */
5922/* FEC_TYPE/TYPE */
5923/* Bitmask of auto-negotiated pause modes */
5924#define MC_CMD_LINK_STATE_OUT_V2_PAUSE_MASK_OFST 11
5925#define MC_CMD_LINK_STATE_OUT_V2_PAUSE_MASK_LEN 1
5926/* enum property: bitshift */
5927/* Enum values, see field(s): */
5928/* MC_CMD_PAUSE_MODE/TYPE */
5929/* Configured loopback mode */
5930#define MC_CMD_LINK_STATE_OUT_V2_LOOPBACK_OFST 12
5931#define MC_CMD_LINK_STATE_OUT_V2_LOOPBACK_LEN 1
5932/* enum property: value */
5933/* Enum values, see field(s): */
5934/* MC_CMD_LOOPBACK_V2/MODE */
5935/* Abilities requested by the driver to advertise during auto-negotiation */
5936#define MC_CMD_LINK_STATE_OUT_V2_ADVERTISED_ABILITIES_OFST 16
5937#define MC_CMD_LINK_STATE_OUT_V2_ADVERTISED_ABILITIES_LEN 32
5938/* Abilities advertised by the link partner during auto-negotiation */
5939#define MC_CMD_LINK_STATE_OUT_V2_LINK_PARTNER_ABILITIES_OFST 48
5940#define MC_CMD_LINK_STATE_OUT_V2_LINK_PARTNER_ABILITIES_LEN 32
5941/* Abilities supported by the local device (including cable abilities) For
5942 * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO
5943 */
5944#define MC_CMD_LINK_STATE_OUT_V2_SUPPORTED_ABILITIES_OFST 80
5945#define MC_CMD_LINK_STATE_OUT_V2_SUPPORTED_ABILITIES_LEN 28
5946/* Control flags */
5947#define MC_CMD_LINK_STATE_OUT_V2_CONTROL_FLAGS_OFST 108
5948#define MC_CMD_LINK_STATE_OUT_V2_CONTROL_FLAGS_LEN 4
5949/* enum property: bitshift */
5950/* Enum values, see field(s): */
5951/* MC_CMD_LINK_FLAGS/MASK */
5952/* Sequence number to synchronize link change events */
5953#define MC_CMD_LINK_STATE_OUT_V2_PORT_LINKCHANGE_SEQ_NUM_OFST 112
5954#define MC_CMD_LINK_STATE_OUT_V2_PORT_LINKCHANGE_SEQ_NUM_LEN 1
5955/* Sequence number to synchronize module change events */
5956#define MC_CMD_LINK_STATE_OUT_V2_PORT_MODULECHANGE_SEQ_NUM_OFST 113
5957#define MC_CMD_LINK_STATE_OUT_V2_PORT_MODULECHANGE_SEQ_NUM_LEN 1
5958/* Reports the auto-negotiation supported by the local device. This depends on
5959 * the port and module properties.
5960 */
5961#define MC_CMD_LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT_OFST 116
5962#define MC_CMD_LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT_LEN 4
5963/* Enum values, see field(s): */
5964/* AN_TYPE/TYPE */
5965
5966/* MC_CMD_LINK_STATE_OUT_V3 msgresponse: Updated LINK_STATE_OUT_V2 for explicit
5967 * reporting of the link speed and duplex mode.
5968 */
5969#define MC_CMD_LINK_STATE_OUT_V3_LEN 128
5970/* Flags used to report the current configuration/state of the link. */
5971#define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_OFST 0
5972#define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LEN 8
5973#define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_OFST 0
5974#define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_LEN 4
5975#define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_LBN 0
5976#define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_WIDTH 32
5977#define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_OFST 4
5978#define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_LEN 4
5979#define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_LBN 32
5980#define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_WIDTH 32
5981/* enum property: value */
5982/* Enum values, see field(s): */
5983/* MC_CMD_LINK_STATUS_FLAGS/STATUS_FLAGS */
5984/* Configured technology. If the specified value does not align with the values
5985 * defined in the enum MC_CMD_ETH_TECH/TECH, it is considered invalid.
5986 */
5987#define MC_CMD_LINK_STATE_OUT_V3_LINK_TECHNOLOGY_OFST 8
5988#define MC_CMD_LINK_STATE_OUT_V3_LINK_TECHNOLOGY_LEN 2
5989/* enum property: value */
5990/* Enum values, see field(s): */
5991/* MC_CMD_ETH_TECH/TECH */
5992/* Configured FEC mode */
5993#define MC_CMD_LINK_STATE_OUT_V3_FEC_MODE_OFST 10
5994#define MC_CMD_LINK_STATE_OUT_V3_FEC_MODE_LEN 1
5995/* enum property: value */
5996/* Enum values, see field(s): */
5997/* FEC_TYPE/TYPE */
5998/* Bitmask of auto-negotiated pause modes */
5999#define MC_CMD_LINK_STATE_OUT_V3_PAUSE_MASK_OFST 11
6000#define MC_CMD_LINK_STATE_OUT_V3_PAUSE_MASK_LEN 1
6001/* enum property: bitshift */
6002/* Enum values, see field(s): */
6003/* MC_CMD_PAUSE_MODE/TYPE */
6004/* Configured loopback mode */
6005#define MC_CMD_LINK_STATE_OUT_V3_LOOPBACK_OFST 12
6006#define MC_CMD_LINK_STATE_OUT_V3_LOOPBACK_LEN 1
6007/* enum property: value */
6008/* Enum values, see field(s): */
6009/* MC_CMD_LOOPBACK_V2/MODE */
6010/* Abilities requested by the driver to advertise during auto-negotiation */
6011#define MC_CMD_LINK_STATE_OUT_V3_ADVERTISED_ABILITIES_OFST 16
6012#define MC_CMD_LINK_STATE_OUT_V3_ADVERTISED_ABILITIES_LEN 32
6013/* Abilities advertised by the link partner during auto-negotiation */
6014#define MC_CMD_LINK_STATE_OUT_V3_LINK_PARTNER_ABILITIES_OFST 48
6015#define MC_CMD_LINK_STATE_OUT_V3_LINK_PARTNER_ABILITIES_LEN 32
6016/* Abilities supported by the local device (including cable abilities) For
6017 * fixed local device capbilities see MC_CMD_GET_LOCAL_DEVICE_INFO
6018 */
6019#define MC_CMD_LINK_STATE_OUT_V3_SUPPORTED_ABILITIES_OFST 80
6020#define MC_CMD_LINK_STATE_OUT_V3_SUPPORTED_ABILITIES_LEN 28
6021/* Control flags */
6022#define MC_CMD_LINK_STATE_OUT_V3_CONTROL_FLAGS_OFST 108
6023#define MC_CMD_LINK_STATE_OUT_V3_CONTROL_FLAGS_LEN 4
6024/* enum property: bitshift */
6025/* Enum values, see field(s): */
6026/* MC_CMD_LINK_FLAGS/MASK */
6027/* Sequence number to synchronize link change events */
6028#define MC_CMD_LINK_STATE_OUT_V3_PORT_LINKCHANGE_SEQ_NUM_OFST 112
6029#define MC_CMD_LINK_STATE_OUT_V3_PORT_LINKCHANGE_SEQ_NUM_LEN 1
6030/* Sequence number to synchronize module change events */
6031#define MC_CMD_LINK_STATE_OUT_V3_PORT_MODULECHANGE_SEQ_NUM_OFST 113
6032#define MC_CMD_LINK_STATE_OUT_V3_PORT_MODULECHANGE_SEQ_NUM_LEN 1
6033/* Reports the auto-negotiation supported by the local device. This depends on
6034 * the port and module properties.
6035 */
6036#define MC_CMD_LINK_STATE_OUT_V3_LOCAL_AN_SUPPORT_OFST 116
6037#define MC_CMD_LINK_STATE_OUT_V3_LOCAL_AN_SUPPORT_LEN 4
6038/* Enum values, see field(s): */
6039/* AN_TYPE/TYPE */
6040/* Autonegotiated speed in mbit/s. The link may still be down even if this
6041 * reads non-zero. LINK_SPEED field is intended to be used by drivers without
6042 * the most up-to-date MCDI definitions, unable to deduce the link speed from
6043 * the reported LINK_TECHNOLOGY field.
6044 */
6045#define MC_CMD_LINK_STATE_OUT_V3_LINK_SPEED_OFST 120
6046#define MC_CMD_LINK_STATE_OUT_V3_LINK_SPEED_LEN 4
6047#define MC_CMD_LINK_STATE_OUT_V3_FLAGS_OFST 124
6048#define MC_CMD_LINK_STATE_OUT_V3_FLAGS_LEN 4
6049#define MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_OFST 124
6050#define MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_LBN 0
6051#define MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_WIDTH 1
6052
6053
6054/***********************************/
6055/* MC_CMD_GET_LINK
6056 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
6057 * ETIME.
6058 */
6059#define MC_CMD_GET_LINK 0x29
6060#undef MC_CMD_0x29_PRIVILEGE_CTG
6061
6062#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6063
6064/* MC_CMD_GET_LINK_IN msgrequest */
6065#define MC_CMD_GET_LINK_IN_LEN 0
6066
6067/* MC_CMD_GET_LINK_IN_V2 msgrequest */
6068#define MC_CMD_GET_LINK_IN_V2_LEN 8
6069/* Target port to request link state for. Uses MAE_LINK_ENDPOINT_SELECTOR which
6070 * identifies a real or virtual network port by MAE port and link end. See the
6071 * structure definition for more details.
6072 */
6073#define MC_CMD_GET_LINK_IN_V2_TARGET_OFST 0
6074#define MC_CMD_GET_LINK_IN_V2_TARGET_LEN 8
6075#define MC_CMD_GET_LINK_IN_V2_TARGET_LO_OFST 0
6076#define MC_CMD_GET_LINK_IN_V2_TARGET_LO_LEN 4
6077#define MC_CMD_GET_LINK_IN_V2_TARGET_LO_LBN 0
6078#define MC_CMD_GET_LINK_IN_V2_TARGET_LO_WIDTH 32
6079#define MC_CMD_GET_LINK_IN_V2_TARGET_HI_OFST 4
6080#define MC_CMD_GET_LINK_IN_V2_TARGET_HI_LEN 4
6081#define MC_CMD_GET_LINK_IN_V2_TARGET_HI_LBN 32
6082#define MC_CMD_GET_LINK_IN_V2_TARGET_HI_WIDTH 32
6083/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
6084#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_OFST 0
6085#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_LEN 4
6086#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0
6087#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4
6088#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_TYPE_OFST 3
6089#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_TYPE_LEN 1
6090#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
6091#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
6092#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
6093#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
6094#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
6095#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
6096#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
6097#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
6098#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
6099#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
6100#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
6101#define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
6102#define MC_CMD_GET_LINK_IN_V2_TARGET_LINK_END_OFST 4
6103#define MC_CMD_GET_LINK_IN_V2_TARGET_LINK_END_LEN 4
6104#define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_OFST 0
6105#define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LEN 8
6106#define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LO_OFST 0
6107#define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LO_LEN 4
6108#define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LO_LBN 0
6109#define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LO_WIDTH 32
6110#define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_HI_OFST 4
6111#define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_HI_LEN 4
6112#define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_HI_LBN 32
6113#define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_HI_WIDTH 32
6114
6115/* MC_CMD_GET_LINK_OUT msgresponse */
6116#define MC_CMD_GET_LINK_OUT_LEN 28
6117/* Near-side advertised capabilities. Refer to
6118 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
6119 */
6120#define MC_CMD_GET_LINK_OUT_CAP_OFST 0
6121#define MC_CMD_GET_LINK_OUT_CAP_LEN 4
6122/* Link-partner advertised capabilities. Refer to
6123 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
6124 */
6125#define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
6126#define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
6127/* Autonegotiated speed in mbit/s. The link may still be down even if this
6128 * reads non-zero.
6129 */
6130#define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
6131#define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
6132/* Current loopback setting. */
6133#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
6134#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
6135/* Enum values, see field(s): */
6136/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
6137#define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
6138#define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
6139#define MC_CMD_GET_LINK_OUT_LINK_UP_OFST 16
6140#define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
6141#define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
6142#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_OFST 16
6143#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
6144#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
6145#define MC_CMD_GET_LINK_OUT_BPX_LINK_OFST 16
6146#define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
6147#define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
6148#define MC_CMD_GET_LINK_OUT_PHY_LINK_OFST 16
6149#define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
6150#define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
6151#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_OFST 16
6152#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
6153#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
6154#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_OFST 16
6155#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
6156#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
6157#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_OFST 16
6158#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_LBN 8
6159#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_WIDTH 1
6160#define MC_CMD_GET_LINK_OUT_MODULE_UP_OFST 16
6161#define MC_CMD_GET_LINK_OUT_MODULE_UP_LBN 9
6162#define MC_CMD_GET_LINK_OUT_MODULE_UP_WIDTH 1
6163/* This returns the negotiated flow control value. */
6164#define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
6165#define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
6166/* enum property: value */
6167/* Enum values, see field(s): */
6168/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
6169#define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
6170#define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
6171#define MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24
6172#define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
6173#define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
6174#define MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24
6175#define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
6176#define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
6177#define MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24
6178#define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
6179#define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
6180#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24
6181#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
6182#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
6183
6184/* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */
6185#define MC_CMD_GET_LINK_OUT_V2_LEN 44
6186/* Near-side advertised capabilities. Refer to
6187 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
6188 */
6189#define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
6190#define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
6191/* Link-partner advertised capabilities. Refer to
6192 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
6193 */
6194#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
6195#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
6196/* Autonegotiated speed in mbit/s. The link may still be down even if this
6197 * reads non-zero.
6198 */
6199#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 8
6200#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
6201/* Current loopback setting. */
6202#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 12
6203#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
6204/* Enum values, see field(s): */
6205/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
6206#define MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16
6207#define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
6208#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_OFST 16
6209#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
6210#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1
6211#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_OFST 16
6212#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1
6213#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1
6214#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_OFST 16
6215#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2
6216#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1
6217#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_OFST 16
6218#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3
6219#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1
6220#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_OFST 16
6221#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6
6222#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1
6223#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_OFST 16
6224#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7
6225#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1
6226#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_OFST 16
6227#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_LBN 8
6228#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_WIDTH 1
6229#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_OFST 16
6230#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_LBN 9
6231#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_WIDTH 1
6232/* This returns the negotiated flow control value. */
6233#define MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20
6234#define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
6235/* enum property: value */
6236/* Enum values, see field(s): */
6237/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
6238#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24
6239#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
6240/* MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24 */
6241/* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
6242/* MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */
6243/* MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24 */
6244/* MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */
6245/* MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */
6246/* MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24 */
6247/* MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */
6248/* MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */
6249/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24 */
6250/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */
6251/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */
6252/* True local device capabilities (taking into account currently used PMD/MDI,
6253 * e.g. plugged-in module). In general, subset of
6254 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST
6255 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
6256 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to
6257 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
6258 */
6259#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 28
6260#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
6261/* Auto-negotiation type used on the link */
6262#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 32
6263#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
6264/* Enum values, see field(s): */
6265/* AN_TYPE/TYPE */
6266/* Forward error correction used on the link */
6267#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 36
6268#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
6269/* Enum values, see field(s): */
6270/* FEC_TYPE/TYPE */
6271#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40
6272#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
6273#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_OFST 40
6274#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
6275#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1
6276#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_OFST 40
6277#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1
6278#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1
6279#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_OFST 40
6280#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2
6281#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1
6282#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_OFST 40
6283#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3
6284#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1
6285#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_OFST 40
6286#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
6287#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1
6288#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_OFST 40
6289#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5
6290#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1
6291#define MC_CMD_GET_LINK_OUT_V2_HI_BER_OFST 40
6292#define MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6
6293#define MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1
6294#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_OFST 40
6295#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7
6296#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1
6297#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_OFST 40
6298#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8
6299#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1
6300#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_OFST 40
6301#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_LBN 9
6302#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_WIDTH 1
6303
6304
6305/***********************************/
6306/* MC_CMD_SET_LINK
6307 * Write the unified MAC/PHY link configuration. Locks required: None. Return
6308 * code: 0, EINVAL, ETIME, EAGAIN
6309 */
6310#define MC_CMD_SET_LINK 0x2a
6311#undef MC_CMD_0x2a_PRIVILEGE_CTG
6312
6313#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
6314
6315/* MC_CMD_SET_LINK_IN msgrequest */
6316#define MC_CMD_SET_LINK_IN_LEN 16
6317/* Near-side advertised capabilities. Refer to
6318 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
6319 */
6320#define MC_CMD_SET_LINK_IN_CAP_OFST 0
6321#define MC_CMD_SET_LINK_IN_CAP_LEN 4
6322/* Flags */
6323#define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
6324#define MC_CMD_SET_LINK_IN_FLAGS_LEN 4
6325#define MC_CMD_SET_LINK_IN_LOWPOWER_OFST 4
6326#define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
6327#define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
6328#define MC_CMD_SET_LINK_IN_POWEROFF_OFST 4
6329#define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
6330#define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
6331#define MC_CMD_SET_LINK_IN_TXDIS_OFST 4
6332#define MC_CMD_SET_LINK_IN_TXDIS_LBN 2
6333#define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
6334#define MC_CMD_SET_LINK_IN_LINKDOWN_OFST 4
6335#define MC_CMD_SET_LINK_IN_LINKDOWN_LBN 3
6336#define MC_CMD_SET_LINK_IN_LINKDOWN_WIDTH 1
6337/* Loopback mode. */
6338#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
6339#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
6340/* Enum values, see field(s): */
6341/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
6342/* A loopback speed of "0" is supported, and means (choose any available
6343 * speed).
6344 */
6345#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
6346#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
6347
6348/* MC_CMD_SET_LINK_IN_V2 msgrequest: Updated SET_LINK to include sequence
6349 * number to ensure this SET_LINK command corresponds to the latest
6350 * MODULECHANGE event.
6351 */
6352#define MC_CMD_SET_LINK_IN_V2_LEN 17
6353/* Near-side advertised capabilities. Refer to
6354 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
6355 */
6356#define MC_CMD_SET_LINK_IN_V2_CAP_OFST 0
6357#define MC_CMD_SET_LINK_IN_V2_CAP_LEN 4
6358/* Flags */
6359#define MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4
6360#define MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4
6361#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4
6362#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 0
6363#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_WIDTH 1
6364#define MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4
6365#define MC_CMD_SET_LINK_IN_V2_POWEROFF_LBN 1
6366#define MC_CMD_SET_LINK_IN_V2_POWEROFF_WIDTH 1
6367#define MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4
6368#define MC_CMD_SET_LINK_IN_V2_TXDIS_LBN 2
6369#define MC_CMD_SET_LINK_IN_V2_TXDIS_WIDTH 1
6370#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4
6371#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_LBN 3
6372#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_WIDTH 1
6373/* Loopback mode. */
6374#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_OFST 8
6375#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4
6376/* Enum values, see field(s): */
6377/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
6378/* A loopback speed of "0" is supported, and means (choose any available
6379 * speed).
6380 */
6381#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_OFST 12
6382#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4
6383#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_OFST 16
6384#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_LEN 1
6385#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_OFST 16
6386#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 0
6387#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_WIDTH 7
6388#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_OFST 16
6389#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_LBN 7
6390#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 1
6391
6392/* MC_CMD_SET_LINK_IN_V3 msgrequest */
6393#define MC_CMD_SET_LINK_IN_V3_LEN 28
6394/* Near-side advertised capabilities. Refer to
6395 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
6396 */
6397#define MC_CMD_SET_LINK_IN_V3_CAP_OFST 0
6398#define MC_CMD_SET_LINK_IN_V3_CAP_LEN 4
6399/* Flags */
6400#define MC_CMD_SET_LINK_IN_V3_FLAGS_OFST 4
6401#define MC_CMD_SET_LINK_IN_V3_FLAGS_LEN 4
6402#define MC_CMD_SET_LINK_IN_V3_LOWPOWER_OFST 4
6403#define MC_CMD_SET_LINK_IN_V3_LOWPOWER_LBN 0
6404#define MC_CMD_SET_LINK_IN_V3_LOWPOWER_WIDTH 1
6405#define MC_CMD_SET_LINK_IN_V3_POWEROFF_OFST 4
6406#define MC_CMD_SET_LINK_IN_V3_POWEROFF_LBN 1
6407#define MC_CMD_SET_LINK_IN_V3_POWEROFF_WIDTH 1
6408#define MC_CMD_SET_LINK_IN_V3_TXDIS_OFST 4
6409#define MC_CMD_SET_LINK_IN_V3_TXDIS_LBN 2
6410#define MC_CMD_SET_LINK_IN_V3_TXDIS_WIDTH 1
6411#define MC_CMD_SET_LINK_IN_V3_LINKDOWN_OFST 4
6412#define MC_CMD_SET_LINK_IN_V3_LINKDOWN_LBN 3
6413#define MC_CMD_SET_LINK_IN_V3_LINKDOWN_WIDTH 1
6414/* Loopback mode. */
6415#define MC_CMD_SET_LINK_IN_V3_LOOPBACK_MODE_OFST 8
6416#define MC_CMD_SET_LINK_IN_V3_LOOPBACK_MODE_LEN 4
6417/* Enum values, see field(s): */
6418/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
6419/* A loopback speed of "0" is supported, and means (choose any available
6420 * speed).
6421 */
6422#define MC_CMD_SET_LINK_IN_V3_LOOPBACK_SPEED_OFST 12
6423#define MC_CMD_SET_LINK_IN_V3_LOOPBACK_SPEED_LEN 4
6424#define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_OFST 16
6425#define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_LEN 1
6426#define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_NUMBER_OFST 16
6427#define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_NUMBER_LBN 0
6428#define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_NUMBER_WIDTH 7
6429#define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_IGNORE_OFST 16
6430#define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_IGNORE_LBN 7
6431#define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_IGNORE_WIDTH 1
6432/* Padding */
6433#define MC_CMD_SET_LINK_IN_V3_RESERVED_OFST 17
6434#define MC_CMD_SET_LINK_IN_V3_RESERVED_LEN 3
6435/* Target port to set link state for. Uses MAE_LINK_ENDPOINT_SELECTOR which
6436 * identifies a real or virtual network port by MAE port and link end. See the
6437 * structure definition for more details
6438 */
6439#define MC_CMD_SET_LINK_IN_V3_TARGET_OFST 20
6440#define MC_CMD_SET_LINK_IN_V3_TARGET_LEN 8
6441#define MC_CMD_SET_LINK_IN_V3_TARGET_LO_OFST 20
6442#define MC_CMD_SET_LINK_IN_V3_TARGET_LO_LEN 4
6443#define MC_CMD_SET_LINK_IN_V3_TARGET_LO_LBN 160
6444#define MC_CMD_SET_LINK_IN_V3_TARGET_LO_WIDTH 32
6445#define MC_CMD_SET_LINK_IN_V3_TARGET_HI_OFST 24
6446#define MC_CMD_SET_LINK_IN_V3_TARGET_HI_LEN 4
6447#define MC_CMD_SET_LINK_IN_V3_TARGET_HI_LBN 192
6448#define MC_CMD_SET_LINK_IN_V3_TARGET_HI_WIDTH 32
6449/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
6450#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_OFST 20
6451#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_LEN 4
6452#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FLAT_OFST 20
6453#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FLAT_LEN 4
6454#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_TYPE_OFST 23
6455#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_TYPE_LEN 1
6456#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 20
6457#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
6458#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 160
6459#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
6460#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 180
6461#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
6462#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 176
6463#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
6464#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 22
6465#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
6466#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 20
6467#define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
6468#define MC_CMD_SET_LINK_IN_V3_TARGET_LINK_END_OFST 24
6469#define MC_CMD_SET_LINK_IN_V3_TARGET_LINK_END_LEN 4
6470#define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_OFST 20
6471#define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_LEN 8
6472#define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_LO_OFST 20
6473#define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_LO_LEN 4
6474#define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_LO_LBN 160
6475#define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_LO_WIDTH 32
6476#define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_HI_OFST 24
6477#define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_HI_LEN 4
6478#define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_HI_LBN 192
6479#define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_HI_WIDTH 32
6480
6481/* MC_CMD_SET_LINK_OUT msgresponse */
6482#define MC_CMD_SET_LINK_OUT_LEN 0
6483
6484
6485/***********************************/
6486/* MC_CMD_SET_ID_LED
6487 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
6488 */
6489#define MC_CMD_SET_ID_LED 0x2b
6490#undef MC_CMD_0x2b_PRIVILEGE_CTG
6491
6492#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
6493
6494/* MC_CMD_SET_ID_LED_IN msgrequest */
6495#define MC_CMD_SET_ID_LED_IN_LEN 4
6496/* Set LED state. */
6497#define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
6498#define MC_CMD_SET_ID_LED_IN_STATE_LEN 4
6499#define MC_CMD_LED_OFF 0x0 /* enum */
6500#define MC_CMD_LED_ON 0x1 /* enum */
6501#define MC_CMD_LED_DEFAULT 0x2 /* enum */
6502
6503/* MC_CMD_SET_ID_LED_OUT msgresponse */
6504#define MC_CMD_SET_ID_LED_OUT_LEN 0
6505
6506
6507/***********************************/
6508/* MC_CMD_SET_MAC
6509 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
6510 */
6511#define MC_CMD_SET_MAC 0x2c
6512#undef MC_CMD_0x2c_PRIVILEGE_CTG
6513
6514#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6515
6516/* MC_CMD_SET_MAC_IN msgrequest */
6517#define MC_CMD_SET_MAC_IN_LEN 28
6518/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
6519 * EtherII, VLAN, bug16011 padding).
6520 */
6521#define MC_CMD_SET_MAC_IN_MTU_OFST 0
6522#define MC_CMD_SET_MAC_IN_MTU_LEN 4
6523#define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
6524#define MC_CMD_SET_MAC_IN_DRAIN_LEN 4
6525#define MC_CMD_SET_MAC_IN_ADDR_OFST 8
6526#define MC_CMD_SET_MAC_IN_ADDR_LEN 8
6527#define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
6528#define MC_CMD_SET_MAC_IN_ADDR_LO_LEN 4
6529#define MC_CMD_SET_MAC_IN_ADDR_LO_LBN 64
6530#define MC_CMD_SET_MAC_IN_ADDR_LO_WIDTH 32
6531#define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
6532#define MC_CMD_SET_MAC_IN_ADDR_HI_LEN 4
6533#define MC_CMD_SET_MAC_IN_ADDR_HI_LBN 96
6534#define MC_CMD_SET_MAC_IN_ADDR_HI_WIDTH 32
6535#define MC_CMD_SET_MAC_IN_REJECT_OFST 16
6536#define MC_CMD_SET_MAC_IN_REJECT_LEN 4
6537#define MC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 16
6538#define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
6539#define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
6540#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_OFST 16
6541#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
6542#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
6543#define MC_CMD_SET_MAC_IN_FCNTL_OFST 20
6544#define MC_CMD_SET_MAC_IN_FCNTL_LEN 4
6545/* enum: Flow control is off. */
6546/* MC_CMD_FCNTL_OFF 0x0 */
6547/* enum: Respond to flow control. */
6548/* MC_CMD_FCNTL_RESPOND 0x1 */
6549/* enum: Respond to and Issue flow control. */
6550/* MC_CMD_FCNTL_BIDIR 0x2 */
6551/* enum: Auto negotiate flow control. */
6552/* MC_CMD_FCNTL_AUTO 0x3 */
6553/* enum: Priority flow control. This is only supported on KSB. */
6554/* MC_CMD_FCNTL_QBB 0x4 */
6555/* enum: Issue flow control. */
6556/* MC_CMD_FCNTL_GENERATE 0x5 */
6557#define MC_CMD_SET_MAC_IN_FLAGS_OFST 24
6558#define MC_CMD_SET_MAC_IN_FLAGS_LEN 4
6559#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 24
6560#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
6561#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1
6562
6563/* MC_CMD_SET_MAC_EXT_IN msgrequest */
6564#define MC_CMD_SET_MAC_EXT_IN_LEN 32
6565/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
6566 * EtherII, VLAN, bug16011 padding).
6567 */
6568#define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
6569#define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
6570#define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
6571#define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
6572#define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
6573#define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
6574#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
6575#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LEN 4
6576#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LBN 64
6577#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_WIDTH 32
6578#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
6579#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LEN 4
6580#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LBN 96
6581#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_WIDTH 32
6582#define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
6583#define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
6584#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 16
6585#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
6586#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
6587#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_OFST 16
6588#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
6589#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
6590#define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20
6591#define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
6592/* enum: Flow control is off. */
6593/* MC_CMD_FCNTL_OFF 0x0 */
6594/* enum: Respond to flow control. */
6595/* MC_CMD_FCNTL_RESPOND 0x1 */
6596/* enum: Respond to and Issue flow control. */
6597/* MC_CMD_FCNTL_BIDIR 0x2 */
6598/* enum: Auto negotiate flow control. */
6599/* MC_CMD_FCNTL_AUTO 0x3 */
6600/* enum: Priority flow control. This is only supported on KSB. */
6601/* MC_CMD_FCNTL_QBB 0x4 */
6602/* enum: Issue flow control. */
6603/* MC_CMD_FCNTL_GENERATE 0x5 */
6604#define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24
6605#define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
6606#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_OFST 24
6607#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
6608#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
6609/* Select which parameters to configure. A parameter will only be modified if
6610 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
6611 * capabilities then this field is ignored (and all flags are assumed to be
6612 * set).
6613 */
6614#define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28
6615#define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
6616#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_OFST 28
6617#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
6618#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
6619#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_OFST 28
6620#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
6621#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
6622#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_OFST 28
6623#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2
6624#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
6625#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_OFST 28
6626#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3
6627#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
6628#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_OFST 28
6629#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
6630#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
6631
6632/* MC_CMD_SET_MAC_V3_IN msgrequest */
6633#define MC_CMD_SET_MAC_V3_IN_LEN 40
6634/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
6635 * EtherII, VLAN, bug16011 padding).
6636 */
6637#define MC_CMD_SET_MAC_V3_IN_MTU_OFST 0
6638#define MC_CMD_SET_MAC_V3_IN_MTU_LEN 4
6639#define MC_CMD_SET_MAC_V3_IN_DRAIN_OFST 4
6640#define MC_CMD_SET_MAC_V3_IN_DRAIN_LEN 4
6641#define MC_CMD_SET_MAC_V3_IN_ADDR_OFST 8
6642#define MC_CMD_SET_MAC_V3_IN_ADDR_LEN 8
6643#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_OFST 8
6644#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LEN 4
6645#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LBN 64
6646#define MC_CMD_SET_MAC_V3_IN_ADDR_LO_WIDTH 32
6647#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_OFST 12
6648#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LEN 4
6649#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LBN 96
6650#define MC_CMD_SET_MAC_V3_IN_ADDR_HI_WIDTH 32
6651#define MC_CMD_SET_MAC_V3_IN_REJECT_OFST 16
6652#define MC_CMD_SET_MAC_V3_IN_REJECT_LEN 4
6653#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_OFST 16
6654#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_LBN 0
6655#define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_WIDTH 1
6656#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_OFST 16
6657#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_LBN 1
6658#define MC_CMD_SET_MAC_V3_IN_REJECT_BRDCST_WIDTH 1
6659#define MC_CMD_SET_MAC_V3_IN_FCNTL_OFST 20
6660#define MC_CMD_SET_MAC_V3_IN_FCNTL_LEN 4
6661/* enum: Flow control is off. */
6662/* MC_CMD_FCNTL_OFF 0x0 */
6663/* enum: Respond to flow control. */
6664/* MC_CMD_FCNTL_RESPOND 0x1 */
6665/* enum: Respond to and Issue flow control. */
6666/* MC_CMD_FCNTL_BIDIR 0x2 */
6667/* enum: Auto negotiate flow control. */
6668/* MC_CMD_FCNTL_AUTO 0x3 */
6669/* enum: Priority flow control. This is only supported on KSB. */
6670/* MC_CMD_FCNTL_QBB 0x4 */
6671/* enum: Issue flow control. */
6672/* MC_CMD_FCNTL_GENERATE 0x5 */
6673#define MC_CMD_SET_MAC_V3_IN_FLAGS_OFST 24
6674#define MC_CMD_SET_MAC_V3_IN_FLAGS_LEN 4
6675#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_OFST 24
6676#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_LBN 0
6677#define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_WIDTH 1
6678/* Select which parameters to configure. A parameter will only be modified if
6679 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
6680 * capabilities then this field is ignored (and all flags are assumed to be
6681 * set).
6682 */
6683#define MC_CMD_SET_MAC_V3_IN_CONTROL_OFST 28
6684#define MC_CMD_SET_MAC_V3_IN_CONTROL_LEN 4
6685#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_OFST 28
6686#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_LBN 0
6687#define MC_CMD_SET_MAC_V3_IN_CFG_MTU_WIDTH 1
6688#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_OFST 28
6689#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_LBN 1
6690#define MC_CMD_SET_MAC_V3_IN_CFG_DRAIN_WIDTH 1
6691#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_OFST 28
6692#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_LBN 2
6693#define MC_CMD_SET_MAC_V3_IN_CFG_REJECT_WIDTH 1
6694#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_OFST 28
6695#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_LBN 3
6696#define MC_CMD_SET_MAC_V3_IN_CFG_FCNTL_WIDTH 1
6697#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_OFST 28
6698#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 4
6699#define MC_CMD_SET_MAC_V3_IN_CFG_FCS_WIDTH 1
6700/* Target port to set mac state for. Uses MAE_LINK_ENDPOINT_SELECTOR which
6701 * identifies a real or virtual network port by MAE port and link end. See the
6702 * structure definition for more details
6703 */
6704#define MC_CMD_SET_MAC_V3_IN_TARGET_OFST 32
6705#define MC_CMD_SET_MAC_V3_IN_TARGET_LEN 8
6706#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_OFST 32
6707#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LEN 4
6708#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LBN 256
6709#define MC_CMD_SET_MAC_V3_IN_TARGET_LO_WIDTH 32
6710#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_OFST 36
6711#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 4
6712#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LBN 288
6713#define MC_CMD_SET_MAC_V3_IN_TARGET_HI_WIDTH 32
6714/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
6715#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_OFST 32
6716#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 4
6717#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 32
6718#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
6719#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 35
6720#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
6721#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 32
6722#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
6723#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 256
6724#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
6725#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 276
6726#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
6727#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 272
6728#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
6729#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 34
6730#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
6731#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 32
6732#define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
6733#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_OFST 36
6734#define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_LEN 4
6735#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_OFST 32
6736#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LEN 8
6737#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_OFST 32
6738#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LEN 4
6739#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LBN 256
6740#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_WIDTH 32
6741#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_OFST 36
6742#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LEN 4
6743#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LBN 288
6744#define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_WIDTH 32
6745
6746/* MC_CMD_SET_MAC_OUT msgresponse */
6747#define MC_CMD_SET_MAC_OUT_LEN 0
6748
6749/* MC_CMD_SET_MAC_V2_OUT msgresponse */
6750#define MC_CMD_SET_MAC_V2_OUT_LEN 4
6751/* MTU as configured after processing the request. See comment at
6752 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL
6753 * to 0.
6754 */
6755#define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
6756#define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
6757
6758
6759/***********************************/
6760/* MC_CMD_PHY_STATS
6761 * Get generic PHY statistics. This call returns the statistics for a generic
6762 * PHY in a sparse array (indexed by the enumerate). Each value is represented
6763 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
6764 * statistics may be read from the message response. If DMA_ADDR != 0, then the
6765 * statistics are dmad to that (page-aligned location). Locks required: None.
6766 * Returns: 0, ETIME
6767 */
6768#define MC_CMD_PHY_STATS 0x2d
6769#undef MC_CMD_0x2d_PRIVILEGE_CTG
6770
6771#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
6772
6773/* MC_CMD_PHY_STATS_IN msgrequest */
6774#define MC_CMD_PHY_STATS_IN_LEN 8
6775/* ??? */
6776#define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
6777#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
6778#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
6779#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LEN 4
6780#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LBN 0
6781#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_WIDTH 32
6782#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
6783#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LEN 4
6784#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LBN 32
6785#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_WIDTH 32
6786
6787/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
6788#define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
6789
6790/* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
6791#define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
6792#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
6793#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
6794#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
6795/* enum: OUI. */
6796#define MC_CMD_OUI 0x0
6797/* enum: PMA-PMD Link Up. */
6798#define MC_CMD_PMA_PMD_LINK_UP 0x1
6799/* enum: PMA-PMD RX Fault. */
6800#define MC_CMD_PMA_PMD_RX_FAULT 0x2
6801/* enum: PMA-PMD TX Fault. */
6802#define MC_CMD_PMA_PMD_TX_FAULT 0x3
6803/* enum: PMA-PMD Signal */
6804#define MC_CMD_PMA_PMD_SIGNAL 0x4
6805/* enum: PMA-PMD SNR A. */
6806#define MC_CMD_PMA_PMD_SNR_A 0x5
6807/* enum: PMA-PMD SNR B. */
6808#define MC_CMD_PMA_PMD_SNR_B 0x6
6809/* enum: PMA-PMD SNR C. */
6810#define MC_CMD_PMA_PMD_SNR_C 0x7
6811/* enum: PMA-PMD SNR D. */
6812#define MC_CMD_PMA_PMD_SNR_D 0x8
6813/* enum: PCS Link Up. */
6814#define MC_CMD_PCS_LINK_UP 0x9
6815/* enum: PCS RX Fault. */
6816#define MC_CMD_PCS_RX_FAULT 0xa
6817/* enum: PCS TX Fault. */
6818#define MC_CMD_PCS_TX_FAULT 0xb
6819/* enum: PCS BER. */
6820#define MC_CMD_PCS_BER 0xc
6821/* enum: PCS Block Errors. */
6822#define MC_CMD_PCS_BLOCK_ERRORS 0xd
6823/* enum: PhyXS Link Up. */
6824#define MC_CMD_PHYXS_LINK_UP 0xe
6825/* enum: PhyXS RX Fault. */
6826#define MC_CMD_PHYXS_RX_FAULT 0xf
6827/* enum: PhyXS TX Fault. */
6828#define MC_CMD_PHYXS_TX_FAULT 0x10
6829/* enum: PhyXS Align. */
6830#define MC_CMD_PHYXS_ALIGN 0x11
6831/* enum: PhyXS Sync. */
6832#define MC_CMD_PHYXS_SYNC 0x12
6833/* enum: AN link-up. */
6834#define MC_CMD_AN_LINK_UP 0x13
6835/* enum: AN Complete. */
6836#define MC_CMD_AN_COMPLETE 0x14
6837/* enum: AN 10GBaseT Status. */
6838#define MC_CMD_AN_10GBT_STATUS 0x15
6839/* enum: Clause 22 Link-Up. */
6840#define MC_CMD_CL22_LINK_UP 0x16
6841/* enum: (Last entry) */
6842#define MC_CMD_PHY_NSTATS 0x17
6843
6844
6845/***********************************/
6846/* MC_CMD_MAC_STATS
6847 * Get generic MAC statistics. This call returns unified statistics maintained
6848 * by the MC as it switches between the GMAC and XMAC. The MC will write out
6849 * all supported stats. The driver should zero initialise the buffer to
6850 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
6851 * performed, and the statistics may be read from the message response. If
6852 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
6853 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no
6854 * effect. Returns: 0, ETIME
6855 */
6856#define MC_CMD_MAC_STATS 0x2e
6857#undef MC_CMD_0x2e_PRIVILEGE_CTG
6858
6859#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6860
6861/* MC_CMD_MAC_STATS_IN msgrequest */
6862#define MC_CMD_MAC_STATS_IN_LEN 20
6863/* ??? */
6864#define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
6865#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
6866#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
6867#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LEN 4
6868#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LBN 0
6869#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_WIDTH 32
6870#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
6871#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LEN 4
6872#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LBN 32
6873#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_WIDTH 32
6874#define MC_CMD_MAC_STATS_IN_CMD_OFST 8
6875#define MC_CMD_MAC_STATS_IN_CMD_LEN 4
6876#define MC_CMD_MAC_STATS_IN_DMA_OFST 8
6877#define MC_CMD_MAC_STATS_IN_DMA_LBN 0
6878#define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
6879#define MC_CMD_MAC_STATS_IN_CLEAR_OFST 8
6880#define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
6881#define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
6882#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_OFST 8
6883#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
6884#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
6885#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_OFST 8
6886#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
6887#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
6888#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_OFST 8
6889#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
6890#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
6891#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_OFST 8
6892#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
6893#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
6894#define MC_CMD_MAC_STATS_IN_PERIOD_MS_OFST 8
6895#define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
6896#define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
6897/* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as
6898 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not
6899 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to
6900 * MC_CMD_MAC_NSTATS * sizeof(uint64_t)
6901 */
6902#define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
6903#define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
6904/* port id so vadapter stats can be provided */
6905#define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16
6906#define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4
6907
6908/* MC_CMD_MAC_STATS_V2_IN msgrequest */
6909#define MC_CMD_MAC_STATS_V2_IN_LEN 28
6910/* ??? */
6911#define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_OFST 0
6912#define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LEN 8
6913#define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LO_OFST 0
6914#define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LO_LEN 4
6915#define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LO_LBN 0
6916#define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LO_WIDTH 32
6917#define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_HI_OFST 4
6918#define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_HI_LEN 4
6919#define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_HI_LBN 32
6920#define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_HI_WIDTH 32
6921#define MC_CMD_MAC_STATS_V2_IN_CMD_OFST 8
6922#define MC_CMD_MAC_STATS_V2_IN_CMD_LEN 4
6923#define MC_CMD_MAC_STATS_V2_IN_DMA_OFST 8
6924#define MC_CMD_MAC_STATS_V2_IN_DMA_LBN 0
6925#define MC_CMD_MAC_STATS_V2_IN_DMA_WIDTH 1
6926#define MC_CMD_MAC_STATS_V2_IN_CLEAR_OFST 8
6927#define MC_CMD_MAC_STATS_V2_IN_CLEAR_LBN 1
6928#define MC_CMD_MAC_STATS_V2_IN_CLEAR_WIDTH 1
6929#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CHANGE_OFST 8
6930#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CHANGE_LBN 2
6931#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CHANGE_WIDTH 1
6932#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_ENABLE_OFST 8
6933#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_ENABLE_LBN 3
6934#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_ENABLE_WIDTH 1
6935#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CLEAR_OFST 8
6936#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CLEAR_LBN 4
6937#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CLEAR_WIDTH 1
6938#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_NOEVENT_OFST 8
6939#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_NOEVENT_LBN 5
6940#define MC_CMD_MAC_STATS_V2_IN_PERIODIC_NOEVENT_WIDTH 1
6941#define MC_CMD_MAC_STATS_V2_IN_PERIOD_MS_OFST 8
6942#define MC_CMD_MAC_STATS_V2_IN_PERIOD_MS_LBN 16
6943#define MC_CMD_MAC_STATS_V2_IN_PERIOD_MS_WIDTH 16
6944/* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as
6945 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not
6946 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to
6947 * MC_CMD_MAC_NSTATS * sizeof(uint64_t)
6948 */
6949#define MC_CMD_MAC_STATS_V2_IN_DMA_LEN_OFST 12
6950#define MC_CMD_MAC_STATS_V2_IN_DMA_LEN_LEN 4
6951/* port id so vadapter stats can be provided */
6952#define MC_CMD_MAC_STATS_V2_IN_PORT_ID_OFST 16
6953#define MC_CMD_MAC_STATS_V2_IN_PORT_ID_LEN 4
6954/* Target port to request statistics for. Uses MAE_LINK_ENDPOINT_SELECTOR which
6955 * identifies a real or virtual network port by MAE port and link end. See the
6956 * structure definition for more details
6957 */
6958#define MC_CMD_MAC_STATS_V2_IN_TARGET_OFST 20
6959#define MC_CMD_MAC_STATS_V2_IN_TARGET_LEN 8
6960#define MC_CMD_MAC_STATS_V2_IN_TARGET_LO_OFST 20
6961#define MC_CMD_MAC_STATS_V2_IN_TARGET_LO_LEN 4
6962#define MC_CMD_MAC_STATS_V2_IN_TARGET_LO_LBN 160
6963#define MC_CMD_MAC_STATS_V2_IN_TARGET_LO_WIDTH 32
6964#define MC_CMD_MAC_STATS_V2_IN_TARGET_HI_OFST 24
6965#define MC_CMD_MAC_STATS_V2_IN_TARGET_HI_LEN 4
6966#define MC_CMD_MAC_STATS_V2_IN_TARGET_HI_LBN 192
6967#define MC_CMD_MAC_STATS_V2_IN_TARGET_HI_WIDTH 32
6968/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
6969#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_OFST 20
6970#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_LEN 4
6971#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FLAT_OFST 20
6972#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
6973#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_TYPE_OFST 23
6974#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_TYPE_LEN 1
6975#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 20
6976#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
6977#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 160
6978#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
6979#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 180
6980#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
6981#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 176
6982#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
6983#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 22
6984#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
6985#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 20
6986#define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
6987#define MC_CMD_MAC_STATS_V2_IN_TARGET_LINK_END_OFST 24
6988#define MC_CMD_MAC_STATS_V2_IN_TARGET_LINK_END_LEN 4
6989#define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_OFST 20
6990#define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_LEN 8
6991#define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_LO_OFST 20
6992#define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_LO_LEN 4
6993#define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_LO_LBN 160
6994#define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_LO_WIDTH 32
6995#define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_HI_OFST 24
6996#define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_HI_LEN 4
6997#define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_HI_LBN 192
6998#define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_HI_WIDTH 32
6999
7000/* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
7001#define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
7002
7003/* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
7004#define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
7005#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
7006#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
7007#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
7008#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LEN 4
7009#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LBN 0
7010#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
7011#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
7012#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LEN 4
7013#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LBN 32
7014#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
7015#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
7016/* enum property: index */
7017#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
7018#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
7019#define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
7020#define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
7021#define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
7022#define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
7023#define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
7024#define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
7025#define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
7026#define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
7027#define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
7028#define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
7029#define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
7030#define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
7031#define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
7032#define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
7033#define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
7034#define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
7035#define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
7036#define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
7037#define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
7038#define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
7039#define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
7040#define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
7041#define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
7042#define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
7043#define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
7044#define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
7045#define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
7046#define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
7047#define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
7048#define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
7049#define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
7050#define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
7051#define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
7052#define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
7053#define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
7054#define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
7055#define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
7056#define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
7057#define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
7058#define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
7059#define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
7060#define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
7061#define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
7062#define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
7063#define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
7064#define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
7065#define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
7066#define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
7067#define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
7068#define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
7069#define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
7070#define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
7071#define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
7072#define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
7073#define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
7074#define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
7075#define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
7076#define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
7077#define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
7078/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
7079 * capability only.
7080 */
7081#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
7082/* enum: PM discard_bb_overflow counter. Valid for EF10 with
7083 * PM_AND_RXDP_COUNTERS capability only.
7084 */
7085#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
7086/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
7087 * capability only.
7088 */
7089#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
7090/* enum: PM discard_vfifo_full counter. Valid for EF10 with
7091 * PM_AND_RXDP_COUNTERS capability only.
7092 */
7093#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
7094/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
7095 * capability only.
7096 */
7097#define MC_CMD_MAC_PM_TRUNC_QBB 0x40
7098/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
7099 * capability only.
7100 */
7101#define MC_CMD_MAC_PM_DISCARD_QBB 0x41
7102/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
7103 * capability only.
7104 */
7105#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
7106/* enum: RXDP counter: Number of packets dropped due to the queue being
7107 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
7108 */
7109#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
7110/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
7111 * with PM_AND_RXDP_COUNTERS capability only.
7112 */
7113#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
7114/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
7115 * PM_AND_RXDP_COUNTERS capability only.
7116 */
7117#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
7118/* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.
7119 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
7120 */
7121#define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
7122/* enum: RXDP counter: Number of times the DPCPU waited for an existing
7123 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
7124 */
7125#define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
7126#define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
7127#define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
7128#define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
7129#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
7130#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
7131#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
7132#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
7133#define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
7134#define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
7135#define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
7136#define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
7137#define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
7138#define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
7139#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
7140#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
7141#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
7142#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
7143#define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
7144#define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
7145#define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
7146/* enum: Start of GMAC stats buffer space, for Siena only. */
7147#define MC_CMD_GMAC_DMABUF_START 0x40
7148/* enum: End of GMAC stats buffer space, for Siena only. */
7149#define MC_CMD_GMAC_DMABUF_END 0x5f
7150/* enum: GENERATION_END value, used together with GENERATION_START to verify
7151 * consistency of DMAd data. For legacy firmware / drivers without extended
7152 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *
7153 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise,
7154 * this value is invalid/ reserved and GENERATION_END is written as the last
7155 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
7156 * this is consistent with the legacy behaviour, in the sense that entry 96 is
7157 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
7158 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
7159 */
7160#define MC_CMD_MAC_GENERATION_END 0x60
7161#define MC_CMD_MAC_NSTATS 0x61 /* enum */
7162
7163/* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */
7164#define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
7165
7166/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */
7167#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3)
7168#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
7169#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8
7170#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
7171#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LEN 4
7172#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LBN 0
7173#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
7174#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
7175#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LEN 4
7176#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LBN 32
7177#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
7178#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
7179/* enum property: index */
7180/* enum: Start of FEC stats buffer space, Medford2 and up */
7181#define MC_CMD_MAC_FEC_DMABUF_START 0x61
7182/* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
7183 */
7184#define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
7185/* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
7186 */
7187#define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
7188/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
7189#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
7190/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
7191#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
7192/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
7193#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
7194/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
7195#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
7196/* enum: This includes the space at offset 103 which is the final
7197 * GENERATION_END in a MAC_STATS_V2 response and otherwise unused.
7198 */
7199#define MC_CMD_MAC_NSTATS_V2 0x68
7200/* Other enum values, see field(s): */
7201/* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */
7202
7203/* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */
7204#define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0
7205
7206/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */
7207#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3)
7208#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
7209#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8
7210#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
7211#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LEN 4
7212#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LBN 0
7213#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
7214#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
7215#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LEN 4
7216#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LBN 32
7217#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
7218#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3
7219/* enum property: index */
7220/* enum: Start of CTPIO stats buffer space, Medford2 and up */
7221#define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
7222/* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the
7223 * target VI
7224 */
7225#define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
7226/* enum: Number of times a CTPIO send wrote beyond frame end (informational
7227 * only)
7228 */
7229#define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
7230/* enum: Number of CTPIO failures because the TX doorbell was written before
7231 * the end of the frame data
7232 */
7233#define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
7234/* enum: Number of CTPIO failures because the internal FIFO overflowed */
7235#define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
7236/* enum: Number of CTPIO failures because the host did not deliver data fast
7237 * enough to avoid MAC underflow
7238 */
7239#define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
7240/* enum: Number of CTPIO failures because the host did not deliver all the
7241 * frame data within the timeout
7242 */
7243#define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
7244/* enum: Number of CTPIO failures because the frame data arrived out of order
7245 * or with gaps
7246 */
7247#define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
7248/* enum: Number of CTPIO failures because the host started a new frame before
7249 * completing the previous one
7250 */
7251#define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
7252/* enum: Number of CTPIO failures because a write was not a multiple of 32 bits
7253 * or not 32-bit aligned
7254 */
7255#define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
7256/* enum: Number of CTPIO fallbacks because another VI on the same port was
7257 * sending a CTPIO frame
7258 */
7259#define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
7260/* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled
7261 */
7262#define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
7263/* enum: Number of CTPIO fallbacks because length in header was less than 29
7264 * bytes
7265 */
7266#define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
7267/* enum: Total number of successful CTPIO sends on this port */
7268#define MC_CMD_MAC_CTPIO_SUCCESS 0x74
7269/* enum: Total number of CTPIO fallbacks on this port */
7270#define MC_CMD_MAC_CTPIO_FALLBACK 0x75
7271/* enum: Total number of CTPIO poisoned frames on this port, whether erased or
7272 * not
7273 */
7274#define MC_CMD_MAC_CTPIO_POISON 0x76
7275/* enum: Total number of CTPIO erased frames on this port */
7276#define MC_CMD_MAC_CTPIO_ERASE 0x77
7277/* enum: This includes the space at offset 120 which is the final
7278 * GENERATION_END in a MAC_STATS_V3 response and otherwise unused.
7279 */
7280#define MC_CMD_MAC_NSTATS_V3 0x79
7281/* Other enum values, see field(s): */
7282/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */
7283
7284/* MC_CMD_MAC_STATS_V4_OUT_DMA msgresponse */
7285#define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0
7286
7287/* MC_CMD_MAC_STATS_V4_OUT_NO_DMA msgresponse */
7288#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V4*64))>>3)
7289#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
7290#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8
7291#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
7292#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LEN 4
7293#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LBN 0
7294#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
7295#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
7296#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LEN 4
7297#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LBN 32
7298#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
7299#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4
7300/* enum property: index */
7301/* enum: Start of V4 stats buffer space */
7302#define MC_CMD_MAC_V4_DMABUF_START 0x79
7303/* enum: RXDP counter: Number of packets truncated because scattering was
7304 * disabled.
7305 */
7306#define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79
7307/* enum: RXDP counter: Number of times the RXDP head of line blocked waiting
7308 * for descriptors. Will be zero unless RXDP_HLB_IDLE capability is set.
7309 */
7310#define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a
7311/* enum: RXDP counter: Number of times the RXDP timed out while head of line
7312 * blocking. Will be zero unless RXDP_HLB_IDLE capability is set.
7313 */
7314#define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b
7315/* enum: This includes the space at offset 124 which is the final
7316 * GENERATION_END in a MAC_STATS_V4 response and otherwise unused.
7317 */
7318#define MC_CMD_MAC_NSTATS_V4 0x7d
7319/* Other enum values, see field(s): */
7320/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */
7321
7322/* MC_CMD_MAC_STATS_V5_OUT_DMA msgresponse */
7323#define MC_CMD_MAC_STATS_V5_OUT_DMA_LEN 0
7324
7325/* MC_CMD_MAC_STATS_V5_OUT_NO_DMA msgresponse */
7326#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V5*64))>>3)
7327#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_OFST 0
7328#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LEN 8
7329#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_OFST 0
7330#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_LEN 4
7331#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_LBN 0
7332#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_WIDTH 32
7333#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_OFST 4
7334#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_LEN 4
7335#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_LBN 32
7336#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_WIDTH 32
7337#define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V5
7338/* enum property: index */
7339/* enum: Start of V5 stats buffer space */
7340#define MC_CMD_MAC_V5_DMABUF_START 0x7c
7341/* enum: Link toggle counter: Number of times the link has toggled between
7342 * up/down and down/up
7343 */
7344#define MC_CMD_MAC_LINK_TOGGLES 0x7c
7345/* enum: This includes the space at offset 125 which is the final
7346 * GENERATION_END in a MAC_STATS_V5 response and otherwise unused.
7347 */
7348#define MC_CMD_MAC_NSTATS_V5 0x7e
7349/* Other enum values, see field(s): */
7350/* MC_CMD_MAC_STATS_V4_OUT_NO_DMA/STATISTICS */
7351
7352
7353/***********************************/
7354/* MC_CMD_WOL_FILTER_SET
7355 * Set a WoL filter.
7356 */
7357#define MC_CMD_WOL_FILTER_SET 0x32
7358#undef MC_CMD_0x32_PRIVILEGE_CTG
7359
7360#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
7361
7362/* MC_CMD_WOL_FILTER_SET_IN msgrequest */
7363#define MC_CMD_WOL_FILTER_SET_IN_LEN 192
7364#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
7365#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
7366#define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
7367#define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
7368/* A type value of 1 is unused. */
7369#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
7370#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
7371/* enum: Magic */
7372#define MC_CMD_WOL_TYPE_MAGIC 0x0
7373/* enum: MS Windows Magic */
7374#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
7375/* enum: IPv4 Syn */
7376#define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
7377/* enum: IPv6 Syn */
7378#define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
7379/* enum: Bitmap */
7380#define MC_CMD_WOL_TYPE_BITMAP 0x5
7381/* enum: Link */
7382#define MC_CMD_WOL_TYPE_LINK 0x6
7383/* enum: (Above this for future use) */
7384#define MC_CMD_WOL_TYPE_MAX 0x7
7385#define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
7386#define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
7387#define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
7388
7389/* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
7390#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
7391/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
7392/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
7393/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
7394/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
7395#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
7396#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
7397#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
7398#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LEN 4
7399#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LBN 64
7400#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_WIDTH 32
7401#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
7402#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LEN 4
7403#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LBN 96
7404#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_WIDTH 32
7405
7406/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
7407#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
7408/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
7409/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
7410/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
7411/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
7412#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
7413#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
7414#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
7415#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
7416#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
7417#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
7418#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
7419#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
7420
7421/* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
7422#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
7423/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
7424/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
7425/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
7426/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
7427#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
7428#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
7429#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
7430#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
7431#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
7432#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
7433#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
7434#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
7435
7436/* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
7437#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
7438/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
7439/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
7440/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
7441/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
7442#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
7443#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
7444#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
7445#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
7446#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
7447#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
7448#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
7449#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
7450#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
7451#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
7452
7453/* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
7454#define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
7455/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
7456/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
7457/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
7458/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
7459#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
7460#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
7461#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_OFST 8
7462#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
7463#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
7464#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_OFST 8
7465#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
7466#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
7467
7468/* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
7469#define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
7470#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
7471#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4
7472
7473
7474/***********************************/
7475/* MC_CMD_WOL_FILTER_REMOVE
7476 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
7477 */
7478#define MC_CMD_WOL_FILTER_REMOVE 0x33
7479#undef MC_CMD_0x33_PRIVILEGE_CTG
7480
7481#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
7482
7483/* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
7484#define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
7485#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
7486#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4
7487
7488/* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
7489#define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
7490
7491
7492/***********************************/
7493/* MC_CMD_WOL_FILTER_RESET
7494 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
7495 * ENOSYS
7496 */
7497#define MC_CMD_WOL_FILTER_RESET 0x34
7498#undef MC_CMD_0x34_PRIVILEGE_CTG
7499
7500#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
7501
7502/* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
7503#define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
7504#define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
7505#define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
7506/* enum property: bitmask */
7507#define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
7508#define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
7509
7510/* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
7511#define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
7512
7513
7514/***********************************/
7515/* MC_CMD_NVRAM_TYPES
7516 * Return bitfield indicating available types of virtual NVRAM partitions.
7517 * Locks required: none. Returns: 0
7518 */
7519#define MC_CMD_NVRAM_TYPES 0x36
7520#undef MC_CMD_0x36_PRIVILEGE_CTG
7521
7522#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7523
7524/* MC_CMD_NVRAM_TYPES_IN msgrequest */
7525#define MC_CMD_NVRAM_TYPES_IN_LEN 0
7526
7527/* MC_CMD_NVRAM_TYPES_OUT msgresponse */
7528#define MC_CMD_NVRAM_TYPES_OUT_LEN 4
7529/* Bit mask of supported types. */
7530#define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
7531#define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
7532/* enum property: bitshift */
7533/* enum: Disabled callisto. */
7534#define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
7535/* enum: MC firmware. */
7536#define MC_CMD_NVRAM_TYPE_MC_FW 0x1
7537/* enum: MC backup firmware. */
7538#define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
7539/* enum: Static configuration Port0. */
7540#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
7541/* enum: Static configuration Port1. */
7542#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
7543/* enum: Dynamic configuration Port0. */
7544#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
7545/* enum: Dynamic configuration Port1. */
7546#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
7547/* enum: Expansion Rom. */
7548#define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
7549/* enum: Expansion Rom Configuration Port0. */
7550#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
7551/* enum: Expansion Rom Configuration Port1. */
7552#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
7553/* enum: Phy Configuration Port0. */
7554#define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
7555/* enum: Phy Configuration Port1. */
7556#define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
7557/* enum: Log. */
7558#define MC_CMD_NVRAM_TYPE_LOG 0xc
7559/* enum: FPGA image. */
7560#define MC_CMD_NVRAM_TYPE_FPGA 0xd
7561/* enum: FPGA backup image */
7562#define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
7563/* enum: FC firmware. */
7564#define MC_CMD_NVRAM_TYPE_FC_FW 0xf
7565/* enum: FC backup firmware. */
7566#define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
7567/* enum: CPLD image. */
7568#define MC_CMD_NVRAM_TYPE_CPLD 0x11
7569/* enum: Licensing information. */
7570#define MC_CMD_NVRAM_TYPE_LICENSE 0x12
7571/* enum: FC Log. */
7572#define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
7573/* enum: Additional flash on FPGA. */
7574#define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
7575
7576
7577/***********************************/
7578/* MC_CMD_NVRAM_INFO
7579 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
7580 * EINVAL (bad type).
7581 */
7582#define MC_CMD_NVRAM_INFO 0x37
7583#undef MC_CMD_0x37_PRIVILEGE_CTG
7584
7585#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7586
7587/* MC_CMD_NVRAM_INFO_IN msgrequest */
7588#define MC_CMD_NVRAM_INFO_IN_LEN 4
7589#define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
7590#define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
7591/* Enum values, see field(s): */
7592/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7593
7594/* MC_CMD_NVRAM_INFO_OUT msgresponse */
7595#define MC_CMD_NVRAM_INFO_OUT_LEN 24
7596#define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
7597#define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
7598/* Enum values, see field(s): */
7599/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7600#define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
7601#define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
7602#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
7603#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
7604#define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
7605#define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
7606#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_OFST 12
7607#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
7608#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
7609#define MC_CMD_NVRAM_INFO_OUT_TLV_OFST 12
7610#define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
7611#define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
7612#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12
7613#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
7614#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
7615#define MC_CMD_NVRAM_INFO_OUT_CRC_OFST 12
7616#define MC_CMD_NVRAM_INFO_OUT_CRC_LBN 3
7617#define MC_CMD_NVRAM_INFO_OUT_CRC_WIDTH 1
7618#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_OFST 12
7619#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5
7620#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
7621#define MC_CMD_NVRAM_INFO_OUT_CMAC_OFST 12
7622#define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6
7623#define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1
7624#define MC_CMD_NVRAM_INFO_OUT_A_B_OFST 12
7625#define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7
7626#define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
7627#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
7628#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
7629#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
7630#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4
7631
7632/* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */
7633#define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28
7634#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
7635#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
7636/* Enum values, see field(s): */
7637/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7638#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
7639#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
7640#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8
7641#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
7642#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12
7643#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
7644#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_OFST 12
7645#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
7646#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
7647#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_OFST 12
7648#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
7649#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
7650#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12
7651#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
7652#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
7653#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_OFST 12
7654#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5
7655#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
7656#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_OFST 12
7657#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7
7658#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1
7659#define MC_CMD_NVRAM_INFO_V2_OUT_WRITE_ONLY_OFST 12
7660#define MC_CMD_NVRAM_INFO_V2_OUT_WRITE_ONLY_LBN 8
7661#define MC_CMD_NVRAM_INFO_V2_OUT_WRITE_ONLY_WIDTH 1
7662#define MC_CMD_NVRAM_INFO_V2_OUT_SEQUENTIAL_WRITE_OFST 12
7663#define MC_CMD_NVRAM_INFO_V2_OUT_SEQUENTIAL_WRITE_LBN 9
7664#define MC_CMD_NVRAM_INFO_V2_OUT_SEQUENTIAL_WRITE_WIDTH 1
7665#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16
7666#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
7667#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20
7668#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
7669/* Writes must be multiples of this size. Added to support the MUM on Sorrento.
7670 */
7671#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24
7672#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4
7673
7674
7675/***********************************/
7676/* MC_CMD_NVRAM_UPDATE_START
7677 * Start a group of update operations on a virtual NVRAM partition. Locks
7678 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
7679 * PHY_LOCK required and not held). In an adapter bound to a TSA controller,
7680 * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types
7681 * i.e. static config, dynamic config and expansion ROM config. Attempting to
7682 * perform this operation on a restricted partition will return the error
7683 * EPERM.
7684 */
7685#define MC_CMD_NVRAM_UPDATE_START 0x38
7686#undef MC_CMD_0x38_PRIVILEGE_CTG
7687
7688#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7689
7690/* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request.
7691 * Use NVRAM_UPDATE_START_V2_IN in new code
7692 */
7693#define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
7694#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
7695#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
7696/* Enum values, see field(s): */
7697/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7698
7699/* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START
7700 * request with additional flags indicating version of command in use. See
7701 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use
7702 * paired up with NVRAM_UPDATE_FINISH_V2_IN.
7703 */
7704#define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8
7705#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
7706#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
7707/* Enum values, see field(s): */
7708/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7709#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
7710#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
7711#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4
7712#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
7713#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
7714
7715/* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
7716#define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
7717
7718
7719/***********************************/
7720/* MC_CMD_NVRAM_READ
7721 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if
7722 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7723 * PHY_LOCK required and not held)
7724 */
7725#define MC_CMD_NVRAM_READ 0x39
7726#undef MC_CMD_0x39_PRIVILEGE_CTG
7727
7728#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7729
7730/* MC_CMD_NVRAM_READ_IN msgrequest */
7731#define MC_CMD_NVRAM_READ_IN_LEN 12
7732#define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
7733#define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
7734/* Enum values, see field(s): */
7735/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7736#define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
7737#define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
7738/* amount to read in bytes */
7739#define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
7740#define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4
7741
7742/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */
7743#define MC_CMD_NVRAM_READ_IN_V2_LEN 16
7744#define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
7745#define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
7746/* Enum values, see field(s): */
7747/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7748#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
7749#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
7750/* amount to read in bytes */
7751#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8
7752#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
7753/* Optional control info. If a partition is stored with an A/B versioning
7754 * scheme (i.e. in more than one physical partition in NVRAM) the host can set
7755 * this to control which underlying physical partition is used to read data
7756 * from. This allows it to perform a read-modify-write-verify with the write
7757 * lock continuously held by calling NVRAM_UPDATE_START, reading the old
7758 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then
7759 * verifying by reading with MODE=TARGET_BACKUP.
7760 */
7761#define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12
7762#define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
7763/* enum: Same as omitting MODE: caller sees data in current partition unless it
7764 * holds the write lock in which case it sees data in the partition it is
7765 * updating.
7766 */
7767#define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
7768/* enum: Read from the current partition of an A/B pair, even if holding the
7769 * write lock.
7770 */
7771#define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
7772/* enum: Read from the non-current (i.e. to be updated) partition of an A/B
7773 * pair
7774 */
7775#define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
7776
7777/* MC_CMD_NVRAM_READ_OUT msgresponse */
7778#define MC_CMD_NVRAM_READ_OUT_LENMIN 1
7779#define MC_CMD_NVRAM_READ_OUT_LENMAX 252
7780#define MC_CMD_NVRAM_READ_OUT_LENMAX_MCDI2 1020
7781#define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
7782#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
7783#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
7784#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
7785#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
7786#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
7787#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM_MCDI2 1020
7788
7789
7790/***********************************/
7791/* MC_CMD_NVRAM_WRITE
7792 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if
7793 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7794 * PHY_LOCK required and not held)
7795 */
7796#define MC_CMD_NVRAM_WRITE 0x3a
7797#undef MC_CMD_0x3a_PRIVILEGE_CTG
7798
7799#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7800
7801/* MC_CMD_NVRAM_WRITE_IN msgrequest */
7802#define MC_CMD_NVRAM_WRITE_IN_LENMIN 13
7803#define MC_CMD_NVRAM_WRITE_IN_LENMAX 252
7804#define MC_CMD_NVRAM_WRITE_IN_LENMAX_MCDI2 1020
7805#define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
7806#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)
7807#define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
7808#define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
7809/* Enum values, see field(s): */
7810/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7811#define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
7812#define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
7813#define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
7814#define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
7815#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
7816#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
7817#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
7818#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
7819#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM_MCDI2 1008
7820
7821/* MC_CMD_NVRAM_WRITE_OUT msgresponse */
7822#define MC_CMD_NVRAM_WRITE_OUT_LEN 0
7823
7824
7825/***********************************/
7826/* MC_CMD_NVRAM_ERASE
7827 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if
7828 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7829 * PHY_LOCK required and not held)
7830 */
7831#define MC_CMD_NVRAM_ERASE 0x3b
7832#undef MC_CMD_0x3b_PRIVILEGE_CTG
7833
7834#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7835
7836/* MC_CMD_NVRAM_ERASE_IN msgrequest */
7837#define MC_CMD_NVRAM_ERASE_IN_LEN 12
7838#define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
7839#define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
7840/* Enum values, see field(s): */
7841/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7842#define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
7843#define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
7844#define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
7845#define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4
7846
7847/* MC_CMD_NVRAM_ERASE_OUT msgresponse */
7848#define MC_CMD_NVRAM_ERASE_OUT_LEN 0
7849
7850
7851/***********************************/
7852/* MC_CMD_NVRAM_UPDATE_FINISH
7853 * Finish a group of update operations on a virtual NVRAM partition. Locks
7854 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
7855 * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to
7856 * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of
7857 * partition types i.e. static config, dynamic config and expansion ROM config.
7858 * Attempting to perform this operation on a restricted partition will return
7859 * the error EPERM.
7860 */
7861#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
7862#undef MC_CMD_0x3c_PRIVILEGE_CTG
7863
7864#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
7865
7866/* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH
7867 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code
7868 */
7869#define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
7870#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
7871#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
7872/* Enum values, see field(s): */
7873/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7874#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
7875#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
7876
7877/* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH
7878 * request with additional flags indicating version of NVRAM_UPDATE commands in
7879 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended
7880 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN.
7881 */
7882#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12
7883#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
7884#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
7885/* Enum values, see field(s): */
7886/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
7887#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
7888#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
7889#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8
7890#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
7891#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 8
7892#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
7893#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
7894#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_OFST 8
7895#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 1
7896#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 1
7897#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8
7898#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2
7899#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
7900#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_OFST 8
7901#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_LBN 3
7902#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_ABORT_WIDTH 1
7903
7904/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
7905 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
7906 */
7907#define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
7908
7909/* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse:
7910 *
7911 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure
7912 * firmware validation where applicable back to the host.
7913 *
7914 * Medford only: For signed firmware images, such as those for medford, the MC
7915 * firmware verifies the signature before marking the firmware image as valid.
7916 * This process takes a few seconds to complete. So is likely to take more than
7917 * the MCDI timeout. Hence signature verification is initiated when
7918 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the
7919 * MCDI command is run in a background MCDI processing thread. This response
7920 * payload includes the results of the signature verification. Note that the
7921 * per-partition nvram lock in firmware is only released after the verification
7922 * has completed.
7923 */
7924#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
7925/* Result of nvram update completion processing. Result codes that indicate an
7926 * internal build failure and therefore not expected to be seen by customers in
7927 * the field are marked with a prefix 'Internal-error'.
7928 */
7929#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
7930#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
7931/* enum: Invalid return code; only non-zero values are defined. Defined as
7932 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.
7933 */
7934#define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
7935/* enum: Verify succeeded without any errors. */
7936#define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
7937/* enum: CMS format verification failed due to an internal error. */
7938#define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
7939/* enum: Invalid CMS format in image metadata. */
7940#define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
7941/* enum: Message digest verification failed due to an internal error. */
7942#define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
7943/* enum: Error in message digest calculated over the reflash-header, payload
7944 * and reflash-trailer.
7945 */
7946#define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
7947/* enum: Signature verification failed due to an internal error. */
7948#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
7949/* enum: There are no valid signatures in the image. */
7950#define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
7951/* enum: Trusted approvers verification failed due to an internal error. */
7952#define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
7953/* enum: The Trusted approver's list is empty. */
7954#define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
7955/* enum: Signature chain verification failed due to an internal error. */
7956#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
7957/* enum: The signers of the signatures in the image are not listed in the
7958 * Trusted approver's list.
7959 */
7960#define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
7961/* enum: The image contains a test-signed certificate, but the adapter accepts
7962 * only production signed images.
7963 */
7964#define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
7965/* enum: The image has a lower security level than the current firmware. */
7966#define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
7967/* enum: Internal-error. The signed image is missing the 'contents' section,
7968 * where the 'contents' section holds the actual image payload to be applied.
7969 */
7970#define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe
7971/* enum: Internal-error. The bundle header is invalid. */
7972#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf
7973/* enum: Internal-error. The bundle does not have a valid reflash image layout.
7974 */
7975#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10
7976/* enum: Internal-error. The bundle has an inconsistent layout of components or
7977 * incorrect checksum.
7978 */
7979#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11
7980/* enum: Internal-error. The bundle manifest is inconsistent with components in
7981 * the bundle.
7982 */
7983#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12
7984/* enum: Internal-error. The number of components in a bundle do not match the
7985 * number of components advertised by the bundle manifest.
7986 */
7987#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13
7988/* enum: Internal-error. The bundle contains too many components for the MC
7989 * firmware to process
7990 */
7991#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14
7992/* enum: Internal-error. The bundle manifest has an invalid/inconsistent
7993 * component.
7994 */
7995#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15
7996/* enum: Internal-error. The hash of a component does not match the hash stored
7997 * in the bundle manifest.
7998 */
7999#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16
8000/* enum: Internal-error. Component hash calculation failed. */
8001#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17
8002/* enum: Internal-error. The component does not have a valid reflash image
8003 * layout.
8004 */
8005#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18
8006/* enum: The bundle processing code failed to copy a component to its target
8007 * partition.
8008 */
8009#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19
8010/* enum: The update operation is in-progress. */
8011#define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a
8012/* enum: The update was an invalid user configuration file. */
8013#define MC_CMD_NVRAM_VERIFY_RC_BAD_CONFIG 0x1b
8014/* enum: The write was to the AUTO partition but the data was not recognised as
8015 * a valid partition.
8016 */
8017#define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN_TYPE 0x1c
8018
8019/* MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT msgresponse */
8020#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_LEN 88
8021/* Result of nvram update completion processing. Result codes that indicate an
8022 * internal build failure and therefore not expected to be seen by customers in
8023 * the field are marked with a prefix 'Internal-error'.
8024 */
8025#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_RESULT_CODE_OFST 0
8026#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_RESULT_CODE_LEN 4
8027/* enum: Invalid return code; only non-zero values are defined. Defined as
8028 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.
8029 */
8030/* MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0 */
8031/* enum: Verify succeeded without any errors. */
8032/* MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 */
8033/* enum: CMS format verification failed due to an internal error. */
8034/* MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 */
8035/* enum: Invalid CMS format in image metadata. */
8036/* MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 */
8037/* enum: Message digest verification failed due to an internal error. */
8038/* MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 */
8039/* enum: Error in message digest calculated over the reflash-header, payload
8040 * and reflash-trailer.
8041 */
8042/* MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 */
8043/* enum: Signature verification failed due to an internal error. */
8044/* MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 */
8045/* enum: There are no valid signatures in the image. */
8046/* MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 */
8047/* enum: Trusted approvers verification failed due to an internal error. */
8048/* MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 */
8049/* enum: The Trusted approver's list is empty. */
8050/* MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 */
8051/* enum: Signature chain verification failed due to an internal error. */
8052/* MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa */
8053/* enum: The signers of the signatures in the image are not listed in the
8054 * Trusted approver's list.
8055 */
8056/* MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb */
8057/* enum: The image contains a test-signed certificate, but the adapter accepts
8058 * only production signed images.
8059 */
8060/* MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc */
8061/* enum: The image has a lower security level than the current firmware. */
8062/* MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd */
8063/* enum: Internal-error. The signed image is missing the 'contents' section,
8064 * where the 'contents' section holds the actual image payload to be applied.
8065 */
8066/* MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe */
8067/* enum: Internal-error. The bundle header is invalid. */
8068/* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf */
8069/* enum: Internal-error. The bundle does not have a valid reflash image layout.
8070 */
8071/* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10 */
8072/* enum: Internal-error. The bundle has an inconsistent layout of components or
8073 * incorrect checksum.
8074 */
8075/* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11 */
8076/* enum: Internal-error. The bundle manifest is inconsistent with components in
8077 * the bundle.
8078 */
8079/* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12 */
8080/* enum: Internal-error. The number of components in a bundle do not match the
8081 * number of components advertised by the bundle manifest.
8082 */
8083/* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13 */
8084/* enum: Internal-error. The bundle contains too many components for the MC
8085 * firmware to process
8086 */
8087/* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14 */
8088/* enum: Internal-error. The bundle manifest has an invalid/inconsistent
8089 * component.
8090 */
8091/* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15 */
8092/* enum: Internal-error. The hash of a component does not match the hash stored
8093 * in the bundle manifest.
8094 */
8095/* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16 */
8096/* enum: Internal-error. Component hash calculation failed. */
8097/* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17 */
8098/* enum: Internal-error. The component does not have a valid reflash image
8099 * layout.
8100 */
8101/* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18 */
8102/* enum: The bundle processing code failed to copy a component to its target
8103 * partition.
8104 */
8105/* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19 */
8106/* enum: The update operation is in-progress. */
8107/* MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a */
8108/* enum: The update was an invalid user configuration file. */
8109/* MC_CMD_NVRAM_VERIFY_RC_BAD_CONFIG 0x1b */
8110/* enum: The write was to the AUTO partition but the data was not recognised as
8111 * a valid partition.
8112 */
8113/* MC_CMD_NVRAM_VERIFY_RC_UNKNOWN_TYPE 0x1c */
8114/* If the update was a user configuration, what action(s) the user must take to
8115 * apply the new configuration.
8116 */
8117#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_ACTIONS_REQUIRED_OFST 4
8118#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_ACTIONS_REQUIRED_LEN 4
8119/* enum: No action required. */
8120#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_NONE 0x0
8121/* enum: The MC firmware must be rebooted (eg with MC_CMD_REBOOT). */
8122#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_FIRMWARE_REBOOT 0x1
8123/* enum: The host must be rebooted. */
8124#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_HOST_REBOOT 0x2
8125/* enum: The firmware and host must be rebooted (in either order). */
8126#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_FIRMWARE_AND_HOST_REBOOT 0x3
8127/* enum: The host must be fully powered off. */
8128#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_HOST_POWERCYCLE 0x4
8129/* If the update failed with MC_CMD_NVRAM_VERIFY_RC_BAD_CONFIG, a null-
8130 * terminated US-ASCII string suitable for showing to the user.
8131 */
8132#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_ERROR_STRING_OFST 8
8133#define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_ERROR_STRING_LEN 80
8134
8135
8136/***********************************/
8137/* MC_CMD_REBOOT
8138 * Reboot the MC.
8139 *
8140 * The AFTER_ASSERTION flag is intended to be used when the driver notices an
8141 * assertion failure (at which point it is expected to perform a complete tear
8142 * down and reinitialise), to allow both ports to reset the MC once in an
8143 * atomic fashion.
8144 *
8145 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
8146 * which means that they will automatically reboot out of the assertion
8147 * handler, so this is in practise an optional operation. It is still
8148 * recommended that drivers execute this to support custom firmwares with
8149 * REBOOT_ON_ASSERT=0.
8150 *
8151 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
8152 * DATALEN=0
8153 */
8154#define MC_CMD_REBOOT 0x3d
8155#undef MC_CMD_0x3d_PRIVILEGE_CTG
8156
8157#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
8158
8159/* MC_CMD_REBOOT_IN msgrequest */
8160#define MC_CMD_REBOOT_IN_LEN 4
8161#define MC_CMD_REBOOT_IN_FLAGS_OFST 0
8162#define MC_CMD_REBOOT_IN_FLAGS_LEN 4
8163#define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
8164
8165/* MC_CMD_REBOOT_OUT msgresponse */
8166#define MC_CMD_REBOOT_OUT_LEN 0
8167
8168
8169/***********************************/
8170/* MC_CMD_SENSOR_INFO
8171 * Returns information about every available sensor.
8172 *
8173 * Each sensor has a single (16bit) value, and a corresponding state. The
8174 * mapping between value and state is nominally determined by the MC, but may
8175 * be implemented using up to 2 ranges per sensor.
8176 *
8177 * This call returns a mask (32bit) of the sensors that are supported by this
8178 * platform, then an array of sensor information structures, in order of sensor
8179 * type (but without gaps for unimplemented sensors). Each structure defines
8180 * the ranges for the corresponding sensor. An unused range is indicated by
8181 * equal limit values. If one range is used, a value outside that range results
8182 * in STATE_FATAL. If two ranges are used, a value outside the second range
8183 * results in STATE_FATAL while a value outside the first and inside the second
8184 * range results in STATE_WARNING.
8185 *
8186 * Sensor masks and sensor information arrays are organised into pages. For
8187 * backward compatibility, older host software can only use sensors in page 0.
8188 * Bit 32 in the sensor mask was previously unused, and is no reserved for use
8189 * as the next page flag.
8190 *
8191 * If the request does not contain a PAGE value then firmware will only return
8192 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
8193 *
8194 * If the request contains a PAGE value then firmware responds with the sensor
8195 * mask and sensor information array for that page of sensors. In this case bit
8196 * 31 in the mask is set if another page exists.
8197 *
8198 * Locks required: None Returns: 0
8199 */
8200#define MC_CMD_SENSOR_INFO 0x41
8201#undef MC_CMD_0x41_PRIVILEGE_CTG
8202
8203#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8204
8205/* MC_CMD_SENSOR_INFO_IN msgrequest */
8206#define MC_CMD_SENSOR_INFO_IN_LEN 0
8207
8208/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */
8209#define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
8210/* Which page of sensors to report.
8211 *
8212 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
8213 *
8214 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
8215 */
8216#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
8217#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
8218
8219/* MC_CMD_SENSOR_INFO_EXT_IN_V2 msgrequest */
8220#define MC_CMD_SENSOR_INFO_EXT_IN_V2_LEN 8
8221/* Which page of sensors to report.
8222 *
8223 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
8224 *
8225 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
8226 */
8227#define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 0
8228#define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4
8229/* Flags controlling information retrieved */
8230#define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4
8231#define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4
8232#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4
8233#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0
8234#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 1
8235
8236/* MC_CMD_SENSOR_INFO_OUT msgresponse */
8237#define MC_CMD_SENSOR_INFO_OUT_LENMIN 4
8238#define MC_CMD_SENSOR_INFO_OUT_LENMAX 252
8239#define MC_CMD_SENSOR_INFO_OUT_LENMAX_MCDI2 1020
8240#define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
8241#define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
8242#define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
8243#define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
8244/* enum: Controller temperature: degC */
8245#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
8246/* enum: Phy common temperature: degC */
8247#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
8248/* enum: Controller cooling: bool */
8249#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
8250/* enum: Phy 0 temperature: degC */
8251#define MC_CMD_SENSOR_PHY0_TEMP 0x3
8252/* enum: Phy 0 cooling: bool */
8253#define MC_CMD_SENSOR_PHY0_COOLING 0x4
8254/* enum: Phy 1 temperature: degC */
8255#define MC_CMD_SENSOR_PHY1_TEMP 0x5
8256/* enum: Phy 1 cooling: bool */
8257#define MC_CMD_SENSOR_PHY1_COOLING 0x6
8258/* enum: 1.0v power: mV */
8259#define MC_CMD_SENSOR_IN_1V0 0x7
8260/* enum: 1.2v power: mV */
8261#define MC_CMD_SENSOR_IN_1V2 0x8
8262/* enum: 1.8v power: mV */
8263#define MC_CMD_SENSOR_IN_1V8 0x9
8264/* enum: 2.5v power: mV */
8265#define MC_CMD_SENSOR_IN_2V5 0xa
8266/* enum: 3.3v power: mV */
8267#define MC_CMD_SENSOR_IN_3V3 0xb
8268/* enum: 12v power: mV */
8269#define MC_CMD_SENSOR_IN_12V0 0xc
8270/* enum: 1.2v analogue power: mV */
8271#define MC_CMD_SENSOR_IN_1V2A 0xd
8272/* enum: reference voltage: mV */
8273#define MC_CMD_SENSOR_IN_VREF 0xe
8274/* enum: AOE FPGA power: mV */
8275#define MC_CMD_SENSOR_OUT_VAOE 0xf
8276/* enum: AOE FPGA temperature: degC */
8277#define MC_CMD_SENSOR_AOE_TEMP 0x10
8278/* enum: AOE FPGA PSU temperature: degC */
8279#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
8280/* enum: AOE PSU temperature: degC */
8281#define MC_CMD_SENSOR_PSU_TEMP 0x12
8282/* enum: Fan 0 speed: RPM */
8283#define MC_CMD_SENSOR_FAN_0 0x13
8284/* enum: Fan 1 speed: RPM */
8285#define MC_CMD_SENSOR_FAN_1 0x14
8286/* enum: Fan 2 speed: RPM */
8287#define MC_CMD_SENSOR_FAN_2 0x15
8288/* enum: Fan 3 speed: RPM */
8289#define MC_CMD_SENSOR_FAN_3 0x16
8290/* enum: Fan 4 speed: RPM */
8291#define MC_CMD_SENSOR_FAN_4 0x17
8292/* enum: AOE FPGA input power: mV */
8293#define MC_CMD_SENSOR_IN_VAOE 0x18
8294/* enum: AOE FPGA current: mA */
8295#define MC_CMD_SENSOR_OUT_IAOE 0x19
8296/* enum: AOE FPGA input current: mA */
8297#define MC_CMD_SENSOR_IN_IAOE 0x1a
8298/* enum: NIC power consumption: W */
8299#define MC_CMD_SENSOR_NIC_POWER 0x1b
8300/* enum: 0.9v power voltage: mV */
8301#define MC_CMD_SENSOR_IN_0V9 0x1c
8302/* enum: 0.9v power current: mA */
8303#define MC_CMD_SENSOR_IN_I0V9 0x1d
8304/* enum: 1.2v power current: mA */
8305#define MC_CMD_SENSOR_IN_I1V2 0x1e
8306/* enum: Not a sensor: reserved for the next page flag */
8307#define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
8308/* enum: 0.9v power voltage (at ADC): mV */
8309#define MC_CMD_SENSOR_IN_0V9_ADC 0x20
8310/* enum: Controller temperature 2: degC */
8311#define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
8312/* enum: Voltage regulator internal temperature: degC */
8313#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
8314/* enum: 0.9V voltage regulator temperature: degC */
8315#define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
8316/* enum: 1.2V voltage regulator temperature: degC */
8317#define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
8318/* enum: controller internal temperature sensor voltage (internal ADC): mV */
8319#define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
8320/* enum: controller internal temperature (internal ADC): degC */
8321#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
8322/* enum: controller internal temperature sensor voltage (external ADC): mV */
8323#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
8324/* enum: controller internal temperature (external ADC): degC */
8325#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
8326/* enum: ambient temperature: degC */
8327#define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
8328/* enum: air flow: bool */
8329#define MC_CMD_SENSOR_AIRFLOW 0x2a
8330/* enum: voltage between VSS08D and VSS08D at CSR: mV */
8331#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
8332/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
8333#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
8334/* enum: Hotpoint temperature: degC */
8335#define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
8336/* enum: Port 0 PHY power switch over-current: bool */
8337#define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
8338/* enum: Port 1 PHY power switch over-current: bool */
8339#define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
8340/* enum: Mop-up microcontroller reference voltage: mV */
8341#define MC_CMD_SENSOR_MUM_VCC 0x30
8342/* enum: 0.9v power phase A voltage: mV */
8343#define MC_CMD_SENSOR_IN_0V9_A 0x31
8344/* enum: 0.9v power phase A current: mA */
8345#define MC_CMD_SENSOR_IN_I0V9_A 0x32
8346/* enum: 0.9V voltage regulator phase A temperature: degC */
8347#define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
8348/* enum: 0.9v power phase B voltage: mV */
8349#define MC_CMD_SENSOR_IN_0V9_B 0x34
8350/* enum: 0.9v power phase B current: mA */
8351#define MC_CMD_SENSOR_IN_I0V9_B 0x35
8352/* enum: 0.9V voltage regulator phase B temperature: degC */
8353#define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
8354/* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
8355#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
8356/* enum: CCOM AVREG 1v2 supply (external ADC): mV */
8357#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
8358/* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
8359#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
8360/* enum: CCOM AVREG 1v8 supply (external ADC): mV */
8361#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
8362/* enum: CCOM RTS temperature: degC */
8363#define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
8364/* enum: Not a sensor: reserved for the next page flag */
8365#define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
8366/* enum: controller internal temperature sensor voltage on master core
8367 * (internal ADC): mV
8368 */
8369#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
8370/* enum: controller internal temperature on master core (internal ADC): degC */
8371#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
8372/* enum: controller internal temperature sensor voltage on master core
8373 * (external ADC): mV
8374 */
8375#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
8376/* enum: controller internal temperature on master core (external ADC): degC */
8377#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
8378/* enum: controller internal temperature on slave core sensor voltage (internal
8379 * ADC): mV
8380 */
8381#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
8382/* enum: controller internal temperature on slave core (internal ADC): degC */
8383#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
8384/* enum: controller internal temperature on slave core sensor voltage (external
8385 * ADC): mV
8386 */
8387#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
8388/* enum: controller internal temperature on slave core (external ADC): degC */
8389#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
8390/* enum: Voltage supplied to the SODIMMs from their power supply: mV */
8391#define MC_CMD_SENSOR_SODIMM_VOUT 0x49
8392/* enum: Temperature of SODIMM 0 (if installed): degC */
8393#define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
8394/* enum: Temperature of SODIMM 1 (if installed): degC */
8395#define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
8396/* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
8397#define MC_CMD_SENSOR_PHY0_VCC 0x4c
8398/* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
8399#define MC_CMD_SENSOR_PHY1_VCC 0x4d
8400/* enum: Controller die temperature (TDIODE): degC */
8401#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
8402/* enum: Board temperature (front): degC */
8403#define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
8404/* enum: Board temperature (back): degC */
8405#define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
8406/* enum: 1.8v power current: mA */
8407#define MC_CMD_SENSOR_IN_I1V8 0x51
8408/* enum: 2.5v power current: mA */
8409#define MC_CMD_SENSOR_IN_I2V5 0x52
8410/* enum: 3.3v power current: mA */
8411#define MC_CMD_SENSOR_IN_I3V3 0x53
8412/* enum: 12v power current: mA */
8413#define MC_CMD_SENSOR_IN_I12V0 0x54
8414/* enum: 1.3v power: mV */
8415#define MC_CMD_SENSOR_IN_1V3 0x55
8416/* enum: 1.3v power current: mA */
8417#define MC_CMD_SENSOR_IN_I1V3 0x56
8418/* enum: Engineering sensor 1 */
8419#define MC_CMD_SENSOR_ENGINEERING_1 0x57
8420/* enum: Engineering sensor 2 */
8421#define MC_CMD_SENSOR_ENGINEERING_2 0x58
8422/* enum: Engineering sensor 3 */
8423#define MC_CMD_SENSOR_ENGINEERING_3 0x59
8424/* enum: Engineering sensor 4 */
8425#define MC_CMD_SENSOR_ENGINEERING_4 0x5a
8426/* enum: Engineering sensor 5 */
8427#define MC_CMD_SENSOR_ENGINEERING_5 0x5b
8428/* enum: Engineering sensor 6 */
8429#define MC_CMD_SENSOR_ENGINEERING_6 0x5c
8430/* enum: Engineering sensor 7 */
8431#define MC_CMD_SENSOR_ENGINEERING_7 0x5d
8432/* enum: Engineering sensor 8 */
8433#define MC_CMD_SENSOR_ENGINEERING_8 0x5e
8434/* enum: Not a sensor: reserved for the next page flag */
8435#define MC_CMD_SENSOR_PAGE2_NEXT 0x5f
8436/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
8437#define MC_CMD_SENSOR_ENTRY_OFST 4
8438#define MC_CMD_SENSOR_ENTRY_LEN 8
8439#define MC_CMD_SENSOR_ENTRY_LO_OFST 4
8440#define MC_CMD_SENSOR_ENTRY_LO_LEN 4
8441#define MC_CMD_SENSOR_ENTRY_LO_LBN 32
8442#define MC_CMD_SENSOR_ENTRY_LO_WIDTH 32
8443#define MC_CMD_SENSOR_ENTRY_HI_OFST 8
8444#define MC_CMD_SENSOR_ENTRY_HI_LEN 4
8445#define MC_CMD_SENSOR_ENTRY_HI_LBN 64
8446#define MC_CMD_SENSOR_ENTRY_HI_WIDTH 32
8447#define MC_CMD_SENSOR_ENTRY_MINNUM 0
8448#define MC_CMD_SENSOR_ENTRY_MAXNUM 31
8449#define MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127
8450
8451/* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */
8452#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
8453#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
8454#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX_MCDI2 1020
8455#define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
8456#define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
8457#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
8458#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
8459/* Enum values, see field(s): */
8460/* MC_CMD_SENSOR_INFO_OUT */
8461#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 0
8462#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31
8463#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
8464/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
8465/* MC_CMD_SENSOR_ENTRY_OFST 4 */
8466/* MC_CMD_SENSOR_ENTRY_LEN 8 */
8467/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
8468/* MC_CMD_SENSOR_ENTRY_LO_LEN 4 */
8469/* MC_CMD_SENSOR_ENTRY_LO_LBN 32 */
8470/* MC_CMD_SENSOR_ENTRY_LO_WIDTH 32 */
8471/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
8472/* MC_CMD_SENSOR_ENTRY_HI_LEN 4 */
8473/* MC_CMD_SENSOR_ENTRY_HI_LBN 64 */
8474/* MC_CMD_SENSOR_ENTRY_HI_WIDTH 32 */
8475/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
8476/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
8477/* MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */
8478
8479/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
8480#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
8481#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
8482#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
8483#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
8484#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
8485#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
8486#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
8487#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
8488#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
8489#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
8490#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
8491#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
8492#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
8493#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
8494#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
8495#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
8496#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
8497
8498
8499/***********************************/
8500/* MC_CMD_READ_SENSORS
8501 * Returns the current reading from each sensor. DMAs an array of sensor
8502 * readings, in order of sensor type (but without gaps for unimplemented
8503 * sensors), into host memory. Each array element is a
8504 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.
8505 *
8506 * If the request does not contain the LENGTH field then only sensors 0 to 30
8507 * are reported, to avoid DMA buffer overflow in older host software. If the
8508 * sensor reading require more space than the LENGTH allows, then return
8509 * EINVAL.
8510 *
8511 * The MC will send a SENSOREVT event every time any sensor changes state. The
8512 * driver is responsible for ensuring that it doesn't miss any events. The
8513 * board will function normally if all sensors are in STATE_OK or
8514 * STATE_WARNING. Otherwise the board should not be expected to function.
8515 */
8516#define MC_CMD_READ_SENSORS 0x42
8517#undef MC_CMD_0x42_PRIVILEGE_CTG
8518
8519#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8520
8521/* MC_CMD_READ_SENSORS_IN msgrequest */
8522#define MC_CMD_READ_SENSORS_IN_LEN 8
8523/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
8524 *
8525 * If the address is 0xffffffffffffffff send the readings in the response (used
8526 * by cmdclient).
8527 */
8528#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
8529#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
8530#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
8531#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LEN 4
8532#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LBN 0
8533#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_WIDTH 32
8534#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
8535#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LEN 4
8536#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LBN 32
8537#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_WIDTH 32
8538
8539/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
8540#define MC_CMD_READ_SENSORS_EXT_IN_LEN 12
8541/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
8542 *
8543 * If the address is 0xffffffffffffffff send the readings in the response (used
8544 * by cmdclient).
8545 */
8546#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
8547#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
8548#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
8549#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LEN 4
8550#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LBN 0
8551#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_WIDTH 32
8552#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
8553#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LEN 4
8554#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LBN 32
8555#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_WIDTH 32
8556/* Size in bytes of host buffer. */
8557#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
8558#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
8559
8560/* MC_CMD_READ_SENSORS_EXT_IN_V2 msgrequest */
8561#define MC_CMD_READ_SENSORS_EXT_IN_V2_LEN 16
8562/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
8563 *
8564 * If the address is 0xffffffffffffffff send the readings in the response (used
8565 * by cmdclient).
8566 */
8567#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
8568#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8
8569#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
8570#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LEN 4
8571#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LBN 0
8572#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_WIDTH 32
8573#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
8574#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LEN 4
8575#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LBN 32
8576#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_WIDTH 32
8577/* Size in bytes of host buffer. */
8578#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 8
8579#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
8580/* Flags controlling information retrieved */
8581#define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_OFST 12
8582#define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4
8583#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_OFST 12
8584#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0
8585#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 1
8586
8587/* MC_CMD_READ_SENSORS_OUT msgresponse */
8588#define MC_CMD_READ_SENSORS_OUT_LEN 0
8589
8590/* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */
8591#define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
8592
8593/* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
8594#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
8595#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
8596#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
8597#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
8598#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
8599#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
8600#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
8601/* enum: Ok. */
8602#define MC_CMD_SENSOR_STATE_OK 0x0
8603/* enum: Breached warning threshold. */
8604#define MC_CMD_SENSOR_STATE_WARNING 0x1
8605/* enum: Breached fatal threshold. */
8606#define MC_CMD_SENSOR_STATE_FATAL 0x2
8607/* enum: Fault with sensor. */
8608#define MC_CMD_SENSOR_STATE_BROKEN 0x3
8609/* enum: Sensor is working but does not currently have a reading. */
8610#define MC_CMD_SENSOR_STATE_NO_READING 0x4
8611/* enum: Sensor initialisation failed. */
8612#define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
8613#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
8614#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
8615#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3
8616#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
8617/* Enum values, see field(s): */
8618/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
8619#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24
8620#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8
8621
8622
8623/***********************************/
8624/* MC_CMD_GET_PHY_STATE
8625 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot
8626 * (e.g. due to missing or corrupted firmware). Locks required: None. Return
8627 * code: 0
8628 */
8629#define MC_CMD_GET_PHY_STATE 0x43
8630#undef MC_CMD_0x43_PRIVILEGE_CTG
8631
8632#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8633
8634/* MC_CMD_GET_PHY_STATE_IN msgrequest */
8635#define MC_CMD_GET_PHY_STATE_IN_LEN 0
8636
8637/* MC_CMD_GET_PHY_STATE_IN_V2 msgrequest */
8638#define MC_CMD_GET_PHY_STATE_IN_V2_LEN 8
8639/* Target port to request PHY state for. Uses MAE_LINK_ENDPOINT_SELECTOR which
8640 * identifies a real or virtual network port by MAE port and link end. See the
8641 * structure definition for more details.
8642 */
8643#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_OFST 0
8644#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LEN 8
8645#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LO_OFST 0
8646#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LO_LEN 4
8647#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LO_LBN 0
8648#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LO_WIDTH 32
8649#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_HI_OFST 4
8650#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_HI_LEN 4
8651#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_HI_LBN 32
8652#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_HI_WIDTH 32
8653/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
8654#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_OFST 0
8655#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_LEN 4
8656#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0
8657#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4
8658#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_TYPE_OFST 3
8659#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_TYPE_LEN 1
8660#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
8661#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
8662#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
8663#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
8664#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
8665#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
8666#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
8667#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
8668#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 2
8669#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
8670#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
8671#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
8672#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LINK_END_OFST 4
8673#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LINK_END_LEN 4
8674#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_OFST 0
8675#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LEN 8
8676#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LO_OFST 0
8677#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LO_LEN 4
8678#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LO_LBN 0
8679#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LO_WIDTH 32
8680#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_HI_OFST 4
8681#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_HI_LEN 4
8682#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_HI_LBN 32
8683#define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_HI_WIDTH 32
8684
8685/* MC_CMD_GET_PHY_STATE_OUT msgresponse */
8686#define MC_CMD_GET_PHY_STATE_OUT_LEN 4
8687#define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
8688#define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
8689/* enum: Ok. */
8690#define MC_CMD_PHY_STATE_OK 0x1
8691/* enum: Faulty. */
8692#define MC_CMD_PHY_STATE_ZOMBIE 0x2
8693
8694
8695/***********************************/
8696/* MC_CMD_WOL_FILTER_GET
8697 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
8698 */
8699#define MC_CMD_WOL_FILTER_GET 0x45
8700#undef MC_CMD_0x45_PRIVILEGE_CTG
8701
8702#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
8703
8704/* MC_CMD_WOL_FILTER_GET_IN msgrequest */
8705#define MC_CMD_WOL_FILTER_GET_IN_LEN 0
8706
8707/* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
8708#define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
8709#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
8710#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4
8711
8712
8713/***********************************/
8714/* MC_CMD_WORKAROUND
8715 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't
8716 * understand the given workaround number - which should not be treated as a
8717 * hard error by client code. This op does not imply any semantics about each
8718 * workaround, that's between the driver and the mcfw on a per-workaround
8719 * basis. Locks required: None. Returns: 0, EINVAL .
8720 */
8721#define MC_CMD_WORKAROUND 0x4a
8722#undef MC_CMD_0x4a_PRIVILEGE_CTG
8723
8724#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8725
8726/* MC_CMD_WORKAROUND_IN msgrequest */
8727#define MC_CMD_WORKAROUND_IN_LEN 8
8728/* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */
8729#define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
8730#define MC_CMD_WORKAROUND_IN_TYPE_LEN 4
8731/* enum: Bug 17230 work around. */
8732#define MC_CMD_WORKAROUND_BUG17230 0x1
8733/* enum: Bug 35388 work around (unsafe EVQ writes). */
8734#define MC_CMD_WORKAROUND_BUG35388 0x2
8735/* enum: Bug35017 workaround (A64 tables must be identity map) */
8736#define MC_CMD_WORKAROUND_BUG35017 0x3
8737/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
8738#define MC_CMD_WORKAROUND_BUG41750 0x4
8739/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
8740 * - before adding code that queries this workaround, remember that there's
8741 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
8742 * and will hence (incorrectly) report that the bug doesn't exist.
8743 */
8744#define MC_CMD_WORKAROUND_BUG42008 0x5
8745/* enum: Bug 26807 features present in firmware (multicast filter chaining)
8746 * This feature cannot be turned on/off while there are any filters already
8747 * present. The behaviour in such case depends on the acting client's privilege
8748 * level. If the client has the admin privilege, then all functions that have
8749 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise
8750 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.
8751 */
8752#define MC_CMD_WORKAROUND_BUG26807 0x6
8753/* enum: Bug 61265 work around (broken EVQ TMR writes). */
8754#define MC_CMD_WORKAROUND_BUG61265 0x7
8755/* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
8756 * the workaround
8757 */
8758#define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
8759#define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
8760
8761/* MC_CMD_WORKAROUND_OUT msgresponse */
8762#define MC_CMD_WORKAROUND_OUT_LEN 0
8763
8764/* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used
8765 * when (TYPE == MC_CMD_WORKAROUND_BUG26807)
8766 */
8767#define MC_CMD_WORKAROUND_EXT_OUT_LEN 4
8768#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
8769#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
8770#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0
8771#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
8772#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
8773
8774
8775/***********************************/
8776/* MC_CMD_GET_PHY_MEDIA_INFO
8777 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
8778 * SFP+ PHYs). The "media type" can be found via GET_PHY_CFG
8779 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid "page number" input values, and the
8780 * output data, are interpreted on a per-type basis. For SFP+, PAGE=0 or 1
8781 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
8782 * For QSFP, PAGE=-1 is the lower (unbanked) page. PAGE=2 is the EEPROM and
8783 * PAGE=3 is the module limits. For DSFP, module addressing requires a
8784 * "BANK:PAGE". Not every bank has the same number of pages. See the Common
8785 * Management Interface Specification (CMIS) for further details. A BANK:PAGE
8786 * of "0xffff:0xffff" retrieves the lower (unbanked) page. Locks required -
8787 * None. Return code - 0.
8788 */
8789#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
8790#undef MC_CMD_0x4b_PRIVILEGE_CTG
8791
8792#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8793
8794/* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
8795#define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
8796#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
8797#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
8798#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_OFST 0
8799#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_LBN 0
8800#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_WIDTH 16
8801#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_OFST 0
8802#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_LBN 16
8803#define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_WIDTH 16
8804
8805/* MC_CMD_GET_PHY_MEDIA_INFO_IN_V2 msgrequest */
8806#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_LEN 12
8807#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_PAGE_OFST 0
8808#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_PAGE_LEN 4
8809#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_PAGE_OFST 0
8810#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_PAGE_LBN 0
8811#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_PAGE_WIDTH 16
8812#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_BANK_OFST 0
8813#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_BANK_LBN 16
8814#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_BANK_WIDTH 16
8815/* Target port to request PHY state for. Uses MAE_LINK_ENDPOINT_SELECTOR which
8816 * identifies a real or virtual network port by MAE port and link end. See the
8817 * structure definition for more details
8818 */
8819#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_OFST 4
8820#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LEN 8
8821#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LO_OFST 4
8822#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LO_LEN 4
8823#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LO_LBN 32
8824#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LO_WIDTH 32
8825#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_HI_OFST 8
8826#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_HI_LEN 4
8827#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_HI_LBN 64
8828#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_HI_WIDTH 32
8829/* See structuredef: MAE_LINK_ENDPOINT_SELECTOR */
8830#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_OFST 4
8831#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_LEN 4
8832#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 4
8833#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4
8834#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_TYPE_OFST 7
8835#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_TYPE_LEN 1
8836#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 4
8837#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_LEN 3
8838#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 32
8839#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
8840#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_LBN 52
8841#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
8842#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 48
8843#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
8844#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_OFST 6
8845#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_PF_ID_LEN 1
8846#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 4
8847#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_LEN 2
8848#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LINK_END_OFST 8
8849#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LINK_END_LEN 4
8850#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_OFST 4
8851#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LEN 8
8852#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LO_OFST 4
8853#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LO_LEN 4
8854#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LO_LBN 32
8855#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LO_WIDTH 32
8856#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_HI_OFST 8
8857#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_HI_LEN 4
8858#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_HI_LBN 64
8859#define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_HI_WIDTH 32
8860
8861/* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
8862#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
8863#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
8864#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX_MCDI2 1020
8865#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
8866#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)
8867/* in bytes */
8868#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
8869#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
8870#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
8871#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
8872#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
8873#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
8874#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM_MCDI2 1016
8875
8876
8877/***********************************/
8878/* MC_CMD_NVRAM_TEST
8879 * Test a particular NVRAM partition for valid contents (where "valid" depends
8880 * on the type of partition).
8881 */
8882#define MC_CMD_NVRAM_TEST 0x4c
8883#undef MC_CMD_0x4c_PRIVILEGE_CTG
8884
8885#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
8886
8887/* MC_CMD_NVRAM_TEST_IN msgrequest */
8888#define MC_CMD_NVRAM_TEST_IN_LEN 4
8889#define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
8890#define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
8891/* Enum values, see field(s): */
8892/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
8893
8894/* MC_CMD_NVRAM_TEST_OUT msgresponse */
8895#define MC_CMD_NVRAM_TEST_OUT_LEN 4
8896#define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
8897#define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
8898/* enum: Passed. */
8899#define MC_CMD_NVRAM_TEST_PASS 0x0
8900/* enum: Failed. */
8901#define MC_CMD_NVRAM_TEST_FAIL 0x1
8902/* enum: Not supported. */
8903#define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
8904
8905
8906/***********************************/
8907/* MC_CMD_NVRAM_PARTITIONS
8908 * Reads the list of available virtual NVRAM partition types. Locks required:
8909 * none. Returns: 0, EINVAL (bad type).
8910 */
8911#define MC_CMD_NVRAM_PARTITIONS 0x51
8912#undef MC_CMD_0x51_PRIVILEGE_CTG
8913
8914#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8915
8916/* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */
8917#define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
8918
8919/* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */
8920#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
8921#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
8922#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX_MCDI2 1020
8923#define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
8924#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)
8925/* total number of partitions */
8926#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
8927#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
8928/* type ID code for each of NUM_PARTITIONS partitions */
8929#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
8930#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
8931#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
8932#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62
8933#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM_MCDI2 254
8934
8935
8936/***********************************/
8937/* MC_CMD_NVRAM_METADATA
8938 * Reads soft metadata for a virtual NVRAM partition type. Locks required:
8939 * none. Returns: 0, EINVAL (bad type).
8940 */
8941#define MC_CMD_NVRAM_METADATA 0x52
8942#undef MC_CMD_0x52_PRIVILEGE_CTG
8943
8944#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
8945
8946/* MC_CMD_NVRAM_METADATA_IN msgrequest */
8947#define MC_CMD_NVRAM_METADATA_IN_LEN 4
8948/* Partition type ID code */
8949#define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
8950#define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
8951
8952/* MC_CMD_NVRAM_METADATA_OUT msgresponse */
8953#define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20
8954#define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
8955#define MC_CMD_NVRAM_METADATA_OUT_LENMAX_MCDI2 1020
8956#define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
8957#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)
8958/* Partition type ID code */
8959#define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
8960#define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
8961#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
8962#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
8963#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4
8964#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
8965#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
8966#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4
8967#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
8968#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
8969#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4
8970#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2
8971#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
8972/* Subtype ID code for content of this partition */
8973#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8
8974#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
8975/* 1st component of W.X.Y.Z version number for content of this partition */
8976#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12
8977#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2
8978/* 2nd component of W.X.Y.Z version number for content of this partition */
8979#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14
8980#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2
8981/* 3rd component of W.X.Y.Z version number for content of this partition */
8982#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16
8983#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2
8984/* 4th component of W.X.Y.Z version number for content of this partition */
8985#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18
8986#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2
8987/* Zero-terminated string describing the content of this partition */
8988#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20
8989#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
8990#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
8991#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232
8992#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM_MCDI2 1000
8993
8994
8995/***********************************/
8996/* MC_CMD_GET_MAC_ADDRESSES
8997 * Returns the base MAC, count and stride for the requesting function
8998 */
8999#define MC_CMD_GET_MAC_ADDRESSES 0x55
9000#undef MC_CMD_0x55_PRIVILEGE_CTG
9001
9002#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9003
9004/* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */
9005#define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
9006
9007/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */
9008#define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16
9009/* Base MAC address */
9010#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
9011#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6
9012/* Padding */
9013#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6
9014#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2
9015/* Number of allocated MAC addresses */
9016#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8
9017#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
9018/* Spacing of allocated MAC addresses */
9019#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12
9020#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
9021
9022/* MC_CMD_DYNAMIC_SENSORS_LIMITS structuredef: Set of sensor limits. This
9023 * should match the equivalent structure in the sensor_query SPHINX service.
9024 */
9025#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LEN 24
9026/* A value below this will trigger a warning event. */
9027#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0
9028#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4
9029#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0
9030#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_WIDTH 32
9031/* A value below this will trigger a critical event. */
9032#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4
9033#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4
9034#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LBN 32
9035#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_WIDTH 32
9036/* A value below this will shut down the card. */
9037#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_OFST 8
9038#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4
9039#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LBN 64
9040#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_WIDTH 32
9041/* A value above this will trigger a warning event. */
9042#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_OFST 12
9043#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4
9044#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LBN 96
9045#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_WIDTH 32
9046/* A value above this will trigger a critical event. */
9047#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_OFST 16
9048#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4
9049#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LBN 128
9050#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_WIDTH 32
9051/* A value above this will shut down the card. */
9052#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_OFST 20
9053#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4
9054#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LBN 160
9055#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_WIDTH 32
9056
9057/* MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structuredef: Description of a sensor.
9058 * This should match the equivalent structure in the sensor_query SPHINX
9059 * service.
9060 */
9061#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LEN 64
9062/* The handle used to identify the sensor in calls to
9063 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES
9064 */
9065#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0
9066#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4
9067#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0
9068#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_WIDTH 32
9069/* A human-readable name for the sensor (zero terminated string, max 32 bytes)
9070 */
9071#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4
9072#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LEN 32
9073#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LBN 32
9074#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_WIDTH 256
9075/* The type of the sensor device, and by implication the unit of that the
9076 * values will be reported in
9077 */
9078#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_OFST 36
9079#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4
9080/* enum: A voltage sensor. Unit is mV */
9081#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0
9082/* enum: A current sensor. Unit is mA */
9083#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1
9084/* enum: A power sensor. Unit is mW */
9085#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2
9086/* enum: A temperature sensor. Unit is Celsius */
9087#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3
9088/* enum: A cooling fan sensor. Unit is RPM */
9089#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4
9090#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LBN 288
9091#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_WIDTH 32
9092/* A single MC_CMD_DYNAMIC_SENSORS_LIMITS structure */
9093#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_OFST 40
9094#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LEN 24
9095#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LBN 320
9096#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_WIDTH 192
9097
9098/* MC_CMD_DYNAMIC_SENSORS_READING structuredef: State and value of a sensor.
9099 * This should match the equivalent structure in the sensor_query SPHINX
9100 * service.
9101 */
9102#define MC_CMD_DYNAMIC_SENSORS_READING_LEN 12
9103/* The handle used to identify the sensor */
9104#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0
9105#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4
9106#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0
9107#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_WIDTH 32
9108/* The current value of the sensor */
9109#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4
9110#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4
9111#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LBN 32
9112#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_WIDTH 32
9113/* The sensor's condition, e.g. good, broken or removed */
9114#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_OFST 8
9115#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4
9116/* enum: Sensor working normally within limits */
9117#define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0
9118/* enum: Warning threshold breached */
9119#define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1
9120/* enum: Critical threshold breached */
9121#define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2
9122/* enum: Fatal threshold breached */
9123#define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3
9124/* enum: Sensor not working */
9125#define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4
9126/* enum: Sensor working but no reading available */
9127#define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5
9128/* enum: Sensor initialization failed */
9129#define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6
9130#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LBN 64
9131#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_WIDTH 32
9132
9133
9134/***********************************/
9135/* MC_CMD_DYNAMIC_SENSORS_LIST
9136 * Return a complete list of handles for sensors currently managed by the MC,
9137 * and a generation count for this version of the sensor table. On systems
9138 * advertising the DYNAMIC_SENSORS capability bit, this replaces the
9139 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors
9140 * added by the NMC. Sensor handles are persistent for the lifetime of the
9141 * sensor and are used to identify sensors in
9142 * MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and
9143 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES. The generation count is maintained by the
9144 * MC, is persistent across reboots and will be incremented each time the
9145 * sensor table is modified. When the table is modified, a
9146 * CODE_DYNAMIC_SENSORS_CHANGE event will be generated containing the new
9147 * generation count. The driver should compare this against the current
9148 * generation count, and if it is different, call MC_CMD_DYNAMIC_SENSORS_LIST
9149 * again to update it's copy of the sensor table. The sensor count is provided
9150 * to allow a future path to supporting more than
9151 * MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 sensors, i.e.
9152 * the maximum number that will fit in a single response. As this is a fairly
9153 * large number (253) it is not anticipated that this will be needed in the
9154 * near future, so can currently be ignored. On Riverhead this command is
9155 * implemented as a wrapper for `list` in the sensor_query SPHINX service.
9156 */
9157#define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
9158#undef MC_CMD_0x66_PRIVILEGE_CTG
9159
9160#define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9161
9162/* MC_CMD_DYNAMIC_SENSORS_LIST_IN msgrequest */
9163#define MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 0
9164
9165/* MC_CMD_DYNAMIC_SENSORS_LIST_OUT msgresponse */
9166#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMIN 8
9167#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX 252
9168#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX_MCDI2 1020
9169#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))
9170#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)
9171/* Generation count, which will be updated each time a sensor is added to or
9172 * removed from the MC sensor table.
9173 */
9174#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0
9175#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4
9176/* Number of sensors managed by the MC. Note that in principle, this can be
9177 * larger than the size of the HANDLES array.
9178 */
9179#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4
9180#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4
9181/* Array of sensor handles */
9182#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_OFST 8
9183#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4
9184#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0
9185#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM 61
9186#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM_MCDI2 253
9187
9188
9189/***********************************/
9190/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS
9191 * Get descriptions for a set of sensors, specified as an array of sensor
9192 * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST. Any handles which do not
9193 * correspond to a sensor currently managed by the MC will be dropped from from
9194 * the response. This may happen when a sensor table update is in progress, and
9195 * effectively means the set of usable sensors is the intersection between the
9196 * sets of sensors known to the driver and the MC. On Riverhead this command is
9197 * implemented as a wrapper for `get_descriptions` in the sensor_query SPHINX
9198 * service.
9199 */
9200#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
9201#undef MC_CMD_0x67_PRIVILEGE_CTG
9202
9203#define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9204
9205/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN msgrequest */
9206#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 0
9207#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX 252
9208#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX_MCDI2 1020
9209#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
9210#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
9211/* Array of sensor handles */
9212#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 0
9213#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4
9214#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 0
9215#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM 63
9216#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM_MCDI2 255
9217
9218/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT msgresponse */
9219#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 0
9220#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX 192
9221#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX_MCDI2 960
9222#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))
9223#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
9224/* Array of MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structures */
9225#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 0
9226#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_LEN 64
9227#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 0
9228#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM 3
9229#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM_MCDI2 15
9230
9231
9232/***********************************/
9233/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS
9234 * Read the state and value for a set of sensors, specified as an array of
9235 * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST. In the case of a
9236 * broken sensor, then the state of the response's MC_CMD_DYNAMIC_SENSORS_VALUE
9237 * entry will be set to BROKEN, and any value provided should be treated as
9238 * erroneous. Any handles which do not correspond to a sensor currently managed
9239 * by the MC will be dropped from from the response. This may happen when a
9240 * sensor table update is in progress, and effectively means the set of usable
9241 * sensors is the intersection between the sets of sensors known to the driver
9242 * and the MC. On Riverhead this command is implemented as a wrapper for
9243 * `get_readings` in the sensor_query SPHINX service.
9244 */
9245#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
9246#undef MC_CMD_0x68_PRIVILEGE_CTG
9247
9248#define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9249
9250/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN msgrequest */
9251#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 0
9252#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX 252
9253#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX_MCDI2 1020
9254#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
9255#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
9256/* Array of sensor handles */
9257#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 0
9258#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4
9259#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 0
9260#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM 63
9261#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 255
9262
9263/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT msgresponse */
9264#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 0
9265#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX 252
9266#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX_MCDI2 1020
9267#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))
9268#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
9269/* Array of MC_CMD_DYNAMIC_SENSORS_READING structures */
9270#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 0
9271#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_LEN 12
9272#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 0
9273#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM 21
9274#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM_MCDI2 85
9275
9276/* MC_CMD_MAC_FLAGS structuredef */
9277#define MC_CMD_MAC_FLAGS_LEN 4
9278/* The enums defined in this field are used as indices into the
9279 * MC_CMD_MAC_FLAGS bitmask.
9280 */
9281#define MC_CMD_MAC_FLAGS_MASK_OFST 0
9282#define MC_CMD_MAC_FLAGS_MASK_LEN 4
9283/* enum property: bitshift */
9284/* enum: Include the FCS in the packet data delivered to the host. Ignored if
9285 * RX_INCLUDE_FCS not set in capabilities.
9286 */
9287#define MC_CMD_MAC_FLAGS_FLAG_INCLUDE_FCS 0x0
9288#define MC_CMD_MAC_FLAGS_MASK_LBN 0
9289#define MC_CMD_MAC_FLAGS_MASK_WIDTH 32
9290
9291/* MC_CMD_TRANSMISSION_MODE structuredef */
9292#define MC_CMD_TRANSMISSION_MODE_LEN 4
9293#define MC_CMD_TRANSMISSION_MODE_MASK_OFST 0
9294#define MC_CMD_TRANSMISSION_MODE_MASK_LEN 4
9295/* enum property: value */
9296#define MC_CMD_TRANSMISSION_MODE_PROMSC_MODE 0x0 /* enum */
9297#define MC_CMD_TRANSMISSION_MODE_UNCST_MODE 0x1 /* enum */
9298#define MC_CMD_TRANSMISSION_MODE_BRDCST_MODE 0x2 /* enum */
9299#define MC_CMD_TRANSMISSION_MODE_MASK_LBN 0
9300#define MC_CMD_TRANSMISSION_MODE_MASK_WIDTH 32
9301
9302/* MC_CMD_MAC_CONFIG_OPTIONS structuredef */
9303#define MC_CMD_MAC_CONFIG_OPTIONS_LEN 4
9304#define MC_CMD_MAC_CONFIG_OPTIONS_MASK_OFST 0
9305#define MC_CMD_MAC_CONFIG_OPTIONS_MASK_LEN 4
9306/* enum property: bitmask */
9307/* enum: Configure the MAC address. */
9308#define MC_CMD_MAC_CONFIG_OPTIONS_CFG_ADDR 0x0
9309/* enum: Configure the maximum frame length. */
9310#define MC_CMD_MAC_CONFIG_OPTIONS_CFG_MAX_FRAME_LEN 0x1
9311/* enum: Configure flow control. */
9312#define MC_CMD_MAC_CONFIG_OPTIONS_CFG_FCNTL 0x2
9313/* enum: Configure the transmission mode. */
9314#define MC_CMD_MAC_CONFIG_OPTIONS_CFG_TRANSMISSION_MODE 0x3
9315/* enum: Configure FCS. */
9316#define MC_CMD_MAC_CONFIG_OPTIONS_CFG_INCLUDE_FCS 0x4
9317#define MC_CMD_MAC_CONFIG_OPTIONS_MASK_LBN 0
9318#define MC_CMD_MAC_CONFIG_OPTIONS_MASK_WIDTH 32
9319
9320
9321/***********************************/
9322/* MC_CMD_MAC_CTRL
9323 * Set MAC configuration. Return code: 0, EINVAL, ENOTSUP
9324 */
9325#define MC_CMD_MAC_CTRL 0x1df
9326#undef MC_CMD_0x1df_PRIVILEGE_CTG
9327
9328#define MC_CMD_0x1df_PRIVILEGE_CTG SRIOV_CTG_LINK
9329
9330/* MC_CMD_MAC_CTRL_IN msgrequest */
9331#define MC_CMD_MAC_CTRL_IN_LEN 32
9332/* Handle for selected network port. */
9333#define MC_CMD_MAC_CTRL_IN_PORT_HANDLE_OFST 0
9334#define MC_CMD_MAC_CTRL_IN_PORT_HANDLE_LEN 4
9335/* Select which parameters to configure. A parameter will only be modified if
9336 * the corresponding control flag is set.
9337 */
9338#define MC_CMD_MAC_CTRL_IN_CONTROL_FLAGS_OFST 4
9339#define MC_CMD_MAC_CTRL_IN_CONTROL_FLAGS_LEN 4
9340/* enum property: bitshift */
9341/* Enum values, see field(s): */
9342/* MC_CMD_MAC_CONFIG_OPTIONS/MASK */
9343/* MAC address of the device. */
9344#define MC_CMD_MAC_CTRL_IN_ADDR_OFST 8
9345#define MC_CMD_MAC_CTRL_IN_ADDR_LEN 8
9346#define MC_CMD_MAC_CTRL_IN_ADDR_LO_OFST 8
9347#define MC_CMD_MAC_CTRL_IN_ADDR_LO_LEN 4
9348#define MC_CMD_MAC_CTRL_IN_ADDR_LO_LBN 64
9349#define MC_CMD_MAC_CTRL_IN_ADDR_LO_WIDTH 32
9350#define MC_CMD_MAC_CTRL_IN_ADDR_HI_OFST 12
9351#define MC_CMD_MAC_CTRL_IN_ADDR_HI_LEN 4
9352#define MC_CMD_MAC_CTRL_IN_ADDR_HI_LBN 96
9353#define MC_CMD_MAC_CTRL_IN_ADDR_HI_WIDTH 32
9354/* Includes the ethernet header, optional VLAN tags, payload and FCS. */
9355#define MC_CMD_MAC_CTRL_IN_MAX_FRAME_LEN_OFST 16
9356#define MC_CMD_MAC_CTRL_IN_MAX_FRAME_LEN_LEN 4
9357/* Settings for flow control. */
9358#define MC_CMD_MAC_CTRL_IN_FCNTL_OFST 20
9359#define MC_CMD_MAC_CTRL_IN_FCNTL_LEN 4
9360/* enum property: value */
9361/* Enum values, see field(s): */
9362/* MC_CMD_FCNTL/MASK */
9363/* Configure the MAC to transmit in one of promiscuous, unicast or broadcast
9364 * mode.
9365 */
9366#define MC_CMD_MAC_CTRL_IN_TRANSMISSION_MODE_OFST 24
9367#define MC_CMD_MAC_CTRL_IN_TRANSMISSION_MODE_LEN 4
9368/* enum property: value */
9369/* Enum values, see field(s): */
9370/* MC_CMD_TRANSMISSION_MODE/MASK */
9371/* Flags to control and expand the configuration of the MAC. */
9372#define MC_CMD_MAC_CTRL_IN_FLAGS_OFST 28
9373#define MC_CMD_MAC_CTRL_IN_FLAGS_LEN 4
9374/* enum property: bitshift */
9375/* Enum values, see field(s): */
9376/* MC_CMD_MAC_FLAGS/MASK */
9377
9378/* MC_CMD_MAC_CTRL_IN_V2 msgrequest: Updated MAC_CTRL with QBB mask */
9379#define MC_CMD_MAC_CTRL_IN_V2_LEN 33
9380/* Handle for selected network port. */
9381#define MC_CMD_MAC_CTRL_IN_V2_PORT_HANDLE_OFST 0
9382#define MC_CMD_MAC_CTRL_IN_V2_PORT_HANDLE_LEN 4
9383/* Select which parameters to configure. A parameter will only be modified if
9384 * the corresponding control flag is set.
9385 */
9386#define MC_CMD_MAC_CTRL_IN_V2_CONTROL_FLAGS_OFST 4
9387#define MC_CMD_MAC_CTRL_IN_V2_CONTROL_FLAGS_LEN 4
9388/* enum property: bitshift */
9389/* Enum values, see field(s): */
9390/* MC_CMD_MAC_CONFIG_OPTIONS/MASK */
9391/* MAC address of the device. */
9392#define MC_CMD_MAC_CTRL_IN_V2_ADDR_OFST 8
9393#define MC_CMD_MAC_CTRL_IN_V2_ADDR_LEN 8
9394#define MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_OFST 8
9395#define MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_LEN 4
9396#define MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_LBN 64
9397#define MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_WIDTH 32
9398#define MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_OFST 12
9399#define MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_LEN 4
9400#define MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_LBN 96
9401#define MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_WIDTH 32
9402/* Includes the ethernet header, optional VLAN tags, payload and FCS. */
9403#define MC_CMD_MAC_CTRL_IN_V2_MAX_FRAME_LEN_OFST 16
9404#define MC_CMD_MAC_CTRL_IN_V2_MAX_FRAME_LEN_LEN 4
9405/* Settings for flow control. */
9406#define MC_CMD_MAC_CTRL_IN_V2_FCNTL_OFST 20
9407#define MC_CMD_MAC_CTRL_IN_V2_FCNTL_LEN 4
9408/* enum property: value */
9409/* Enum values, see field(s): */
9410/* MC_CMD_FCNTL/MASK */
9411/* Configure the MAC to transmit in one of promiscuous, unicast or broadcast
9412 * mode.
9413 */
9414#define MC_CMD_MAC_CTRL_IN_V2_TRANSMISSION_MODE_OFST 24
9415#define MC_CMD_MAC_CTRL_IN_V2_TRANSMISSION_MODE_LEN 4
9416/* enum property: value */
9417/* Enum values, see field(s): */
9418/* MC_CMD_TRANSMISSION_MODE/MASK */
9419/* Flags to control and expand the configuration of the MAC. */
9420#define MC_CMD_MAC_CTRL_IN_V2_FLAGS_OFST 28
9421#define MC_CMD_MAC_CTRL_IN_V2_FLAGS_LEN 4
9422/* enum property: bitshift */
9423/* Enum values, see field(s): */
9424/* MC_CMD_MAC_FLAGS/MASK */
9425/* Priority-based flow control mask (QBB). PRIO7 corresponds to the highest
9426 * priority, and PRIO0 to the lowest. This field is only used when CFG_FCNTL is
9427 * set and FCNTL is QBB
9428 */
9429#define MC_CMD_MAC_CTRL_IN_V2_PRIO_FCNTL_MASK_OFST 32
9430#define MC_CMD_MAC_CTRL_IN_V2_PRIO_FCNTL_MASK_LEN 1
9431/* enum property: bitmask */
9432#define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO0 0x0 /* enum */
9433#define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO1 0x1 /* enum */
9434#define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO2 0x2 /* enum */
9435#define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO3 0x3 /* enum */
9436#define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO4 0x4 /* enum */
9437#define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO5 0x5 /* enum */
9438#define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO6 0x6 /* enum */
9439#define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO7 0x7 /* enum */
9440
9441/* MC_CMD_MAC_CTRL_OUT msgresponse */
9442#define MC_CMD_MAC_CTRL_OUT_LEN 0
9443
9444
9445/***********************************/
9446/* MC_CMD_MAC_STATE
9447 * Read the MAC state. Return code: 0, ETIME.
9448 */
9449#define MC_CMD_MAC_STATE 0x1e0
9450#undef MC_CMD_0x1e0_PRIVILEGE_CTG
9451
9452#define MC_CMD_0x1e0_PRIVILEGE_CTG SRIOV_CTG_LINK
9453
9454/* MC_CMD_MAC_STATE_IN msgrequest */
9455#define MC_CMD_MAC_STATE_IN_LEN 4
9456/* Handle for selected network port. */
9457#define MC_CMD_MAC_STATE_IN_PORT_HANDLE_OFST 0
9458#define MC_CMD_MAC_STATE_IN_PORT_HANDLE_LEN 4
9459
9460/* MC_CMD_MAC_STATE_OUT msgresponse */
9461#define MC_CMD_MAC_STATE_OUT_LEN 32
9462/* The configured maximum frame length of the MAC. */
9463#define MC_CMD_MAC_STATE_OUT_MAX_FRAME_LEN_OFST 0
9464#define MC_CMD_MAC_STATE_OUT_MAX_FRAME_LEN_LEN 4
9465/* This returns the negotiated flow control value. */
9466#define MC_CMD_MAC_STATE_OUT_FCNTL_OFST 4
9467#define MC_CMD_MAC_STATE_OUT_FCNTL_LEN 4
9468/* enum property: value */
9469/* Enum values, see field(s): */
9470/* MC_CMD_FCNTL/MASK */
9471/* MAC address of the device. */
9472#define MC_CMD_MAC_STATE_OUT_ADDR_OFST 8
9473#define MC_CMD_MAC_STATE_OUT_ADDR_LEN 8
9474#define MC_CMD_MAC_STATE_OUT_ADDR_LO_OFST 8
9475#define MC_CMD_MAC_STATE_OUT_ADDR_LO_LEN 4
9476#define MC_CMD_MAC_STATE_OUT_ADDR_LO_LBN 64
9477#define MC_CMD_MAC_STATE_OUT_ADDR_LO_WIDTH 32
9478#define MC_CMD_MAC_STATE_OUT_ADDR_HI_OFST 12
9479#define MC_CMD_MAC_STATE_OUT_ADDR_HI_LEN 4
9480#define MC_CMD_MAC_STATE_OUT_ADDR_HI_LBN 96
9481#define MC_CMD_MAC_STATE_OUT_ADDR_HI_WIDTH 32
9482/* Flags indicating MAC faults. */
9483#define MC_CMD_MAC_STATE_OUT_MAC_FAULT_FLAGS_OFST 16
9484#define MC_CMD_MAC_STATE_OUT_MAC_FAULT_FLAGS_LEN 4
9485/* enum property: bitshift */
9486/* enum: Indicates a local MAC fault. */
9487#define MC_CMD_MAC_STATE_OUT_LOCAL 0x0
9488/* enum: Indicates a remote MAC fault. */
9489#define MC_CMD_MAC_STATE_OUT_REMOTE 0x1
9490/* enum: Indicates a pending reconfiguration of the MAC. */
9491#define MC_CMD_MAC_STATE_OUT_PENDING_RECONFIG 0x2
9492/* The flags that were used to configure the MAC. This is a copy of the FLAGS
9493 * field in the MC_CMD_MAC_CTRL_IN command.
9494 */
9495#define MC_CMD_MAC_STATE_OUT_FLAGS_OFST 20
9496#define MC_CMD_MAC_STATE_OUT_FLAGS_LEN 4
9497/* enum property: bitshift */
9498/* Enum values, see field(s): */
9499/* MC_CMD_MAC_FLAGS/MASK */
9500/* The transmission mode that was used to configure the MAC. This is a copy of
9501 * the TRANSMISSION_MODE field in the MC_CMD_MAC_CTRL_IN command.
9502 */
9503#define MC_CMD_MAC_STATE_OUT_TRANSMISSION_MODE_OFST 24
9504#define MC_CMD_MAC_STATE_OUT_TRANSMISSION_MODE_LEN 4
9505/* enum property: value */
9506/* Enum values, see field(s): */
9507/* MC_CMD_TRANSMISSION_MODE/MASK */
9508/* The control flags that were used to configure the MAC. This is a copy of the
9509 * CONTROL field in the MC_CMD_MAC_CTRL_IN command.
9510 */
9511#define MC_CMD_MAC_STATE_OUT_CONTROL_FLAGS_OFST 28
9512#define MC_CMD_MAC_STATE_OUT_CONTROL_FLAGS_LEN 4
9513/* enum property: bitshift */
9514/* Enum values, see field(s): */
9515/* MC_CMD_MAC_CONFIG_OPTIONS/MASK */
9516
9517
9518/***********************************/
9519/* MC_CMD_GET_ASSIGNED_PORT_HANDLE
9520 * Obtain a handle that can be operated on to configure and query the status of
9521 * the link. ENOENT is returned when no port is assigned to the client. Return
9522 * code: 0, ENOENT
9523 */
9524#define MC_CMD_GET_ASSIGNED_PORT_HANDLE 0x1e2
9525#undef MC_CMD_0x1e2_PRIVILEGE_CTG
9526
9527#define MC_CMD_0x1e2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9528
9529/* MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN msgrequest */
9530#define MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN_LEN 0
9531
9532/* MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT msgresponse */
9533#define MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_LEN 4
9534/* Handle for assigned port. */
9535#define MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE_OFST 0
9536#define MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE_LEN 4
9537
9538/* MC_CMD_STAT_ID structuredef */
9539#define MC_CMD_STAT_ID_LEN 4
9540#define MC_CMD_STAT_ID_SOURCE_ID_OFST 0
9541#define MC_CMD_STAT_ID_SOURCE_ID_LEN 2
9542/* enum property: index */
9543/* enum: Internal markers (generation start and end markers) */
9544#define MC_CMD_STAT_ID_MARKER 0x1
9545/* enum: Network port MAC statistics. */
9546#define MC_CMD_STAT_ID_MAC 0x2
9547/* enum: Network port PHY statistics. */
9548#define MC_CMD_STAT_ID_PHY 0x3
9549#define MC_CMD_STAT_ID_SOURCE_ID_LBN 0
9550#define MC_CMD_STAT_ID_SOURCE_ID_WIDTH 16
9551#define MC_CMD_STAT_ID_MARKER_STAT_ID_OFST 2
9552#define MC_CMD_STAT_ID_MARKER_STAT_ID_LEN 2
9553/* enum property: index */
9554/* enum: This value is used to mark the start of a generation of statistics for
9555 * DMA synchronization. It is incremented whenever a new set of statistics is
9556 * transferred. Always the first entry in the DMA buffer.
9557 */
9558#define MC_CMD_STAT_ID_GENERATION_START 0x1
9559/* enum: This value is used to mark the end of a generation of statistics for
9560 * DMA synchronizaion. Always the last entry in the DMA buffer and set to the
9561 * same value as GENERATION_START. The host driver must compare the
9562 * GENERATION_START and GENERATION_END values to verify that the DMA buffer is
9563 * consistent upon copying the the DMA buffer. If they do not match, it means
9564 * that new DMA transfer has started while the host driver was copying the DMA
9565 * buffer. In this case, the host driver must repeat the copy operation.
9566 */
9567#define MC_CMD_STAT_ID_GENERATION_END 0x2
9568#define MC_CMD_STAT_ID_MARKER_STAT_ID_LBN 16
9569#define MC_CMD_STAT_ID_MARKER_STAT_ID_WIDTH 16
9570#define MC_CMD_STAT_ID_MAC_STAT_ID_OFST 2
9571#define MC_CMD_STAT_ID_MAC_STAT_ID_LEN 2
9572/* enum property: index */
9573/* enum: Total number of packets transmitted (includes pause frames). */
9574#define MC_CMD_STAT_ID_TX_PKTS 0x1
9575/* enum: Pause frames transmitted. */
9576#define MC_CMD_STAT_ID_TX_PAUSE_PKTS 0x2
9577/* enum: Control frames transmitted. */
9578#define MC_CMD_STAT_ID_TX_CONTROL_PKTS 0x3
9579/* enum: Unicast packets transmitted (includes pause frames). */
9580#define MC_CMD_STAT_ID_TX_UNICAST_PKTS 0x4
9581/* enum: Multicast packets transmitted (includes pause frames). */
9582#define MC_CMD_STAT_ID_TX_MULTICAST_PKTS 0x5
9583/* enum: Broadcast packets transmitted (includes pause frames). */
9584#define MC_CMD_STAT_ID_TX_BROADCAST_PKTS 0x6
9585/* enum: Bytes transmitted (includes pause frames). */
9586#define MC_CMD_STAT_ID_TX_BYTES 0x7
9587/* enum: Bytes transmitted with bad CRC. */
9588#define MC_CMD_STAT_ID_TX_BAD_BYTES 0x8
9589/* enum: Bytes transmitted with good CRC. */
9590#define MC_CMD_STAT_ID_TX_GOOD_BYTES 0x9
9591/* enum: Packets transmitted with length less than 64 bytes. */
9592#define MC_CMD_STAT_ID_TX_LT64_PKTS 0xa
9593/* enum: Packets transmitted with length equal to 64 bytes. */
9594#define MC_CMD_STAT_ID_TX_64_PKTS 0xb
9595/* enum: Packets transmitted with length between 65 and 127 bytes. */
9596#define MC_CMD_STAT_ID_TX_65_TO_127_PKTS 0xc
9597/* enum: Packets transmitted with length between 128 and 255 bytes. */
9598#define MC_CMD_STAT_ID_TX_128_TO_255_PKTS 0xd
9599/* enum: Packets transmitted with length between 256 and 511 bytes. */
9600#define MC_CMD_STAT_ID_TX_256_TO_511_PKTS 0xe
9601/* enum: Packets transmitted with length between 512 and 1023 bytes. */
9602#define MC_CMD_STAT_ID_TX_512_TO_1023_PKTS 0xf
9603/* enum: Packets transmitted with length between 1024 and 1518 bytes. */
9604#define MC_CMD_STAT_ID_TX_1024_TO_15XX_PKTS 0x10
9605/* enum: Packets transmitted with length between 1519 and 9216 bytes. */
9606#define MC_CMD_STAT_ID_TX_15XX_TO_JUMBO_PKTS 0x11
9607/* enum: Packets transmitted with length greater than 9216 bytes. */
9608#define MC_CMD_STAT_ID_TX_GTJUMBO_PKTS 0x12
9609/* enum: Packets transmitted with bad FCS. */
9610#define MC_CMD_STAT_ID_TX_BAD_FCS_PKTS 0x13
9611/* enum: Packets transmitted with good FCS. */
9612#define MC_CMD_STAT_ID_TX_GOOD_FCS_PKTS 0x14
9613/* enum: Packets received. */
9614#define MC_CMD_STAT_ID_RX_PKTS 0x15
9615/* enum: Pause frames received. */
9616#define MC_CMD_STAT_ID_RX_PAUSE_PKTS 0x16
9617/* enum: Total number of good packets received. */
9618#define MC_CMD_STAT_ID_RX_GOOD_PKTS 0x17
9619/* enum: Total number of BAD packets received. */
9620#define MC_CMD_STAT_ID_RX_BAD_PKTS 0x18
9621/* enum: Total number of control frames received. */
9622#define MC_CMD_STAT_ID_RX_CONTROL_PKTS 0x19
9623/* enum: Total number of unicast packets received. */
9624#define MC_CMD_STAT_ID_RX_UNICAST_PKTS 0x1a
9625/* enum: Total number of multicast packets received. */
9626#define MC_CMD_STAT_ID_RX_MULTICAST_PKTS 0x1b
9627/* enum: Total number of broadcast packets received. */
9628#define MC_CMD_STAT_ID_RX_BROADCAST_PKTS 0x1c
9629/* enum: Total number of bytes received. */
9630#define MC_CMD_STAT_ID_RX_BYTES 0x1d
9631/* enum: Total number of bytes received with bad CRC. */
9632#define MC_CMD_STAT_ID_RX_BAD_BYTES 0x1e
9633/* enum: Total number of bytes received with GOOD CRC. */
9634#define MC_CMD_STAT_ID_RX_GOOD_BYTES 0x1f
9635/* enum: Packets received with length equal to 64 bytes. */
9636#define MC_CMD_STAT_ID_RX_64_PKTS 0x20
9637/* enum: Packets received with length between 65 and 127 bytes. */
9638#define MC_CMD_STAT_ID_RX_65_TO_127_PKTS 0x21
9639/* enum: Packets received with length between 128 and 255 bytes. */
9640#define MC_CMD_STAT_ID_RX_128_TO_255_PKTS 0x22
9641/* enum: Packets received with length between 256 and 511 bytes. */
9642#define MC_CMD_STAT_ID_RX_256_TO_511_PKTS 0x23
9643/* enum: Packets received with length between 512 and 1023 bytes. */
9644#define MC_CMD_STAT_ID_RX_512_TO_1023_PKTS 0x24
9645/* enum: Packets received with length between 1024 and 1518 bytes. */
9646#define MC_CMD_STAT_ID_RX_1024_TO_15XX_PKTS 0x25
9647/* enum: Packets received with length between 1519 and 9216 bytes. */
9648#define MC_CMD_STAT_ID_RX_15XX_TO_JUMBO_PKTS 0x26
9649/* enum: Packets received with length greater than 9216 bytes. */
9650#define MC_CMD_STAT_ID_RX_GTJUMBO_PKTS 0x27
9651/* enum: Packets received with length less than 64 bytes. */
9652#define MC_CMD_STAT_ID_RX_UNDERSIZE_PKTS 0x28
9653/* enum: Packets received with bad FCS. */
9654#define MC_CMD_STAT_ID_RX_BAD_FCS_PKTS 0x29
9655/* enum: Packets received with GOOD FCS. */
9656#define MC_CMD_STAT_ID_RX_GOOD_FCS_PKTS 0x2a
9657/* enum: Packets received with overflow. */
9658#define MC_CMD_STAT_ID_RX_OVERFLOW_PKTS 0x2b
9659/* enum: Packets received with symbol error. */
9660#define MC_CMD_STAT_ID_RX_SYMBOL_ERROR_PKTS 0x2c
9661/* enum: Packets received with alignment error. */
9662#define MC_CMD_STAT_ID_RX_ALIGN_ERROR_PKTS 0x2d
9663/* enum: Packets received with length error. */
9664#define MC_CMD_STAT_ID_RX_LENGTH_ERROR_PKTS 0x2e
9665/* enum: Packets received with internal error. */
9666#define MC_CMD_STAT_ID_RX_INTERNAL_ERROR_PKTS 0x2f
9667/* enum: Packets received with jabber. These packets are larger than the
9668 * allowed maximum receive unit (MRU). This indicates that a packet either has
9669 * a bad CRC or has an RX error.
9670 */
9671#define MC_CMD_STAT_ID_RX_JABBER_PKTS 0x30
9672/* enum: Packets dropped due to having no descriptor. This is a datapath stat
9673 */
9674#define MC_CMD_STAT_ID_RX_NODESC_DROPS 0x31
9675/* enum: Packets received with lanes 0 and 1 character error. */
9676#define MC_CMD_STAT_ID_RX_LANES01_CHAR_ERR 0x32
9677/* enum: Packets received with lanes 2 and 3 character error. */
9678#define MC_CMD_STAT_ID_RX_LANES23_CHAR_ERR 0x33
9679/* enum: Packets received with lanes 0 and 1 disparity error. */
9680#define MC_CMD_STAT_ID_RX_LANES01_DISP_ERR 0x34
9681/* enum: Packets received with lanes 2 and 3 disparity error. */
9682#define MC_CMD_STAT_ID_RX_LANES23_DISP_ERR 0x35
9683/* enum: Packets received with match fault. */
9684#define MC_CMD_STAT_ID_RX_MATCH_FAULT 0x36
9685#define MC_CMD_STAT_ID_MAC_STAT_ID_LBN 16
9686#define MC_CMD_STAT_ID_MAC_STAT_ID_WIDTH 16
9687/* Include FEC stats. */
9688#define MC_CMD_STAT_ID_PHY_STAT_ID_OFST 2
9689#define MC_CMD_STAT_ID_PHY_STAT_ID_LEN 2
9690/* enum property: index */
9691/* enum: Number of uncorrected FEC codewords on link (RS-FEC only from Medford2
9692 * onwards)
9693 */
9694#define MC_CMD_STAT_ID_FEC_UNCORRECTED_ERRORS 0x1
9695/* enum: Number of corrected FEC codewords on link (RS-FEC only from Medford2
9696 * onwards)
9697 */
9698#define MC_CMD_STAT_ID_FEC_CORRECTED_ERRORS 0x2
9699/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
9700#define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE0 0x3
9701/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
9702#define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE1 0x4
9703/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
9704#define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE2 0x5
9705/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
9706#define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE3 0x6
9707#define MC_CMD_STAT_ID_PHY_STAT_ID_LBN 16
9708#define MC_CMD_STAT_ID_PHY_STAT_ID_WIDTH 16
9709
9710/* MC_CMD_STAT_DESC structuredef: Structure describing the layout and size of
9711 * the stats DMA buffer descriptor.
9712 */
9713#define MC_CMD_STAT_DESC_LEN 8
9714/* Unique identifier of the statistic. Formatted as MC_CMD_STAT_ID */
9715#define MC_CMD_STAT_DESC_STAT_ID_OFST 0
9716#define MC_CMD_STAT_DESC_STAT_ID_LEN 4
9717#define MC_CMD_STAT_DESC_STAT_ID_LBN 0
9718#define MC_CMD_STAT_DESC_STAT_ID_WIDTH 32
9719/* See structuredef: MC_CMD_STAT_ID */
9720#define MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_OFST 0
9721#define MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_LEN 2
9722#define MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_LBN 0
9723#define MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_WIDTH 16
9724#define MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_OFST 2
9725#define MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_LEN 2
9726#define MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_LBN 16
9727#define MC_CMD_STAT_DESC_STAT_ID_MARKER_STAT_ID_WIDTH 16
9728#define MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_OFST 2
9729#define MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_LEN 2
9730#define MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_LBN 16
9731#define MC_CMD_STAT_DESC_STAT_ID_MAC_STAT_ID_WIDTH 16
9732#define MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_OFST 2
9733#define MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_LEN 2
9734#define MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_LBN 16
9735#define MC_CMD_STAT_DESC_STAT_ID_PHY_STAT_ID_WIDTH 16
9736/* Index of the statistic in the DMA buffer. */
9737#define MC_CMD_STAT_DESC_STAT_INDEX_OFST 4
9738#define MC_CMD_STAT_DESC_STAT_INDEX_LEN 2
9739#define MC_CMD_STAT_DESC_STAT_INDEX_LBN 32
9740#define MC_CMD_STAT_DESC_STAT_INDEX_WIDTH 16
9741/* Reserved for future extension (e.g. flags field) - currently always 0. */
9742#define MC_CMD_STAT_DESC_RESERVED_OFST 6
9743#define MC_CMD_STAT_DESC_RESERVED_LEN 2
9744#define MC_CMD_STAT_DESC_RESERVED_LBN 48
9745#define MC_CMD_STAT_DESC_RESERVED_WIDTH 16
9746
9747
9748/***********************************/
9749/* MC_CMD_MAC_STATISTICS_DESCRIPTOR
9750 * Get a list of descriptors that describe the layout and size of the stats
9751 * buffer required for retrieving statistics for a given port. Each entry in
9752 * the list is formatted as MC_CMD_STAT_DESC and provides the ID of each stat
9753 * and its location and size in the buffer. It also gives the overall minimum
9754 * size of the DMA buffer required when DMA mode is used. Note that the first
9755 * and last entries in the list are reserved for the generation start
9756 * (MC_CMD_MARKER_STAT_GENERATION_START) and end
9757 * (MC_CMD_MARKER_STAT_GENERATION_END) markers respectively, to be used for DMA
9758 * synchronisation as described in the documentation for the relevant enum
9759 * entries. The entries are present in the buffer even if DMA mode is not used.
9760 * Provisions are made (but currently unused) for extending the size of the
9761 * descriptors, extending the size of the list beyond the maximum MCDI response
9762 * size, as well as the dynamic runtime updates of the list. Returns: 0 on
9763 * success, ENOENT on non-existent port handle
9764 */
9765#define MC_CMD_MAC_STATISTICS_DESCRIPTOR 0x1e3
9766#undef MC_CMD_0x1e3_PRIVILEGE_CTG
9767
9768#define MC_CMD_0x1e3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9769
9770/* MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN msgrequest */
9771#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_LEN 8
9772/* Handle of port to get MAC statitstics descriptors for. */
9773#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE_OFST 0
9774#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE_LEN 4
9775/* Offset of the first entry to return, for cases where not all entries fit in
9776 * the MCDI response. Should be set to 0 on initial request, and on subsequent
9777 * requests updated by the number of entries already returned, as long as the
9778 * MORE_ENTRIES flag is set.
9779 */
9780#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_OFFSET_OFST 4
9781#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_OFFSET_LEN 4
9782
9783/* MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT msgresponse */
9784#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMIN 28
9785#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX 252
9786#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LENMAX_MCDI2 1020
9787#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_LEN(num) (20+8*(num))
9788#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_NUM(len) (((len)-20)/8)
9789/* Generation number of the stats buffer. This is incremented each time the
9790 * buffer is updated, and is used to verify the consistency of the buffer
9791 * contents. Reserved for future extension (dynamic list updates). Currently
9792 * always set to 0.
9793 */
9794#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_GENERATION_OFST 0
9795#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_GENERATION_LEN 4
9796/* Minimum size of the DMA buffer required to retrieve all statistics for the
9797 * port. This is the sum of the sizes of all the statistics, plus the size of
9798 * the generation markers. Minimum buffer size in bytes required to fit all
9799 * statistics. Drivers will typically round up this value to the granularity of
9800 * the host DMA allocation units.
9801 */
9802#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE_OFST 4
9803#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE_LEN 4
9804#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_FLAGS_OFST 8
9805#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_FLAGS_LEN 4
9806#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_OFST 8
9807#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_LBN 0
9808#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_WIDTH 1
9809/* Size of the individual descriptor entry in the list. Determines the entry
9810 * stride in the list. Currently always set to size of MC_CMD_STAT_DESC, larger
9811 * values can be used in the future for extending the descriptor, by appending
9812 * new data to the end of the existing structure.
9813 */
9814#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_SIZE_OFST 12
9815#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_SIZE_LEN 4
9816/* Number of entries returned in the descriptor list. */
9817#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_COUNT_OFST 16
9818#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_COUNT_LEN 4
9819/* List of descriptors. Each entry is formatted as MC_CMD_STAT_DESC and
9820 * provides the ID of each stat and its location and size in the buffer. The
9821 * first and last entries are reserved for the generation start and end markers
9822 * respectively.
9823 */
9824#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_OFST 20
9825#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LEN 8
9826#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_OFST 20
9827#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_LEN 4
9828#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_LBN 160
9829#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_WIDTH 32
9830#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_OFST 24
9831#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_LEN 4
9832#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_LBN 192
9833#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_WIDTH 32
9834#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MINNUM 1
9835#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MAXNUM 29
9836#define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_MAXNUM_MCDI2 125
9837
9838
9839/***********************************/
9840/* MC_CMD_MAC_STATISTICS
9841 * Get generic MAC statistics. This call retrieves unified statistics managed
9842 * by the MC. The MC will populate and provide all supported statistics in the
9843 * format as returned by MC_CMD_MAC_STATISTICS_DESCRIPTOR. Refer to the
9844 * aforementioned command for the format and contents of the stats DMA buffer.
9845 * To ensure consistent and accurate results, it is essential for the driver to
9846 * initialize the DMA buffer with zeros when DMA mode is used. Returns: 0 on
9847 * success, ETIME if the DMA buffer is not ready, ENOENT on non-existent port
9848 * handle, and EINVAL on invalid parameters (DMA buffer too small)
9849 */
9850#define MC_CMD_MAC_STATISTICS 0x1e4
9851#undef MC_CMD_0x1e4_PRIVILEGE_CTG
9852
9853#define MC_CMD_0x1e4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9854
9855/* MC_CMD_MAC_STATISTICS_IN msgrequest */
9856#define MC_CMD_MAC_STATISTICS_IN_LEN 20
9857/* Handle of port to get MAC statistics for. */
9858#define MC_CMD_MAC_STATISTICS_IN_PORT_HANDLE_OFST 0
9859#define MC_CMD_MAC_STATISTICS_IN_PORT_HANDLE_LEN 4
9860/* Contains options for querying the MAC statistics. */
9861#define MC_CMD_MAC_STATISTICS_IN_CMD_OFST 4
9862#define MC_CMD_MAC_STATISTICS_IN_CMD_LEN 4
9863#define MC_CMD_MAC_STATISTICS_IN_DMA_OFST 4
9864#define MC_CMD_MAC_STATISTICS_IN_DMA_LBN 0
9865#define MC_CMD_MAC_STATISTICS_IN_DMA_WIDTH 1
9866#define MC_CMD_MAC_STATISTICS_IN_CLEAR_OFST 4
9867#define MC_CMD_MAC_STATISTICS_IN_CLEAR_LBN 1
9868#define MC_CMD_MAC_STATISTICS_IN_CLEAR_WIDTH 1
9869#define MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_OFST 4
9870#define MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_LBN 2
9871#define MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_WIDTH 1
9872#define MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_OFST 4
9873#define MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_LBN 3
9874#define MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_WIDTH 1
9875#define MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_OFST 4
9876#define MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_LBN 4
9877#define MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_WIDTH 1
9878#define MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_OFST 4
9879#define MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_LBN 16
9880#define MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_WIDTH 16
9881/* This is the address of the DMA buffer to use for transfer of the statistics.
9882 * Only valid if the DMA flag is set to 1.
9883 */
9884#define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_OFST 8
9885#define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LEN 8
9886#define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_OFST 8
9887#define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_LEN 4
9888#define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_LBN 64
9889#define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_WIDTH 32
9890#define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_OFST 12
9891#define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_LEN 4
9892#define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_LBN 96
9893#define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_WIDTH 32
9894/* This is the length of the DMA buffer to use for the transfer of the
9895 * statistics. The buffer should be at least DMA_BUFFER_SIZE long, as returned
9896 * by MC_CMD_MAC_STATISTICS_DESCRIPTOR. If the supplied buffer is too small,
9897 * the command will fail with EINVAL. Only valid if the DMA flag is set to 1.
9898 */
9899#define MC_CMD_MAC_STATISTICS_IN_DMA_LEN_OFST 16
9900#define MC_CMD_MAC_STATISTICS_IN_DMA_LEN_LEN 4
9901
9902/* MC_CMD_MAC_STATISTICS_OUT msgresponse */
9903#define MC_CMD_MAC_STATISTICS_OUT_LENMIN 5
9904#define MC_CMD_MAC_STATISTICS_OUT_LENMAX 252
9905#define MC_CMD_MAC_STATISTICS_OUT_LENMAX_MCDI2 1020
9906#define MC_CMD_MAC_STATISTICS_OUT_LEN(num) (4+1*(num))
9907#define MC_CMD_MAC_STATISTICS_OUT_DATA_NUM(len) (((len)-4)/1)
9908/* length of the data in bytes */
9909#define MC_CMD_MAC_STATISTICS_OUT_DATALEN_OFST 0
9910#define MC_CMD_MAC_STATISTICS_OUT_DATALEN_LEN 4
9911#define MC_CMD_MAC_STATISTICS_OUT_DATA_OFST 4
9912#define MC_CMD_MAC_STATISTICS_OUT_DATA_LEN 1
9913#define MC_CMD_MAC_STATISTICS_OUT_DATA_MINNUM 1
9914#define MC_CMD_MAC_STATISTICS_OUT_DATA_MAXNUM 248
9915#define MC_CMD_MAC_STATISTICS_OUT_DATA_MAXNUM_MCDI2 1016
9916
9917/* NET_PORT_HANDLE_DESC structuredef: Network port descriptor containing a port
9918 * handle and attributes used, for example, in MC_CMD_ENUM_PORTS.
9919 */
9920#define NET_PORT_HANDLE_DESC_LEN 53
9921/* The handle to identify the port */
9922#define NET_PORT_HANDLE_DESC_PORT_HANDLE_OFST 0
9923#define NET_PORT_HANDLE_DESC_PORT_HANDLE_LEN 4
9924#define NET_PORT_HANDLE_DESC_PORT_HANDLE_LBN 0
9925#define NET_PORT_HANDLE_DESC_PORT_HANDLE_WIDTH 32
9926/* Includes the type of port e.g. physical, virtual or MAE MPORT and other
9927 * properties relevant to the port.
9928 */
9929#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_OFST 4
9930#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LEN 8
9931#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_OFST 4
9932#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_LEN 4
9933#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_LBN 32
9934#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_WIDTH 32
9935#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_OFST 8
9936#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_LEN 4
9937#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_LBN 64
9938#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_WIDTH 32
9939#define NET_PORT_HANDLE_DESC_PORT_TYPE_OFST 4
9940#define NET_PORT_HANDLE_DESC_PORT_TYPE_LBN 0
9941#define NET_PORT_HANDLE_DESC_PORT_TYPE_WIDTH 3
9942#define NET_PORT_HANDLE_DESC_PHYSICAL 0x0 /* enum */
9943#define NET_PORT_HANDLE_DESC_VIRTUAL 0x1 /* enum */
9944#define NET_PORT_HANDLE_DESC_MPORT 0x2 /* enum */
9945#define NET_PORT_HANDLE_DESC_IS_ZOMBIE_OFST 4
9946#define NET_PORT_HANDLE_DESC_IS_ZOMBIE_LBN 8
9947#define NET_PORT_HANDLE_DESC_IS_ZOMBIE_WIDTH 1
9948#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LBN 32
9949#define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_WIDTH 64
9950/* The dynamic change that led to the port enumeration */
9951#define NET_PORT_HANDLE_DESC_ENTRY_SRC_OFST 12
9952#define NET_PORT_HANDLE_DESC_ENTRY_SRC_LEN 1
9953/* enum: Indicates that the ENTRY_SRC field has not been initialized. */
9954#define NET_PORT_HANDLE_DESC_UNKNOWN 0x0
9955/* enum: The port was enumerated at start of day. */
9956#define NET_PORT_HANDLE_DESC_PRESENT 0x1
9957/* enum: The port was dynamically added. */
9958#define NET_PORT_HANDLE_DESC_ADDED 0x2
9959/* enum: The port was dynamically deleted. */
9960#define NET_PORT_HANDLE_DESC_DELETED 0x3
9961#define NET_PORT_HANDLE_DESC_ENTRY_SRC_LBN 96
9962#define NET_PORT_HANDLE_DESC_ENTRY_SRC_WIDTH 8
9963/* This is an opaque 40 byte label exposed to users as a unique identifier of
9964 * the port. It is represented as a zero-terminated ASCII string and assigned
9965 * by the port administrator which is typically either the firmware for a
9966 * physical port or the host software responsible for creating the virtual
9967 * port. The label is conveyed to the driver after assignment, which, unlike
9968 * the port administrator, does not need to know how to interpret the label.
9969 */
9970#define NET_PORT_HANDLE_DESC_PORT_LABEL_OFST 13
9971#define NET_PORT_HANDLE_DESC_PORT_LABEL_LEN 40
9972#define NET_PORT_HANDLE_DESC_PORT_LABEL_LBN 104
9973#define NET_PORT_HANDLE_DESC_PORT_LABEL_WIDTH 320
9974
9975
9976/***********************************/
9977/* MC_CMD_ENUM_PORTS
9978 * This command returns handles for all ports present in the system. The PCIe
9979 * function type of each port (either physical or virtual) is also reported.
9980 * After a start-of-day port enumeration, firmware keeps track of all available
9981 * ports upon creation or deletion and updates the ports if there is a change.
9982 * This command is cleared after a control interface reset (e.g. FLR,
9983 * ENTITY_RESET), in which case it must be called again to reenumerate the
9984 * ports. The command is also clear-on-read and repeated calls will drain the
9985 * buffer.
9986 */
9987#define MC_CMD_ENUM_PORTS 0x1e5
9988#undef MC_CMD_0x1e5_PRIVILEGE_CTG
9989
9990#define MC_CMD_0x1e5_PRIVILEGE_CTG SRIOV_CTG_LINK
9991
9992/* MC_CMD_ENUM_PORTS_IN msgrequest */
9993#define MC_CMD_ENUM_PORTS_IN_LEN 0
9994
9995/* MC_CMD_ENUM_PORTS_OUT msgresponse */
9996#define MC_CMD_ENUM_PORTS_OUT_LENMIN 12
9997#define MC_CMD_ENUM_PORTS_OUT_LENMAX 252
9998#define MC_CMD_ENUM_PORTS_OUT_LENMAX_MCDI2 1020
9999#define MC_CMD_ENUM_PORTS_OUT_LEN(num) (12+1*(num))
10000#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_NUM(len) (((len)-12)/1)
10001/* Any unused flags are reserved and must be ignored. */
10002#define MC_CMD_ENUM_PORTS_OUT_FLAGS_OFST 0
10003#define MC_CMD_ENUM_PORTS_OUT_FLAGS_LEN 4
10004#define MC_CMD_ENUM_PORTS_OUT_MORE_OFST 0
10005#define MC_CMD_ENUM_PORTS_OUT_MORE_LBN 0
10006#define MC_CMD_ENUM_PORTS_OUT_MORE_WIDTH 1
10007/* The number of NET_PORT_HANDLE_DESC structures in PORT_HANDLES. */
10008#define MC_CMD_ENUM_PORTS_OUT_PORT_COUNT_OFST 4
10009#define MC_CMD_ENUM_PORTS_OUT_PORT_COUNT_LEN 4
10010#define MC_CMD_ENUM_PORTS_OUT_SIZEOF_NET_PORT_HANDLE_DESC_OFST 8
10011#define MC_CMD_ENUM_PORTS_OUT_SIZEOF_NET_PORT_HANDLE_DESC_LEN 4
10012/* Array of NET_PORT_HANDLE_DESC structures. Callers must use must use the
10013 * SIZEOF_NET_PORT_HANDLE_DESC field field as the array stride between entries.
10014 * This may also allow for tail padding for alignment. Fields beyond
10015 * SIZEOF_NET_PORT_HANDLE_DESC are not present.
10016 */
10017#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_OFST 12
10018#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_LEN 1
10019#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MINNUM 0
10020#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MAXNUM 240
10021#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MAXNUM_MCDI2 1008
10022/* See structuredef: NET_PORT_HANDLE_DESC */
10023#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_HANDLE_OFST 12
10024#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_HANDLE_LEN 4
10025#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_OFST 16
10026#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LEN 8
10027#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_OFST 16
10028#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_LEN 4
10029#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_LBN 128
10030#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_WIDTH 32
10031#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_OFST 20
10032#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_LEN 4
10033#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_LBN 160
10034#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_WIDTH 32
10035#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_TYPE_LBN 128
10036#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_TYPE_WIDTH 3
10037#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_IS_ZOMBIE_LBN 136
10038#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_IS_ZOMBIE_WIDTH 1
10039#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_ENTRY_SRC_OFST 24
10040#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_ENTRY_SRC_LEN 1
10041#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_LABEL_OFST 25
10042#define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_LABEL_LEN 40
10043
10044
10045/***********************************/
10046/* MC_CMD_GET_TRANSCEIVER_PROPERTIES
10047 * Read properties of the transceiver associated with the port. Can be either
10048 * for a fixed onboard transceiver or an inserted module. The returned data is
10049 * interpreted from the transceiver hardware and may be fixed up by the
10050 * firmware. Use MC_CMD_GET_MODULE_DATA to get raw undecoded data.
10051 */
10052#define MC_CMD_GET_TRANSCEIVER_PROPERTIES 0x1e6
10053#undef MC_CMD_0x1e6_PRIVILEGE_CTG
10054
10055#define MC_CMD_0x1e6_PRIVILEGE_CTG SRIOV_CTG_LINK
10056
10057/* MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN msgrequest */
10058#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_LEN 4
10059/* Handle to port to get transceiver properties from. */
10060#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_PORT_HANDLE_OFST 0
10061#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_PORT_HANDLE_LEN 4
10062
10063/* MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT msgresponse */
10064#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LEN 89
10065/* Supported technology abilities. */
10066#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_TECH_ABILITIES_MASK_OFST 0
10067#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_TECH_ABILITIES_MASK_LEN 16
10068/* enum property: bitshift */
10069/* Enum values, see field(s): */
10070/* MC_CMD_ETH_TECH/TECH */
10071/* Reserved for future expansion to accommodate future Ethernet technology
10072 * expansion.
10073 */
10074#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_RESERVED_OFST 16
10075#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_RESERVED_LEN 16
10076/* Preferred FEC modes. This is a function of the cable type and length. */
10077#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PREFERRED_FEC_MASK_OFST 32
10078#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PREFERRED_FEC_MASK_LEN 4
10079/* enum property: bitshift */
10080/* Enum values, see field(s): */
10081/* FEC_TYPE/TYPE */
10082/* SFF-8042 code reported by the module. */
10083#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CODE_OFST 36
10084#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CODE_LEN 2
10085/* Medium. */
10086#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIUM_OFST 38
10087#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIUM_LEN 1
10088/* enum property: value */
10089#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_UNKNOWN 0x0 /* enum */
10090#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_COPPER 0x1 /* enum */
10091#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_OPTICAL 0x2 /* enum */
10092#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BACKPLANE 0x3 /* enum */
10093/* Identifies the tech */
10094#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIA_SUBTYPE_OFST 39
10095#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_MEDIA_SUBTYPE_LEN 1
10096/* enum property: value */
10097/* MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_UNKNOWN 0x0 */
10098/* enum: Ethernet over twisted-pair copper cables for distances up to 100
10099 * meters.
10100 */
10101#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BASET 0x1
10102/* enum: Ethernet over twin-axial, balanced copper cable. */
10103#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CR 0x2
10104/* enum: Ethernet over backplane for connections on the same board. */
10105#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KX 0x3
10106/* enum: Ethernet over a single backplane lane for connections between
10107 * different boards.
10108 */
10109#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KR 0x4
10110/* enum: Ethernet over copper backplane. */
10111#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KP 0x5
10112/* enum: Ethernet over fiber optic. */
10113#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BASEX 0x6
10114/* enum: Short range ethernet over multimode fiber optic (See IEEE 802.3 Clause
10115 * 49 and 52).
10116 */
10117#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SR 0x7
10118/* enum: Long range, extended range or far reach ethernet used with single mode
10119 * fiber optics.
10120 */
10121#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LR_ER_FR 0x8
10122/* enum: Long reach multimode ethernet over multimode optical fiber. */
10123#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LRM 0x9
10124/* enum: Very short reach PAM4 ethernet over multimode optical fiber (see IEEE
10125 * 802.3db).
10126 */
10127#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VR 0xa
10128/* enum: BASE-R encoding and PAM4 over single-mode fiber with reach up to at
10129 * least 500 meters (803.2 Clause 121 and 124)
10130 */
10131#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_DR 0xb
10132/* String of the vendor name as intepreted by NMC firmware. NMC firmware
10133 * applies workarounds for known buggy transceivers. The vendor name is
10134 * presented as 16 bytes of ASCII characters padded with spaces. It can also be
10135 * represented as 16 bytes of zeros if the field is unspecified for the
10136 * connected module. See SFF-8472/CMIS specifications for details.
10137 */
10138#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_OFST 40
10139#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_LEN 1
10140#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_NAME_NUM 16
10141/* The vendor part number as intepreted by NMC firmware. The field is presented
10142 * as 16 bytes of ASCII chars padded with spaces. It can also be 16 bytes of
10143 * zeros if the field is unspecified for the connected module.
10144 */
10145#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_OFST 56
10146#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_LEN 1
10147#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VENDOR_PN_NUM 16
10148/* Serial number of the module presented as 16 bytes of ASCII characters padded
10149 * with spaces. It can also be 16 bytes of zeros if the field is unspecified
10150 * for the connected module. See SFF-8472/CMIS specifications for details.
10151 */
10152#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_OFST 72
10153#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_LEN 1
10154#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SERIAL_NUMBER_NUM 16
10155/* This reports the number of module changes detected by the NMC firmware. */
10156#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PORT_MODULECHANGE_SEQ_NUM_OFST 88
10157#define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PORT_MODULECHANGE_SEQ_NUM_LEN 1
10158
10159
10160/***********************************/
10161/* MC_CMD_GET_FIXED_PORT_PROPERTIES
10162 */
10163#define MC_CMD_GET_FIXED_PORT_PROPERTIES 0x1e7
10164#undef MC_CMD_0x1e7_PRIVILEGE_CTG
10165
10166#define MC_CMD_0x1e7_PRIVILEGE_CTG SRIOV_CTG_LINK
10167
10168/* MC_CMD_GET_FIXED_PORT_PROPERTIES_IN msgrequest: In this context, the port
10169 * consists of the MAC and the PHY, and excludes any modules inserted into the
10170 * cage. This information is fixed for a given board but not for a given ASIC.
10171 * This command reports properties for the port as it is currently configured,
10172 * and not its hardware capabilities, which can be better than the current
10173 * configuration.
10174 */
10175#define MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_LEN 4
10176/* Handle to the port to from which to retreive properties */
10177#define MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE_OFST 0
10178#define MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE_LEN 4
10179
10180/* MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT msgresponse */
10181#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LEN 36
10182/* Supported capabilities of the port in its current configuration. */
10183#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_OFST 0
10184#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_LEN 25
10185/* See structuredef: MC_CMD_ETH_AN_FIELDS */
10186#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_TECH_MASK_OFST 0
10187#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_TECH_MASK_LEN 16
10188#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_MASK_OFST 16
10189#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_MASK_LEN 4
10190#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_REQ_OFST 20
10191#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_REQ_LEN 4
10192#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_PAUSE_MASK_OFST 24
10193#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_PAUSE_MASK_LEN 1
10194/* Number of lanes supported by the port in its current configuration. */
10195#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_NUM_LANES_OFST 25
10196#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_NUM_LANES_LEN 1
10197/* Bitmask of supported loopback modes. Where the response to this command
10198 * includes the LOOPBACK_MODES_MASK_V2 field, that field should be used in
10199 * preference to ensure that all available loopback modes are seen.
10200 */
10201#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LOOPBACK_MODES_MASK_OFST 26
10202#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_LOOPBACK_MODES_MASK_LEN 1
10203/* enum property: bitshift */
10204/* Enum values, see field(s): */
10205/* MC_CMD_LOOPBACK_V2/MODE */
10206/* This field serves as a cage index that uniquely identifies the cage to which
10207 * the module is connected. This is useful when splitter cables that have
10208 * multiple ports on a single cage are used.
10209 */
10210#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_INDEX_OFST 27
10211#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_INDEX_LEN 1
10212/* This bitmask is used to specify the lanes within the cage identified by
10213 * MDI_INDEX that are allocated to the port.
10214 */
10215#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_LANE_MASK_OFST 28
10216#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MDI_LANE_MASK_LEN 1
10217/* Maximum frame length supported by the port in its current configuration. */
10218#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MAX_FRAME_LEN_OFST 32
10219#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MAX_FRAME_LEN_LEN 4
10220
10221/* MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2 msgresponse */
10222#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LEN 48
10223/* Supported capabilities of the port in its current configuration. */
10224#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_ABILITIES_OFST 0
10225#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_ABILITIES_LEN 25
10226/* Number of lanes supported by the port in its current configuration. */
10227#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_NUM_LANES_OFST 25
10228#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_NUM_LANES_LEN 1
10229/* Bitmask of supported loopback modes. Where the response to this command
10230 * includes the LOOPBACK_MODES_MASK_V2 field, that field should be used in
10231 * preference to ensure that all available loopback modes are seen.
10232 */
10233#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_OFST 26
10234#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_LEN 1
10235/* enum property: bitshift */
10236/* Enum values, see field(s): */
10237/* MC_CMD_LOOPBACK_V2/MODE */
10238/* This field serves as a cage index that uniquely identifies the cage to which
10239 * the module is connected. This is useful when splitter cables that have
10240 * multiple ports on a single cage are used.
10241 */
10242#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_INDEX_OFST 27
10243#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_INDEX_LEN 1
10244/* This bitmask is used to specify the lanes within the cage identified by
10245 * MDI_INDEX that are allocated to the port.
10246 */
10247#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_LANE_MASK_OFST 28
10248#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MDI_LANE_MASK_LEN 1
10249/* Maximum frame length supported by the port in its current configuration. */
10250#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MAX_FRAME_LEN_OFST 32
10251#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MAX_FRAME_LEN_LEN 4
10252/* Bitmask of supported loopback modes. This field replaces the
10253 * LOOPBACK_MODES_MASK field which is defined under version 1 of this command.
10254 */
10255#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_OFST 40
10256#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LEN 8
10257#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_OFST 40
10258#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_LEN 4
10259#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_LBN 320
10260#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_WIDTH 32
10261#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_OFST 44
10262#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_LEN 4
10263#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_LBN 352
10264#define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_WIDTH 32
10265/* enum property: bitshift */
10266/* Enum values, see field(s): */
10267/* MC_CMD_LOOPBACK_V2/MODE */
10268
10269
10270/***********************************/
10271/* MC_CMD_GET_MODULE_DATA
10272 * Read media-specific data from the PHY (e.g. SFP/SFP+ module ID information
10273 * for SFP+ PHYs). This command returns raw data from the module's EEPROM and
10274 * it is not interpreted by the MC. Use MC_CMD_GET_TRANSCEIVER_PROPERTIES to
10275 * get interpreted data. Return code: 0, ENOENT
10276 */
10277#define MC_CMD_GET_MODULE_DATA 0x1e8
10278#undef MC_CMD_0x1e8_PRIVILEGE_CTG
10279
10280#define MC_CMD_0x1e8_PRIVILEGE_CTG SRIOV_CTG_LINK
10281
10282/* MC_CMD_GET_MODULE_DATA_IN msgrequest */
10283#define MC_CMD_GET_MODULE_DATA_IN_LEN 16
10284/* Handle to identify the port from which to request module properties. */
10285#define MC_CMD_GET_MODULE_DATA_IN_PORT_HANDLE_OFST 0
10286#define MC_CMD_GET_MODULE_DATA_IN_PORT_HANDLE_LEN 4
10287/* 7 bit I2C address of the device. DEPRECATED: This field is replaced by
10288 * MODULE_ADDR in V2. Use V2 of this command for proper alignment and easier
10289 * access.
10290 */
10291#define MC_CMD_GET_MODULE_DATA_IN_DEVADDR_LBN 32
10292#define MC_CMD_GET_MODULE_DATA_IN_DEVADDR_WIDTH 7
10293/* 0 if the page does not support banked access, non-zero otherwise. Non-zero
10294 * BANK is valid if OFFSET is in the range 80h - ffh, i.e. in the Upper Memory
10295 * region.
10296 */
10297#define MC_CMD_GET_MODULE_DATA_IN_BANK_OFST 6
10298#define MC_CMD_GET_MODULE_DATA_IN_BANK_LEN 2
10299/* 0 if paged access is not supported, non-zero otherwise. Non-zero PAGE is
10300 * valid if OFFSET is in the range 80h - ffh.
10301 */
10302#define MC_CMD_GET_MODULE_DATA_IN_PAGE_OFST 8
10303#define MC_CMD_GET_MODULE_DATA_IN_PAGE_LEN 2
10304/* Offset in the range 00h - 7fh to access lower memory. Offset in the range
10305 * 80h - ffh to access upper memory
10306 */
10307#define MC_CMD_GET_MODULE_DATA_IN_OFFSET_OFST 10
10308#define MC_CMD_GET_MODULE_DATA_IN_OFFSET_LEN 1
10309#define MC_CMD_GET_MODULE_DATA_IN_LENGTH_OFST 12
10310#define MC_CMD_GET_MODULE_DATA_IN_LENGTH_LEN 4
10311
10312/* MC_CMD_GET_MODULE_DATA_IN_V2 msgrequest: Updated MC_CMD_GET_MODULE_DATA with
10313 * 8-bit wide ADDRESSING field. This new field provides a correctly aligned
10314 * container for the 7-bit DEVADDR field from V1, now renamed MODULE_ADDR, to
10315 * ensure proper alignment.
10316 */
10317#define MC_CMD_GET_MODULE_DATA_IN_V2_LEN 16
10318/* Handle to identify the port from which to request module properties. */
10319#define MC_CMD_GET_MODULE_DATA_IN_V2_PORT_HANDLE_OFST 0
10320#define MC_CMD_GET_MODULE_DATA_IN_V2_PORT_HANDLE_LEN 4
10321/* 7 bit I2C address of the device. DEPRECATED: This field is replaced by
10322 * MODULE_ADDR in V2. Use V2 of this command for proper alignment and easier
10323 * access.
10324 */
10325#define MC_CMD_GET_MODULE_DATA_IN_V2_DEVADDR_LBN 32
10326#define MC_CMD_GET_MODULE_DATA_IN_V2_DEVADDR_WIDTH 7
10327/* 0 if the page does not support banked access, non-zero otherwise. Non-zero
10328 * BANK is valid if OFFSET is in the range 80h - ffh, i.e. in the Upper Memory
10329 * region.
10330 */
10331#define MC_CMD_GET_MODULE_DATA_IN_V2_BANK_OFST 6
10332#define MC_CMD_GET_MODULE_DATA_IN_V2_BANK_LEN 2
10333/* 0 if paged access is not supported, non-zero otherwise. Non-zero PAGE is
10334 * valid if OFFSET is in the range 80h - ffh.
10335 */
10336#define MC_CMD_GET_MODULE_DATA_IN_V2_PAGE_OFST 8
10337#define MC_CMD_GET_MODULE_DATA_IN_V2_PAGE_LEN 2
10338/* Offset in the range 00h - 7fh to access lower memory. Offset in the range
10339 * 80h - ffh to access upper memory
10340 */
10341#define MC_CMD_GET_MODULE_DATA_IN_V2_OFFSET_OFST 10
10342#define MC_CMD_GET_MODULE_DATA_IN_V2_OFFSET_LEN 1
10343#define MC_CMD_GET_MODULE_DATA_IN_V2_LENGTH_OFST 12
10344#define MC_CMD_GET_MODULE_DATA_IN_V2_LENGTH_LEN 4
10345/* Container for 7 bit I2C addresses. */
10346#define MC_CMD_GET_MODULE_DATA_IN_V2_ADDRESSING_OFST 4
10347#define MC_CMD_GET_MODULE_DATA_IN_V2_ADDRESSING_LEN 1
10348#define MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_OFST 4
10349#define MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_LBN 0
10350#define MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_WIDTH 7
10351
10352/* MC_CMD_GET_MODULE_DATA_OUT msgresponse */
10353#define MC_CMD_GET_MODULE_DATA_OUT_LENMIN 5
10354#define MC_CMD_GET_MODULE_DATA_OUT_LENMAX 252
10355#define MC_CMD_GET_MODULE_DATA_OUT_LENMAX_MCDI2 1020
10356#define MC_CMD_GET_MODULE_DATA_OUT_LEN(num) (4+1*(num))
10357#define MC_CMD_GET_MODULE_DATA_OUT_DATA_NUM(len) (((len)-4)/1)
10358/* length of the data in bytes */
10359#define MC_CMD_GET_MODULE_DATA_OUT_DATALEN_OFST 0
10360#define MC_CMD_GET_MODULE_DATA_OUT_DATALEN_LEN 4
10361#define MC_CMD_GET_MODULE_DATA_OUT_DATA_OFST 4
10362#define MC_CMD_GET_MODULE_DATA_OUT_DATA_LEN 1
10363#define MC_CMD_GET_MODULE_DATA_OUT_DATA_MINNUM 1
10364#define MC_CMD_GET_MODULE_DATA_OUT_DATA_MAXNUM 248
10365#define MC_CMD_GET_MODULE_DATA_OUT_DATA_MAXNUM_MCDI2 1016
10366
10367/* EVENT_MASK structuredef */
10368#define EVENT_MASK_LEN 4
10369#define EVENT_MASK_TYPE_OFST 0
10370#define EVENT_MASK_TYPE_LEN 4
10371/* enum: PORT_LINKCHANGE event is enabled */
10372#define EVENT_MASK_PORT_LINKCHANGE 0x0
10373/* enum: PORT_MODULECHANGE event is enabled */
10374#define EVENT_MASK_PORT_MODULECHANGE 0x1
10375#define EVENT_MASK_TYPE_LBN 0
10376#define EVENT_MASK_TYPE_WIDTH 32
10377
10378
10379/***********************************/
10380/* MC_CMD_SET_NETPORT_EVENTS_MASK
10381 */
10382#define MC_CMD_SET_NETPORT_EVENTS_MASK 0x1e9
10383#undef MC_CMD_0x1e9_PRIVILEGE_CTG
10384
10385#define MC_CMD_0x1e9_PRIVILEGE_CTG SRIOV_CTG_LINK
10386
10387/* MC_CMD_SET_NETPORT_EVENTS_MASK_IN msgrequest: Enable or disable delivery of
10388 * specified network port events for a given port identified by PORT_HANDLE. At
10389 * start of day, or after any control interface reset (FLR, ENTITY_RESET,
10390 * etc.), all event delivery is disabled for all ports associated with the
10391 * control interface.
10392 */
10393#define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_LEN 8
10394/* Handle to port to set event delivery mask. */
10395#define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_OFST 0
10396#define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_LEN 4
10397/* Bitmask of events to enable. Event delivery is enabled when corresponding
10398 * bit is 1, disabled when 0.
10399 */
10400#define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK_OFST 4
10401#define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK_LEN 4
10402/* enum property: bitshift */
10403/* Enum values, see field(s): */
10404/* EVENT_MASK/TYPE */
10405
10406/* MC_CMD_SET_NETPORT_EVENTS_MASK_OUT msgresponse */
10407#define MC_CMD_SET_NETPORT_EVENTS_MASK_OUT_LEN 0
10408
10409
10410/***********************************/
10411/* MC_CMD_GET_NETPORT_EVENTS_MASK
10412 */
10413#define MC_CMD_GET_NETPORT_EVENTS_MASK 0x1ea
10414#undef MC_CMD_0x1ea_PRIVILEGE_CTG
10415
10416#define MC_CMD_0x1ea_PRIVILEGE_CTG SRIOV_CTG_LINK
10417
10418/* MC_CMD_GET_NETPORT_EVENTS_MASK_IN msgrequest: Get event delivery mask a
10419 * given port identified by PORT_HANDLE.
10420 */
10421#define MC_CMD_GET_NETPORT_EVENTS_MASK_IN_LEN 4
10422/* Handle to port to get event deliver mask for. */
10423#define MC_CMD_GET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_OFST 0
10424#define MC_CMD_GET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_LEN 4
10425
10426/* MC_CMD_GET_NETPORT_EVENTS_MASK_OUT msgresponse */
10427#define MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_LEN 4
10428/* Bitmask of events enabled. Event delivery is enabled when corresponding bit
10429 * is 1, disabled when 0.
10430 */
10431#define MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_EVENT_MASK_OFST 0
10432#define MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_EVENT_MASK_LEN 4
10433/* enum property: bitshift */
10434/* Enum values, see field(s): */
10435/* EVENT_MASK/TYPE */
10436
10437
10438/***********************************/
10439/* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS
10440 */
10441#define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS 0x1eb
10442#undef MC_CMD_0x1eb_PRIVILEGE_CTG
10443
10444#define MC_CMD_0x1eb_PRIVILEGE_CTG SRIOV_CTG_LINK
10445
10446/* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_IN msgrequest: Get network port events
10447 * supported by the platform. Information returned is fixed for a given NIC
10448 * platform.
10449 */
10450#define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_IN_LEN 0
10451
10452/* MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT msgresponse */
10453#define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_LEN 4
10454/* Bitmask of events enabled. Event delivery is enabled when corresponding bit
10455 * is 1, disabled when 0.
10456 */
10457#define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_EVENT_MASK_OFST 0
10458#define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_EVENT_MASK_LEN 4
10459/* enum property: bitshift */
10460/* Enum values, see field(s): */
10461/* EVENT_MASK/TYPE */
10462
10463
10464/***********************************/
10465/* MC_CMD_GET_NETPORT_STATISTICS
10466 * Get generic MAC statistics. This call retrieves unified statistics managed
10467 * by the MC. The MC will populate and provide all supported statistics in the
10468 * format as returned by MC_CMD_MAC_STATISTICS_DESCRIPTOR. Refer to the
10469 * aforementioned command for the format and contents of the stats DMA buffer.
10470 * To ensure consistent and accurate results, it is essential for the driver to
10471 * initialize the DMA buffer with zeros when DMA mode is used. Returns: 0 on
10472 * success, ETIME if the DMA buffer is not ready, ENOENT on non-existent port
10473 * handle, and EINVAL on invalid parameters (DMA buffer too small)
10474 */
10475#define MC_CMD_GET_NETPORT_STATISTICS 0x1fa
10476#undef MC_CMD_0x1fa_PRIVILEGE_CTG
10477
10478#define MC_CMD_0x1fa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10479
10480/* MC_CMD_GET_NETPORT_STATISTICS_IN msgrequest */
10481#define MC_CMD_GET_NETPORT_STATISTICS_IN_LEN 20
10482/* Handle of port to get MAC statistics for. */
10483#define MC_CMD_GET_NETPORT_STATISTICS_IN_PORT_HANDLE_OFST 0
10484#define MC_CMD_GET_NETPORT_STATISTICS_IN_PORT_HANDLE_LEN 4
10485/* Contains options for querying the MAC statistics. */
10486#define MC_CMD_GET_NETPORT_STATISTICS_IN_CMD_OFST 4
10487#define MC_CMD_GET_NETPORT_STATISTICS_IN_CMD_LEN 4
10488#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_OFST 4
10489#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LBN 0
10490#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_WIDTH 1
10491#define MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_OFST 4
10492#define MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_LBN 1
10493#define MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_WIDTH 1
10494#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_OFST 4
10495#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_LBN 2
10496#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_WIDTH 1
10497#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_OFST 4
10498#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_LBN 3
10499#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_WIDTH 1
10500#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_OFST 4
10501#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_LBN 4
10502#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_WIDTH 1
10503#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_OFST 4
10504#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_LBN 15
10505#define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_WIDTH 17
10506/* Specifies the physical address of the DMA buffer to use for statistics
10507 * transfer. This field must contain a valid address under either of these
10508 * conditions: 1. DMA flag is set (immediate DMA requested) 2. Both
10509 * PERIODIC_CHANGE and PERIODIC_ENABLE are set (periodic DMA configured)
10510 */
10511#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_OFST 8
10512#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LEN 8
10513#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_OFST 8
10514#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_LEN 4
10515#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_LBN 64
10516#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_WIDTH 32
10517#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_OFST 12
10518#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_LEN 4
10519#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_LBN 96
10520#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_WIDTH 32
10521/* Specifies the length of the DMA buffer in bytes for statistics transfer. The
10522 * buffer size must be at least DMA_BUFFER_SIZE bytes (as returned by
10523 * MC_CMD_MAC_STATISTICS_DESCRIPTOR). Providing an insufficient buffer size
10524 * will result in an EINVAL error. This field must contain a valid length under
10525 * either of these conditions: 1. DMA flag is set (immediate DMA requested) 2.
10526 * Both PERIODIC_CHANGE and PERIODIC_ENABLE are set (periodic DMA configured)
10527 */
10528#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LEN_OFST 16
10529#define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LEN_LEN 4
10530
10531/* MC_CMD_GET_NETPORT_STATISTICS_OUT msgresponse */
10532#define MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMIN 0
10533#define MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMAX 248
10534#define MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMAX_MCDI2 1016
10535#define MC_CMD_GET_NETPORT_STATISTICS_OUT_LEN(num) (0+8*(num))
10536#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_NUM(len) (((len)-0)/8)
10537/* Statistics buffer. Zero-length if DMA mode is used. The statistics buffer is
10538 * an array of 8-byte counter values, containing the generation start marker,
10539 * stats counters, and generation end marker. The index of each counter in the
10540 * array is reported by the MAC_STATISTICS_DESCRIPTOR command. The same layout
10541 * is used for the DMA buffer for DMA mode stats.
10542 */
10543#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_OFST 0
10544#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LEN 8
10545#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_OFST 0
10546#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_LEN 4
10547#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_LBN 0
10548#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_WIDTH 32
10549#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_OFST 4
10550#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_LEN 4
10551#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_LBN 32
10552#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_WIDTH 32
10553#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MINNUM 0
10554#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MAXNUM 31
10555#define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MAXNUM_MCDI2 127
10556
10557/* EVB_PORT_ID structuredef */
10558#define EVB_PORT_ID_LEN 4
10559#define EVB_PORT_ID_PORT_ID_OFST 0
10560#define EVB_PORT_ID_PORT_ID_LEN 4
10561/* enum: An invalid port handle. */
10562#define EVB_PORT_ID_NULL 0x0
10563/* enum: The port assigned to this function.. */
10564#define EVB_PORT_ID_ASSIGNED 0x1000000
10565/* enum: External network port 0 */
10566#define EVB_PORT_ID_MAC0 0x2000000
10567/* enum: External network port 1 */
10568#define EVB_PORT_ID_MAC1 0x2000001
10569/* enum: External network port 2 */
10570#define EVB_PORT_ID_MAC2 0x2000002
10571/* enum: External network port 3 */
10572#define EVB_PORT_ID_MAC3 0x2000003
10573#define EVB_PORT_ID_PORT_ID_LBN 0
10574#define EVB_PORT_ID_PORT_ID_WIDTH 32
10575
10576/* NVRAM_PARTITION_TYPE structuredef */
10577#define NVRAM_PARTITION_TYPE_LEN 2
10578#define NVRAM_PARTITION_TYPE_ID_OFST 0
10579#define NVRAM_PARTITION_TYPE_ID_LEN 2
10580/* enum: Primary MC firmware partition */
10581#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
10582/* enum: NMC firmware partition (this is intentionally an alias of MC_FIRMWARE)
10583 */
10584#define NVRAM_PARTITION_TYPE_NMC_FIRMWARE 0x100
10585/* enum: Secondary MC firmware partition */
10586#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
10587/* enum: Expansion ROM partition */
10588#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
10589/* enum: Static configuration TLV partition */
10590#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
10591/* enum: Factory configuration TLV partition (this is intentionally an alias of
10592 * STATIC_CONFIG)
10593 */
10594#define NVRAM_PARTITION_TYPE_FACTORY_CONFIG 0x400
10595/* enum: Dynamic configuration TLV partition */
10596#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
10597/* enum: User configuration TLV partition (this is intentionally an alias of
10598 * DYNAMIC_CONFIG)
10599 */
10600#define NVRAM_PARTITION_TYPE_USER_CONFIG 0x500
10601/* enum: Expansion ROM configuration data for port 0 */
10602#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
10603/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
10604#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
10605/* enum: Expansion ROM configuration data for port 1 */
10606#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
10607/* enum: Expansion ROM configuration data for port 2 */
10608#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
10609/* enum: Expansion ROM configuration data for port 3 */
10610#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
10611/* enum: Non-volatile log output partition */
10612#define NVRAM_PARTITION_TYPE_LOG 0x700
10613/* enum: Non-volatile log output partition for NMC firmware (this is
10614 * intentionally an alias of LOG)
10615 */
10616#define NVRAM_PARTITION_TYPE_NMC_LOG 0x700
10617/* enum: Non-volatile log output of second core on dual-core device */
10618#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
10619/* enum: RAM (volatile) log output partition */
10620#define NVRAM_PARTITION_TYPE_RAM_LOG 0x702
10621/* enum: Device state dump output partition */
10622#define NVRAM_PARTITION_TYPE_DUMP 0x800
10623/* enum: Crash log partition for NMC firmware */
10624#define NVRAM_PARTITION_TYPE_NMC_CRASH_LOG 0x801
10625/* enum: Application license key storage partition */
10626#define NVRAM_PARTITION_TYPE_LICENSE 0x900
10627/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
10628#define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
10629/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
10630#define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
10631/* enum: Primary FPGA partition */
10632#define NVRAM_PARTITION_TYPE_FPGA 0xb00
10633/* enum: Secondary FPGA partition */
10634#define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
10635/* enum: FC firmware partition */
10636#define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
10637/* enum: FC License partition */
10638#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
10639/* enum: Non-volatile log output partition for FC */
10640#define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
10641/* enum: FPGA Stage 1 bitstream */
10642#define NVRAM_PARTITION_TYPE_FPGA_STAGE1 0xb05
10643/* enum: FPGA Stage 2 bitstream */
10644#define NVRAM_PARTITION_TYPE_FPGA_STAGE2 0xb06
10645/* enum: FPGA User XCLBIN / Programmable Region 0 bitstream */
10646#define NVRAM_PARTITION_TYPE_FPGA_REGION0 0xb07
10647/* enum: FPGA User XCLBIN (this is intentionally an alias of FPGA_REGION0) */
10648#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_USER 0xb07
10649/* enum: FPGA jump instruction (a.k.a. boot) partition to select Stage1
10650 * bitstream
10651 */
10652#define NVRAM_PARTITION_TYPE_FPGA_JUMP 0xb08
10653/* enum: FPGA Validate XCLBIN */
10654#define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_VALIDATE 0xb09
10655/* enum: FPGA XOCL Configuration information */
10656#define NVRAM_PARTITION_TYPE_FPGA_XOCL_CONFIG 0xb0a
10657/* enum: MUM firmware partition */
10658#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
10659/* enum: SUC firmware partition (this is intentionally an alias of
10660 * MUM_FIRMWARE)
10661 */
10662#define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
10663/* enum: MUM Non-volatile log output partition. */
10664#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
10665/* enum: SUC Non-volatile log output partition (this is intentionally an alias
10666 * of MUM_LOG).
10667 */
10668#define NVRAM_PARTITION_TYPE_SUC_LOG 0xc01
10669/* enum: MUM Application table partition. */
10670#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
10671/* enum: MUM boot rom partition. */
10672#define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
10673/* enum: MUM production signatures & calibration rom partition. */
10674#define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
10675/* enum: MUM user signatures & calibration rom partition. */
10676#define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
10677/* enum: MUM fuses and lockbits partition. */
10678#define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
10679/* enum: UEFI expansion ROM if separate from PXE */
10680#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
10681/* enum: Used by the expansion ROM for logging */
10682#define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
10683/* enum: Non-volatile log output partition for Expansion ROM (this is
10684 * intentionally an alias of PXE_LOG).
10685 */
10686#define NVRAM_PARTITION_TYPE_EXPROM_LOG 0x1000
10687/* enum: Used for XIP code of shmbooted images */
10688#define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
10689/* enum: Spare partition 2 */
10690#define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
10691/* enum: Manufacturing partition. Used during manufacture to pass information
10692 * between XJTAG and Manftest.
10693 */
10694#define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
10695/* enum: Deployment configuration TLV partition (this is intentionally an alias
10696 * of MANUFACTURING)
10697 */
10698#define NVRAM_PARTITION_TYPE_DEPLOYMENT_CONFIG 0x1300
10699/* enum: Spare partition 4 */
10700#define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
10701/* enum: Spare partition 5 */
10702#define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
10703/* enum: Partition for reporting MC status. See mc_flash_layout.h
10704 * medford_mc_status_hdr_t for layout on Medford.
10705 */
10706#define NVRAM_PARTITION_TYPE_STATUS 0x1600
10707/* enum: Spare partition 13 */
10708#define NVRAM_PARTITION_TYPE_SPARE_13 0x1700
10709/* enum: Spare partition 14 */
10710#define NVRAM_PARTITION_TYPE_SPARE_14 0x1800
10711/* enum: Spare partition 15 */
10712#define NVRAM_PARTITION_TYPE_SPARE_15 0x1900
10713/* enum: Spare partition 16 */
10714#define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
10715/* enum: Factory defaults for dynamic configuration */
10716#define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
10717/* enum: Factory defaults for expansion ROM configuration */
10718#define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
10719/* enum: Field Replaceable Unit inventory information for use on IPMI
10720 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
10721 * subset of the information stored in this partition.
10722 */
10723#define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
10724/* enum: Bundle image partition */
10725#define NVRAM_PARTITION_TYPE_BUNDLE 0x1e00
10726/* enum: Bundle metadata partition that holds additional information related to
10727 * a bundle update in TLV format
10728 */
10729#define NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
10730/* enum: Bundle update non-volatile log output partition */
10731#define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
10732/* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */
10733#define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
10734/* enum: Partition to store ASN.1 format Bundle Signature for checking. */
10735#define NVRAM_PARTITION_TYPE_BUNDLE_SIGNATURE 0x1e04
10736/* enum: Test partition on SmartNIC system microcontroller (SUC) */
10737#define NVRAM_PARTITION_TYPE_SUC_TEST 0x1f00
10738/* enum: System microcontroller access to primary FPGA flash. */
10739#define NVRAM_PARTITION_TYPE_SUC_FPGA_PRIMARY 0x1f01
10740/* enum: System microcontroller access to secondary FPGA flash (if present) */
10741#define NVRAM_PARTITION_TYPE_SUC_FPGA_SECONDARY 0x1f02
10742/* enum: System microcontroller access to primary System-on-Chip flash */
10743#define NVRAM_PARTITION_TYPE_SUC_SOC_PRIMARY 0x1f03
10744/* enum: System microcontroller access to secondary System-on-Chip flash (if
10745 * present)
10746 */
10747#define NVRAM_PARTITION_TYPE_SUC_SOC_SECONDARY 0x1f04
10748/* enum: System microcontroller critical failure logs. Contains structured
10749 * details of sensors leading up to a critical failure (where the board is shut
10750 * down).
10751 */
10752#define NVRAM_PARTITION_TYPE_SUC_FAILURE_LOG 0x1f05
10753/* enum: System-on-Chip configuration information (see XN-200467-PS). */
10754#define NVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f07
10755/* enum: System-on-Chip update information. */
10756#define NVRAM_PARTITION_TYPE_SOC_UPDATE 0x2003
10757/* enum: Virtual partition. Write-only. Writes will actually be sent to an
10758 * appropriate partition (for instance BUNDLE if the data starts with the magic
10759 * number for a bundle update), or discarded with an error if not recognised as
10760 * a supported type.
10761 */
10762#define NVRAM_PARTITION_TYPE_AUTO 0x2100
10763/* enum: MC/NMC (first stage) bootloader firmware. (For X4, see XN-202072-PS
10764 * and XN-202084-SW section 3.1).
10765 */
10766#define NVRAM_PARTITION_TYPE_BOOTLOADER 0x2200
10767/* enum: Start of reserved value range (firmware may use for any purpose) */
10768#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
10769/* enum: End of reserved value range (firmware may use for any purpose) */
10770#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
10771/* enum: Recovery partition map (provided if real map is missing or corrupt) */
10772#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
10773/* enum: Recovery Flash Partition Table, see SF-122606-TC. (this is
10774 * intentionally an alias of RECOVERY_MAP)
10775 */
10776#define NVRAM_PARTITION_TYPE_RECOVERY_FPT 0xfffe
10777/* enum: Partition map (real map as stored in flash) */
10778#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
10779/* enum: Flash Partition Table, see SF-122606-TC. (this is intentionally an
10780 * alias of PARTITION_MAP)
10781 */
10782#define NVRAM_PARTITION_TYPE_FPT 0xffff
10783#define NVRAM_PARTITION_TYPE_ID_LBN 0
10784#define NVRAM_PARTITION_TYPE_ID_WIDTH 16
10785
10786/* LICENSED_APP_ID structuredef */
10787#define LICENSED_APP_ID_LEN 4
10788#define LICENSED_APP_ID_ID_OFST 0
10789#define LICENSED_APP_ID_ID_LEN 4
10790/* enum: OpenOnload */
10791#define LICENSED_APP_ID_ONLOAD 0x1
10792/* enum: PTP timestamping */
10793#define LICENSED_APP_ID_PTP 0x2
10794/* enum: SolarCapture Pro */
10795#define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
10796/* enum: SolarSecure filter engine */
10797#define LICENSED_APP_ID_SOLARSECURE 0x8
10798/* enum: Performance monitor */
10799#define LICENSED_APP_ID_PERF_MONITOR 0x10
10800/* enum: SolarCapture Live */
10801#define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
10802/* enum: Capture SolarSystem */
10803#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
10804/* enum: Network Access Control */
10805#define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
10806/* enum: TCP Direct */
10807#define LICENSED_APP_ID_TCP_DIRECT 0x100
10808/* enum: Low Latency */
10809#define LICENSED_APP_ID_LOW_LATENCY 0x200
10810/* enum: SolarCapture Tap */
10811#define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
10812/* enum: Capture SolarSystem 40G */
10813#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
10814/* enum: Capture SolarSystem 1G */
10815#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
10816/* enum: ScaleOut Onload */
10817#define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
10818/* enum: SCS Network Analytics Dashboard */
10819#define LICENSED_APP_ID_DSHBRD 0x4000
10820/* enum: SolarCapture Trading Analytics */
10821#define LICENSED_APP_ID_SCATRD 0x8000
10822#define LICENSED_APP_ID_ID_LBN 0
10823#define LICENSED_APP_ID_ID_WIDTH 32
10824
10825/* LICENSED_V3_FEATURES structuredef */
10826#define LICENSED_V3_FEATURES_LEN 8
10827/* Bitmask of licensed firmware features */
10828#define LICENSED_V3_FEATURES_MASK_OFST 0
10829#define LICENSED_V3_FEATURES_MASK_LEN 8
10830#define LICENSED_V3_FEATURES_MASK_LO_OFST 0
10831#define LICENSED_V3_FEATURES_MASK_LO_LEN 4
10832#define LICENSED_V3_FEATURES_MASK_LO_LBN 0
10833#define LICENSED_V3_FEATURES_MASK_LO_WIDTH 32
10834#define LICENSED_V3_FEATURES_MASK_HI_OFST 4
10835#define LICENSED_V3_FEATURES_MASK_HI_LEN 4
10836#define LICENSED_V3_FEATURES_MASK_HI_LBN 32
10837#define LICENSED_V3_FEATURES_MASK_HI_WIDTH 32
10838#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
10839#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
10840#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
10841#define LICENSED_V3_FEATURES_PIO_OFST 0
10842#define LICENSED_V3_FEATURES_PIO_LBN 1
10843#define LICENSED_V3_FEATURES_PIO_WIDTH 1
10844#define LICENSED_V3_FEATURES_EVQ_TIMER_OFST 0
10845#define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2
10846#define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1
10847#define LICENSED_V3_FEATURES_CLOCK_OFST 0
10848#define LICENSED_V3_FEATURES_CLOCK_LBN 3
10849#define LICENSED_V3_FEATURES_CLOCK_WIDTH 1
10850#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 0
10851#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
10852#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1
10853#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 0
10854#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5
10855#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1
10856#define LICENSED_V3_FEATURES_RX_SNIFF_OFST 0
10857#define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6
10858#define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1
10859#define LICENSED_V3_FEATURES_TX_SNIFF_OFST 0
10860#define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7
10861#define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1
10862#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 0
10863#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8
10864#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1
10865#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 0
10866#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9
10867#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
10868#define LICENSED_V3_FEATURES_MASK_LBN 0
10869#define LICENSED_V3_FEATURES_MASK_WIDTH 64
10870
10871/* TX_TIMESTAMP_EVENT structuredef */
10872#define TX_TIMESTAMP_EVENT_LEN 6
10873/* lower 16 bits of timestamp data */
10874#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
10875#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2
10876#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
10877#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16
10878/* Type of TX event, ordinary TX completion, low or high part of TX timestamp
10879 */
10880#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3
10881#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1
10882/* enum: This is a TX completion event, not a timestamp */
10883#define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
10884/* enum: This is a TX completion event for a CTPIO transmit. The event format
10885 * is the same as for TX_EV_COMPLETION.
10886 */
10887#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
10888/* enum: This is the low part of a TX timestamp for a CTPIO transmission. The
10889 * event format is the same as for TX_EV_TSTAMP_LO
10890 */
10891#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
10892/* enum: This is the high part of a TX timestamp for a CTPIO transmission. The
10893 * event format is the same as for TX_EV_TSTAMP_HI
10894 */
10895#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
10896/* enum: This is the low part of a TX timestamp event */
10897#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
10898/* enum: This is the high part of a TX timestamp event */
10899#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
10900#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24
10901#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8
10902/* upper 16 bits of timestamp data */
10903#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
10904#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2
10905#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32
10906#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16
10907
10908/* RSS_MODE structuredef */
10909#define RSS_MODE_LEN 1
10910/* The RSS mode for a particular packet type is a value from 0 - 15 which can
10911 * be considered as 4 bits selecting which fields are included in the hash. (A
10912 * value 0 effectively disables RSS spreading for the packet type.) The YAML
10913 * generation tools require this structure to be a whole number of bytes wide,
10914 * but only 4 bits are relevant.
10915 */
10916#define RSS_MODE_HASH_SELECTOR_OFST 0
10917#define RSS_MODE_HASH_SELECTOR_LEN 1
10918#define RSS_MODE_HASH_SRC_ADDR_OFST 0
10919#define RSS_MODE_HASH_SRC_ADDR_LBN 0
10920#define RSS_MODE_HASH_SRC_ADDR_WIDTH 1
10921#define RSS_MODE_HASH_DST_ADDR_OFST 0
10922#define RSS_MODE_HASH_DST_ADDR_LBN 1
10923#define RSS_MODE_HASH_DST_ADDR_WIDTH 1
10924#define RSS_MODE_HASH_SRC_PORT_OFST 0
10925#define RSS_MODE_HASH_SRC_PORT_LBN 2
10926#define RSS_MODE_HASH_SRC_PORT_WIDTH 1
10927#define RSS_MODE_HASH_DST_PORT_OFST 0
10928#define RSS_MODE_HASH_DST_PORT_LBN 3
10929#define RSS_MODE_HASH_DST_PORT_WIDTH 1
10930#define RSS_MODE_HASH_SELECTOR_LBN 0
10931#define RSS_MODE_HASH_SELECTOR_WIDTH 8
10932
10933
10934/***********************************/
10935/* MC_CMD_INIT_EVQ
10936 * Set up an event queue according to the supplied parameters. The IN arguments
10937 * end with an address for each 4k of host memory required to back the EVQ.
10938 */
10939#define MC_CMD_INIT_EVQ 0x80
10940#undef MC_CMD_0x80_PRIVILEGE_CTG
10941
10942#define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10943
10944/* MC_CMD_INIT_EVQ_IN msgrequest */
10945#define MC_CMD_INIT_EVQ_IN_LENMIN 44
10946#define MC_CMD_INIT_EVQ_IN_LENMAX 548
10947#define MC_CMD_INIT_EVQ_IN_LENMAX_MCDI2 548
10948#define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
10949#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
10950/* Size, in entries */
10951#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
10952#define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
10953/* Desired instance. Must be set to a specific instance, which is a function
10954 * local queue index. The calling client must be the currently-assigned user of
10955 * this VI (see MC_CMD_SET_VI_USER).
10956 */
10957#define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
10958#define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
10959/* The initial timer value. The load value is ignored if the timer mode is DIS.
10960 */
10961#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
10962#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4
10963/* The reload value is ignored in one-shot modes */
10964#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
10965#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4
10966/* tbd */
10967#define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
10968#define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
10969#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_OFST 16
10970#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
10971#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
10972#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_OFST 16
10973#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
10974#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
10975#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_OFST 16
10976#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2
10977#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
10978#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_OFST 16
10979#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3
10980#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
10981#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_OFST 16
10982#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
10983#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
10984#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_OFST 16
10985#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5
10986#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
10987#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_OFST 16
10988#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6
10989#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1
10990#define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
10991#define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4
10992/* enum: Disabled */
10993#define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
10994/* enum: Immediate */
10995#define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
10996/* enum: Triggered */
10997#define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
10998/* enum: Hold-off */
10999#define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
11000/* Target EVQ for wakeups if in wakeup mode. */
11001#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
11002#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4
11003/* Target interrupt if in interrupting mode (note union with target EVQ). Use
11004 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
11005 * purposes.
11006 */
11007#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
11008#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4
11009/* Event Counter Mode. */
11010#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28
11011#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4
11012/* enum: Disabled */
11013#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
11014/* enum: Disabled */
11015#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
11016/* enum: Disabled */
11017#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
11018/* enum: Disabled */
11019#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
11020/* Event queue packet count threshold. */
11021#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32
11022#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4
11023/* 64-bit address of 4k of 4k-aligned host memory buffer */
11024#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
11025#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
11026#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
11027#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LEN 4
11028#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LBN 288
11029#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_WIDTH 32
11030#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
11031#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LEN 4
11032#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LBN 320
11033#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_WIDTH 32
11034#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
11035#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
11036#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM_MCDI2 64
11037
11038/* MC_CMD_INIT_EVQ_OUT msgresponse */
11039#define MC_CMD_INIT_EVQ_OUT_LEN 4
11040/* Only valid if INTRFLAG was true */
11041#define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
11042#define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4
11043
11044/* MC_CMD_INIT_EVQ_V2_IN msgrequest */
11045#define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44
11046#define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548
11047#define MC_CMD_INIT_EVQ_V2_IN_LENMAX_MCDI2 548
11048#define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))
11049#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
11050/* Size, in entries */
11051#define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
11052#define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
11053/* Desired instance. Must be set to a specific instance, which is a function
11054 * local queue index. The calling client must be the currently-assigned user of
11055 * this VI (see MC_CMD_SET_VI_USER).
11056 */
11057#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
11058#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
11059/* The initial timer value. The load value is ignored if the timer mode is DIS.
11060 */
11061#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8
11062#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4
11063/* The reload value is ignored in one-shot modes */
11064#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12
11065#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4
11066/* tbd */
11067#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16
11068#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
11069#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_OFST 16
11070#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
11071#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1
11072#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_OFST 16
11073#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1
11074#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1
11075#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_OFST 16
11076#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2
11077#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1
11078#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_OFST 16
11079#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3
11080#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1
11081#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_OFST 16
11082#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
11083#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1
11084#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_OFST 16
11085#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5
11086#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1
11087#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_OFST 16
11088#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6
11089#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1
11090#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_OFST 16
11091#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7
11092#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
11093/* enum: All initialisation flags specified by host. */
11094#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
11095/* enum: MEDFORD only. Certain initialisation flags specified by host may be
11096 * over-ridden by firmware based on licenses and firmware variant in order to
11097 * provide the lowest latency achievable. See
11098 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
11099 */
11100#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
11101/* enum: MEDFORD only. Certain initialisation flags specified by host may be
11102 * over-ridden by firmware based on licenses and firmware variant in order to
11103 * provide the best throughput achievable. See
11104 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
11105 */
11106#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
11107/* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
11108 * firmware based on licenses and firmware variant. See
11109 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
11110 */
11111#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
11112#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_OFST 16
11113#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_LBN 11
11114#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_WIDTH 1
11115#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20
11116#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
11117/* enum: Disabled */
11118#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
11119/* enum: Immediate */
11120#define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
11121/* enum: Triggered */
11122#define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
11123/* enum: Hold-off */
11124#define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
11125/* Target EVQ for wakeups if in wakeup mode. */
11126#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24
11127#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4
11128/* Target interrupt if in interrupting mode (note union with target EVQ). Use
11129 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
11130 * purposes.
11131 */
11132#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24
11133#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4
11134/* Event Counter Mode. */
11135#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28
11136#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4
11137/* enum: Disabled */
11138#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
11139/* enum: Disabled */
11140#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
11141/* enum: Disabled */
11142#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
11143/* enum: Disabled */
11144#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
11145/* Event queue packet count threshold. */
11146#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32
11147#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4
11148/* 64-bit address of 4k of 4k-aligned host memory buffer */
11149#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36
11150#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8
11151#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36
11152#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LEN 4
11153#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LBN 288
11154#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_WIDTH 32
11155#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
11156#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LEN 4
11157#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LBN 320
11158#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_WIDTH 32
11159#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
11160#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
11161#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM_MCDI2 64
11162
11163/* MC_CMD_INIT_EVQ_V2_OUT msgresponse */
11164#define MC_CMD_INIT_EVQ_V2_OUT_LEN 8
11165/* Only valid if INTRFLAG was true */
11166#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
11167#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4
11168/* Actual configuration applied on the card */
11169#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
11170#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
11171#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 4
11172#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
11173#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1
11174#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 4
11175#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1
11176#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1
11177#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 4
11178#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2
11179#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1
11180#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
11181#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3
11182#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
11183
11184/* MC_CMD_INIT_EVQ_V3_IN msgrequest: Extended request to specify per-queue
11185 * event merge timeouts.
11186 */
11187#define MC_CMD_INIT_EVQ_V3_IN_LEN 556
11188/* Size, in entries */
11189#define MC_CMD_INIT_EVQ_V3_IN_SIZE_OFST 0
11190#define MC_CMD_INIT_EVQ_V3_IN_SIZE_LEN 4
11191/* Desired instance. Must be set to a specific instance, which is a function
11192 * local queue index. The calling client must be the currently-assigned user of
11193 * this VI (see MC_CMD_SET_VI_USER).
11194 */
11195#define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_OFST 4
11196#define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_LEN 4
11197/* The initial timer value. The load value is ignored if the timer mode is DIS.
11198 */
11199#define MC_CMD_INIT_EVQ_V3_IN_TMR_LOAD_OFST 8
11200#define MC_CMD_INIT_EVQ_V3_IN_TMR_LOAD_LEN 4
11201/* The reload value is ignored in one-shot modes */
11202#define MC_CMD_INIT_EVQ_V3_IN_TMR_RELOAD_OFST 12
11203#define MC_CMD_INIT_EVQ_V3_IN_TMR_RELOAD_LEN 4
11204/* tbd */
11205#define MC_CMD_INIT_EVQ_V3_IN_FLAGS_OFST 16
11206#define MC_CMD_INIT_EVQ_V3_IN_FLAGS_LEN 4
11207#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_OFST 16
11208#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_LBN 0
11209#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_WIDTH 1
11210#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RPTR_DOS_OFST 16
11211#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RPTR_DOS_LBN 1
11212#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RPTR_DOS_WIDTH 1
11213#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INT_ARMD_OFST 16
11214#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INT_ARMD_LBN 2
11215#define MC_CMD_INIT_EVQ_V3_IN_FLAG_INT_ARMD_WIDTH 1
11216#define MC_CMD_INIT_EVQ_V3_IN_FLAG_CUT_THRU_OFST 16
11217#define MC_CMD_INIT_EVQ_V3_IN_FLAG_CUT_THRU_LBN 3
11218#define MC_CMD_INIT_EVQ_V3_IN_FLAG_CUT_THRU_WIDTH 1
11219#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_OFST 16
11220#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_LBN 4
11221#define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_WIDTH 1
11222#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TX_MERGE_OFST 16
11223#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TX_MERGE_LBN 5
11224#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TX_MERGE_WIDTH 1
11225#define MC_CMD_INIT_EVQ_V3_IN_FLAG_USE_TIMER_OFST 16
11226#define MC_CMD_INIT_EVQ_V3_IN_FLAG_USE_TIMER_LBN 6
11227#define MC_CMD_INIT_EVQ_V3_IN_FLAG_USE_TIMER_WIDTH 1
11228#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_OFST 16
11229#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_LBN 7
11230#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_WIDTH 4
11231/* enum: All initialisation flags specified by host. */
11232#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_MANUAL 0x0
11233/* enum: MEDFORD only. Certain initialisation flags specified by host may be
11234 * over-ridden by firmware based on licenses and firmware variant in order to
11235 * provide the lowest latency achievable. See
11236 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
11237 */
11238#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_LOW_LATENCY 0x1
11239/* enum: MEDFORD only. Certain initialisation flags specified by host may be
11240 * over-ridden by firmware based on licenses and firmware variant in order to
11241 * provide the best throughput achievable. See
11242 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
11243 */
11244#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_THROUGHPUT 0x2
11245/* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
11246 * firmware based on licenses and firmware variant. See
11247 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
11248 */
11249#define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_AUTO 0x3
11250#define MC_CMD_INIT_EVQ_V3_IN_FLAG_EXT_WIDTH_OFST 16
11251#define MC_CMD_INIT_EVQ_V3_IN_FLAG_EXT_WIDTH_LBN 11
11252#define MC_CMD_INIT_EVQ_V3_IN_FLAG_EXT_WIDTH_WIDTH 1
11253#define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_OFST 20
11254#define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_LEN 4
11255/* enum: Disabled */
11256#define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_DIS 0x0
11257/* enum: Immediate */
11258#define MC_CMD_INIT_EVQ_V3_IN_TMR_IMMED_START 0x1
11259/* enum: Triggered */
11260#define MC_CMD_INIT_EVQ_V3_IN_TMR_TRIG_START 0x2
11261/* enum: Hold-off */
11262#define MC_CMD_INIT_EVQ_V3_IN_TMR_INT_HLDOFF 0x3
11263/* Target EVQ for wakeups if in wakeup mode. */
11264#define MC_CMD_INIT_EVQ_V3_IN_TARGET_EVQ_OFST 24
11265#define MC_CMD_INIT_EVQ_V3_IN_TARGET_EVQ_LEN 4
11266/* Target interrupt if in interrupting mode (note union with target EVQ). Use
11267 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
11268 * purposes.
11269 */
11270#define MC_CMD_INIT_EVQ_V3_IN_IRQ_NUM_OFST 24
11271#define MC_CMD_INIT_EVQ_V3_IN_IRQ_NUM_LEN 4
11272/* Event Counter Mode. */
11273#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_OFST 28
11274#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_LEN 4
11275/* enum: Disabled */
11276#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_DIS 0x0
11277/* enum: Disabled */
11278#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RX 0x1
11279/* enum: Disabled */
11280#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_TX 0x2
11281/* enum: Disabled */
11282#define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RXTX 0x3
11283/* Event queue packet count threshold. */
11284#define MC_CMD_INIT_EVQ_V3_IN_COUNT_THRSHLD_OFST 32
11285#define MC_CMD_INIT_EVQ_V3_IN_COUNT_THRSHLD_LEN 4
11286/* 64-bit address of 4k of 4k-aligned host memory buffer */
11287#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_OFST 36
11288#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LEN 8
11289#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_OFST 36
11290#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_LEN 4
11291#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_LBN 288
11292#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_WIDTH 32
11293#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_OFST 40
11294#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_LEN 4
11295#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_LBN 320
11296#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_WIDTH 32
11297#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_MINNUM 1
11298#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_MAXNUM 64
11299#define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_MAXNUM_MCDI2 64
11300/* Receive event merge timeout to configure, in nanoseconds. The valid range
11301 * and granularity are device specific. Specify 0 to use the firmware's default
11302 * value. This field is ignored and per-queue merging is disabled if
11303 * MC_CMD_INIT_EVQ/MC_CMD_INIT_EVQ_IN/FLAG_RX_MERGE is not set.
11304 */
11305#define MC_CMD_INIT_EVQ_V3_IN_RX_MERGE_TIMEOUT_NS_OFST 548
11306#define MC_CMD_INIT_EVQ_V3_IN_RX_MERGE_TIMEOUT_NS_LEN 4
11307/* Transmit event merge timeout to configure, in nanoseconds. The valid range
11308 * and granularity are device specific. Specify 0 to use the firmware's default
11309 * value. This field is ignored and per-queue merging is disabled if
11310 * MC_CMD_INIT_EVQ/MC_CMD_INIT_EVQ_IN/FLAG_TX_MERGE is not set.
11311 */
11312#define MC_CMD_INIT_EVQ_V3_IN_TX_MERGE_TIMEOUT_NS_OFST 552
11313#define MC_CMD_INIT_EVQ_V3_IN_TX_MERGE_TIMEOUT_NS_LEN 4
11314
11315/* MC_CMD_INIT_EVQ_V3_OUT msgresponse */
11316#define MC_CMD_INIT_EVQ_V3_OUT_LEN 8
11317/* Only valid if INTRFLAG was true */
11318#define MC_CMD_INIT_EVQ_V3_OUT_IRQ_OFST 0
11319#define MC_CMD_INIT_EVQ_V3_OUT_IRQ_LEN 4
11320/* Actual configuration applied on the card */
11321#define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_OFST 4
11322#define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_LEN 4
11323#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_OFST 4
11324#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_LBN 0
11325#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_WIDTH 1
11326#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_OFST 4
11327#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_LBN 1
11328#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_WIDTH 1
11329#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_OFST 4
11330#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_LBN 2
11331#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_WIDTH 1
11332#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
11333#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3
11334#define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
11335
11336
11337/***********************************/
11338/* MC_CMD_INIT_RXQ
11339 * set up a receive queue according to the supplied parameters. The IN
11340 * arguments end with an address for each 4k of host memory required to back
11341 * the RXQ.
11342 */
11343#define MC_CMD_INIT_RXQ 0x81
11344#undef MC_CMD_0x81_PRIVILEGE_CTG
11345
11346#define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11347
11348/* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version
11349 * in new code.
11350 */
11351#define MC_CMD_INIT_RXQ_IN_LENMIN 36
11352#define MC_CMD_INIT_RXQ_IN_LENMAX 252
11353#define MC_CMD_INIT_RXQ_IN_LENMAX_MCDI2 1020
11354#define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
11355#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
11356/* Size, in entries */
11357#define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
11358#define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
11359/* The EVQ to send events to. This is an index originally specified to INIT_EVQ
11360 */
11361#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
11362#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4
11363/* The value to put in the event data. Check hardware spec. for valid range. */
11364#define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
11365#define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
11366/* Desired instance. Must be set to a specific instance, which is a function
11367 * local queue index. The calling client must be the currently-assigned user of
11368 * this VI (see MC_CMD_SET_VI_USER).
11369 */
11370#define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
11371#define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
11372/* There will be more flags here. */
11373#define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
11374#define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
11375#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_OFST 16
11376#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
11377#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
11378#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_OFST 16
11379#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
11380#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
11381#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_OFST 16
11382#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2
11383#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
11384#define MC_CMD_INIT_RXQ_IN_CRC_MODE_OFST 16
11385#define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
11386#define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
11387#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_OFST 16
11388#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7
11389#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
11390#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_OFST 16
11391#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8
11392#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
11393#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_OFST 16
11394#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9
11395#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
11396#define MC_CMD_INIT_RXQ_IN_UNUSED_OFST 16
11397#define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10
11398#define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1
11399/* Owner ID to use if in buffer mode (zero if physical) */
11400#define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
11401#define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4
11402/* The port ID associated with the v-adaptor which should contain this DMAQ. */
11403#define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24
11404#define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4
11405/* 64-bit address of 4k of 4k-aligned host memory buffer */
11406#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
11407#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
11408#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
11409#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LEN 4
11410#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LBN 224
11411#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_WIDTH 32
11412#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
11413#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LEN 4
11414#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LBN 256
11415#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_WIDTH 32
11416#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
11417#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
11418#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
11419
11420/* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode
11421 * flags
11422 */
11423#define MC_CMD_INIT_RXQ_EXT_IN_LEN 544
11424/* Size, in entries */
11425#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
11426#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
11427/* The EVQ to send events to. This is an index originally specified to
11428 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
11429 */
11430#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
11431#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
11432/* The value to put in the event data. Check hardware spec. for valid range.
11433 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
11434 * == PACKED_STREAM.
11435 */
11436#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
11437#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
11438/* Desired instance. Must be set to a specific instance, which is a function
11439 * local queue index. The calling client must be the currently-assigned user of
11440 * this VI (see MC_CMD_SET_VI_USER).
11441 */
11442#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12
11443#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
11444/* There will be more flags here. */
11445#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16
11446#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
11447#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16
11448#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
11449#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
11450#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_OFST 16
11451#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1
11452#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1
11453#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16
11454#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2
11455#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
11456#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_OFST 16
11457#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3
11458#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
11459#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_OFST 16
11460#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7
11461#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1
11462#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_OFST 16
11463#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8
11464#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1
11465#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_OFST 16
11466#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9
11467#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1
11468#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_OFST 16
11469#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10
11470#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
11471/* enum: One packet per descriptor (for normal networking) */
11472#define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
11473/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
11474#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
11475/* enum: Pack multiple packets into large descriptors using the format designed
11476 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
11477 * multiple fixed-size packet buffers within each bucket. For a full
11478 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11479 * firmware.
11480 */
11481#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11482/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
11483#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11484#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_OFST 16
11485#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14
11486#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
11487#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
11488#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
11489#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
11490#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
11491#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
11492#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
11493#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
11494#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
11495#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
11496#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
11497#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
11498#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_OFST 16
11499#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19
11500#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
11501#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 16
11502#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 20
11503#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1
11504#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
11505#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
11506#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
11507/* Owner ID to use if in buffer mode (zero if physical) */
11508#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20
11509#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
11510/* The port ID associated with the v-adaptor which should contain this DMAQ. */
11511#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24
11512#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4
11513/* 64-bit address of 4k of 4k-aligned host memory buffer */
11514#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28
11515#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8
11516#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28
11517#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LEN 4
11518#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LBN 224
11519#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32
11520#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32
11521#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LEN 4
11522#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LBN 256
11523#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32
11524#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MINNUM 0
11525#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MAXNUM 64
11526#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 64
11527/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
11528#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
11529#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
11530
11531/* MC_CMD_INIT_RXQ_V3_IN msgrequest */
11532#define MC_CMD_INIT_RXQ_V3_IN_LEN 560
11533/* Size, in entries */
11534#define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0
11535#define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4
11536/* The EVQ to send events to. This is an index originally specified to
11537 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
11538 */
11539#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
11540#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
11541/* The value to put in the event data. Check hardware spec. for valid range.
11542 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
11543 * == PACKED_STREAM.
11544 */
11545#define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8
11546#define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
11547/* Desired instance. Must be set to a specific instance, which is a function
11548 * local queue index. The calling client must be the currently-assigned user of
11549 * this VI (see MC_CMD_SET_VI_USER).
11550 */
11551#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12
11552#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
11553/* There will be more flags here. */
11554#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16
11555#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
11556#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_OFST 16
11557#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
11558#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1
11559#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_OFST 16
11560#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1
11561#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1
11562#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_OFST 16
11563#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2
11564#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1
11565#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_OFST 16
11566#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3
11567#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
11568#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_OFST 16
11569#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7
11570#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1
11571#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_OFST 16
11572#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8
11573#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1
11574#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_OFST 16
11575#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9
11576#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1
11577#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_OFST 16
11578#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10
11579#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
11580/* enum: One packet per descriptor (for normal networking) */
11581#define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
11582/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
11583#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
11584/* enum: Pack multiple packets into large descriptors using the format designed
11585 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
11586 * multiple fixed-size packet buffers within each bucket. For a full
11587 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11588 * firmware.
11589 */
11590#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11591/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
11592#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11593#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_OFST 16
11594#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14
11595#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
11596#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
11597#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
11598#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
11599#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
11600#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
11601#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
11602#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
11603#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
11604#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
11605#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
11606#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
11607#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_OFST 16
11608#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19
11609#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
11610#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 16
11611#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 20
11612#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1
11613#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
11614#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
11615#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
11616/* Owner ID to use if in buffer mode (zero if physical) */
11617#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20
11618#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
11619/* The port ID associated with the v-adaptor which should contain this DMAQ. */
11620#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 24
11621#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4
11622/* 64-bit address of 4k of 4k-aligned host memory buffer */
11623#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28
11624#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8
11625#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28
11626#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LEN 4
11627#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LBN 224
11628#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_WIDTH 32
11629#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32
11630#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LEN 4
11631#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LBN 256
11632#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_WIDTH 32
11633#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MINNUM 0
11634#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MAXNUM 64
11635#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MAXNUM_MCDI2 64
11636/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
11637#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540
11638#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
11639/* The number of packet buffers that will be contained within each
11640 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
11641 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11642 */
11643#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
11644#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11645/* The length in bytes of the area in each packet buffer that can be written to
11646 * by the adapter. This is used to store the packet prefix and the packet
11647 * payload. This length does not include any end padding added by the driver.
11648 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11649 */
11650#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548
11651#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
11652/* The length in bytes of a single packet buffer within a
11653 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
11654 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11655 */
11656#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552
11657#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
11658/* The maximum time in nanoseconds that the datapath will be backpressured if
11659 * there are no RX descriptors available. If the timeout is reached and there
11660 * are still no descriptors then the packet will be dropped. A timeout of 0
11661 * means the datapath will never be blocked. This field is ignored unless
11662 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11663 */
11664#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
11665#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11666
11667/* MC_CMD_INIT_RXQ_V4_IN msgrequest: INIT_RXQ request with new field required
11668 * for systems with a QDMA (currently, Riverhead)
11669 */
11670#define MC_CMD_INIT_RXQ_V4_IN_LEN 564
11671/* Size, in entries */
11672#define MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 0
11673#define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 4
11674/* The EVQ to send events to. This is an index originally specified to
11675 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
11676 */
11677#define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 4
11678#define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 4
11679/* The value to put in the event data. Check hardware spec. for valid range.
11680 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
11681 * == PACKED_STREAM.
11682 */
11683#define MC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 8
11684#define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
11685/* Desired instance. Must be set to a specific instance, which is a function
11686 * local queue index. The calling client must be the currently-assigned user of
11687 * this VI (see MC_CMD_SET_VI_USER).
11688 */
11689#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 12
11690#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
11691/* There will be more flags here. */
11692#define MC_CMD_INIT_RXQ_V4_IN_FLAGS_OFST 16
11693#define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4
11694#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_OFST 16
11695#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 0
11696#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_WIDTH 1
11697#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_OFST 16
11698#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_LBN 1
11699#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_WIDTH 1
11700#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_OFST 16
11701#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_LBN 2
11702#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_WIDTH 1
11703#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_OFST 16
11704#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_LBN 3
11705#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4
11706#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_OFST 16
11707#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_LBN 7
11708#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_WIDTH 1
11709#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_OFST 16
11710#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_LBN 8
11711#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_WIDTH 1
11712#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_OFST 16
11713#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_LBN 9
11714#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_WIDTH 1
11715#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_OFST 16
11716#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_LBN 10
11717#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4
11718/* enum: One packet per descriptor (for normal networking) */
11719#define MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x0
11720/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
11721#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x1
11722/* enum: Pack multiple packets into large descriptors using the format designed
11723 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
11724 * multiple fixed-size packet buffers within each bucket. For a full
11725 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11726 * firmware.
11727 */
11728#define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11729/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
11730#define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11731#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_OFST 16
11732#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_LBN 14
11733#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
11734#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
11735#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
11736#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
11737#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */
11738#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */
11739#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */
11740#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */
11741#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */
11742#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
11743#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
11744#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
11745#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_OFST 16
11746#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_LBN 19
11747#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
11748#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 16
11749#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 20
11750#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1
11751#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
11752#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
11753#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
11754/* Owner ID to use if in buffer mode (zero if physical) */
11755#define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_OFST 20
11756#define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4
11757/* The port ID associated with the v-adaptor which should contain this DMAQ. */
11758#define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_OFST 24
11759#define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 4
11760/* 64-bit address of 4k of 4k-aligned host memory buffer */
11761#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 28
11762#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 8
11763#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 28
11764#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LEN 4
11765#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LBN 224
11766#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_WIDTH 32
11767#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 32
11768#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LEN 4
11769#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LBN 256
11770#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_WIDTH 32
11771#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MINNUM 0
11772#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MAXNUM 64
11773#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MAXNUM_MCDI2 64
11774/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
11775#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 540
11776#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 4
11777/* The number of packet buffers that will be contained within each
11778 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
11779 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11780 */
11781#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
11782#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11783/* The length in bytes of the area in each packet buffer that can be written to
11784 * by the adapter. This is used to store the packet prefix and the packet
11785 * payload. This length does not include any end padding added by the driver.
11786 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11787 */
11788#define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_OFST 548
11789#define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 4
11790/* The length in bytes of a single packet buffer within a
11791 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
11792 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11793 */
11794#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_OFST 552
11795#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 4
11796/* The maximum time in nanoseconds that the datapath will be backpressured if
11797 * there are no RX descriptors available. If the timeout is reached and there
11798 * are still no descriptors then the packet will be dropped. A timeout of 0
11799 * means the datapath will never be blocked. This field is ignored unless
11800 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11801 */
11802#define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
11803#define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11804/* V4 message data */
11805#define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_OFST 560
11806#define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 4
11807/* Size in bytes of buffers attached to descriptors posted to this queue. Set
11808 * to zero if using this message on non-QDMA based platforms. Currently in
11809 * Riverhead there is a global limit of eight different buffer sizes across all
11810 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
11811 * request for a different buffer size will fail if there are already eight
11812 * other buffer sizes in use. In future Riverhead this limit will go away and
11813 * any size will be accepted.
11814 */
11815#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_OFST 560
11816#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4
11817
11818/* MC_CMD_INIT_RXQ_V5_IN msgrequest: INIT_RXQ request with ability to request a
11819 * different RX packet prefix
11820 */
11821#define MC_CMD_INIT_RXQ_V5_IN_LEN 568
11822/* Size, in entries */
11823#define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 0
11824#define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4
11825/* The EVQ to send events to. This is an index originally specified to
11826 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
11827 */
11828#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4
11829#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4
11830/* The value to put in the event data. Check hardware spec. for valid range.
11831 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
11832 * == PACKED_STREAM.
11833 */
11834#define MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 8
11835#define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
11836/* Desired instance. Must be set to a specific instance, which is a function
11837 * local queue index. The calling client must be the currently-assigned user of
11838 * this VI (see MC_CMD_SET_VI_USER).
11839 */
11840#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 12
11841#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
11842/* There will be more flags here. */
11843#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_OFST 16
11844#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4
11845#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_OFST 16
11846#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0
11847#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 1
11848#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_OFST 16
11849#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 1
11850#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 1
11851#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_OFST 16
11852#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_LBN 2
11853#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 1
11854#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_OFST 16
11855#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_LBN 3
11856#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4
11857#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_OFST 16
11858#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_LBN 7
11859#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 1
11860#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_OFST 16
11861#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_LBN 8
11862#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 1
11863#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_OFST 16
11864#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_LBN 9
11865#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 1
11866#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_OFST 16
11867#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_LBN 10
11868#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4
11869/* enum: One packet per descriptor (for normal networking) */
11870#define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x0
11871/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
11872#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x1
11873/* enum: Pack multiple packets into large descriptors using the format designed
11874 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
11875 * multiple fixed-size packet buffers within each bucket. For a full
11876 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11877 * firmware.
11878 */
11879#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11880/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
11881#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11882#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_OFST 16
11883#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_LBN 14
11884#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
11885#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
11886#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
11887#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
11888#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */
11889#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */
11890#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */
11891#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */
11892#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */
11893#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
11894#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
11895#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
11896#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_OFST 16
11897#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_LBN 19
11898#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
11899#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 16
11900#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 20
11901#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1
11902#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_OFST 16
11903#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_LBN 21
11904#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SUPPRESS_RX_EVENTS_WIDTH 1
11905/* Owner ID to use if in buffer mode (zero if physical) */
11906#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 20
11907#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
11908/* The port ID associated with the v-adaptor which should contain this DMAQ. */
11909#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_OFST 24
11910#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4
11911/* 64-bit address of 4k of 4k-aligned host memory buffer */
11912#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 28
11913#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 8
11914#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 28
11915#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LEN 4
11916#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LBN 224
11917#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_WIDTH 32
11918#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 32
11919#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LEN 4
11920#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LBN 256
11921#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_WIDTH 32
11922#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MINNUM 0
11923#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MAXNUM 64
11924#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MAXNUM_MCDI2 64
11925/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
11926#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 540
11927#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4
11928/* The number of packet buffers that will be contained within each
11929 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
11930 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11931 */
11932#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
11933#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11934/* The length in bytes of the area in each packet buffer that can be written to
11935 * by the adapter. This is used to store the packet prefix and the packet
11936 * payload. This length does not include any end padding added by the driver.
11937 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11938 */
11939#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_OFST 548
11940#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4
11941/* The length in bytes of a single packet buffer within a
11942 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
11943 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11944 */
11945#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_OFST 552
11946#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4
11947/* The maximum time in nanoseconds that the datapath will be backpressured if
11948 * there are no RX descriptors available. If the timeout is reached and there
11949 * are still no descriptors then the packet will be dropped. A timeout of 0
11950 * means the datapath will never be blocked. This field is ignored unless
11951 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
11952 */
11953#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
11954#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11955/* V4 message data */
11956#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_OFST 560
11957#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4
11958/* Size in bytes of buffers attached to descriptors posted to this queue. Set
11959 * to zero if using this message on non-QDMA based platforms. Currently in
11960 * Riverhead there is a global limit of eight different buffer sizes across all
11961 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
11962 * request for a different buffer size will fail if there are already eight
11963 * other buffer sizes in use. In future Riverhead this limit will go away and
11964 * any size will be accepted.
11965 */
11966#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_OFST 560
11967#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4
11968/* Prefix id for the RX prefix format to use on packets delivered this queue.
11969 * Zero is always a valid prefix id and means the default prefix format
11970 * documented for the platform. Other prefix ids can be obtained by calling
11971 * MC_CMD_GET_RX_PREFIX_ID with a requested set of prefix fields.
11972 */
11973#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_OFST 564
11974#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4
11975
11976/* MC_CMD_INIT_RXQ_OUT msgresponse */
11977#define MC_CMD_INIT_RXQ_OUT_LEN 0
11978
11979/* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */
11980#define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
11981
11982/* MC_CMD_INIT_RXQ_V3_OUT msgresponse */
11983#define MC_CMD_INIT_RXQ_V3_OUT_LEN 0
11984
11985/* MC_CMD_INIT_RXQ_V4_OUT msgresponse */
11986#define MC_CMD_INIT_RXQ_V4_OUT_LEN 0
11987
11988/* MC_CMD_INIT_RXQ_V5_OUT msgresponse */
11989#define MC_CMD_INIT_RXQ_V5_OUT_LEN 0
11990
11991
11992/***********************************/
11993/* MC_CMD_INIT_TXQ
11994 */
11995#define MC_CMD_INIT_TXQ 0x82
11996#undef MC_CMD_0x82_PRIVILEGE_CTG
11997
11998#define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
11999
12000/* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version
12001 * in new code.
12002 */
12003#define MC_CMD_INIT_TXQ_IN_LENMIN 36
12004#define MC_CMD_INIT_TXQ_IN_LENMAX 252
12005#define MC_CMD_INIT_TXQ_IN_LENMAX_MCDI2 1020
12006#define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
12007#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
12008/* Size, in entries */
12009#define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
12010#define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
12011/* The EVQ to send events to. This is an index originally specified to
12012 * INIT_EVQ.
12013 */
12014#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
12015#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4
12016/* The value to put in the event data. Check hardware spec. for valid range. */
12017#define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
12018#define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
12019/* Desired instance. Must be set to a specific instance, which is a function
12020 * local queue index. The calling client must be the currently-assigned user of
12021 * this VI (see MC_CMD_SET_VI_USER).
12022 */
12023#define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
12024#define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
12025/* There will be more flags here. */
12026#define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
12027#define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
12028#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_OFST 16
12029#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
12030#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
12031#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_OFST 16
12032#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
12033#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
12034#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_OFST 16
12035#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
12036#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
12037#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_OFST 16
12038#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
12039#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
12040#define MC_CMD_INIT_TXQ_IN_CRC_MODE_OFST 16
12041#define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
12042#define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
12043#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_OFST 16
12044#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8
12045#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
12046#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_OFST 16
12047#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9
12048#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
12049#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_OFST 16
12050#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
12051#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
12052#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16
12053#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
12054#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
12055/* Owner ID to use if in buffer mode (zero if physical) */
12056#define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
12057#define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4
12058/* The port ID associated with the v-adaptor which should contain this DMAQ. */
12059#define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24
12060#define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4
12061/* 64-bit address of 4k of 4k-aligned host memory buffer */
12062#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
12063#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
12064#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
12065#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LEN 4
12066#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LBN 224
12067#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_WIDTH 32
12068#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
12069#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LEN 4
12070#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LBN 256
12071#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_WIDTH 32
12072#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
12073#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
12074#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
12075
12076/* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode
12077 * flags
12078 */
12079#define MC_CMD_INIT_TXQ_EXT_IN_LEN 544
12080/* Size, in entries */
12081#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
12082#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4
12083/* The EVQ to send events to. This is an index originally specified to
12084 * INIT_EVQ.
12085 */
12086#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
12087#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4
12088/* The value to put in the event data. Check hardware spec. for valid range. */
12089#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8
12090#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
12091/* Desired instance. Must be set to a specific instance, which is a function
12092 * local queue index. The calling client must be the currently-assigned user of
12093 * this VI (see MC_CMD_SET_VI_USER).
12094 */
12095#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12
12096#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
12097/* There will be more flags here. */
12098#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16
12099#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
12100#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16
12101#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
12102#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
12103#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_OFST 16
12104#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1
12105#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1
12106#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_OFST 16
12107#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2
12108#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
12109#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_OFST 16
12110#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3
12111#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
12112#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_OFST 16
12113#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
12114#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
12115#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16
12116#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8
12117#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
12118#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_OFST 16
12119#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9
12120#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1
12121#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_OFST 16
12122#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
12123#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
12124#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16
12125#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
12126#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
12127#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_OFST 16
12128#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12
12129#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1
12130#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_OFST 16
12131#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13
12132#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1
12133#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_OFST 16
12134#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 14
12135#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1
12136#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_OFST 16
12137#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_LBN 15
12138#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_WIDTH 1
12139#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_OFST 16
12140#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_LBN 16
12141#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_WIDTH 1
12142#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_OFST 16
12143#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_LBN 17
12144#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_ABS_TARGET_EVQ_WIDTH 1
12145/* Owner ID to use if in buffer mode (zero if physical) */
12146#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20
12147#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
12148/* The port ID associated with the v-adaptor which should contain this DMAQ. */
12149#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24
12150#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4
12151/* 64-bit address of 4k of 4k-aligned host memory buffer */
12152#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28
12153#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8
12154#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28
12155#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LEN 4
12156#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LBN 224
12157#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_WIDTH 32
12158#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
12159#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LEN 4
12160#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LBN 256
12161#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_WIDTH 32
12162#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 0
12163#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
12164#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 64
12165/* Flags related to Qbb flow control mode. */
12166#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540
12167#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
12168#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_OFST 540
12169#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
12170#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1
12171#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_OFST 540
12172#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1
12173#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3
12174
12175/* MC_CMD_INIT_TXQ_OUT msgresponse */
12176#define MC_CMD_INIT_TXQ_OUT_LEN 0
12177
12178
12179/***********************************/
12180/* MC_CMD_FINI_EVQ
12181 * Teardown an EVQ.
12182 *
12183 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first
12184 * or the operation will fail with EBUSY
12185 */
12186#define MC_CMD_FINI_EVQ 0x83
12187#undef MC_CMD_0x83_PRIVILEGE_CTG
12188
12189#define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12190
12191/* MC_CMD_FINI_EVQ_IN msgrequest */
12192#define MC_CMD_FINI_EVQ_IN_LEN 4
12193/* Instance of EVQ to destroy. Should be the same instance as that previously
12194 * passed to INIT_EVQ
12195 */
12196#define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
12197#define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
12198
12199/* MC_CMD_FINI_EVQ_OUT msgresponse */
12200#define MC_CMD_FINI_EVQ_OUT_LEN 0
12201
12202
12203/***********************************/
12204/* MC_CMD_FINI_RXQ
12205 * Teardown a RXQ.
12206 */
12207#define MC_CMD_FINI_RXQ 0x84
12208#undef MC_CMD_0x84_PRIVILEGE_CTG
12209
12210#define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12211
12212/* MC_CMD_FINI_RXQ_IN msgrequest */
12213#define MC_CMD_FINI_RXQ_IN_LEN 4
12214/* Instance of RXQ to destroy */
12215#define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
12216#define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4
12217
12218/* MC_CMD_FINI_RXQ_OUT msgresponse */
12219#define MC_CMD_FINI_RXQ_OUT_LEN 0
12220
12221
12222/***********************************/
12223/* MC_CMD_FINI_TXQ
12224 * Teardown a TXQ.
12225 */
12226#define MC_CMD_FINI_TXQ 0x85
12227#undef MC_CMD_0x85_PRIVILEGE_CTG
12228
12229#define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12230
12231/* MC_CMD_FINI_TXQ_IN msgrequest */
12232#define MC_CMD_FINI_TXQ_IN_LEN 4
12233/* Instance of TXQ to destroy */
12234#define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
12235#define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4
12236
12237/* MC_CMD_FINI_TXQ_OUT msgresponse */
12238#define MC_CMD_FINI_TXQ_OUT_LEN 0
12239
12240
12241/***********************************/
12242/* MC_CMD_DRIVER_EVENT
12243 * Generate an event on an EVQ belonging to the function issuing the command.
12244 */
12245#define MC_CMD_DRIVER_EVENT 0x86
12246#undef MC_CMD_0x86_PRIVILEGE_CTG
12247
12248#define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12249
12250/* MC_CMD_DRIVER_EVENT_IN msgrequest */
12251#define MC_CMD_DRIVER_EVENT_IN_LEN 12
12252/* Handle of target EVQ */
12253#define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
12254#define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4
12255/* Bits 0 - 63 of event */
12256#define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
12257#define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
12258#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
12259#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LEN 4
12260#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LBN 32
12261#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_WIDTH 32
12262#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
12263#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LEN 4
12264#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LBN 64
12265#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_WIDTH 32
12266
12267/* MC_CMD_DRIVER_EVENT_OUT msgresponse */
12268#define MC_CMD_DRIVER_EVENT_OUT_LEN 0
12269
12270
12271/***********************************/
12272/* MC_CMD_PROXY_CMD
12273 * Execute an arbitrary MCDI command on behalf of a different function, subject
12274 * to security restrictions. The command to be proxied follows immediately
12275 * afterward in the host buffer (or on the UART). This command supercedes
12276 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
12277 */
12278#define MC_CMD_PROXY_CMD 0x5b
12279#undef MC_CMD_0x5b_PRIVILEGE_CTG
12280
12281#define MC_CMD_0x5b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
12282
12283/* MC_CMD_PROXY_CMD_IN msgrequest */
12284#define MC_CMD_PROXY_CMD_IN_LEN 4
12285/* The handle of the target function. */
12286#define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
12287#define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4
12288#define MC_CMD_PROXY_CMD_IN_TARGET_PF_OFST 0
12289#define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
12290#define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16
12291#define MC_CMD_PROXY_CMD_IN_TARGET_VF_OFST 0
12292#define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16
12293#define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16
12294#define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
12295
12296/* MC_CMD_PROXY_CMD_OUT msgresponse */
12297#define MC_CMD_PROXY_CMD_OUT_LEN 0
12298
12299
12300/***********************************/
12301/* MC_CMD_FILTER_OP
12302 * Multiplexed MCDI call for filter operations
12303 */
12304#define MC_CMD_FILTER_OP 0x8a
12305#undef MC_CMD_0x8a_PRIVILEGE_CTG
12306
12307#define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
12308
12309/* MC_CMD_FILTER_OP_IN msgrequest */
12310#define MC_CMD_FILTER_OP_IN_LEN 108
12311/* identifies the type of operation requested */
12312#define MC_CMD_FILTER_OP_IN_OP_OFST 0
12313#define MC_CMD_FILTER_OP_IN_OP_LEN 4
12314/* enum: single-recipient filter insert */
12315#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
12316/* enum: single-recipient filter remove */
12317#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
12318/* enum: multi-recipient filter subscribe */
12319#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
12320/* enum: multi-recipient filter unsubscribe */
12321#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
12322/* enum: replace one recipient with another (warning - the filter handle may
12323 * change)
12324 */
12325#define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
12326/* filter handle (for remove / unsubscribe operations) */
12327#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
12328#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
12329#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
12330#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LEN 4
12331#define MC_CMD_FILTER_OP_IN_HANDLE_LO_LBN 32
12332#define MC_CMD_FILTER_OP_IN_HANDLE_LO_WIDTH 32
12333#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
12334#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LEN 4
12335#define MC_CMD_FILTER_OP_IN_HANDLE_HI_LBN 64
12336#define MC_CMD_FILTER_OP_IN_HANDLE_HI_WIDTH 32
12337/* The port ID associated with the v-adaptor which should contain this filter.
12338 */
12339#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
12340#define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4
12341/* fields to include in match criteria */
12342#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16
12343#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
12344#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_OFST 16
12345#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
12346#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
12347#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_OFST 16
12348#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
12349#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
12350#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_OFST 16
12351#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
12352#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
12353#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_OFST 16
12354#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
12355#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
12356#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_OFST 16
12357#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
12358#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
12359#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_OFST 16
12360#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
12361#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
12362#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_OFST 16
12363#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
12364#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
12365#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_OFST 16
12366#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
12367#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
12368#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_OFST 16
12369#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
12370#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
12371#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_OFST 16
12372#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
12373#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
12374#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_OFST 16
12375#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
12376#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
12377#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_OFST 16
12378#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
12379#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
12380#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_OFST 16
12381#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_LBN 29
12382#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 1
12383#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
12384#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
12385#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
12386#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
12387#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
12388#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
12389/* receive destination */
12390#define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20
12391#define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
12392/* enum: drop packets */
12393#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
12394/* enum: receive to host */
12395#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
12396/* enum: receive to MC */
12397#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
12398/* enum: loop back to TXDP 0 */
12399#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
12400/* enum: loop back to TXDP 1 */
12401#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
12402/* receive queue handle (for multiple queue modes, this is the base queue) */
12403#define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24
12404#define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
12405/* receive mode */
12406#define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28
12407#define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
12408/* enum: receive to just the specified queue */
12409#define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
12410/* enum: receive to multiple queues using RSS context */
12411#define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
12412/* enum: receive to multiple queues using .1p mapping */
12413#define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
12414/* enum: install a filter entry that will never match; for test purposes only
12415 */
12416#define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12417/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
12418 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
12419 * MC_CMD_DOT1P_MAPPING_ALLOC.
12420 */
12421#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32
12422#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4
12423/* transmit domain (reserved; set to 0) */
12424#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36
12425#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4
12426/* transmit destination (either set the MAC and/or PM bits for explicit
12427 * control, or set this field to TX_DEST_DEFAULT for sensible default
12428 * behaviour)
12429 */
12430#define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40
12431#define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
12432/* enum: request default behaviour (based on filter type) */
12433#define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
12434#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_OFST 40
12435#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
12436#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
12437#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_OFST 40
12438#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
12439#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
12440/* source MAC address to match (as bytes in network order) */
12441#define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44
12442#define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
12443/* source port to match (as bytes in network order) */
12444#define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50
12445#define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
12446/* destination MAC address to match (as bytes in network order) */
12447#define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52
12448#define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
12449/* destination port to match (as bytes in network order) */
12450#define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58
12451#define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
12452/* Ethernet type to match (as bytes in network order) */
12453#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60
12454#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
12455/* Inner VLAN tag to match (as bytes in network order) */
12456#define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62
12457#define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
12458/* Outer VLAN tag to match (as bytes in network order) */
12459#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64
12460#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
12461/* IP protocol to match (in low byte; set high byte to 0) */
12462#define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66
12463#define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
12464/* Firmware defined register 0 to match (reserved; set to 0) */
12465#define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68
12466#define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4
12467/* Firmware defined register 1 to match (reserved; set to 0) */
12468#define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72
12469#define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4
12470/* source IP address to match (as bytes in network order; set last 12 bytes to
12471 * 0 for IPv4 address)
12472 */
12473#define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76
12474#define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
12475/* destination IP address to match (as bytes in network order; set last 12
12476 * bytes to 0 for IPv4 address)
12477 */
12478#define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92
12479#define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
12480
12481/* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to
12482 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is
12483 * supported on Medford only).
12484 */
12485#define MC_CMD_FILTER_OP_EXT_IN_LEN 172
12486/* identifies the type of operation requested */
12487#define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
12488#define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4
12489/* Enum values, see field(s): */
12490/* MC_CMD_FILTER_OP_IN/OP */
12491/* filter handle (for remove / unsubscribe operations) */
12492#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
12493#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8
12494#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
12495#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LEN 4
12496#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LBN 32
12497#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_WIDTH 32
12498#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8
12499#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LEN 4
12500#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LBN 64
12501#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_WIDTH 32
12502/* The port ID associated with the v-adaptor which should contain this filter.
12503 */
12504#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12
12505#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4
12506/* fields to include in match criteria */
12507#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16
12508#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
12509#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_OFST 16
12510#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
12511#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1
12512#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_OFST 16
12513#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1
12514#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1
12515#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_OFST 16
12516#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2
12517#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1
12518#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_OFST 16
12519#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3
12520#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1
12521#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_OFST 16
12522#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
12523#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1
12524#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_OFST 16
12525#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5
12526#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1
12527#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_OFST 16
12528#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6
12529#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1
12530#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_OFST 16
12531#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7
12532#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1
12533#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_OFST 16
12534#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8
12535#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1
12536#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_OFST 16
12537#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9
12538#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1
12539#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_OFST 16
12540#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10
12541#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1
12542#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_OFST 16
12543#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11
12544#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1
12545#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_OFST 16
12546#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12
12547#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1
12548#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_OFST 16
12549#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13
12550#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1
12551#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_OFST 16
12552#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14
12553#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
12554#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_OFST 16
12555#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15
12556#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
12557#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_OFST 16
12558#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16
12559#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1
12560#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_OFST 16
12561#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17
12562#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1
12563#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_OFST 16
12564#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
12565#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
12566#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_OFST 16
12567#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19
12568#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
12569#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_OFST 16
12570#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
12571#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
12572#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_OFST 16
12573#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21
12574#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
12575#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_OFST 16
12576#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22
12577#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1
12578#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_OFST 16
12579#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23
12580#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1
12581#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16
12582#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
12583#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
12584#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16
12585#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
12586#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
12587#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_OFST 16
12588#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_LBN 29
12589#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 1
12590#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
12591#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
12592#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
12593#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
12594#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
12595#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
12596/* receive destination */
12597#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20
12598#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
12599/* enum: drop packets */
12600#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
12601/* enum: receive to host */
12602#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
12603/* enum: receive to MC */
12604#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
12605/* enum: loop back to TXDP 0 */
12606#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
12607/* enum: loop back to TXDP 1 */
12608#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
12609/* receive queue handle (for multiple queue modes, this is the base queue) */
12610#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24
12611#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
12612/* receive mode */
12613#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28
12614#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
12615/* enum: receive to just the specified queue */
12616#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
12617/* enum: receive to multiple queues using RSS context */
12618#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
12619/* enum: receive to multiple queues using .1p mapping */
12620#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
12621/* enum: install a filter entry that will never match; for test purposes only
12622 */
12623#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12624/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
12625 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
12626 * MC_CMD_DOT1P_MAPPING_ALLOC.
12627 */
12628#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32
12629#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4
12630/* transmit domain (reserved; set to 0) */
12631#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36
12632#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4
12633/* transmit destination (either set the MAC and/or PM bits for explicit
12634 * control, or set this field to TX_DEST_DEFAULT for sensible default
12635 * behaviour)
12636 */
12637#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40
12638#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
12639/* enum: request default behaviour (based on filter type) */
12640#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
12641#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_OFST 40
12642#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
12643#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
12644#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_OFST 40
12645#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
12646#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1
12647/* source MAC address to match (as bytes in network order) */
12648#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44
12649#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6
12650/* source port to match (as bytes in network order) */
12651#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50
12652#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2
12653/* destination MAC address to match (as bytes in network order) */
12654#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52
12655#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6
12656/* destination port to match (as bytes in network order) */
12657#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58
12658#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2
12659/* Ethernet type to match (as bytes in network order) */
12660#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60
12661#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2
12662/* Inner VLAN tag to match (as bytes in network order) */
12663#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62
12664#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2
12665/* Outer VLAN tag to match (as bytes in network order) */
12666#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64
12667#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2
12668/* IP protocol to match (in low byte; set high byte to 0) */
12669#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66
12670#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2
12671/* Firmware defined register 0 to match (reserved; set to 0) */
12672#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68
12673#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4
12674/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
12675 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
12676 * VXLAN/NVGRE, or 1 for Geneve)
12677 */
12678#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72
12679#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
12680#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_OFST 72
12681#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
12682#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24
12683#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_OFST 72
12684#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24
12685#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8
12686/* enum: Match VXLAN traffic with this VNI */
12687#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
12688/* enum: Match Geneve traffic with this VNI */
12689#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
12690/* enum: Reserved for experimental development use */
12691#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
12692#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_OFST 72
12693#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
12694#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24
12695#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_OFST 72
12696#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24
12697#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8
12698/* enum: Match NVGRE traffic with this VSID */
12699#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
12700/* source IP address to match (as bytes in network order; set last 12 bytes to
12701 * 0 for IPv4 address)
12702 */
12703#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76
12704#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16
12705/* destination IP address to match (as bytes in network order; set last 12
12706 * bytes to 0 for IPv4 address)
12707 */
12708#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92
12709#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16
12710/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
12711 * order)
12712 */
12713#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108
12714#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6
12715/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
12716#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114
12717#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2
12718/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
12719 * network order)
12720 */
12721#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116
12722#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6
12723/* VXLAN/NVGRE inner frame destination port to match (as bytes in network
12724 * order)
12725 */
12726#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122
12727#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2
12728/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
12729 */
12730#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124
12731#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2
12732/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
12733 */
12734#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126
12735#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2
12736/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
12737 */
12738#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128
12739#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2
12740/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
12741 * 0)
12742 */
12743#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130
12744#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2
12745/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
12746 * to 0)
12747 */
12748#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132
12749#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4
12750/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
12751 * to 0)
12752 */
12753#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136
12754#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4
12755/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
12756 * order; set last 12 bytes to 0 for IPv4 address)
12757 */
12758#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140
12759#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16
12760/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
12761 * order; set last 12 bytes to 0 for IPv4 address)
12762 */
12763#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156
12764#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16
12765
12766/* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional
12767 * filter actions for EF100. Some of these actions are also supported on EF10,
12768 * for Intel's DPDK (Data Plane Development Kit, dpdk.org) via its rte_flow
12769 * API. In the latter case, this extension is only useful with the sfc_efx
12770 * driver included as part of DPDK, used in conjunction with the dpdk datapath
12771 * firmware variant.
12772 */
12773#define MC_CMD_FILTER_OP_V3_IN_LEN 180
12774/* identifies the type of operation requested */
12775#define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0
12776#define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4
12777/* Enum values, see field(s): */
12778/* MC_CMD_FILTER_OP_IN/OP */
12779/* filter handle (for remove / unsubscribe operations) */
12780#define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
12781#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8
12782#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
12783#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LEN 4
12784#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LBN 32
12785#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_WIDTH 32
12786#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8
12787#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LEN 4
12788#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LBN 64
12789#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_WIDTH 32
12790/* The port ID associated with the v-adaptor which should contain this filter.
12791 */
12792#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12
12793#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4
12794/* fields to include in match criteria */
12795#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16
12796#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
12797#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_OFST 16
12798#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
12799#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1
12800#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_OFST 16
12801#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1
12802#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1
12803#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_OFST 16
12804#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2
12805#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1
12806#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_OFST 16
12807#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3
12808#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1
12809#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_OFST 16
12810#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
12811#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1
12812#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_OFST 16
12813#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5
12814#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1
12815#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_OFST 16
12816#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6
12817#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1
12818#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_OFST 16
12819#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7
12820#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1
12821#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_OFST 16
12822#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8
12823#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1
12824#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_OFST 16
12825#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9
12826#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1
12827#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_OFST 16
12828#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10
12829#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1
12830#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_OFST 16
12831#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11
12832#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1
12833#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_OFST 16
12834#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12
12835#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1
12836#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_OFST 16
12837#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13
12838#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1
12839#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_OFST 16
12840#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14
12841#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
12842#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_OFST 16
12843#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15
12844#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
12845#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_OFST 16
12846#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16
12847#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1
12848#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_OFST 16
12849#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17
12850#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1
12851#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_OFST 16
12852#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
12853#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
12854#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_OFST 16
12855#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19
12856#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
12857#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_OFST 16
12858#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
12859#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
12860#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_OFST 16
12861#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21
12862#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
12863#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_OFST 16
12864#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22
12865#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1
12866#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_OFST 16
12867#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23
12868#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1
12869#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16
12870#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
12871#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
12872#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16
12873#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
12874#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
12875#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_OFST 16
12876#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_LBN 29
12877#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_IPV4_MCAST_DST_WIDTH 1
12878#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
12879#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
12880#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
12881#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
12882#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
12883#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
12884/* receive destination */
12885#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20
12886#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
12887/* enum: drop packets */
12888#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
12889/* enum: receive to host */
12890#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
12891/* enum: receive to MC */
12892#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
12893/* enum: loop back to TXDP 0 */
12894#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
12895/* enum: loop back to TXDP 1 */
12896#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
12897/* receive queue handle (for multiple queue modes, this is the base queue) */
12898#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24
12899#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
12900/* receive mode */
12901#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28
12902#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
12903/* enum: receive to just the specified queue */
12904#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
12905/* enum: receive to multiple queues using RSS context */
12906#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
12907/* enum: receive to multiple queues using .1p mapping */
12908#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
12909/* enum: install a filter entry that will never match; for test purposes only
12910 */
12911#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12912/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
12913 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
12914 * MC_CMD_DOT1P_MAPPING_ALLOC.
12915 */
12916#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 32
12917#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4
12918/* transmit domain (reserved; set to 0) */
12919#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 36
12920#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4
12921/* transmit destination (either set the MAC and/or PM bits for explicit
12922 * control, or set this field to TX_DEST_DEFAULT for sensible default
12923 * behaviour)
12924 */
12925#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40
12926#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
12927/* enum: request default behaviour (based on filter type) */
12928#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
12929#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_OFST 40
12930#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
12931#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1
12932#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_OFST 40
12933#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1
12934#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1
12935/* source MAC address to match (as bytes in network order) */
12936#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 44
12937#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 6
12938/* source port to match (as bytes in network order) */
12939#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 50
12940#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 2
12941/* destination MAC address to match (as bytes in network order) */
12942#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 52
12943#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 6
12944/* destination port to match (as bytes in network order) */
12945#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 58
12946#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 2
12947/* Ethernet type to match (as bytes in network order) */
12948#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 60
12949#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 2
12950/* Inner VLAN tag to match (as bytes in network order) */
12951#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 62
12952#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 2
12953/* Outer VLAN tag to match (as bytes in network order) */
12954#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 64
12955#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 2
12956/* IP protocol to match (in low byte; set high byte to 0) */
12957#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 66
12958#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 2
12959/* Firmware defined register 0 to match (reserved; set to 0) */
12960#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 68
12961#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4
12962/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
12963 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
12964 * VXLAN/NVGRE, or 1 for Geneve)
12965 */
12966#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72
12967#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
12968#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_OFST 72
12969#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
12970#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24
12971#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_OFST 72
12972#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24
12973#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8
12974/* enum: Match VXLAN traffic with this VNI */
12975#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
12976/* enum: Match Geneve traffic with this VNI */
12977#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
12978/* enum: Reserved for experimental development use */
12979#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
12980#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_OFST 72
12981#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
12982#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24
12983#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_OFST 72
12984#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24
12985#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8
12986/* enum: Match NVGRE traffic with this VSID */
12987#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
12988/* source IP address to match (as bytes in network order; set last 12 bytes to
12989 * 0 for IPv4 address)
12990 */
12991#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 76
12992#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 16
12993/* destination IP address to match (as bytes in network order; set last 12
12994 * bytes to 0 for IPv4 address)
12995 */
12996#define MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 92
12997#define MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 16
12998/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
12999 * order)
13000 */
13001#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 108
13002#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 6
13003/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
13004#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 114
13005#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 2
13006/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
13007 * network order)
13008 */
13009#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 116
13010#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 6
13011/* VXLAN/NVGRE inner frame destination port to match (as bytes in network
13012 * order)
13013 */
13014#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 122
13015#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 2
13016/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
13017 */
13018#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 124
13019#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 2
13020/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
13021 */
13022#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 126
13023#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 2
13024/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
13025 */
13026#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 128
13027#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 2
13028/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
13029 * 0)
13030 */
13031#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 130
13032#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 2
13033/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
13034 * to 0)
13035 */
13036#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 132
13037#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4
13038/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
13039 * to 0)
13040 */
13041#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 136
13042#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4
13043/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
13044 * order; set last 12 bytes to 0 for IPv4 address)
13045 */
13046#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 140
13047#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 16
13048/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
13049 * order; set last 12 bytes to 0 for IPv4 address)
13050 */
13051#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156
13052#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16
13053/* Flags controlling mutations of the packet and/or metadata when the filter is
13054 * matched. The user_mark and user_flag fields' logic is as follows: if
13055 * (req.MATCH_BITOR_FLAG == 1) user_flag = req.MATCH_SET_FLAG bit_or user_flag;
13056 * else user_flag = req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark
13057 * = 0; else if (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK
13058 * bit_or user_mark; else user_mark = req.MATCH_SET_MARK; N.B. These flags
13059 * overlap with the MATCH_ACTION field, which is deprecated in favour of this
13060 * field. For the cases where these flags induce a valid encoding of the
13061 * MATCH_ACTION field, the semantics agree.
13062 */
13063#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_OFST 172
13064#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_LEN 4
13065#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_OFST 172
13066#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_LBN 0
13067#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_WIDTH 1
13068#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_OFST 172
13069#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_LBN 1
13070#define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_MARK_WIDTH 1
13071#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_OFST 172
13072#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_LBN 2
13073#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_FLAG_WIDTH 1
13074#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_OFST 172
13075#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_LBN 3
13076#define MC_CMD_FILTER_OP_V3_IN_MATCH_BITOR_MARK_WIDTH 1
13077#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_OFST 172
13078#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_LBN 4
13079#define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_WIDTH 1
13080/* Deprecated: the overlapping MATCH_ACTION_FLAGS field exposes all of the
13081 * functionality of this field in an ABI-backwards-compatible manner, and
13082 * should be used instead. Any future extensions should be made to the
13083 * MATCH_ACTION_FLAGS field, and not to this field. Set an action for all
13084 * packets matching this filter. The DPDK driver and (on EF10) dpdk f/w variant
13085 * use their own specific delivery structures, which are documented in the DPDK
13086 * Firmware Driver Interface (SF-119419-TC). Requesting anything other than
13087 * MATCH_ACTION_NONE on an EF10 NIC running another f/w variant will cause the
13088 * filter insertion to fail with ENOTSUP.
13089 */
13090#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172
13091#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
13092/* enum: do nothing extra */
13093#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
13094/* enum: Set the match flag in the packet prefix for packets matching the
13095 * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
13096 * support the DPDK rte_flow "FLAG" action.
13097 */
13098#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
13099/* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching
13100 * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
13101 * support the DPDK rte_flow "MARK" action.
13102 */
13103#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
13104/* the mark value for MATCH_ACTION_MARK. Requesting a value larger than the
13105 * maximum (obtained from MC_CMD_GET_CAPABILITIES_V5/FILTER_ACTION_MARK_MAX)
13106 * will cause the filter insertion to fail with EINVAL.
13107 */
13108#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176
13109#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
13110
13111/* MC_CMD_FILTER_OP_OUT msgresponse */
13112#define MC_CMD_FILTER_OP_OUT_LEN 12
13113/* identifies the type of operation requested */
13114#define MC_CMD_FILTER_OP_OUT_OP_OFST 0
13115#define MC_CMD_FILTER_OP_OUT_OP_LEN 4
13116/* Enum values, see field(s): */
13117/* MC_CMD_FILTER_OP_IN/OP */
13118/* Returned filter handle (for insert / subscribe operations). Note that these
13119 * handles should be considered opaque to the host, although a value of
13120 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
13121 */
13122#define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
13123#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
13124#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
13125#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LEN 4
13126#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LBN 32
13127#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_WIDTH 32
13128#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
13129#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LEN 4
13130#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LBN 64
13131#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_WIDTH 32
13132/* enum: guaranteed invalid filter handle (low 32 bits) */
13133#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
13134/* enum: guaranteed invalid filter handle (high 32 bits) */
13135#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
13136
13137/* MC_CMD_FILTER_OP_EXT_OUT msgresponse */
13138#define MC_CMD_FILTER_OP_EXT_OUT_LEN 12
13139/* identifies the type of operation requested */
13140#define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
13141#define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4
13142/* Enum values, see field(s): */
13143/* MC_CMD_FILTER_OP_EXT_IN/OP */
13144/* Returned filter handle (for insert / subscribe operations). Note that these
13145 * handles should be considered opaque to the host, although a value of
13146 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
13147 */
13148#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
13149#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8
13150#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
13151#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LEN 4
13152#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LBN 32
13153#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_WIDTH 32
13154#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8
13155#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LEN 4
13156#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LBN 64
13157#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_WIDTH 32
13158/* Enum values, see field(s): */
13159/* MC_CMD_FILTER_OP_OUT/HANDLE */
13160
13161
13162/***********************************/
13163/* MC_CMD_GET_PARSER_DISP_INFO
13164 * Get information related to the parser-dispatcher subsystem
13165 */
13166#define MC_CMD_GET_PARSER_DISP_INFO 0xe4
13167#undef MC_CMD_0xe4_PRIVILEGE_CTG
13168
13169#define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13170
13171/* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */
13172#define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
13173/* identifies the type of operation requested */
13174#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
13175#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
13176/* enum: read the list of supported RX filter matches */
13177#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
13178/* enum: read flags indicating restrictions on filter insertion for the calling
13179 * client
13180 */
13181#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
13182/* enum: read properties relating to security rules (Medford-only; for use by
13183 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
13184 */
13185#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
13186/* enum: read the list of supported RX filter matches for VXLAN/NVGRE
13187 * encapsulated frames, which follow a different match sequence to normal
13188 * frames (Medford only)
13189 */
13190#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
13191/* enum: read the list of supported matches for the encapsulation detection
13192 * rules inserted by MC_CMD_VNIC_ENCAP_RULE_ADD. (ef100 and later)
13193 */
13194#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5
13195/* enum: read the supported encapsulation types for the VNIC */
13196#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_TYPES 0x6
13197/* enum: read the supported RX filter matches for low-latency queues (as
13198 * allocated by MC_CMD_ALLOC_LL_QUEUES)
13199 */
13200#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_LL_RX_MATCHES 0x7
13201
13202/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
13203#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
13204#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252
13205#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX_MCDI2 1020
13206#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
13207#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
13208/* identifies the type of operation requested */
13209#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
13210#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
13211/* Enum values, see field(s): */
13212/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
13213/* number of supported match types */
13214#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
13215#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4
13216/* array of supported match types (valid MATCH_FIELDS values for
13217 * MC_CMD_FILTER_OP) sorted in decreasing priority order
13218 */
13219#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8
13220#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
13221#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
13222#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61
13223#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253
13224
13225/* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */
13226#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8
13227/* identifies the type of operation requested */
13228#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
13229#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4
13230/* Enum values, see field(s): */
13231/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
13232/* bitfield of filter insertion restrictions */
13233#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
13234#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
13235#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4
13236#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
13237#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1
13238
13239/* MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT msgresponse:
13240 * GET_PARSER_DISP_INFO response format for OP_GET_SECURITY_RULE_INFO.
13241 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
13242 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
13243 * been used in any released code and may change during development. This note
13244 * will be removed once it is regarded as stable.
13245 */
13246#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_LEN 36
13247/* identifies the type of operation requested */
13248#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0
13249#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_LEN 4
13250/* Enum values, see field(s): */
13251/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
13252/* a version number representing the set of rule lookups that are implemented
13253 * by the currently running firmware
13254 */
13255#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4
13256#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_LEN 4
13257/* enum: implements lookup sequences described in SF-114946-SW draft C */
13258#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0
13259/* the number of nodes in the subnet map */
13260#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8
13261#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_LEN 4
13262/* the number of entries in one subnet map node */
13263#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_OFST 12
13264#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_LEN 4
13265/* minimum valid value for a subnet ID in a subnet map leaf */
13266#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_OFST 16
13267#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_LEN 4
13268/* maximum valid value for a subnet ID in a subnet map leaf */
13269#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_OFST 20
13270#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_LEN 4
13271/* the number of entries in the local and remote port range maps */
13272#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_OFST 24
13273#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_LEN 4
13274/* minimum valid value for a portrange ID in a port range map leaf */
13275#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_OFST 28
13276#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_LEN 4
13277/* maximum valid value for a portrange ID in a port range map leaf */
13278#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32
13279#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_LEN 4
13280
13281/* MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT msgresponse: This response is
13282 * returned if a MC_CMD_GET_PARSER_DISP_INFO_IN request is sent with OP value
13283 * OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES. It contains information about the
13284 * supported match types that can be used in the encapsulation detection rules
13285 * inserted by MC_CMD_VNIC_ENCAP_RULE_ADD.
13286 */
13287#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMIN 8
13288#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX 252
13289#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX_MCDI2 1020
13290#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))
13291#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
13292/* The op code OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES is returned. */
13293#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 0
13294#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4
13295/* Enum values, see field(s): */
13296/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
13297/* number of supported match types */
13298#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4
13299#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4
13300/* array of supported match types (valid MATCH_FLAGS values for
13301 * MC_CMD_VNIC_ENCAP_RULE_ADD) sorted in decreasing priority order
13302 */
13303#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_OFST 8
13304#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4
13305#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 0
13306#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM 61
13307#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253
13308
13309/* MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT msgresponse: Returns
13310 * the supported encapsulation types for the VNIC
13311 */
13312#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_LEN 8
13313/* The op code OP_GET_SUPPORTED_VNIC_ENCAP_TYPES is returned */
13314#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_OFST 0
13315#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_LEN 4
13316/* Enum values, see field(s): */
13317/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
13318#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
13319#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
13320#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_OFST 4
13321#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_LBN 0
13322#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
13323#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_OFST 4
13324#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_LBN 1
13325#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
13326#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_OFST 4
13327#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_LBN 2
13328#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
13329#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_OFST 4
13330#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_LBN 3
13331#define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
13332
13333
13334/***********************************/
13335/* MC_CMD_GET_PORT_ASSIGNMENT
13336 * Get port assignment for current PCI function.
13337 */
13338#define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
13339#undef MC_CMD_0xb8_PRIVILEGE_CTG
13340
13341#define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13342
13343/* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
13344#define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
13345
13346/* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
13347#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
13348/* Identifies the port assignment for this function. On EF100, it is possible
13349 * for the function to have no network port assigned (either because it is not
13350 * yet configured, or assigning a port to a given function personality makes no
13351 * sense - e.g. virtio-blk), in which case the return value is NULL_PORT.
13352 */
13353#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
13354#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
13355/* enum: Special value to indicate no port is assigned to a function. */
13356#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_NULL_PORT 0xffffffff
13357
13358
13359/***********************************/
13360/* MC_CMD_ALLOC_VIS
13361 * Allocate VIs for current PCI function.
13362 */
13363#define MC_CMD_ALLOC_VIS 0x8b
13364#undef MC_CMD_0x8b_PRIVILEGE_CTG
13365
13366#define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13367
13368/* MC_CMD_ALLOC_VIS_IN msgrequest */
13369#define MC_CMD_ALLOC_VIS_IN_LEN 8
13370/* The minimum number of VIs that is acceptable */
13371#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
13372#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4
13373/* The maximum number of VIs that would be useful */
13374#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
13375#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
13376
13377/* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
13378 * Use extended version in new code.
13379 */
13380#define MC_CMD_ALLOC_VIS_OUT_LEN 8
13381/* The number of VIs allocated on this function */
13382#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
13383#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4
13384/* The base absolute VI number allocated to this function. Required to
13385 * correctly interpret wakeup events.
13386 */
13387#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
13388#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
13389
13390/* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */
13391#define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12
13392/* The number of VIs allocated on this function */
13393#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
13394#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4
13395/* The base absolute VI number allocated to this function. Required to
13396 * correctly interpret wakeup events.
13397 */
13398#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
13399#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4
13400/* Function's port vi_shift value (always 0 on Huntington) */
13401#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8
13402#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
13403
13404
13405/***********************************/
13406/* MC_CMD_FREE_VIS
13407 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,
13408 * but not freed.
13409 */
13410#define MC_CMD_FREE_VIS 0x8c
13411#undef MC_CMD_0x8c_PRIVILEGE_CTG
13412
13413#define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13414
13415/* MC_CMD_FREE_VIS_IN msgrequest */
13416#define MC_CMD_FREE_VIS_IN_LEN 0
13417
13418/* MC_CMD_FREE_VIS_OUT msgresponse */
13419#define MC_CMD_FREE_VIS_OUT_LEN 0
13420
13421
13422/***********************************/
13423/* MC_CMD_GET_SRIOV_CFG
13424 * Get SRIOV config for this PF.
13425 */
13426#define MC_CMD_GET_SRIOV_CFG 0xba
13427#undef MC_CMD_0xba_PRIVILEGE_CTG
13428
13429#define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13430
13431/* MC_CMD_GET_SRIOV_CFG_IN msgrequest */
13432#define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
13433
13434/* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */
13435#define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20
13436/* Number of VFs currently enabled. */
13437#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
13438#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4
13439/* Max number of VFs before sriov stride and offset may need to be changed. */
13440#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
13441#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
13442#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
13443#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
13444#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_OFST 8
13445#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
13446#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
13447/* RID offset of first VF from PF. */
13448#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12
13449#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4
13450/* RID offset of each subsequent VF from the previous. */
13451#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16
13452#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
13453
13454
13455/***********************************/
13456/* MC_CMD_ALLOC_PIOBUF
13457 * Allocate a push I/O buffer for later use with a tx queue.
13458 */
13459#define MC_CMD_ALLOC_PIOBUF 0x8f
13460#undef MC_CMD_0x8f_PRIVILEGE_CTG
13461
13462#define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
13463
13464/* MC_CMD_ALLOC_PIOBUF_IN msgrequest */
13465#define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
13466
13467/* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */
13468#define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
13469/* Handle for allocated push I/O buffer. */
13470#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
13471#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4
13472
13473
13474/***********************************/
13475/* MC_CMD_FREE_PIOBUF
13476 * Free a push I/O buffer.
13477 */
13478#define MC_CMD_FREE_PIOBUF 0x90
13479#undef MC_CMD_0x90_PRIVILEGE_CTG
13480
13481#define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
13482
13483/* MC_CMD_FREE_PIOBUF_IN msgrequest */
13484#define MC_CMD_FREE_PIOBUF_IN_LEN 4
13485/* Handle for allocated push I/O buffer. */
13486#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
13487#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
13488
13489/* MC_CMD_FREE_PIOBUF_OUT msgresponse */
13490#define MC_CMD_FREE_PIOBUF_OUT_LEN 0
13491
13492
13493/***********************************/
13494/* MC_CMD_GET_VI_TLP_PROCESSING
13495 * Get TLP steering and ordering information for a VI. The caller must have the
13496 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
13497 * an ancestor of the current user (see MC_CMD_SET_VI_USER).
13498 */
13499#define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
13500#undef MC_CMD_0xb0_PRIVILEGE_CTG
13501
13502#define MC_CMD_0xb0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13503
13504/* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */
13505#define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
13506/* Queue handle, encodes queue type and VI number to get information for. */
13507#define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
13508#define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
13509
13510/* MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT msgresponse: This message has the same
13511 * layout as GET_VI_TLP_PROCESSING_OUT, but with corrected field ordering to
13512 * simplify use in drivers
13513 */
13514#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_LEN 4
13515#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_DATA_OFST 0
13516#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_DATA_LEN 4
13517#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_OFST 0
13518#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_LBN 0
13519#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_WIDTH 8
13520#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_OFST 0
13521#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_LBN 8
13522#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_WIDTH 8
13523#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_OFST 0
13524#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_LBN 16
13525#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_WIDTH 1
13526#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_OFST 0
13527#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_LBN 16
13528#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_WIDTH 1
13529#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_OFST 0
13530#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_LBN 17
13531#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_WIDTH 1
13532#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_OFST 0
13533#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_LBN 18
13534#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_WIDTH 1
13535#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_OFST 0
13536#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_LBN 19
13537#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_WIDTH 1
13538#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_OFST 0
13539#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_LBN 20
13540#define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_WIDTH 1
13541
13542
13543/***********************************/
13544/* MC_CMD_SET_VI_TLP_PROCESSING
13545 * Set TLP steering and ordering information for a VI. The caller must have the
13546 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
13547 * an ancestor of the current user (see MC_CMD_SET_VI_USER). Note that LL
13548 * queues require this to be called after allocation but before initialisation
13549 * of the queue. TLP options of a queue are fixed after queue is initialised,
13550 * with the values set to current global value or they can be overriden using
13551 * this command. At LL queue allocation, all overrides are cleared.
13552 */
13553#define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
13554#undef MC_CMD_0xb1_PRIVILEGE_CTG
13555
13556#define MC_CMD_0xb1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13557
13558/* MC_CMD_SET_VI_TLP_PROCESSING_V2_IN msgrequest: This message has the same
13559 * layout as SET_VI_TLP_PROCESSING_OUT, but with corrected field ordering to
13560 * simplify use in drivers.
13561 */
13562#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_LEN 8
13563/* Queue handle, encodes queue type and VI number to set information for. */
13564#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_INSTANCE_OFST 0
13565#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_INSTANCE_LEN 4
13566#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_DATA_OFST 4
13567#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_DATA_LEN 4
13568#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_OFST 4
13569#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_LBN 0
13570#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_WIDTH 8
13571#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_OFST 4
13572#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_LBN 8
13573#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_WIDTH 8
13574#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_OFST 4
13575#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_LBN 16
13576#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_WIDTH 1
13577#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_OFST 4
13578#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_LBN 16
13579#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_WIDTH 1
13580#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_OFST 4
13581#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_LBN 17
13582#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_WIDTH 1
13583#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_OFST 4
13584#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_LBN 18
13585#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_WIDTH 1
13586#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_OFST 4
13587#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_LBN 19
13588#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_WIDTH 1
13589#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_OFST 4
13590#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_LBN 20
13591#define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_WIDTH 1
13592
13593/* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */
13594#define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
13595
13596
13597/***********************************/
13598/* MC_CMD_GET_CAPABILITIES
13599 * Get device capabilities. This is supplementary to the MC_CMD_GET_BOARD_CFG
13600 * command, and intended to reference inherent device capabilities as opposed
13601 * to current NVRAM config.
13602 */
13603#define MC_CMD_GET_CAPABILITIES 0xbe
13604#undef MC_CMD_0xbe_PRIVILEGE_CTG
13605
13606#define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
13607
13608/* MC_CMD_GET_CAPABILITIES_IN msgrequest */
13609#define MC_CMD_GET_CAPABILITIES_IN_LEN 0
13610
13611/* MC_CMD_GET_CAPABILITIES_OUT msgresponse */
13612#define MC_CMD_GET_CAPABILITIES_OUT_LEN 20
13613/* First word of flags. */
13614#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
13615#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
13616#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 0
13617#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3
13618#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1
13619#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 0
13620#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
13621#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1
13622#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 0
13623#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5
13624#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1
13625#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13626#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
13627#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
13628#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 0
13629#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7
13630#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
13631#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13632#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8
13633#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
13634#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 0
13635#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9
13636#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1
13637#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13638#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
13639#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
13640#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13641#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
13642#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
13643#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13644#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
13645#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
13646#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 0
13647#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13
13648#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
13649#define MC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 0
13650#define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14
13651#define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1
13652#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13653#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
13654#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
13655#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 0
13656#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16
13657#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1
13658#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 0
13659#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17
13660#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1
13661#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 0
13662#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18
13663#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1
13664#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 0
13665#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19
13666#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
13667#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 0
13668#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20
13669#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
13670#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 0
13671#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21
13672#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
13673#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 0
13674#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22
13675#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
13676#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 0
13677#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23
13678#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
13679#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 0
13680#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24
13681#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
13682#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 0
13683#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25
13684#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
13685#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 0
13686#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26
13687#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
13688#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13689#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27
13690#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
13691#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 0
13692#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28
13693#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1
13694#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13695#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
13696#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
13697#define MC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 0
13698#define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30
13699#define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1
13700#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 0
13701#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31
13702#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1
13703/* RxDPCPU firmware id. */
13704#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
13705#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2
13706/* enum: Standard RXDP firmware */
13707#define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
13708/* enum: Low latency RXDP firmware */
13709#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
13710/* enum: Packed stream RXDP firmware */
13711#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
13712/* enum: Rules engine RXDP firmware */
13713#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
13714/* enum: DPDK RXDP firmware */
13715#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
13716/* enum: BIST RXDP firmware */
13717#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
13718/* enum: RXDP Test firmware image 1 */
13719#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13720/* enum: RXDP Test firmware image 2 */
13721#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13722/* enum: RXDP Test firmware image 3 */
13723#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13724/* enum: RXDP Test firmware image 4 */
13725#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13726/* enum: RXDP Test firmware image 5 */
13727#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
13728/* enum: RXDP Test firmware image 6 */
13729#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13730/* enum: RXDP Test firmware image 7 */
13731#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13732/* enum: RXDP Test firmware image 8 */
13733#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13734/* enum: RXDP Test firmware image 9 */
13735#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13736/* enum: RXDP Test firmware image 10 */
13737#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
13738/* TxDPCPU firmware id. */
13739#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6
13740#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2
13741/* enum: Standard TXDP firmware */
13742#define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
13743/* enum: Low latency TXDP firmware */
13744#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
13745/* enum: High packet rate TXDP firmware */
13746#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
13747/* enum: Rules engine TXDP firmware */
13748#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
13749/* enum: DPDK TXDP firmware */
13750#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
13751/* enum: BIST TXDP firmware */
13752#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
13753/* enum: TXDP Test firmware image 1 */
13754#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13755/* enum: TXDP Test firmware image 2 */
13756#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13757/* enum: TXDP CSR bus test firmware */
13758#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
13759#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8
13760#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2
13761#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_OFST 8
13762#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
13763#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12
13764#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_OFST 8
13765#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12
13766#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13767/* enum: reserved value - do not use (may indicate alternative interpretation
13768 * of REV field in future)
13769 */
13770#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
13771/* enum: Trivial RX PD firmware for early Huntington development (Huntington
13772 * development only)
13773 */
13774#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
13775/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
13776 */
13777#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13778/* enum: RX PD firmware with approximately Siena-compatible behaviour
13779 * (Huntington development only)
13780 */
13781#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
13782/* enum: Full featured RX PD production firmware */
13783#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
13784/* enum: (deprecated original name for the FULL_FEATURED variant) */
13785#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
13786/* enum: siena_compat variant RX PD firmware using PM rather than MAC
13787 * (Huntington development only)
13788 */
13789#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13790/* enum: Low latency RX PD production firmware */
13791#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
13792/* enum: Packed stream RX PD production firmware */
13793#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
13794/* enum: RX PD firmware handling layer 2 only for high packet rate performance
13795 * tests (Medford development only)
13796 */
13797#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
13798/* enum: Rules engine RX PD production firmware */
13799#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
13800/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13801#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
13802/* enum: DPDK RX PD production firmware */
13803#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
13804/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
13805#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13806/* enum: RX PD firmware parsing but not filtering network overlay tunnel
13807 * encapsulations (Medford development only)
13808 */
13809#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
13810#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10
13811#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2
13812#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_OFST 10
13813#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
13814#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12
13815#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_OFST 10
13816#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12
13817#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
13818/* enum: reserved value - do not use (may indicate alternative interpretation
13819 * of REV field in future)
13820 */
13821#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
13822/* enum: Trivial TX PD firmware for early Huntington development (Huntington
13823 * development only)
13824 */
13825#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
13826/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
13827 */
13828#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13829/* enum: TX PD firmware with approximately Siena-compatible behaviour
13830 * (Huntington development only)
13831 */
13832#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
13833/* enum: Full featured TX PD production firmware */
13834#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
13835/* enum: (deprecated original name for the FULL_FEATURED variant) */
13836#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
13837/* enum: siena_compat variant TX PD firmware using PM rather than MAC
13838 * (Huntington development only)
13839 */
13840#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13841#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
13842/* enum: TX PD firmware handling layer 2 only for high packet rate performance
13843 * tests (Medford development only)
13844 */
13845#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
13846/* enum: Rules engine TX PD production firmware */
13847#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
13848/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13849#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
13850/* enum: DPDK TX PD production firmware */
13851#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
13852/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
13853#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13854/* Hardware capabilities of NIC */
13855#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12
13856#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
13857/* Licensed capabilities */
13858#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16
13859#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4
13860
13861/* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */
13862#define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
13863
13864/* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */
13865#define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72
13866/* First word of flags. */
13867#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
13868#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
13869#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 0
13870#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3
13871#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1
13872#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 0
13873#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
13874#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1
13875#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 0
13876#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5
13877#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1
13878#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13879#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
13880#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
13881#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 0
13882#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7
13883#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
13884#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13885#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8
13886#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
13887#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 0
13888#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9
13889#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1
13890#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13891#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
13892#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
13893#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13894#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
13895#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
13896#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13897#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
13898#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
13899#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 0
13900#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13
13901#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
13902#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 0
13903#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14
13904#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1
13905#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13906#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
13907#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
13908#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 0
13909#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16
13910#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1
13911#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 0
13912#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17
13913#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1
13914#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 0
13915#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18
13916#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1
13917#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 0
13918#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19
13919#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1
13920#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 0
13921#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20
13922#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1
13923#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 0
13924#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21
13925#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1
13926#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 0
13927#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22
13928#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1
13929#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 0
13930#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23
13931#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1
13932#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 0
13933#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24
13934#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1
13935#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 0
13936#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25
13937#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1
13938#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 0
13939#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26
13940#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1
13941#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13942#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27
13943#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
13944#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 0
13945#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28
13946#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1
13947#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13948#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
13949#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
13950#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 0
13951#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30
13952#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1
13953#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 0
13954#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31
13955#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1
13956/* RxDPCPU firmware id. */
13957#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
13958#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2
13959/* enum: Standard RXDP firmware */
13960#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
13961/* enum: Low latency RXDP firmware */
13962#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
13963/* enum: Packed stream RXDP firmware */
13964#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
13965/* enum: Rules engine RXDP firmware */
13966#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
13967/* enum: DPDK RXDP firmware */
13968#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
13969/* enum: BIST RXDP firmware */
13970#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
13971/* enum: RXDP Test firmware image 1 */
13972#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13973/* enum: RXDP Test firmware image 2 */
13974#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13975/* enum: RXDP Test firmware image 3 */
13976#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13977/* enum: RXDP Test firmware image 4 */
13978#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13979/* enum: RXDP Test firmware image 5 */
13980#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
13981/* enum: RXDP Test firmware image 6 */
13982#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13983/* enum: RXDP Test firmware image 7 */
13984#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13985/* enum: RXDP Test firmware image 8 */
13986#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13987/* enum: RXDP Test firmware image 9 */
13988#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13989/* enum: RXDP Test firmware image 10 */
13990#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
13991/* TxDPCPU firmware id. */
13992#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6
13993#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2
13994/* enum: Standard TXDP firmware */
13995#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
13996/* enum: Low latency TXDP firmware */
13997#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
13998/* enum: High packet rate TXDP firmware */
13999#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
14000/* enum: Rules engine TXDP firmware */
14001#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
14002/* enum: DPDK TXDP firmware */
14003#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
14004/* enum: BIST TXDP firmware */
14005#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
14006/* enum: TXDP Test firmware image 1 */
14007#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14008/* enum: TXDP Test firmware image 2 */
14009#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14010/* enum: TXDP CSR bus test firmware */
14011#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
14012#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8
14013#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2
14014#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_OFST 8
14015#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
14016#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12
14017#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_OFST 8
14018#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12
14019#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14020/* enum: reserved value - do not use (may indicate alternative interpretation
14021 * of REV field in future)
14022 */
14023#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
14024/* enum: Trivial RX PD firmware for early Huntington development (Huntington
14025 * development only)
14026 */
14027#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14028/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
14029 */
14030#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14031/* enum: RX PD firmware with approximately Siena-compatible behaviour
14032 * (Huntington development only)
14033 */
14034#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14035/* enum: Full featured RX PD production firmware */
14036#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14037/* enum: (deprecated original name for the FULL_FEATURED variant) */
14038#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14039/* enum: siena_compat variant RX PD firmware using PM rather than MAC
14040 * (Huntington development only)
14041 */
14042#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14043/* enum: Low latency RX PD production firmware */
14044#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14045/* enum: Packed stream RX PD production firmware */
14046#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14047/* enum: RX PD firmware handling layer 2 only for high packet rate performance
14048 * tests (Medford development only)
14049 */
14050#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14051/* enum: Rules engine RX PD production firmware */
14052#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14053/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14054#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14055/* enum: DPDK RX PD production firmware */
14056#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
14057/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14058#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14059/* enum: RX PD firmware parsing but not filtering network overlay tunnel
14060 * encapsulations (Medford development only)
14061 */
14062#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14063#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10
14064#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2
14065#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_OFST 10
14066#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
14067#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12
14068#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_OFST 10
14069#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12
14070#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14071/* enum: reserved value - do not use (may indicate alternative interpretation
14072 * of REV field in future)
14073 */
14074#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
14075/* enum: Trivial TX PD firmware for early Huntington development (Huntington
14076 * development only)
14077 */
14078#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14079/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
14080 */
14081#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14082/* enum: TX PD firmware with approximately Siena-compatible behaviour
14083 * (Huntington development only)
14084 */
14085#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14086/* enum: Full featured TX PD production firmware */
14087#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14088/* enum: (deprecated original name for the FULL_FEATURED variant) */
14089#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14090/* enum: siena_compat variant TX PD firmware using PM rather than MAC
14091 * (Huntington development only)
14092 */
14093#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14094#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14095/* enum: TX PD firmware handling layer 2 only for high packet rate performance
14096 * tests (Medford development only)
14097 */
14098#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14099/* enum: Rules engine TX PD production firmware */
14100#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14101/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14102#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14103/* enum: DPDK TX PD production firmware */
14104#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
14105/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14106#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14107/* Hardware capabilities of NIC */
14108#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12
14109#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
14110/* Licensed capabilities */
14111#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16
14112#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4
14113/* Second word of flags. Not present on older firmware (check the length). */
14114#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20
14115#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
14116#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_OFST 20
14117#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
14118#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1
14119#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_OFST 20
14120#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1
14121#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14122#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_OFST 20
14123#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2
14124#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1
14125#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_OFST 20
14126#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3
14127#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1
14128#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_OFST 20
14129#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
14130#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1
14131#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_OFST 20
14132#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5
14133#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14134#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
14135#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
14136#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14137#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
14138#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
14139#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14140#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_OFST 20
14141#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7
14142#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1
14143#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_OFST 20
14144#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8
14145#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14146#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_OFST 20
14147#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9
14148#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1
14149#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_OFST 20
14150#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10
14151#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1
14152#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_OFST 20
14153#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11
14154#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1
14155#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
14156#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
14157#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14158#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_OFST 20
14159#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13
14160#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1
14161#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_OFST 20
14162#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14
14163#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1
14164#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_OFST 20
14165#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15
14166#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1
14167#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_OFST 20
14168#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16
14169#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1
14170#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_OFST 20
14171#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17
14172#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1
14173#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
14174#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
14175#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14176#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_OFST 20
14177#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19
14178#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1
14179#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_OFST 20
14180#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20
14181#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1
14182#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
14183#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
14184#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14185#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
14186#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
14187#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14188#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_OFST 20
14189#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22
14190#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1
14191#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
14192#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
14193#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14194#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_OFST 20
14195#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 24
14196#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1
14197#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_OFST 20
14198#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_LBN 25
14199#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 1
14200#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
14201#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
14202#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14203#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
14204#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
14205#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14206#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_OFST 20
14207#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_LBN 28
14208#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_WIDTH 1
14209#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_OFST 20
14210#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_LBN 29
14211#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_WIDTH 1
14212#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_OFST 20
14213#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_LBN 30
14214#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_WIDTH 1
14215#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
14216#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
14217#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14218/* Number of FATSOv2 contexts per datapath supported by this NIC (when
14219 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14220 */
14221#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
14222#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
14223/* One byte per PF containing the number of the external port assigned to this
14224 * PF, indexed by PF number. Special values indicate that a PF is either not
14225 * present or not assigned.
14226 */
14227#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
14228#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14229#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
14230/* enum: The caller is not permitted to access information on this PF. */
14231#define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
14232/* enum: PF does not exist. */
14233#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
14234/* enum: PF does exist but is not assigned to any external port. */
14235#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
14236/* enum: This value indicates that PF is assigned, but it cannot be expressed
14237 * in this field. It is intended for a possible future situation where a more
14238 * complex scheme of PFs to ports mapping is being used. The future driver
14239 * should look for a new field supporting the new scheme. The current/old
14240 * driver should treat this value as PF_NOT_ASSIGNED.
14241 */
14242#define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14243/* One byte per PF containing the number of its VFs, indexed by PF number. A
14244 * special value indicates that a PF is not present.
14245 */
14246#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42
14247#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1
14248#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16
14249/* enum: The caller is not permitted to access information on this PF. */
14250/* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
14251/* enum: PF does not exist. */
14252/* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
14253/* Number of VIs available for external ports 0-3. For devices with more than
14254 * four ports, the remainder are in NUM_VIS_PER_PORT2 in
14255 * GET_CAPABILITIES_V12_OUT.
14256 */
14257#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58
14258#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2
14259#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
14260/* Size of RX descriptor cache expressed as binary logarithm The actual size
14261 * equals (2 ^ RX_DESC_CACHE_SIZE)
14262 */
14263#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66
14264#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1
14265/* Size of TX descriptor cache expressed as binary logarithm The actual size
14266 * equals (2 ^ TX_DESC_CACHE_SIZE)
14267 */
14268#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67
14269#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1
14270/* Total number of available PIO buffers */
14271#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68
14272#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2
14273/* Size of a single PIO buffer */
14274#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70
14275#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2
14276
14277/* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */
14278#define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76
14279/* First word of flags. */
14280#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
14281#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
14282#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 0
14283#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3
14284#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1
14285#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 0
14286#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
14287#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1
14288#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 0
14289#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5
14290#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1
14291#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14292#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
14293#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14294#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 0
14295#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7
14296#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14297#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14298#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8
14299#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14300#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 0
14301#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9
14302#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1
14303#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14304#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
14305#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14306#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14307#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
14308#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14309#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14310#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
14311#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14312#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 0
14313#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13
14314#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14315#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 0
14316#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14
14317#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1
14318#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14319#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
14320#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14321#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 0
14322#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16
14323#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1
14324#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 0
14325#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17
14326#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1
14327#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 0
14328#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18
14329#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1
14330#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 0
14331#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19
14332#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1
14333#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 0
14334#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20
14335#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1
14336#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 0
14337#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21
14338#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1
14339#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 0
14340#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22
14341#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1
14342#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 0
14343#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23
14344#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1
14345#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 0
14346#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24
14347#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1
14348#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 0
14349#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25
14350#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1
14351#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 0
14352#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26
14353#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1
14354#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14355#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27
14356#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
14357#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 0
14358#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28
14359#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1
14360#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14361#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
14362#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
14363#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 0
14364#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30
14365#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1
14366#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 0
14367#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31
14368#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1
14369/* RxDPCPU firmware id. */
14370#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
14371#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2
14372/* enum: Standard RXDP firmware */
14373#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
14374/* enum: Low latency RXDP firmware */
14375#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
14376/* enum: Packed stream RXDP firmware */
14377#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
14378/* enum: Rules engine RXDP firmware */
14379#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
14380/* enum: DPDK RXDP firmware */
14381#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
14382/* enum: BIST RXDP firmware */
14383#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
14384/* enum: RXDP Test firmware image 1 */
14385#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14386/* enum: RXDP Test firmware image 2 */
14387#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14388/* enum: RXDP Test firmware image 3 */
14389#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14390/* enum: RXDP Test firmware image 4 */
14391#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14392/* enum: RXDP Test firmware image 5 */
14393#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
14394/* enum: RXDP Test firmware image 6 */
14395#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14396/* enum: RXDP Test firmware image 7 */
14397#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14398/* enum: RXDP Test firmware image 8 */
14399#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14400/* enum: RXDP Test firmware image 9 */
14401#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14402/* enum: RXDP Test firmware image 10 */
14403#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
14404/* TxDPCPU firmware id. */
14405#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6
14406#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2
14407/* enum: Standard TXDP firmware */
14408#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
14409/* enum: Low latency TXDP firmware */
14410#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
14411/* enum: High packet rate TXDP firmware */
14412#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
14413/* enum: Rules engine TXDP firmware */
14414#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
14415/* enum: DPDK TXDP firmware */
14416#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
14417/* enum: BIST TXDP firmware */
14418#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
14419/* enum: TXDP Test firmware image 1 */
14420#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14421/* enum: TXDP Test firmware image 2 */
14422#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14423/* enum: TXDP CSR bus test firmware */
14424#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
14425#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8
14426#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2
14427#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_OFST 8
14428#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
14429#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12
14430#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_OFST 8
14431#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12
14432#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14433/* enum: reserved value - do not use (may indicate alternative interpretation
14434 * of REV field in future)
14435 */
14436#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
14437/* enum: Trivial RX PD firmware for early Huntington development (Huntington
14438 * development only)
14439 */
14440#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14441/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
14442 */
14443#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14444/* enum: RX PD firmware with approximately Siena-compatible behaviour
14445 * (Huntington development only)
14446 */
14447#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14448/* enum: Full featured RX PD production firmware */
14449#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14450/* enum: (deprecated original name for the FULL_FEATURED variant) */
14451#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14452/* enum: siena_compat variant RX PD firmware using PM rather than MAC
14453 * (Huntington development only)
14454 */
14455#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14456/* enum: Low latency RX PD production firmware */
14457#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14458/* enum: Packed stream RX PD production firmware */
14459#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14460/* enum: RX PD firmware handling layer 2 only for high packet rate performance
14461 * tests (Medford development only)
14462 */
14463#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14464/* enum: Rules engine RX PD production firmware */
14465#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14466/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14467#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14468/* enum: DPDK RX PD production firmware */
14469#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
14470/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14471#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14472/* enum: RX PD firmware parsing but not filtering network overlay tunnel
14473 * encapsulations (Medford development only)
14474 */
14475#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14476#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10
14477#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2
14478#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_OFST 10
14479#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
14480#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12
14481#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_OFST 10
14482#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12
14483#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14484/* enum: reserved value - do not use (may indicate alternative interpretation
14485 * of REV field in future)
14486 */
14487#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
14488/* enum: Trivial TX PD firmware for early Huntington development (Huntington
14489 * development only)
14490 */
14491#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14492/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
14493 */
14494#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14495/* enum: TX PD firmware with approximately Siena-compatible behaviour
14496 * (Huntington development only)
14497 */
14498#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14499/* enum: Full featured TX PD production firmware */
14500#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14501/* enum: (deprecated original name for the FULL_FEATURED variant) */
14502#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14503/* enum: siena_compat variant TX PD firmware using PM rather than MAC
14504 * (Huntington development only)
14505 */
14506#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14507#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14508/* enum: TX PD firmware handling layer 2 only for high packet rate performance
14509 * tests (Medford development only)
14510 */
14511#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14512/* enum: Rules engine TX PD production firmware */
14513#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14514/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14515#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14516/* enum: DPDK TX PD production firmware */
14517#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
14518/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14519#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14520/* Hardware capabilities of NIC */
14521#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12
14522#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
14523/* Licensed capabilities */
14524#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16
14525#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4
14526/* Second word of flags. Not present on older firmware (check the length). */
14527#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20
14528#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
14529#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_OFST 20
14530#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
14531#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1
14532#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_OFST 20
14533#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1
14534#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14535#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_OFST 20
14536#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2
14537#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1
14538#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_OFST 20
14539#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3
14540#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1
14541#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_OFST 20
14542#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
14543#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1
14544#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_OFST 20
14545#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5
14546#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14547#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
14548#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
14549#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14550#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
14551#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
14552#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14553#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_OFST 20
14554#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7
14555#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1
14556#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_OFST 20
14557#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8
14558#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14559#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_OFST 20
14560#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9
14561#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1
14562#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_OFST 20
14563#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10
14564#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1
14565#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_OFST 20
14566#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11
14567#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1
14568#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
14569#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
14570#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14571#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_OFST 20
14572#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13
14573#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1
14574#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_OFST 20
14575#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14
14576#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1
14577#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_OFST 20
14578#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15
14579#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1
14580#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_OFST 20
14581#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16
14582#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1
14583#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_OFST 20
14584#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17
14585#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1
14586#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
14587#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
14588#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14589#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_OFST 20
14590#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19
14591#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1
14592#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_OFST 20
14593#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20
14594#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1
14595#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
14596#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
14597#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14598#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
14599#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
14600#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14601#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_OFST 20
14602#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22
14603#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1
14604#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
14605#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
14606#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14607#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_OFST 20
14608#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 24
14609#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1
14610#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_OFST 20
14611#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_LBN 25
14612#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 1
14613#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
14614#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
14615#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14616#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
14617#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
14618#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14619#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_OFST 20
14620#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_LBN 28
14621#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_WIDTH 1
14622#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_OFST 20
14623#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_LBN 29
14624#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_WIDTH 1
14625#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_OFST 20
14626#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_LBN 30
14627#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_WIDTH 1
14628#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
14629#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
14630#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14631/* Number of FATSOv2 contexts per datapath supported by this NIC (when
14632 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14633 */
14634#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
14635#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
14636/* One byte per PF containing the number of the external port assigned to this
14637 * PF, indexed by PF number. Special values indicate that a PF is either not
14638 * present or not assigned.
14639 */
14640#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
14641#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14642#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
14643/* enum: The caller is not permitted to access information on this PF. */
14644#define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
14645/* enum: PF does not exist. */
14646#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
14647/* enum: PF does exist but is not assigned to any external port. */
14648#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
14649/* enum: This value indicates that PF is assigned, but it cannot be expressed
14650 * in this field. It is intended for a possible future situation where a more
14651 * complex scheme of PFs to ports mapping is being used. The future driver
14652 * should look for a new field supporting the new scheme. The current/old
14653 * driver should treat this value as PF_NOT_ASSIGNED.
14654 */
14655#define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14656/* One byte per PF containing the number of its VFs, indexed by PF number. A
14657 * special value indicates that a PF is not present.
14658 */
14659#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42
14660#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1
14661#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16
14662/* enum: The caller is not permitted to access information on this PF. */
14663/* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
14664/* enum: PF does not exist. */
14665/* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
14666/* Number of VIs available for external ports 0-3. For devices with more than
14667 * four ports, the remainder are in NUM_VIS_PER_PORT2 in
14668 * GET_CAPABILITIES_V12_OUT.
14669 */
14670#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58
14671#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2
14672#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
14673/* Size of RX descriptor cache expressed as binary logarithm The actual size
14674 * equals (2 ^ RX_DESC_CACHE_SIZE)
14675 */
14676#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66
14677#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1
14678/* Size of TX descriptor cache expressed as binary logarithm The actual size
14679 * equals (2 ^ TX_DESC_CACHE_SIZE)
14680 */
14681#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67
14682#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1
14683/* Total number of available PIO buffers */
14684#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68
14685#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2
14686/* Size of a single PIO buffer */
14687#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70
14688#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2
14689/* On chips later than Medford the amount of address space assigned to each VI
14690 * is configurable. This is a global setting that the driver must query to
14691 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14692 * with 8k VI windows.
14693 */
14694#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72
14695#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1
14696/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14697 * CTPIO is not mapped.
14698 */
14699#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
14700/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14701#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
14702/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14703#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
14704/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
14705 * (SF-115995-SW) in the present configuration of firmware and port mode.
14706 */
14707#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
14708#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
14709/* Number of buffers per adapter that can be used for VFIFO Stuffing
14710 * (SF-115995-SW) in the present configuration of firmware and port mode.
14711 */
14712#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
14713#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
14714
14715/* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */
14716#define MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78
14717/* First word of flags. */
14718#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
14719#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
14720#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 0
14721#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3
14722#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1
14723#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 0
14724#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
14725#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1
14726#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 0
14727#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5
14728#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1
14729#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14730#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
14731#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14732#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 0
14733#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7
14734#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14735#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14736#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8
14737#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14738#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 0
14739#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9
14740#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1
14741#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14742#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
14743#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14744#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14745#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
14746#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14747#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14748#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
14749#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14750#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 0
14751#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13
14752#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14753#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 0
14754#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14
14755#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1
14756#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14757#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
14758#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14759#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 0
14760#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16
14761#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1
14762#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 0
14763#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17
14764#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1
14765#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 0
14766#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18
14767#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1
14768#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 0
14769#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19
14770#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1
14771#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 0
14772#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20
14773#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1
14774#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 0
14775#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21
14776#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1
14777#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 0
14778#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22
14779#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1
14780#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 0
14781#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23
14782#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1
14783#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 0
14784#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24
14785#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1
14786#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 0
14787#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25
14788#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1
14789#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 0
14790#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26
14791#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1
14792#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14793#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27
14794#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
14795#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 0
14796#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28
14797#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1
14798#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14799#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
14800#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
14801#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 0
14802#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30
14803#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1
14804#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 0
14805#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31
14806#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1
14807/* RxDPCPU firmware id. */
14808#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
14809#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2
14810/* enum: Standard RXDP firmware */
14811#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
14812/* enum: Low latency RXDP firmware */
14813#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
14814/* enum: Packed stream RXDP firmware */
14815#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
14816/* enum: Rules engine RXDP firmware */
14817#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
14818/* enum: DPDK RXDP firmware */
14819#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
14820/* enum: BIST RXDP firmware */
14821#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
14822/* enum: RXDP Test firmware image 1 */
14823#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14824/* enum: RXDP Test firmware image 2 */
14825#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14826/* enum: RXDP Test firmware image 3 */
14827#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14828/* enum: RXDP Test firmware image 4 */
14829#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14830/* enum: RXDP Test firmware image 5 */
14831#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
14832/* enum: RXDP Test firmware image 6 */
14833#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14834/* enum: RXDP Test firmware image 7 */
14835#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14836/* enum: RXDP Test firmware image 8 */
14837#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14838/* enum: RXDP Test firmware image 9 */
14839#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14840/* enum: RXDP Test firmware image 10 */
14841#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
14842/* TxDPCPU firmware id. */
14843#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6
14844#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2
14845/* enum: Standard TXDP firmware */
14846#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
14847/* enum: Low latency TXDP firmware */
14848#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
14849/* enum: High packet rate TXDP firmware */
14850#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
14851/* enum: Rules engine TXDP firmware */
14852#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
14853/* enum: DPDK TXDP firmware */
14854#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
14855/* enum: BIST TXDP firmware */
14856#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
14857/* enum: TXDP Test firmware image 1 */
14858#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14859/* enum: TXDP Test firmware image 2 */
14860#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14861/* enum: TXDP CSR bus test firmware */
14862#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
14863#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8
14864#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2
14865#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_OFST 8
14866#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
14867#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12
14868#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_OFST 8
14869#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12
14870#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14871/* enum: reserved value - do not use (may indicate alternative interpretation
14872 * of REV field in future)
14873 */
14874#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
14875/* enum: Trivial RX PD firmware for early Huntington development (Huntington
14876 * development only)
14877 */
14878#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14879/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
14880 */
14881#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14882/* enum: RX PD firmware with approximately Siena-compatible behaviour
14883 * (Huntington development only)
14884 */
14885#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14886/* enum: Full featured RX PD production firmware */
14887#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14888/* enum: (deprecated original name for the FULL_FEATURED variant) */
14889#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14890/* enum: siena_compat variant RX PD firmware using PM rather than MAC
14891 * (Huntington development only)
14892 */
14893#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14894/* enum: Low latency RX PD production firmware */
14895#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14896/* enum: Packed stream RX PD production firmware */
14897#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14898/* enum: RX PD firmware handling layer 2 only for high packet rate performance
14899 * tests (Medford development only)
14900 */
14901#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14902/* enum: Rules engine RX PD production firmware */
14903#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14904/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14905#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14906/* enum: DPDK RX PD production firmware */
14907#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
14908/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14909#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14910/* enum: RX PD firmware parsing but not filtering network overlay tunnel
14911 * encapsulations (Medford development only)
14912 */
14913#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14914#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10
14915#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2
14916#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_OFST 10
14917#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
14918#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12
14919#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_OFST 10
14920#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12
14921#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14922/* enum: reserved value - do not use (may indicate alternative interpretation
14923 * of REV field in future)
14924 */
14925#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
14926/* enum: Trivial TX PD firmware for early Huntington development (Huntington
14927 * development only)
14928 */
14929#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14930/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
14931 */
14932#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14933/* enum: TX PD firmware with approximately Siena-compatible behaviour
14934 * (Huntington development only)
14935 */
14936#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14937/* enum: Full featured TX PD production firmware */
14938#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14939/* enum: (deprecated original name for the FULL_FEATURED variant) */
14940#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14941/* enum: siena_compat variant TX PD firmware using PM rather than MAC
14942 * (Huntington development only)
14943 */
14944#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14945#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14946/* enum: TX PD firmware handling layer 2 only for high packet rate performance
14947 * tests (Medford development only)
14948 */
14949#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14950/* enum: Rules engine TX PD production firmware */
14951#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14952/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14953#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14954/* enum: DPDK TX PD production firmware */
14955#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
14956/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14957#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14958/* Hardware capabilities of NIC */
14959#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12
14960#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
14961/* Licensed capabilities */
14962#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16
14963#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4
14964/* Second word of flags. Not present on older firmware (check the length). */
14965#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20
14966#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
14967#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_OFST 20
14968#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
14969#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1
14970#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_OFST 20
14971#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1
14972#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14973#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_OFST 20
14974#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2
14975#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1
14976#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_OFST 20
14977#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3
14978#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1
14979#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_OFST 20
14980#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
14981#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1
14982#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_OFST 20
14983#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5
14984#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14985#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
14986#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
14987#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14988#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
14989#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
14990#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14991#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_OFST 20
14992#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7
14993#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1
14994#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_OFST 20
14995#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8
14996#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14997#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_OFST 20
14998#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9
14999#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1
15000#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_OFST 20
15001#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10
15002#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1
15003#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_OFST 20
15004#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11
15005#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1
15006#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
15007#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
15008#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
15009#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_OFST 20
15010#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13
15011#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1
15012#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_OFST 20
15013#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14
15014#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1
15015#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_OFST 20
15016#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15
15017#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1
15018#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_OFST 20
15019#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16
15020#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1
15021#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_OFST 20
15022#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17
15023#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1
15024#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
15025#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
15026#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
15027#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_OFST 20
15028#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19
15029#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1
15030#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_OFST 20
15031#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20
15032#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1
15033#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
15034#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
15035#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
15036#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
15037#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
15038#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
15039#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_OFST 20
15040#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22
15041#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1
15042#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
15043#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
15044#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
15045#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_OFST 20
15046#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 24
15047#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1
15048#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_OFST 20
15049#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_LBN 25
15050#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 1
15051#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
15052#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
15053#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
15054#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
15055#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
15056#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
15057#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_OFST 20
15058#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_LBN 28
15059#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_WIDTH 1
15060#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_OFST 20
15061#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_LBN 29
15062#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_WIDTH 1
15063#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_OFST 20
15064#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_LBN 30
15065#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_WIDTH 1
15066#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
15067#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
15068#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
15069/* Number of FATSOv2 contexts per datapath supported by this NIC (when
15070 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
15071 */
15072#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
15073#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
15074/* One byte per PF containing the number of the external port assigned to this
15075 * PF, indexed by PF number. Special values indicate that a PF is either not
15076 * present or not assigned.
15077 */
15078#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
15079#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
15080#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
15081/* enum: The caller is not permitted to access information on this PF. */
15082#define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
15083/* enum: PF does not exist. */
15084#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
15085/* enum: PF does exist but is not assigned to any external port. */
15086#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
15087/* enum: This value indicates that PF is assigned, but it cannot be expressed
15088 * in this field. It is intended for a possible future situation where a more
15089 * complex scheme of PFs to ports mapping is being used. The future driver
15090 * should look for a new field supporting the new scheme. The current/old
15091 * driver should treat this value as PF_NOT_ASSIGNED.
15092 */
15093#define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15094/* One byte per PF containing the number of its VFs, indexed by PF number. A
15095 * special value indicates that a PF is not present.
15096 */
15097#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42
15098#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1
15099#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16
15100/* enum: The caller is not permitted to access information on this PF. */
15101/* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
15102/* enum: PF does not exist. */
15103/* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
15104/* Number of VIs available for external ports 0-3. For devices with more than
15105 * four ports, the remainder are in NUM_VIS_PER_PORT2 in
15106 * GET_CAPABILITIES_V12_OUT.
15107 */
15108#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58
15109#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2
15110#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
15111/* Size of RX descriptor cache expressed as binary logarithm The actual size
15112 * equals (2 ^ RX_DESC_CACHE_SIZE)
15113 */
15114#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66
15115#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1
15116/* Size of TX descriptor cache expressed as binary logarithm The actual size
15117 * equals (2 ^ TX_DESC_CACHE_SIZE)
15118 */
15119#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67
15120#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1
15121/* Total number of available PIO buffers */
15122#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68
15123#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2
15124/* Size of a single PIO buffer */
15125#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70
15126#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2
15127/* On chips later than Medford the amount of address space assigned to each VI
15128 * is configurable. This is a global setting that the driver must query to
15129 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15130 * with 8k VI windows.
15131 */
15132#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72
15133#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1
15134/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15135 * CTPIO is not mapped.
15136 */
15137#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
15138/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15139#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
15140/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15141#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
15142/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
15143 * (SF-115995-SW) in the present configuration of firmware and port mode.
15144 */
15145#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
15146#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
15147/* Number of buffers per adapter that can be used for VFIFO Stuffing
15148 * (SF-115995-SW) in the present configuration of firmware and port mode.
15149 */
15150#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
15151#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
15152/* Entry count in the MAC stats array, including the final GENERATION_END
15153 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
15154 * hold at least this many 64-bit stats values, if they wish to receive all
15155 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
15156 * stats array returned will be truncated.
15157 */
15158#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76
15159#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2
15160
15161/* MC_CMD_GET_CAPABILITIES_V5_OUT msgresponse */
15162#define MC_CMD_GET_CAPABILITIES_V5_OUT_LEN 84
15163/* First word of flags. */
15164#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0
15165#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4
15166#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 0
15167#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_LBN 3
15168#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 1
15169#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 0
15170#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4
15171#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 1
15172#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 0
15173#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_LBN 5
15174#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 1
15175#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
15176#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
15177#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
15178#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 0
15179#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_LBN 7
15180#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
15181#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 0
15182#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_LBN 8
15183#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
15184#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 0
15185#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_LBN 9
15186#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 1
15187#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
15188#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
15189#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
15190#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
15191#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
15192#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
15193#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
15194#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
15195#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
15196#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 0
15197#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_LBN 13
15198#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
15199#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 0
15200#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_LBN 14
15201#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 1
15202#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
15203#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
15204#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
15205#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 0
15206#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_LBN 16
15207#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 1
15208#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 0
15209#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_LBN 17
15210#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 1
15211#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 0
15212#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_LBN 18
15213#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 1
15214#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 0
15215#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_LBN 19
15216#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 1
15217#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 0
15218#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_LBN 20
15219#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 1
15220#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 0
15221#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_LBN 21
15222#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 1
15223#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 0
15224#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_LBN 22
15225#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 1
15226#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 0
15227#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_LBN 23
15228#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 1
15229#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 0
15230#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_LBN 24
15231#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 1
15232#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 0
15233#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_LBN 25
15234#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 1
15235#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 0
15236#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_LBN 26
15237#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 1
15238#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15239#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_LBN 27
15240#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
15241#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 0
15242#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_LBN 28
15243#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 1
15244#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15245#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
15246#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
15247#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 0
15248#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_LBN 30
15249#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 1
15250#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 0
15251#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_LBN 31
15252#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 1
15253/* RxDPCPU firmware id. */
15254#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4
15255#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_LEN 2
15256/* enum: Standard RXDP firmware */
15257#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0
15258/* enum: Low latency RXDP firmware */
15259#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1
15260/* enum: Packed stream RXDP firmware */
15261#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2
15262/* enum: Rules engine RXDP firmware */
15263#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5
15264/* enum: DPDK RXDP firmware */
15265#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6
15266/* enum: BIST RXDP firmware */
15267#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a
15268/* enum: RXDP Test firmware image 1 */
15269#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15270/* enum: RXDP Test firmware image 2 */
15271#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15272/* enum: RXDP Test firmware image 3 */
15273#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15274/* enum: RXDP Test firmware image 4 */
15275#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15276/* enum: RXDP Test firmware image 5 */
15277#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105
15278/* enum: RXDP Test firmware image 6 */
15279#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15280/* enum: RXDP Test firmware image 7 */
15281#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15282/* enum: RXDP Test firmware image 8 */
15283#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15284/* enum: RXDP Test firmware image 9 */
15285#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15286/* enum: RXDP Test firmware image 10 */
15287#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c
15288/* TxDPCPU firmware id. */
15289#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_OFST 6
15290#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_LEN 2
15291/* enum: Standard TXDP firmware */
15292#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0
15293/* enum: Low latency TXDP firmware */
15294#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1
15295/* enum: High packet rate TXDP firmware */
15296#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3
15297/* enum: Rules engine TXDP firmware */
15298#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5
15299/* enum: DPDK TXDP firmware */
15300#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6
15301/* enum: BIST TXDP firmware */
15302#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d
15303/* enum: TXDP Test firmware image 1 */
15304#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15305/* enum: TXDP Test firmware image 2 */
15306#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15307/* enum: TXDP CSR bus test firmware */
15308#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103
15309#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_OFST 8
15310#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_LEN 2
15311#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_OFST 8
15312#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0
15313#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_WIDTH 12
15314#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_OFST 8
15315#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_LBN 12
15316#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15317/* enum: reserved value - do not use (may indicate alternative interpretation
15318 * of REV field in future)
15319 */
15320#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0
15321/* enum: Trivial RX PD firmware for early Huntington development (Huntington
15322 * development only)
15323 */
15324#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
15325/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
15326 */
15327#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15328/* enum: RX PD firmware with approximately Siena-compatible behaviour
15329 * (Huntington development only)
15330 */
15331#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
15332/* enum: Full featured RX PD production firmware */
15333#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
15334/* enum: (deprecated original name for the FULL_FEATURED variant) */
15335#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3
15336/* enum: siena_compat variant RX PD firmware using PM rather than MAC
15337 * (Huntington development only)
15338 */
15339#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15340/* enum: Low latency RX PD production firmware */
15341#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
15342/* enum: Packed stream RX PD production firmware */
15343#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
15344/* enum: RX PD firmware handling layer 2 only for high packet rate performance
15345 * tests (Medford development only)
15346 */
15347#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
15348/* enum: Rules engine RX PD production firmware */
15349#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
15350/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15351#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9
15352/* enum: DPDK RX PD production firmware */
15353#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa
15354/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
15355#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15356/* enum: RX PD firmware parsing but not filtering network overlay tunnel
15357 * encapsulations (Medford development only)
15358 */
15359#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
15360#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_OFST 10
15361#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_LEN 2
15362#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_OFST 10
15363#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0
15364#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_WIDTH 12
15365#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_OFST 10
15366#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_LBN 12
15367#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15368/* enum: reserved value - do not use (may indicate alternative interpretation
15369 * of REV field in future)
15370 */
15371#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0
15372/* enum: Trivial TX PD firmware for early Huntington development (Huntington
15373 * development only)
15374 */
15375#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
15376/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
15377 */
15378#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15379/* enum: TX PD firmware with approximately Siena-compatible behaviour
15380 * (Huntington development only)
15381 */
15382#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
15383/* enum: Full featured TX PD production firmware */
15384#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
15385/* enum: (deprecated original name for the FULL_FEATURED variant) */
15386#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3
15387/* enum: siena_compat variant TX PD firmware using PM rather than MAC
15388 * (Huntington development only)
15389 */
15390#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15391#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
15392/* enum: TX PD firmware handling layer 2 only for high packet rate performance
15393 * tests (Medford development only)
15394 */
15395#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
15396/* enum: Rules engine TX PD production firmware */
15397#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
15398/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15399#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9
15400/* enum: DPDK TX PD production firmware */
15401#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa
15402/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
15403#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15404/* Hardware capabilities of NIC */
15405#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_OFST 12
15406#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4
15407/* Licensed capabilities */
15408#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_OFST 16
15409#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4
15410/* Second word of flags. Not present on older firmware (check the length). */
15411#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_OFST 20
15412#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4
15413#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_OFST 20
15414#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0
15415#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 1
15416#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_OFST 20
15417#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 1
15418#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 1
15419#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_OFST 20
15420#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_LBN 2
15421#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 1
15422#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_OFST 20
15423#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_LBN 3
15424#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 1
15425#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_OFST 20
15426#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4
15427#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 1
15428#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_OFST 20
15429#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_LBN 5
15430#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
15431#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
15432#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
15433#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
15434#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
15435#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
15436#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
15437#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_OFST 20
15438#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_LBN 7
15439#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 1
15440#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_OFST 20
15441#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_LBN 8
15442#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
15443#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_OFST 20
15444#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_LBN 9
15445#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 1
15446#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_OFST 20
15447#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_LBN 10
15448#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 1
15449#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_OFST 20
15450#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_LBN 11
15451#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 1
15452#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
15453#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
15454#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
15455#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_OFST 20
15456#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_LBN 13
15457#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 1
15458#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_OFST 20
15459#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_LBN 14
15460#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 1
15461#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_OFST 20
15462#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_LBN 15
15463#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 1
15464#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_OFST 20
15465#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_LBN 16
15466#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 1
15467#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_OFST 20
15468#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_LBN 17
15469#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 1
15470#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
15471#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
15472#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
15473#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_OFST 20
15474#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_LBN 19
15475#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 1
15476#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_OFST 20
15477#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_LBN 20
15478#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 1
15479#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
15480#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
15481#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
15482#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
15483#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
15484#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
15485#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_OFST 20
15486#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_LBN 22
15487#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 1
15488#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
15489#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
15490#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
15491#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_OFST 20
15492#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_LBN 24
15493#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 1
15494#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_OFST 20
15495#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_LBN 25
15496#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 1
15497#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
15498#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
15499#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
15500#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
15501#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
15502#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
15503#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_OFST 20
15504#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_LBN 28
15505#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_WIDTH 1
15506#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_OFST 20
15507#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_LBN 29
15508#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_WIDTH 1
15509#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_OFST 20
15510#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_LBN 30
15511#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_WIDTH 1
15512#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
15513#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
15514#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
15515/* Number of FATSOv2 contexts per datapath supported by this NIC (when
15516 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
15517 */
15518#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
15519#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
15520/* One byte per PF containing the number of the external port assigned to this
15521 * PF, indexed by PF number. Special values indicate that a PF is either not
15522 * present or not assigned.
15523 */
15524#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
15525#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
15526#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
15527/* enum: The caller is not permitted to access information on this PF. */
15528#define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff
15529/* enum: PF does not exist. */
15530#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe
15531/* enum: PF does exist but is not assigned to any external port. */
15532#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd
15533/* enum: This value indicates that PF is assigned, but it cannot be expressed
15534 * in this field. It is intended for a possible future situation where a more
15535 * complex scheme of PFs to ports mapping is being used. The future driver
15536 * should look for a new field supporting the new scheme. The current/old
15537 * driver should treat this value as PF_NOT_ASSIGNED.
15538 */
15539#define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15540/* One byte per PF containing the number of its VFs, indexed by PF number. A
15541 * special value indicates that a PF is not present.
15542 */
15543#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_OFST 42
15544#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_LEN 1
15545#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_NUM 16
15546/* enum: The caller is not permitted to access information on this PF. */
15547/* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */
15548/* enum: PF does not exist. */
15549/* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */
15550/* Number of VIs available for external ports 0-3. For devices with more than
15551 * four ports, the remainder are in NUM_VIS_PER_PORT2 in
15552 * GET_CAPABILITIES_V12_OUT.
15553 */
15554#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 58
15555#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 2
15556#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4
15557/* Size of RX descriptor cache expressed as binary logarithm The actual size
15558 * equals (2 ^ RX_DESC_CACHE_SIZE)
15559 */
15560#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_OFST 66
15561#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_LEN 1
15562/* Size of TX descriptor cache expressed as binary logarithm The actual size
15563 * equals (2 ^ TX_DESC_CACHE_SIZE)
15564 */
15565#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_OFST 67
15566#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_LEN 1
15567/* Total number of available PIO buffers */
15568#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_OFST 68
15569#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_LEN 2
15570/* Size of a single PIO buffer */
15571#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_OFST 70
15572#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_LEN 2
15573/* On chips later than Medford the amount of address space assigned to each VI
15574 * is configurable. This is a global setting that the driver must query to
15575 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15576 * with 8k VI windows.
15577 */
15578#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_OFST 72
15579#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_LEN 1
15580/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15581 * CTPIO is not mapped.
15582 */
15583#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0
15584/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15585#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1
15586/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15587#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2
15588/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
15589 * (SF-115995-SW) in the present configuration of firmware and port mode.
15590 */
15591#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
15592#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
15593/* Number of buffers per adapter that can be used for VFIFO Stuffing
15594 * (SF-115995-SW) in the present configuration of firmware and port mode.
15595 */
15596#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
15597#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
15598/* Entry count in the MAC stats array, including the final GENERATION_END
15599 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
15600 * hold at least this many 64-bit stats values, if they wish to receive all
15601 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
15602 * stats array returned will be truncated.
15603 */
15604#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_OFST 76
15605#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_LEN 2
15606/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
15607 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
15608 */
15609#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_OFST 80
15610#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4
15611
15612/* MC_CMD_GET_CAPABILITIES_V6_OUT msgresponse */
15613#define MC_CMD_GET_CAPABILITIES_V6_OUT_LEN 148
15614/* First word of flags. */
15615#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 0
15616#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4
15617#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 0
15618#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_LBN 3
15619#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_WIDTH 1
15620#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 0
15621#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4
15622#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_WIDTH 1
15623#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 0
15624#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_LBN 5
15625#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_WIDTH 1
15626#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
15627#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
15628#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
15629#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 0
15630#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_LBN 7
15631#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
15632#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 0
15633#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_LBN 8
15634#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
15635#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 0
15636#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_LBN 9
15637#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_WIDTH 1
15638#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
15639#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
15640#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
15641#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
15642#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
15643#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
15644#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
15645#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
15646#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
15647#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 0
15648#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_LBN 13
15649#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
15650#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 0
15651#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_LBN 14
15652#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_WIDTH 1
15653#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
15654#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
15655#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
15656#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 0
15657#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_LBN 16
15658#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_WIDTH 1
15659#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 0
15660#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_LBN 17
15661#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_WIDTH 1
15662#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 0
15663#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_LBN 18
15664#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_WIDTH 1
15665#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 0
15666#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_LBN 19
15667#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_WIDTH 1
15668#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 0
15669#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_LBN 20
15670#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_WIDTH 1
15671#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 0
15672#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_LBN 21
15673#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_WIDTH 1
15674#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 0
15675#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_LBN 22
15676#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_WIDTH 1
15677#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 0
15678#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_LBN 23
15679#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_WIDTH 1
15680#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 0
15681#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_LBN 24
15682#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_WIDTH 1
15683#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 0
15684#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_LBN 25
15685#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_WIDTH 1
15686#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 0
15687#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_LBN 26
15688#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_WIDTH 1
15689#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15690#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_LBN 27
15691#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
15692#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 0
15693#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_LBN 28
15694#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_WIDTH 1
15695#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15696#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
15697#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
15698#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 0
15699#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_LBN 30
15700#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_WIDTH 1
15701#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 0
15702#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_LBN 31
15703#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_WIDTH 1
15704/* RxDPCPU firmware id. */
15705#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 4
15706#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_LEN 2
15707/* enum: Standard RXDP firmware */
15708#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x0
15709/* enum: Low latency RXDP firmware */
15710#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x1
15711/* enum: Packed stream RXDP firmware */
15712#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x2
15713/* enum: Rules engine RXDP firmware */
15714#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x5
15715/* enum: DPDK RXDP firmware */
15716#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x6
15717/* enum: BIST RXDP firmware */
15718#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a
15719/* enum: RXDP Test firmware image 1 */
15720#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15721/* enum: RXDP Test firmware image 2 */
15722#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15723/* enum: RXDP Test firmware image 3 */
15724#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15725/* enum: RXDP Test firmware image 4 */
15726#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15727/* enum: RXDP Test firmware image 5 */
15728#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x105
15729/* enum: RXDP Test firmware image 6 */
15730#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15731/* enum: RXDP Test firmware image 7 */
15732#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15733/* enum: RXDP Test firmware image 8 */
15734#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15735/* enum: RXDP Test firmware image 9 */
15736#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15737/* enum: RXDP Test firmware image 10 */
15738#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c
15739/* TxDPCPU firmware id. */
15740#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_OFST 6
15741#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_LEN 2
15742/* enum: Standard TXDP firmware */
15743#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x0
15744/* enum: Low latency TXDP firmware */
15745#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x1
15746/* enum: High packet rate TXDP firmware */
15747#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x3
15748/* enum: Rules engine TXDP firmware */
15749#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x5
15750/* enum: DPDK TXDP firmware */
15751#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x6
15752/* enum: BIST TXDP firmware */
15753#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d
15754/* enum: TXDP Test firmware image 1 */
15755#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15756/* enum: TXDP Test firmware image 2 */
15757#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15758/* enum: TXDP CSR bus test firmware */
15759#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x103
15760#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_OFST 8
15761#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_LEN 2
15762#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_OFST 8
15763#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 0
15764#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_WIDTH 12
15765#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_OFST 8
15766#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_LBN 12
15767#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15768/* enum: reserved value - do not use (may indicate alternative interpretation
15769 * of REV field in future)
15770 */
15771#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x0
15772/* enum: Trivial RX PD firmware for early Huntington development (Huntington
15773 * development only)
15774 */
15775#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
15776/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
15777 */
15778#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15779/* enum: RX PD firmware with approximately Siena-compatible behaviour
15780 * (Huntington development only)
15781 */
15782#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
15783/* enum: Full featured RX PD production firmware */
15784#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
15785/* enum: (deprecated original name for the FULL_FEATURED variant) */
15786#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x3
15787/* enum: siena_compat variant RX PD firmware using PM rather than MAC
15788 * (Huntington development only)
15789 */
15790#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15791/* enum: Low latency RX PD production firmware */
15792#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
15793/* enum: Packed stream RX PD production firmware */
15794#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
15795/* enum: RX PD firmware handling layer 2 only for high packet rate performance
15796 * tests (Medford development only)
15797 */
15798#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
15799/* enum: Rules engine RX PD production firmware */
15800#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
15801/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15802#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x9
15803/* enum: DPDK RX PD production firmware */
15804#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa
15805/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
15806#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15807/* enum: RX PD firmware parsing but not filtering network overlay tunnel
15808 * encapsulations (Medford development only)
15809 */
15810#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
15811#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_OFST 10
15812#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_LEN 2
15813#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_OFST 10
15814#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 0
15815#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_WIDTH 12
15816#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_OFST 10
15817#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_LBN 12
15818#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15819/* enum: reserved value - do not use (may indicate alternative interpretation
15820 * of REV field in future)
15821 */
15822#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x0
15823/* enum: Trivial TX PD firmware for early Huntington development (Huntington
15824 * development only)
15825 */
15826#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
15827/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
15828 */
15829#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15830/* enum: TX PD firmware with approximately Siena-compatible behaviour
15831 * (Huntington development only)
15832 */
15833#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
15834/* enum: Full featured TX PD production firmware */
15835#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
15836/* enum: (deprecated original name for the FULL_FEATURED variant) */
15837#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x3
15838/* enum: siena_compat variant TX PD firmware using PM rather than MAC
15839 * (Huntington development only)
15840 */
15841#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15842#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
15843/* enum: TX PD firmware handling layer 2 only for high packet rate performance
15844 * tests (Medford development only)
15845 */
15846#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
15847/* enum: Rules engine TX PD production firmware */
15848#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
15849/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15850#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x9
15851/* enum: DPDK TX PD production firmware */
15852#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa
15853/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
15854#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15855/* Hardware capabilities of NIC */
15856#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_OFST 12
15857#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 4
15858/* Licensed capabilities */
15859#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_OFST 16
15860#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 4
15861/* Second word of flags. Not present on older firmware (check the length). */
15862#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_OFST 20
15863#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4
15864#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_OFST 20
15865#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 0
15866#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_WIDTH 1
15867#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_OFST 20
15868#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_LBN 1
15869#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_WIDTH 1
15870#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_OFST 20
15871#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_LBN 2
15872#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_WIDTH 1
15873#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_OFST 20
15874#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_LBN 3
15875#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_WIDTH 1
15876#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_OFST 20
15877#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4
15878#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_WIDTH 1
15879#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_OFST 20
15880#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_LBN 5
15881#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
15882#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
15883#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
15884#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
15885#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
15886#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
15887#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
15888#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_OFST 20
15889#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_LBN 7
15890#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_WIDTH 1
15891#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_OFST 20
15892#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_LBN 8
15893#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
15894#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_OFST 20
15895#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_LBN 9
15896#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_WIDTH 1
15897#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_OFST 20
15898#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_LBN 10
15899#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_WIDTH 1
15900#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_OFST 20
15901#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_LBN 11
15902#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_WIDTH 1
15903#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
15904#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
15905#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
15906#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_OFST 20
15907#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_LBN 13
15908#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_WIDTH 1
15909#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_OFST 20
15910#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_LBN 14
15911#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_WIDTH 1
15912#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_OFST 20
15913#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_LBN 15
15914#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_WIDTH 1
15915#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_OFST 20
15916#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_LBN 16
15917#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_WIDTH 1
15918#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_OFST 20
15919#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_LBN 17
15920#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_WIDTH 1
15921#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
15922#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
15923#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
15924#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_OFST 20
15925#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_LBN 19
15926#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_WIDTH 1
15927#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_OFST 20
15928#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_LBN 20
15929#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_WIDTH 1
15930#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
15931#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
15932#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
15933#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
15934#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
15935#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
15936#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_OFST 20
15937#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_LBN 22
15938#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_WIDTH 1
15939#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
15940#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
15941#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
15942#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_OFST 20
15943#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_LBN 24
15944#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_WIDTH 1
15945#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_OFST 20
15946#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_LBN 25
15947#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_WIDTH 1
15948#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
15949#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
15950#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
15951#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
15952#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
15953#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
15954#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_OFST 20
15955#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_LBN 28
15956#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_WIDTH 1
15957#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_OFST 20
15958#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_LBN 29
15959#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_WIDTH 1
15960#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_OFST 20
15961#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_LBN 30
15962#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_WIDTH 1
15963#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
15964#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
15965#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
15966/* Number of FATSOv2 contexts per datapath supported by this NIC (when
15967 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
15968 */
15969#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
15970#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
15971/* One byte per PF containing the number of the external port assigned to this
15972 * PF, indexed by PF number. Special values indicate that a PF is either not
15973 * present or not assigned.
15974 */
15975#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
15976#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
15977#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
15978/* enum: The caller is not permitted to access information on this PF. */
15979#define MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff
15980/* enum: PF does not exist. */
15981#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe
15982/* enum: PF does exist but is not assigned to any external port. */
15983#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd
15984/* enum: This value indicates that PF is assigned, but it cannot be expressed
15985 * in this field. It is intended for a possible future situation where a more
15986 * complex scheme of PFs to ports mapping is being used. The future driver
15987 * should look for a new field supporting the new scheme. The current/old
15988 * driver should treat this value as PF_NOT_ASSIGNED.
15989 */
15990#define MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15991/* One byte per PF containing the number of its VFs, indexed by PF number. A
15992 * special value indicates that a PF is not present.
15993 */
15994#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_OFST 42
15995#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_LEN 1
15996#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_NUM 16
15997/* enum: The caller is not permitted to access information on this PF. */
15998/* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */
15999/* enum: PF does not exist. */
16000/* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */
16001/* Number of VIs available for external ports 0-3. For devices with more than
16002 * four ports, the remainder are in NUM_VIS_PER_PORT2 in
16003 * GET_CAPABILITIES_V12_OUT.
16004 */
16005#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_OFST 58
16006#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_LEN 2
16007#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
16008/* Size of RX descriptor cache expressed as binary logarithm The actual size
16009 * equals (2 ^ RX_DESC_CACHE_SIZE)
16010 */
16011#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_OFST 66
16012#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_LEN 1
16013/* Size of TX descriptor cache expressed as binary logarithm The actual size
16014 * equals (2 ^ TX_DESC_CACHE_SIZE)
16015 */
16016#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_OFST 67
16017#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_LEN 1
16018/* Total number of available PIO buffers */
16019#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_OFST 68
16020#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_LEN 2
16021/* Size of a single PIO buffer */
16022#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_OFST 70
16023#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_LEN 2
16024/* On chips later than Medford the amount of address space assigned to each VI
16025 * is configurable. This is a global setting that the driver must query to
16026 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
16027 * with 8k VI windows.
16028 */
16029#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_OFST 72
16030#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_LEN 1
16031/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
16032 * CTPIO is not mapped.
16033 */
16034#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x0
16035/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
16036#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x1
16037/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
16038#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x2
16039/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
16040 * (SF-115995-SW) in the present configuration of firmware and port mode.
16041 */
16042#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
16043#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
16044/* Number of buffers per adapter that can be used for VFIFO Stuffing
16045 * (SF-115995-SW) in the present configuration of firmware and port mode.
16046 */
16047#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
16048#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
16049/* Entry count in the MAC stats array, including the final GENERATION_END
16050 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
16051 * hold at least this many 64-bit stats values, if they wish to receive all
16052 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
16053 * stats array returned will be truncated.
16054 */
16055#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_OFST 76
16056#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_LEN 2
16057/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
16058 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
16059 */
16060#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_OFST 80
16061#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 4
16062/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
16063 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
16064 * they create an RX queue. Due to hardware limitations, only a small number of
16065 * different buffer sizes may be available concurrently. Nonzero entries in
16066 * this array are the sizes of buffers which the system guarantees will be
16067 * available for use. If the list is empty, there are no limitations on
16068 * concurrent buffer sizes.
16069 */
16070#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
16071#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
16072#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
16073
16074/* MC_CMD_GET_CAPABILITIES_V7_OUT msgresponse */
16075#define MC_CMD_GET_CAPABILITIES_V7_OUT_LEN 152
16076/* First word of flags. */
16077#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 0
16078#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 4
16079#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 0
16080#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_LBN 3
16081#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_WIDTH 1
16082#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 0
16083#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 4
16084#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_WIDTH 1
16085#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 0
16086#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_LBN 5
16087#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_WIDTH 1
16088#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
16089#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
16090#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
16091#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 0
16092#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_LBN 7
16093#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
16094#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 0
16095#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_LBN 8
16096#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
16097#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 0
16098#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_LBN 9
16099#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_WIDTH 1
16100#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
16101#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
16102#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
16103#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
16104#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
16105#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
16106#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
16107#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
16108#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
16109#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 0
16110#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_LBN 13
16111#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
16112#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 0
16113#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_LBN 14
16114#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_WIDTH 1
16115#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
16116#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
16117#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
16118#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 0
16119#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_LBN 16
16120#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_WIDTH 1
16121#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 0
16122#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_LBN 17
16123#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_WIDTH 1
16124#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 0
16125#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_LBN 18
16126#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_WIDTH 1
16127#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 0
16128#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_LBN 19
16129#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_WIDTH 1
16130#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 0
16131#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_LBN 20
16132#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_WIDTH 1
16133#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 0
16134#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_LBN 21
16135#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_WIDTH 1
16136#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 0
16137#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_LBN 22
16138#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_WIDTH 1
16139#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 0
16140#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_LBN 23
16141#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_WIDTH 1
16142#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 0
16143#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_LBN 24
16144#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_WIDTH 1
16145#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 0
16146#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_LBN 25
16147#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_WIDTH 1
16148#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 0
16149#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_LBN 26
16150#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_WIDTH 1
16151#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 0
16152#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_LBN 27
16153#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
16154#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 0
16155#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_LBN 28
16156#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_WIDTH 1
16157#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
16158#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
16159#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
16160#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 0
16161#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_LBN 30
16162#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_WIDTH 1
16163#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 0
16164#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_LBN 31
16165#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_WIDTH 1
16166/* RxDPCPU firmware id. */
16167#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 4
16168#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_LEN 2
16169/* enum: Standard RXDP firmware */
16170#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x0
16171/* enum: Low latency RXDP firmware */
16172#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x1
16173/* enum: Packed stream RXDP firmware */
16174#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x2
16175/* enum: Rules engine RXDP firmware */
16176#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x5
16177/* enum: DPDK RXDP firmware */
16178#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x6
16179/* enum: BIST RXDP firmware */
16180#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a
16181/* enum: RXDP Test firmware image 1 */
16182#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
16183/* enum: RXDP Test firmware image 2 */
16184#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
16185/* enum: RXDP Test firmware image 3 */
16186#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
16187/* enum: RXDP Test firmware image 4 */
16188#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
16189/* enum: RXDP Test firmware image 5 */
16190#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x105
16191/* enum: RXDP Test firmware image 6 */
16192#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
16193/* enum: RXDP Test firmware image 7 */
16194#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
16195/* enum: RXDP Test firmware image 8 */
16196#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
16197/* enum: RXDP Test firmware image 9 */
16198#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
16199/* enum: RXDP Test firmware image 10 */
16200#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c
16201/* TxDPCPU firmware id. */
16202#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_OFST 6
16203#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_LEN 2
16204/* enum: Standard TXDP firmware */
16205#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x0
16206/* enum: Low latency TXDP firmware */
16207#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x1
16208/* enum: High packet rate TXDP firmware */
16209#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x3
16210/* enum: Rules engine TXDP firmware */
16211#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x5
16212/* enum: DPDK TXDP firmware */
16213#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x6
16214/* enum: BIST TXDP firmware */
16215#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d
16216/* enum: TXDP Test firmware image 1 */
16217#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
16218/* enum: TXDP Test firmware image 2 */
16219#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
16220/* enum: TXDP CSR bus test firmware */
16221#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x103
16222#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_OFST 8
16223#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_LEN 2
16224#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_OFST 8
16225#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 0
16226#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_WIDTH 12
16227#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_OFST 8
16228#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_LBN 12
16229#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
16230/* enum: reserved value - do not use (may indicate alternative interpretation
16231 * of REV field in future)
16232 */
16233#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x0
16234/* enum: Trivial RX PD firmware for early Huntington development (Huntington
16235 * development only)
16236 */
16237#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16238/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
16239 */
16240#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16241/* enum: RX PD firmware with approximately Siena-compatible behaviour
16242 * (Huntington development only)
16243 */
16244#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16245/* enum: Full featured RX PD production firmware */
16246#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16247/* enum: (deprecated original name for the FULL_FEATURED variant) */
16248#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16249/* enum: siena_compat variant RX PD firmware using PM rather than MAC
16250 * (Huntington development only)
16251 */
16252#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16253/* enum: Low latency RX PD production firmware */
16254#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16255/* enum: Packed stream RX PD production firmware */
16256#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16257/* enum: RX PD firmware handling layer 2 only for high packet rate performance
16258 * tests (Medford development only)
16259 */
16260#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16261/* enum: Rules engine RX PD production firmware */
16262#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16263/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16264#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16265/* enum: DPDK RX PD production firmware */
16266#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa
16267/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
16268#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16269/* enum: RX PD firmware parsing but not filtering network overlay tunnel
16270 * encapsulations (Medford development only)
16271 */
16272#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
16273#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_OFST 10
16274#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_LEN 2
16275#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_OFST 10
16276#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 0
16277#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_WIDTH 12
16278#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_OFST 10
16279#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_LBN 12
16280#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
16281/* enum: reserved value - do not use (may indicate alternative interpretation
16282 * of REV field in future)
16283 */
16284#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x0
16285/* enum: Trivial TX PD firmware for early Huntington development (Huntington
16286 * development only)
16287 */
16288#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
16289/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
16290 */
16291#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16292/* enum: TX PD firmware with approximately Siena-compatible behaviour
16293 * (Huntington development only)
16294 */
16295#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
16296/* enum: Full featured TX PD production firmware */
16297#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
16298/* enum: (deprecated original name for the FULL_FEATURED variant) */
16299#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x3
16300/* enum: siena_compat variant TX PD firmware using PM rather than MAC
16301 * (Huntington development only)
16302 */
16303#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16304#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
16305/* enum: TX PD firmware handling layer 2 only for high packet rate performance
16306 * tests (Medford development only)
16307 */
16308#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
16309/* enum: Rules engine TX PD production firmware */
16310#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
16311/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16312#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x9
16313/* enum: DPDK TX PD production firmware */
16314#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa
16315/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
16316#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16317/* Hardware capabilities of NIC */
16318#define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_OFST 12
16319#define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 4
16320/* Licensed capabilities */
16321#define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_OFST 16
16322#define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 4
16323/* Second word of flags. Not present on older firmware (check the length). */
16324#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_OFST 20
16325#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 4
16326#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_OFST 20
16327#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 0
16328#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_WIDTH 1
16329#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_OFST 20
16330#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_LBN 1
16331#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_WIDTH 1
16332#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_OFST 20
16333#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_LBN 2
16334#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_WIDTH 1
16335#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_OFST 20
16336#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_LBN 3
16337#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_WIDTH 1
16338#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_OFST 20
16339#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 4
16340#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_WIDTH 1
16341#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_OFST 20
16342#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_LBN 5
16343#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
16344#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
16345#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
16346#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
16347#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
16348#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
16349#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
16350#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_OFST 20
16351#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_LBN 7
16352#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_WIDTH 1
16353#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_OFST 20
16354#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_LBN 8
16355#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
16356#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_OFST 20
16357#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_LBN 9
16358#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_WIDTH 1
16359#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_OFST 20
16360#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_LBN 10
16361#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_WIDTH 1
16362#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_OFST 20
16363#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_LBN 11
16364#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_WIDTH 1
16365#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
16366#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
16367#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
16368#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_OFST 20
16369#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_LBN 13
16370#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_WIDTH 1
16371#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_OFST 20
16372#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_LBN 14
16373#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_WIDTH 1
16374#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_OFST 20
16375#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_LBN 15
16376#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_WIDTH 1
16377#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_OFST 20
16378#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_LBN 16
16379#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_WIDTH 1
16380#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_OFST 20
16381#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_LBN 17
16382#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_WIDTH 1
16383#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
16384#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
16385#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
16386#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_OFST 20
16387#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_LBN 19
16388#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_WIDTH 1
16389#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_OFST 20
16390#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_LBN 20
16391#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_WIDTH 1
16392#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
16393#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
16394#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
16395#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
16396#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
16397#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
16398#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_OFST 20
16399#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_LBN 22
16400#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_WIDTH 1
16401#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
16402#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
16403#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
16404#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_OFST 20
16405#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_LBN 24
16406#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_WIDTH 1
16407#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_OFST 20
16408#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_LBN 25
16409#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_WIDTH 1
16410#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
16411#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
16412#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
16413#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
16414#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
16415#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
16416#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_OFST 20
16417#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_LBN 28
16418#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_WIDTH 1
16419#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_OFST 20
16420#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_LBN 29
16421#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_WIDTH 1
16422#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_OFST 20
16423#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_LBN 30
16424#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_WIDTH 1
16425#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
16426#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
16427#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
16428/* Number of FATSOv2 contexts per datapath supported by this NIC (when
16429 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
16430 */
16431#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
16432#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
16433/* One byte per PF containing the number of the external port assigned to this
16434 * PF, indexed by PF number. Special values indicate that a PF is either not
16435 * present or not assigned.
16436 */
16437#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
16438#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
16439#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
16440/* enum: The caller is not permitted to access information on this PF. */
16441#define MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff
16442/* enum: PF does not exist. */
16443#define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe
16444/* enum: PF does exist but is not assigned to any external port. */
16445#define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd
16446/* enum: This value indicates that PF is assigned, but it cannot be expressed
16447 * in this field. It is intended for a possible future situation where a more
16448 * complex scheme of PFs to ports mapping is being used. The future driver
16449 * should look for a new field supporting the new scheme. The current/old
16450 * driver should treat this value as PF_NOT_ASSIGNED.
16451 */
16452#define MC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
16453/* One byte per PF containing the number of its VFs, indexed by PF number. A
16454 * special value indicates that a PF is not present.
16455 */
16456#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_OFST 42
16457#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_LEN 1
16458#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_NUM 16
16459/* enum: The caller is not permitted to access information on this PF. */
16460/* MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */
16461/* enum: PF does not exist. */
16462/* MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */
16463/* Number of VIs available for external ports 0-3. For devices with more than
16464 * four ports, the remainder are in NUM_VIS_PER_PORT2 in
16465 * GET_CAPABILITIES_V12_OUT.
16466 */
16467#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_OFST 58
16468#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_LEN 2
16469#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4
16470/* Size of RX descriptor cache expressed as binary logarithm The actual size
16471 * equals (2 ^ RX_DESC_CACHE_SIZE)
16472 */
16473#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_OFST 66
16474#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_LEN 1
16475/* Size of TX descriptor cache expressed as binary logarithm The actual size
16476 * equals (2 ^ TX_DESC_CACHE_SIZE)
16477 */
16478#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_OFST 67
16479#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_LEN 1
16480/* Total number of available PIO buffers */
16481#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_OFST 68
16482#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_LEN 2
16483/* Size of a single PIO buffer */
16484#define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_OFST 70
16485#define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_LEN 2
16486/* On chips later than Medford the amount of address space assigned to each VI
16487 * is configurable. This is a global setting that the driver must query to
16488 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
16489 * with 8k VI windows.
16490 */
16491#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_OFST 72
16492#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_LEN 1
16493/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
16494 * CTPIO is not mapped.
16495 */
16496#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x0
16497/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
16498#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x1
16499/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
16500#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x2
16501/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
16502 * (SF-115995-SW) in the present configuration of firmware and port mode.
16503 */
16504#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
16505#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
16506/* Number of buffers per adapter that can be used for VFIFO Stuffing
16507 * (SF-115995-SW) in the present configuration of firmware and port mode.
16508 */
16509#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
16510#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
16511/* Entry count in the MAC stats array, including the final GENERATION_END
16512 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
16513 * hold at least this many 64-bit stats values, if they wish to receive all
16514 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
16515 * stats array returned will be truncated.
16516 */
16517#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_OFST 76
16518#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_LEN 2
16519/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
16520 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
16521 */
16522#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_OFST 80
16523#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 4
16524/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
16525 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
16526 * they create an RX queue. Due to hardware limitations, only a small number of
16527 * different buffer sizes may be available concurrently. Nonzero entries in
16528 * this array are the sizes of buffers which the system guarantees will be
16529 * available for use. If the list is empty, there are no limitations on
16530 * concurrent buffer sizes.
16531 */
16532#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
16533#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
16534#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
16535/* Third word of flags. Not present on older firmware (check the length). */
16536#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_OFST 148
16537#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 4
16538#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_OFST 148
16539#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 0
16540#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_WIDTH 1
16541#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_OFST 148
16542#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_LBN 1
16543#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_WIDTH 1
16544#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
16545#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
16546#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
16547#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_OFST 148
16548#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_LBN 3
16549#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_WIDTH 1
16550#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_OFST 148
16551#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 4
16552#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_WIDTH 1
16553#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
16554#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
16555#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
16556#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
16557#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
16558#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
16559#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
16560#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
16561#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
16562#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
16563#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
16564#define MC_CMD_GET_CAPABILITIES_V7_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
16565#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
16566#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
16567#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
16568#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
16569#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
16570#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
16571#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
16572#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
16573#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
16574#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
16575#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
16576#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
16577#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148
16578#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13
16579#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1
16580#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
16581#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
16582#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
16583#define MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_OFST 148
16584#define MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_LBN 15
16585#define MC_CMD_GET_CAPABILITIES_V7_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
16586#define MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
16587#define MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
16588#define MC_CMD_GET_CAPABILITIES_V7_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
16589#define MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_OFST 148
16590#define MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_LBN 17
16591#define MC_CMD_GET_CAPABILITIES_V7_OUT_CXL_CONFIG_ENABLE_WIDTH 1
16592
16593/* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */
16594#define MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160
16595/* First word of flags. */
16596#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 0
16597#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 4
16598#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 0
16599#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_LBN 3
16600#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_WIDTH 1
16601#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 0
16602#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 4
16603#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_WIDTH 1
16604#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 0
16605#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_LBN 5
16606#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_WIDTH 1
16607#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
16608#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
16609#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
16610#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 0
16611#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_LBN 7
16612#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
16613#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 0
16614#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_LBN 8
16615#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
16616#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 0
16617#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_LBN 9
16618#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_WIDTH 1
16619#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
16620#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
16621#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
16622#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
16623#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
16624#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
16625#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
16626#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
16627#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
16628#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 0
16629#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_LBN 13
16630#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
16631#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 0
16632#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_LBN 14
16633#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_WIDTH 1
16634#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
16635#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
16636#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
16637#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 0
16638#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_LBN 16
16639#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_WIDTH 1
16640#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 0
16641#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_LBN 17
16642#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_WIDTH 1
16643#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 0
16644#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_LBN 18
16645#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_WIDTH 1
16646#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 0
16647#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_LBN 19
16648#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_WIDTH 1
16649#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 0
16650#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_LBN 20
16651#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_WIDTH 1
16652#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 0
16653#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_LBN 21
16654#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_WIDTH 1
16655#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 0
16656#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_LBN 22
16657#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_WIDTH 1
16658#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 0
16659#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_LBN 23
16660#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_WIDTH 1
16661#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 0
16662#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_LBN 24
16663#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_WIDTH 1
16664#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 0
16665#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_LBN 25
16666#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_WIDTH 1
16667#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 0
16668#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_LBN 26
16669#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_WIDTH 1
16670#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 0
16671#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_LBN 27
16672#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
16673#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 0
16674#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_LBN 28
16675#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_WIDTH 1
16676#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
16677#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
16678#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
16679#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 0
16680#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_LBN 30
16681#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_WIDTH 1
16682#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 0
16683#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_LBN 31
16684#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_WIDTH 1
16685/* RxDPCPU firmware id. */
16686#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 4
16687#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_LEN 2
16688/* enum: Standard RXDP firmware */
16689#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x0
16690/* enum: Low latency RXDP firmware */
16691#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x1
16692/* enum: Packed stream RXDP firmware */
16693#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x2
16694/* enum: Rules engine RXDP firmware */
16695#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x5
16696/* enum: DPDK RXDP firmware */
16697#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x6
16698/* enum: BIST RXDP firmware */
16699#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a
16700/* enum: RXDP Test firmware image 1 */
16701#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
16702/* enum: RXDP Test firmware image 2 */
16703#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
16704/* enum: RXDP Test firmware image 3 */
16705#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
16706/* enum: RXDP Test firmware image 4 */
16707#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
16708/* enum: RXDP Test firmware image 5 */
16709#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x105
16710/* enum: RXDP Test firmware image 6 */
16711#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
16712/* enum: RXDP Test firmware image 7 */
16713#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
16714/* enum: RXDP Test firmware image 8 */
16715#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
16716/* enum: RXDP Test firmware image 9 */
16717#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
16718/* enum: RXDP Test firmware image 10 */
16719#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c
16720/* TxDPCPU firmware id. */
16721#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_OFST 6
16722#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_LEN 2
16723/* enum: Standard TXDP firmware */
16724#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x0
16725/* enum: Low latency TXDP firmware */
16726#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x1
16727/* enum: High packet rate TXDP firmware */
16728#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x3
16729/* enum: Rules engine TXDP firmware */
16730#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x5
16731/* enum: DPDK TXDP firmware */
16732#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x6
16733/* enum: BIST TXDP firmware */
16734#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d
16735/* enum: TXDP Test firmware image 1 */
16736#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
16737/* enum: TXDP Test firmware image 2 */
16738#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
16739/* enum: TXDP CSR bus test firmware */
16740#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x103
16741#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_OFST 8
16742#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_LEN 2
16743#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_OFST 8
16744#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 0
16745#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_WIDTH 12
16746#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_OFST 8
16747#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_LBN 12
16748#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
16749/* enum: reserved value - do not use (may indicate alternative interpretation
16750 * of REV field in future)
16751 */
16752#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x0
16753/* enum: Trivial RX PD firmware for early Huntington development (Huntington
16754 * development only)
16755 */
16756#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16757/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
16758 */
16759#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16760/* enum: RX PD firmware with approximately Siena-compatible behaviour
16761 * (Huntington development only)
16762 */
16763#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16764/* enum: Full featured RX PD production firmware */
16765#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16766/* enum: (deprecated original name for the FULL_FEATURED variant) */
16767#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16768/* enum: siena_compat variant RX PD firmware using PM rather than MAC
16769 * (Huntington development only)
16770 */
16771#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16772/* enum: Low latency RX PD production firmware */
16773#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16774/* enum: Packed stream RX PD production firmware */
16775#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16776/* enum: RX PD firmware handling layer 2 only for high packet rate performance
16777 * tests (Medford development only)
16778 */
16779#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16780/* enum: Rules engine RX PD production firmware */
16781#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16782/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16783#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16784/* enum: DPDK RX PD production firmware */
16785#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa
16786/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
16787#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16788/* enum: RX PD firmware parsing but not filtering network overlay tunnel
16789 * encapsulations (Medford development only)
16790 */
16791#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
16792#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_OFST 10
16793#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_LEN 2
16794#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_OFST 10
16795#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 0
16796#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_WIDTH 12
16797#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_OFST 10
16798#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_LBN 12
16799#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
16800/* enum: reserved value - do not use (may indicate alternative interpretation
16801 * of REV field in future)
16802 */
16803#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x0
16804/* enum: Trivial TX PD firmware for early Huntington development (Huntington
16805 * development only)
16806 */
16807#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
16808/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
16809 */
16810#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16811/* enum: TX PD firmware with approximately Siena-compatible behaviour
16812 * (Huntington development only)
16813 */
16814#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
16815/* enum: Full featured TX PD production firmware */
16816#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
16817/* enum: (deprecated original name for the FULL_FEATURED variant) */
16818#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x3
16819/* enum: siena_compat variant TX PD firmware using PM rather than MAC
16820 * (Huntington development only)
16821 */
16822#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16823#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
16824/* enum: TX PD firmware handling layer 2 only for high packet rate performance
16825 * tests (Medford development only)
16826 */
16827#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
16828/* enum: Rules engine TX PD production firmware */
16829#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
16830/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16831#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x9
16832/* enum: DPDK TX PD production firmware */
16833#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa
16834/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
16835#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16836/* Hardware capabilities of NIC */
16837#define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_OFST 12
16838#define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 4
16839/* Licensed capabilities */
16840#define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_OFST 16
16841#define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 4
16842/* Second word of flags. Not present on older firmware (check the length). */
16843#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST 20
16844#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 4
16845#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_OFST 20
16846#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 0
16847#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_WIDTH 1
16848#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_OFST 20
16849#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_LBN 1
16850#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_WIDTH 1
16851#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_OFST 20
16852#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_LBN 2
16853#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_WIDTH 1
16854#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_OFST 20
16855#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_LBN 3
16856#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_WIDTH 1
16857#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_OFST 20
16858#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 4
16859#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_WIDTH 1
16860#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_OFST 20
16861#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_LBN 5
16862#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
16863#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
16864#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
16865#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
16866#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
16867#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
16868#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
16869#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_OFST 20
16870#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_LBN 7
16871#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_WIDTH 1
16872#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_OFST 20
16873#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_LBN 8
16874#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
16875#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_OFST 20
16876#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_LBN 9
16877#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_WIDTH 1
16878#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_OFST 20
16879#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_LBN 10
16880#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_WIDTH 1
16881#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_OFST 20
16882#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_LBN 11
16883#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_WIDTH 1
16884#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
16885#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
16886#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
16887#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_OFST 20
16888#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_LBN 13
16889#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_WIDTH 1
16890#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_OFST 20
16891#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_LBN 14
16892#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_WIDTH 1
16893#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_OFST 20
16894#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_LBN 15
16895#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_WIDTH 1
16896#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_OFST 20
16897#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_LBN 16
16898#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_WIDTH 1
16899#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_OFST 20
16900#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_LBN 17
16901#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_WIDTH 1
16902#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
16903#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
16904#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
16905#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_OFST 20
16906#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_LBN 19
16907#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_WIDTH 1
16908#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_OFST 20
16909#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_LBN 20
16910#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_WIDTH 1
16911#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
16912#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
16913#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
16914#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
16915#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
16916#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
16917#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_OFST 20
16918#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_LBN 22
16919#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_WIDTH 1
16920#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
16921#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
16922#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
16923#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_OFST 20
16924#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_LBN 24
16925#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_WIDTH 1
16926#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_OFST 20
16927#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_LBN 25
16928#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_WIDTH 1
16929#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
16930#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
16931#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
16932#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
16933#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
16934#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
16935#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_OFST 20
16936#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_LBN 28
16937#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_WIDTH 1
16938#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_OFST 20
16939#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_LBN 29
16940#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_WIDTH 1
16941#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_OFST 20
16942#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_LBN 30
16943#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_WIDTH 1
16944#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
16945#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
16946#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
16947/* Number of FATSOv2 contexts per datapath supported by this NIC (when
16948 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
16949 */
16950#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
16951#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
16952/* One byte per PF containing the number of the external port assigned to this
16953 * PF, indexed by PF number. Special values indicate that a PF is either not
16954 * present or not assigned.
16955 */
16956#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
16957#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
16958#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
16959/* enum: The caller is not permitted to access information on this PF. */
16960#define MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff
16961/* enum: PF does not exist. */
16962#define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe
16963/* enum: PF does exist but is not assigned to any external port. */
16964#define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd
16965/* enum: This value indicates that PF is assigned, but it cannot be expressed
16966 * in this field. It is intended for a possible future situation where a more
16967 * complex scheme of PFs to ports mapping is being used. The future driver
16968 * should look for a new field supporting the new scheme. The current/old
16969 * driver should treat this value as PF_NOT_ASSIGNED.
16970 */
16971#define MC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
16972/* One byte per PF containing the number of its VFs, indexed by PF number. A
16973 * special value indicates that a PF is not present.
16974 */
16975#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_OFST 42
16976#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_LEN 1
16977#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_NUM 16
16978/* enum: The caller is not permitted to access information on this PF. */
16979/* MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */
16980/* enum: PF does not exist. */
16981/* MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */
16982/* Number of VIs available for external ports 0-3. For devices with more than
16983 * four ports, the remainder are in NUM_VIS_PER_PORT2 in
16984 * GET_CAPABILITIES_V12_OUT.
16985 */
16986#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_OFST 58
16987#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_LEN 2
16988#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4
16989/* Size of RX descriptor cache expressed as binary logarithm The actual size
16990 * equals (2 ^ RX_DESC_CACHE_SIZE)
16991 */
16992#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_OFST 66
16993#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_LEN 1
16994/* Size of TX descriptor cache expressed as binary logarithm The actual size
16995 * equals (2 ^ TX_DESC_CACHE_SIZE)
16996 */
16997#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_OFST 67
16998#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_LEN 1
16999/* Total number of available PIO buffers */
17000#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_OFST 68
17001#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_LEN 2
17002/* Size of a single PIO buffer */
17003#define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_OFST 70
17004#define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_LEN 2
17005/* On chips later than Medford the amount of address space assigned to each VI
17006 * is configurable. This is a global setting that the driver must query to
17007 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
17008 * with 8k VI windows.
17009 */
17010#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_OFST 72
17011#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_LEN 1
17012/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
17013 * CTPIO is not mapped.
17014 */
17015#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x0
17016/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
17017#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x1
17018/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
17019#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x2
17020/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
17021 * (SF-115995-SW) in the present configuration of firmware and port mode.
17022 */
17023#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
17024#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
17025/* Number of buffers per adapter that can be used for VFIFO Stuffing
17026 * (SF-115995-SW) in the present configuration of firmware and port mode.
17027 */
17028#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
17029#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
17030/* Entry count in the MAC stats array, including the final GENERATION_END
17031 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
17032 * hold at least this many 64-bit stats values, if they wish to receive all
17033 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
17034 * stats array returned will be truncated.
17035 */
17036#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_OFST 76
17037#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_LEN 2
17038/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
17039 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
17040 */
17041#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_OFST 80
17042#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 4
17043/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
17044 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
17045 * they create an RX queue. Due to hardware limitations, only a small number of
17046 * different buffer sizes may be available concurrently. Nonzero entries in
17047 * this array are the sizes of buffers which the system guarantees will be
17048 * available for use. If the list is empty, there are no limitations on
17049 * concurrent buffer sizes.
17050 */
17051#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
17052#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
17053#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
17054/* Third word of flags. Not present on older firmware (check the length). */
17055#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST 148
17056#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 4
17057#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_OFST 148
17058#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 0
17059#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_WIDTH 1
17060#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_OFST 148
17061#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_LBN 1
17062#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_WIDTH 1
17063#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
17064#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
17065#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
17066#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_OFST 148
17067#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_LBN 3
17068#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_WIDTH 1
17069#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_OFST 148
17070#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 4
17071#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_WIDTH 1
17072#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
17073#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
17074#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
17075#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
17076#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
17077#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
17078#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
17079#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
17080#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
17081#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
17082#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
17083#define MC_CMD_GET_CAPABILITIES_V8_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
17084#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
17085#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
17086#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
17087#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
17088#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
17089#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
17090#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
17091#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
17092#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
17093#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
17094#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
17095#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
17096#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148
17097#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13
17098#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1
17099#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
17100#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
17101#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
17102#define MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_OFST 148
17103#define MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_LBN 15
17104#define MC_CMD_GET_CAPABILITIES_V8_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
17105#define MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
17106#define MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
17107#define MC_CMD_GET_CAPABILITIES_V8_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
17108#define MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_OFST 148
17109#define MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_LBN 17
17110#define MC_CMD_GET_CAPABILITIES_V8_OUT_CXL_CONFIG_ENABLE_WIDTH 1
17111/* These bits are reserved for communicating test-specific capabilities to
17112 * host-side test software. All production drivers should treat this field as
17113 * opaque.
17114 */
17115#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 152
17116#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 8
17117#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 152
17118#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LEN 4
17119#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LBN 1216
17120#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_WIDTH 32
17121#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 156
17122#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LEN 4
17123#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LBN 1248
17124#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_WIDTH 32
17125
17126/* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */
17127#define MC_CMD_GET_CAPABILITIES_V9_OUT_LEN 184
17128/* First word of flags. */
17129#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 0
17130#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 4
17131#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 0
17132#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_LBN 3
17133#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_WIDTH 1
17134#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 0
17135#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 4
17136#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_WIDTH 1
17137#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 0
17138#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_LBN 5
17139#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_WIDTH 1
17140#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
17141#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
17142#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
17143#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 0
17144#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_LBN 7
17145#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
17146#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 0
17147#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_LBN 8
17148#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
17149#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 0
17150#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_LBN 9
17151#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_WIDTH 1
17152#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
17153#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
17154#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
17155#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
17156#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
17157#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
17158#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
17159#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
17160#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
17161#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 0
17162#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_LBN 13
17163#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
17164#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 0
17165#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_LBN 14
17166#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_WIDTH 1
17167#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
17168#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
17169#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
17170#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 0
17171#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_LBN 16
17172#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_WIDTH 1
17173#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 0
17174#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_LBN 17
17175#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_WIDTH 1
17176#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 0
17177#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_LBN 18
17178#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_WIDTH 1
17179#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 0
17180#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_LBN 19
17181#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_WIDTH 1
17182#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 0
17183#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_LBN 20
17184#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_WIDTH 1
17185#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 0
17186#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_LBN 21
17187#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_WIDTH 1
17188#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 0
17189#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_LBN 22
17190#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_WIDTH 1
17191#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 0
17192#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_LBN 23
17193#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_WIDTH 1
17194#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 0
17195#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_LBN 24
17196#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_WIDTH 1
17197#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 0
17198#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_LBN 25
17199#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_WIDTH 1
17200#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 0
17201#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_LBN 26
17202#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_WIDTH 1
17203#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 0
17204#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_LBN 27
17205#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
17206#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 0
17207#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_LBN 28
17208#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_WIDTH 1
17209#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
17210#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
17211#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
17212#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 0
17213#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_LBN 30
17214#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_WIDTH 1
17215#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 0
17216#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_LBN 31
17217#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_WIDTH 1
17218/* RxDPCPU firmware id. */
17219#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 4
17220#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_LEN 2
17221/* enum: Standard RXDP firmware */
17222#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x0
17223/* enum: Low latency RXDP firmware */
17224#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x1
17225/* enum: Packed stream RXDP firmware */
17226#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x2
17227/* enum: Rules engine RXDP firmware */
17228#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x5
17229/* enum: DPDK RXDP firmware */
17230#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x6
17231/* enum: BIST RXDP firmware */
17232#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a
17233/* enum: RXDP Test firmware image 1 */
17234#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
17235/* enum: RXDP Test firmware image 2 */
17236#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
17237/* enum: RXDP Test firmware image 3 */
17238#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
17239/* enum: RXDP Test firmware image 4 */
17240#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
17241/* enum: RXDP Test firmware image 5 */
17242#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x105
17243/* enum: RXDP Test firmware image 6 */
17244#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
17245/* enum: RXDP Test firmware image 7 */
17246#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
17247/* enum: RXDP Test firmware image 8 */
17248#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
17249/* enum: RXDP Test firmware image 9 */
17250#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
17251/* enum: RXDP Test firmware image 10 */
17252#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c
17253/* TxDPCPU firmware id. */
17254#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_OFST 6
17255#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_LEN 2
17256/* enum: Standard TXDP firmware */
17257#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x0
17258/* enum: Low latency TXDP firmware */
17259#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x1
17260/* enum: High packet rate TXDP firmware */
17261#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x3
17262/* enum: Rules engine TXDP firmware */
17263#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x5
17264/* enum: DPDK TXDP firmware */
17265#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x6
17266/* enum: BIST TXDP firmware */
17267#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d
17268/* enum: TXDP Test firmware image 1 */
17269#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
17270/* enum: TXDP Test firmware image 2 */
17271#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
17272/* enum: TXDP CSR bus test firmware */
17273#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x103
17274#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_OFST 8
17275#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_LEN 2
17276#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_OFST 8
17277#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 0
17278#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_WIDTH 12
17279#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_OFST 8
17280#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_LBN 12
17281#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
17282/* enum: reserved value - do not use (may indicate alternative interpretation
17283 * of REV field in future)
17284 */
17285#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x0
17286/* enum: Trivial RX PD firmware for early Huntington development (Huntington
17287 * development only)
17288 */
17289#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
17290/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
17291 */
17292#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17293/* enum: RX PD firmware with approximately Siena-compatible behaviour
17294 * (Huntington development only)
17295 */
17296#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
17297/* enum: Full featured RX PD production firmware */
17298#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
17299/* enum: (deprecated original name for the FULL_FEATURED variant) */
17300#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x3
17301/* enum: siena_compat variant RX PD firmware using PM rather than MAC
17302 * (Huntington development only)
17303 */
17304#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17305/* enum: Low latency RX PD production firmware */
17306#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
17307/* enum: Packed stream RX PD production firmware */
17308#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
17309/* enum: RX PD firmware handling layer 2 only for high packet rate performance
17310 * tests (Medford development only)
17311 */
17312#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
17313/* enum: Rules engine RX PD production firmware */
17314#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
17315/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17316#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x9
17317/* enum: DPDK RX PD production firmware */
17318#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa
17319/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
17320#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17321/* enum: RX PD firmware parsing but not filtering network overlay tunnel
17322 * encapsulations (Medford development only)
17323 */
17324#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
17325#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_OFST 10
17326#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_LEN 2
17327#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_OFST 10
17328#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 0
17329#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_WIDTH 12
17330#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_OFST 10
17331#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_LBN 12
17332#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
17333/* enum: reserved value - do not use (may indicate alternative interpretation
17334 * of REV field in future)
17335 */
17336#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x0
17337/* enum: Trivial TX PD firmware for early Huntington development (Huntington
17338 * development only)
17339 */
17340#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
17341/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
17342 */
17343#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17344/* enum: TX PD firmware with approximately Siena-compatible behaviour
17345 * (Huntington development only)
17346 */
17347#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
17348/* enum: Full featured TX PD production firmware */
17349#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
17350/* enum: (deprecated original name for the FULL_FEATURED variant) */
17351#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x3
17352/* enum: siena_compat variant TX PD firmware using PM rather than MAC
17353 * (Huntington development only)
17354 */
17355#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17356#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
17357/* enum: TX PD firmware handling layer 2 only for high packet rate performance
17358 * tests (Medford development only)
17359 */
17360#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
17361/* enum: Rules engine TX PD production firmware */
17362#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
17363/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17364#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x9
17365/* enum: DPDK TX PD production firmware */
17366#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa
17367/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
17368#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17369/* Hardware capabilities of NIC */
17370#define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_OFST 12
17371#define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 4
17372/* Licensed capabilities */
17373#define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_OFST 16
17374#define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 4
17375/* Second word of flags. Not present on older firmware (check the length). */
17376#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_OFST 20
17377#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 4
17378#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_OFST 20
17379#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 0
17380#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_WIDTH 1
17381#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_OFST 20
17382#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_LBN 1
17383#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_WIDTH 1
17384#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_OFST 20
17385#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_LBN 2
17386#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_WIDTH 1
17387#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_OFST 20
17388#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_LBN 3
17389#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_WIDTH 1
17390#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_OFST 20
17391#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 4
17392#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_WIDTH 1
17393#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_OFST 20
17394#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_LBN 5
17395#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
17396#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
17397#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
17398#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
17399#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
17400#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
17401#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
17402#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_OFST 20
17403#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_LBN 7
17404#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_WIDTH 1
17405#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_OFST 20
17406#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_LBN 8
17407#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
17408#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_OFST 20
17409#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_LBN 9
17410#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_WIDTH 1
17411#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_OFST 20
17412#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_LBN 10
17413#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_WIDTH 1
17414#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_OFST 20
17415#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_LBN 11
17416#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_WIDTH 1
17417#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
17418#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
17419#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
17420#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_OFST 20
17421#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_LBN 13
17422#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_WIDTH 1
17423#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_OFST 20
17424#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_LBN 14
17425#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_WIDTH 1
17426#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_OFST 20
17427#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_LBN 15
17428#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_WIDTH 1
17429#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_OFST 20
17430#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_LBN 16
17431#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_WIDTH 1
17432#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_OFST 20
17433#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_LBN 17
17434#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_WIDTH 1
17435#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
17436#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
17437#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
17438#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_OFST 20
17439#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_LBN 19
17440#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_WIDTH 1
17441#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_OFST 20
17442#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_LBN 20
17443#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_WIDTH 1
17444#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
17445#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
17446#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
17447#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
17448#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
17449#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
17450#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_OFST 20
17451#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_LBN 22
17452#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_WIDTH 1
17453#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
17454#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
17455#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
17456#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_OFST 20
17457#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_LBN 24
17458#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_WIDTH 1
17459#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_OFST 20
17460#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_LBN 25
17461#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_WIDTH 1
17462#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
17463#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
17464#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
17465#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
17466#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
17467#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
17468#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_OFST 20
17469#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_LBN 28
17470#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_WIDTH 1
17471#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_OFST 20
17472#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_LBN 29
17473#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_WIDTH 1
17474#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_OFST 20
17475#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_LBN 30
17476#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_WIDTH 1
17477#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
17478#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
17479#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
17480/* Number of FATSOv2 contexts per datapath supported by this NIC (when
17481 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
17482 */
17483#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
17484#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
17485/* One byte per PF containing the number of the external port assigned to this
17486 * PF, indexed by PF number. Special values indicate that a PF is either not
17487 * present or not assigned.
17488 */
17489#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
17490#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
17491#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
17492/* enum: The caller is not permitted to access information on this PF. */
17493#define MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff
17494/* enum: PF does not exist. */
17495#define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe
17496/* enum: PF does exist but is not assigned to any external port. */
17497#define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd
17498/* enum: This value indicates that PF is assigned, but it cannot be expressed
17499 * in this field. It is intended for a possible future situation where a more
17500 * complex scheme of PFs to ports mapping is being used. The future driver
17501 * should look for a new field supporting the new scheme. The current/old
17502 * driver should treat this value as PF_NOT_ASSIGNED.
17503 */
17504#define MC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
17505/* One byte per PF containing the number of its VFs, indexed by PF number. A
17506 * special value indicates that a PF is not present.
17507 */
17508#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_OFST 42
17509#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_LEN 1
17510#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_NUM 16
17511/* enum: The caller is not permitted to access information on this PF. */
17512/* MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */
17513/* enum: PF does not exist. */
17514/* MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */
17515/* Number of VIs available for external ports 0-3. For devices with more than
17516 * four ports, the remainder are in NUM_VIS_PER_PORT2 in
17517 * GET_CAPABILITIES_V12_OUT.
17518 */
17519#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_OFST 58
17520#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_LEN 2
17521#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4
17522/* Size of RX descriptor cache expressed as binary logarithm The actual size
17523 * equals (2 ^ RX_DESC_CACHE_SIZE)
17524 */
17525#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_OFST 66
17526#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_LEN 1
17527/* Size of TX descriptor cache expressed as binary logarithm The actual size
17528 * equals (2 ^ TX_DESC_CACHE_SIZE)
17529 */
17530#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_OFST 67
17531#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_LEN 1
17532/* Total number of available PIO buffers */
17533#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_OFST 68
17534#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_LEN 2
17535/* Size of a single PIO buffer */
17536#define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_OFST 70
17537#define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_LEN 2
17538/* On chips later than Medford the amount of address space assigned to each VI
17539 * is configurable. This is a global setting that the driver must query to
17540 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
17541 * with 8k VI windows.
17542 */
17543#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_OFST 72
17544#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_LEN 1
17545/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
17546 * CTPIO is not mapped.
17547 */
17548#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x0
17549/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
17550#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x1
17551/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
17552#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x2
17553/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
17554 * (SF-115995-SW) in the present configuration of firmware and port mode.
17555 */
17556#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
17557#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
17558/* Number of buffers per adapter that can be used for VFIFO Stuffing
17559 * (SF-115995-SW) in the present configuration of firmware and port mode.
17560 */
17561#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
17562#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
17563/* Entry count in the MAC stats array, including the final GENERATION_END
17564 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
17565 * hold at least this many 64-bit stats values, if they wish to receive all
17566 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
17567 * stats array returned will be truncated.
17568 */
17569#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_OFST 76
17570#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_LEN 2
17571/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
17572 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
17573 */
17574#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_OFST 80
17575#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 4
17576/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
17577 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
17578 * they create an RX queue. Due to hardware limitations, only a small number of
17579 * different buffer sizes may be available concurrently. Nonzero entries in
17580 * this array are the sizes of buffers which the system guarantees will be
17581 * available for use. If the list is empty, there are no limitations on
17582 * concurrent buffer sizes.
17583 */
17584#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
17585#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
17586#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
17587/* Third word of flags. Not present on older firmware (check the length). */
17588#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_OFST 148
17589#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 4
17590#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_OFST 148
17591#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 0
17592#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_WIDTH 1
17593#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_OFST 148
17594#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_LBN 1
17595#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_WIDTH 1
17596#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
17597#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
17598#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
17599#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_OFST 148
17600#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_LBN 3
17601#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_WIDTH 1
17602#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_OFST 148
17603#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 4
17604#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_WIDTH 1
17605#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
17606#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
17607#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
17608#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
17609#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
17610#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
17611#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
17612#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
17613#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
17614#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
17615#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
17616#define MC_CMD_GET_CAPABILITIES_V9_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
17617#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
17618#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
17619#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
17620#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
17621#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
17622#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
17623#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
17624#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
17625#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
17626#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
17627#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
17628#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
17629#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148
17630#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13
17631#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1
17632#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
17633#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
17634#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
17635#define MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_OFST 148
17636#define MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_LBN 15
17637#define MC_CMD_GET_CAPABILITIES_V9_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
17638#define MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
17639#define MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
17640#define MC_CMD_GET_CAPABILITIES_V9_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
17641#define MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_OFST 148
17642#define MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_LBN 17
17643#define MC_CMD_GET_CAPABILITIES_V9_OUT_CXL_CONFIG_ENABLE_WIDTH 1
17644/* These bits are reserved for communicating test-specific capabilities to
17645 * host-side test software. All production drivers should treat this field as
17646 * opaque.
17647 */
17648#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 152
17649#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 8
17650#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 152
17651#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LEN 4
17652#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LBN 1216
17653#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_WIDTH 32
17654#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 156
17655#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LEN 4
17656#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LBN 1248
17657#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_WIDTH 32
17658/* The minimum size (in table entries) of indirection table to be allocated
17659 * from the pool for an RSS context. Note that the table size used must be a
17660 * power of 2.
17661 */
17662#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
17663#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
17664/* The maximum size (in table entries) of indirection table to be allocated
17665 * from the pool for an RSS context. Note that the table size used must be a
17666 * power of 2.
17667 */
17668#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
17669#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
17670/* The maximum number of queues that can be used by an RSS context in exclusive
17671 * mode. In exclusive mode the context has a configurable indirection table and
17672 * a configurable RSS key.
17673 */
17674#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
17675#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
17676/* The maximum number of queues that can be used by an RSS context in even-
17677 * spreading mode. In even-spreading mode the context has no indirection table
17678 * but it does have a configurable RSS key.
17679 */
17680#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
17681#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
17682/* The total number of RSS contexts supported. Note that the number of
17683 * available contexts using indirection tables is also limited by the
17684 * availability of indirection table space allocated from a common pool.
17685 */
17686#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_OFST 176
17687#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 4
17688/* The total amount of indirection table space that can be shared between RSS
17689 * contexts.
17690 */
17691#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_OFST 180
17692#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 4
17693
17694/* MC_CMD_GET_CAPABILITIES_V10_OUT msgresponse */
17695#define MC_CMD_GET_CAPABILITIES_V10_OUT_LEN 192
17696/* First word of flags. */
17697#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_OFST 0
17698#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_LEN 4
17699#define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_OFST 0
17700#define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_LBN 3
17701#define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_WIDTH 1
17702#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_OFST 0
17703#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_LBN 4
17704#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_WIDTH 1
17705#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_OFST 0
17706#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_LBN 5
17707#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_WIDTH 1
17708#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
17709#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
17710#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
17711#define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_OFST 0
17712#define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_LBN 7
17713#define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
17714#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_OFST 0
17715#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_LBN 8
17716#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
17717#define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_OFST 0
17718#define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_LBN 9
17719#define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_WIDTH 1
17720#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
17721#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
17722#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
17723#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
17724#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
17725#define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
17726#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
17727#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
17728#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
17729#define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_OFST 0
17730#define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_LBN 13
17731#define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
17732#define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_OFST 0
17733#define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_LBN 14
17734#define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_WIDTH 1
17735#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
17736#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
17737#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
17738#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_OFST 0
17739#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_LBN 16
17740#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_WIDTH 1
17741#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_OFST 0
17742#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_LBN 17
17743#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_WIDTH 1
17744#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_OFST 0
17745#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_LBN 18
17746#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_WIDTH 1
17747#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_OFST 0
17748#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_LBN 19
17749#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_WIDTH 1
17750#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_OFST 0
17751#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_LBN 20
17752#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_WIDTH 1
17753#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_OFST 0
17754#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_LBN 21
17755#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_WIDTH 1
17756#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_OFST 0
17757#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_LBN 22
17758#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_WIDTH 1
17759#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_OFST 0
17760#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_LBN 23
17761#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_WIDTH 1
17762#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_OFST 0
17763#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_LBN 24
17764#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_WIDTH 1
17765#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_OFST 0
17766#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_LBN 25
17767#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_WIDTH 1
17768#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_OFST 0
17769#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_LBN 26
17770#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_WIDTH 1
17771#define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_OFST 0
17772#define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_LBN 27
17773#define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
17774#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_OFST 0
17775#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_LBN 28
17776#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_WIDTH 1
17777#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
17778#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
17779#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
17780#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_OFST 0
17781#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_LBN 30
17782#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_WIDTH 1
17783#define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_OFST 0
17784#define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_LBN 31
17785#define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_WIDTH 1
17786/* RxDPCPU firmware id. */
17787#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DPCPU_FW_ID_OFST 4
17788#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DPCPU_FW_ID_LEN 2
17789/* enum: Standard RXDP firmware */
17790#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP 0x0
17791/* enum: Low latency RXDP firmware */
17792#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_LOW_LATENCY 0x1
17793/* enum: Packed stream RXDP firmware */
17794#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_PACKED_STREAM 0x2
17795/* enum: Rules engine RXDP firmware */
17796#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_RULES_ENGINE 0x5
17797/* enum: DPDK RXDP firmware */
17798#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_DPDK 0x6
17799/* enum: BIST RXDP firmware */
17800#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_BIST 0x10a
17801/* enum: RXDP Test firmware image 1 */
17802#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
17803/* enum: RXDP Test firmware image 2 */
17804#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
17805/* enum: RXDP Test firmware image 3 */
17806#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
17807/* enum: RXDP Test firmware image 4 */
17808#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
17809/* enum: RXDP Test firmware image 5 */
17810#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_BACKPRESSURE 0x105
17811/* enum: RXDP Test firmware image 6 */
17812#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
17813/* enum: RXDP Test firmware image 7 */
17814#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
17815/* enum: RXDP Test firmware image 8 */
17816#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
17817/* enum: RXDP Test firmware image 9 */
17818#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
17819/* enum: RXDP Test firmware image 10 */
17820#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_SLOW 0x10c
17821/* TxDPCPU firmware id. */
17822#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DPCPU_FW_ID_OFST 6
17823#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DPCPU_FW_ID_LEN 2
17824/* enum: Standard TXDP firmware */
17825#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP 0x0
17826/* enum: Low latency TXDP firmware */
17827#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_LOW_LATENCY 0x1
17828/* enum: High packet rate TXDP firmware */
17829#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_HIGH_PACKET_RATE 0x3
17830/* enum: Rules engine TXDP firmware */
17831#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_RULES_ENGINE 0x5
17832/* enum: DPDK TXDP firmware */
17833#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_DPDK 0x6
17834/* enum: BIST TXDP firmware */
17835#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_BIST 0x12d
17836/* enum: TXDP Test firmware image 1 */
17837#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
17838/* enum: TXDP Test firmware image 2 */
17839#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
17840/* enum: TXDP CSR bus test firmware */
17841#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_CSR 0x103
17842#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_OFST 8
17843#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_LEN 2
17844#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_OFST 8
17845#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_LBN 0
17846#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_WIDTH 12
17847#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_OFST 8
17848#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_LBN 12
17849#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
17850/* enum: reserved value - do not use (may indicate alternative interpretation
17851 * of REV field in future)
17852 */
17853#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RESERVED 0x0
17854/* enum: Trivial RX PD firmware for early Huntington development (Huntington
17855 * development only)
17856 */
17857#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
17858/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
17859 */
17860#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17861/* enum: RX PD firmware with approximately Siena-compatible behaviour
17862 * (Huntington development only)
17863 */
17864#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
17865/* enum: Full featured RX PD production firmware */
17866#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
17867/* enum: (deprecated original name for the FULL_FEATURED variant) */
17868#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_VSWITCH 0x3
17869/* enum: siena_compat variant RX PD firmware using PM rather than MAC
17870 * (Huntington development only)
17871 */
17872#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17873/* enum: Low latency RX PD production firmware */
17874#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
17875/* enum: Packed stream RX PD production firmware */
17876#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
17877/* enum: RX PD firmware handling layer 2 only for high packet rate performance
17878 * tests (Medford development only)
17879 */
17880#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
17881/* enum: Rules engine RX PD production firmware */
17882#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
17883/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17884#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_L3XUDP 0x9
17885/* enum: DPDK RX PD production firmware */
17886#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_DPDK 0xa
17887/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
17888#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17889/* enum: RX PD firmware parsing but not filtering network overlay tunnel
17890 * encapsulations (Medford development only)
17891 */
17892#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
17893#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_OFST 10
17894#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_LEN 2
17895#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_OFST 10
17896#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_LBN 0
17897#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_WIDTH 12
17898#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_OFST 10
17899#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_LBN 12
17900#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
17901/* enum: reserved value - do not use (may indicate alternative interpretation
17902 * of REV field in future)
17903 */
17904#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RESERVED 0x0
17905/* enum: Trivial TX PD firmware for early Huntington development (Huntington
17906 * development only)
17907 */
17908#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
17909/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
17910 */
17911#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17912/* enum: TX PD firmware with approximately Siena-compatible behaviour
17913 * (Huntington development only)
17914 */
17915#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
17916/* enum: Full featured TX PD production firmware */
17917#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
17918/* enum: (deprecated original name for the FULL_FEATURED variant) */
17919#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_VSWITCH 0x3
17920/* enum: siena_compat variant TX PD firmware using PM rather than MAC
17921 * (Huntington development only)
17922 */
17923#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17924#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
17925/* enum: TX PD firmware handling layer 2 only for high packet rate performance
17926 * tests (Medford development only)
17927 */
17928#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
17929/* enum: Rules engine TX PD production firmware */
17930#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
17931/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17932#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_L3XUDP 0x9
17933/* enum: DPDK TX PD production firmware */
17934#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_DPDK 0xa
17935/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
17936#define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17937/* Hardware capabilities of NIC */
17938#define MC_CMD_GET_CAPABILITIES_V10_OUT_HW_CAPABILITIES_OFST 12
17939#define MC_CMD_GET_CAPABILITIES_V10_OUT_HW_CAPABILITIES_LEN 4
17940/* Licensed capabilities */
17941#define MC_CMD_GET_CAPABILITIES_V10_OUT_LICENSE_CAPABILITIES_OFST 16
17942#define MC_CMD_GET_CAPABILITIES_V10_OUT_LICENSE_CAPABILITIES_LEN 4
17943/* Second word of flags. Not present on older firmware (check the length). */
17944#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS2_OFST 20
17945#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS2_LEN 4
17946#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_OFST 20
17947#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_LBN 0
17948#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_WIDTH 1
17949#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_OFST 20
17950#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_LBN 1
17951#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_ENCAP_WIDTH 1
17952#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_OFST 20
17953#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_LBN 2
17954#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVQ_TIMER_CTRL_WIDTH 1
17955#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_OFST 20
17956#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_LBN 3
17957#define MC_CMD_GET_CAPABILITIES_V10_OUT_EVENT_CUT_THROUGH_WIDTH 1
17958#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_OFST 20
17959#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_LBN 4
17960#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_WIDTH 1
17961#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_OFST 20
17962#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_LBN 5
17963#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
17964#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
17965#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
17966#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
17967#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
17968#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
17969#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
17970#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_OFST 20
17971#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_LBN 7
17972#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_EVQ_V2_WIDTH 1
17973#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_OFST 20
17974#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_LBN 8
17975#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
17976#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_OFST 20
17977#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_LBN 9
17978#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TIMESTAMP_WIDTH 1
17979#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_OFST 20
17980#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_LBN 10
17981#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_SNIFF_WIDTH 1
17982#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_OFST 20
17983#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_LBN 11
17984#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_SNIFF_WIDTH 1
17985#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
17986#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
17987#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
17988#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_OFST 20
17989#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_LBN 13
17990#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_BACKGROUND_WIDTH 1
17991#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_OFST 20
17992#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_LBN 14
17993#define MC_CMD_GET_CAPABILITIES_V10_OUT_MCDI_DB_RETURN_WIDTH 1
17994#define MC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_OFST 20
17995#define MC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_LBN 15
17996#define MC_CMD_GET_CAPABILITIES_V10_OUT_CTPIO_WIDTH 1
17997#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_OFST 20
17998#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_LBN 16
17999#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_SUPPORT_WIDTH 1
18000#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_OFST 20
18001#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_LBN 17
18002#define MC_CMD_GET_CAPABILITIES_V10_OUT_TSA_BOUND_WIDTH 1
18003#define MC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
18004#define MC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
18005#define MC_CMD_GET_CAPABILITIES_V10_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
18006#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_OFST 20
18007#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_LBN 19
18008#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_FLAG_WIDTH 1
18009#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_OFST 20
18010#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_LBN 20
18011#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_WIDTH 1
18012#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
18013#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
18014#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
18015#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
18016#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
18017#define MC_CMD_GET_CAPABILITIES_V10_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
18018#define MC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_OFST 20
18019#define MC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_LBN 22
18020#define MC_CMD_GET_CAPABILITIES_V10_OUT_L3XUDP_SUPPORT_WIDTH 1
18021#define MC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
18022#define MC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
18023#define MC_CMD_GET_CAPABILITIES_V10_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
18024#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_OFST 20
18025#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_LBN 24
18026#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_SPREADING_WIDTH 1
18027#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_OFST 20
18028#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_LBN 25
18029#define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_HLB_IDLE_WIDTH 1
18030#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
18031#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
18032#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
18033#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
18034#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
18035#define MC_CMD_GET_CAPABILITIES_V10_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
18036#define MC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_OFST 20
18037#define MC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_LBN 28
18038#define MC_CMD_GET_CAPABILITIES_V10_OUT_BUNDLE_UPDATE_WIDTH 1
18039#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_OFST 20
18040#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_LBN 29
18041#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V3_WIDTH 1
18042#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_OFST 20
18043#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_LBN 30
18044#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_SENSORS_WIDTH 1
18045#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
18046#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
18047#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
18048/* Number of FATSOv2 contexts per datapath supported by this NIC (when
18049 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
18050 */
18051#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
18052#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
18053/* One byte per PF containing the number of the external port assigned to this
18054 * PF, indexed by PF number. Special values indicate that a PF is either not
18055 * present or not assigned.
18056 */
18057#define MC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
18058#define MC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
18059#define MC_CMD_GET_CAPABILITIES_V10_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
18060/* enum: The caller is not permitted to access information on this PF. */
18061#define MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff
18062/* enum: PF does not exist. */
18063#define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe
18064/* enum: PF does exist but is not assigned to any external port. */
18065#define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_ASSIGNED 0xfd
18066/* enum: This value indicates that PF is assigned, but it cannot be expressed
18067 * in this field. It is intended for a possible future situation where a more
18068 * complex scheme of PFs to ports mapping is being used. The future driver
18069 * should look for a new field supporting the new scheme. The current/old
18070 * driver should treat this value as PF_NOT_ASSIGNED.
18071 */
18072#define MC_CMD_GET_CAPABILITIES_V10_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
18073/* One byte per PF containing the number of its VFs, indexed by PF number. A
18074 * special value indicates that a PF is not present.
18075 */
18076#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_OFST 42
18077#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_LEN 1
18078#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VFS_PER_PF_NUM 16
18079/* enum: The caller is not permitted to access information on this PF. */
18080/* MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff */
18081/* enum: PF does not exist. */
18082/* MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe */
18083/* Number of VIs available for external ports 0-3. For devices with more than
18084 * four ports, the remainder are in NUM_VIS_PER_PORT2 in
18085 * GET_CAPABILITIES_V12_OUT.
18086 */
18087#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_OFST 58
18088#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_LEN 2
18089#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_NUM 4
18090/* Size of RX descriptor cache expressed as binary logarithm The actual size
18091 * equals (2 ^ RX_DESC_CACHE_SIZE)
18092 */
18093#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DESC_CACHE_SIZE_OFST 66
18094#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DESC_CACHE_SIZE_LEN 1
18095/* Size of TX descriptor cache expressed as binary logarithm The actual size
18096 * equals (2 ^ TX_DESC_CACHE_SIZE)
18097 */
18098#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DESC_CACHE_SIZE_OFST 67
18099#define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_DESC_CACHE_SIZE_LEN 1
18100/* Total number of available PIO buffers */
18101#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_PIO_BUFFS_OFST 68
18102#define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_PIO_BUFFS_LEN 2
18103/* Size of a single PIO buffer */
18104#define MC_CMD_GET_CAPABILITIES_V10_OUT_SIZE_PIO_BUFF_OFST 70
18105#define MC_CMD_GET_CAPABILITIES_V10_OUT_SIZE_PIO_BUFF_LEN 2
18106/* On chips later than Medford the amount of address space assigned to each VI
18107 * is configurable. This is a global setting that the driver must query to
18108 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
18109 * with 8k VI windows.
18110 */
18111#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_OFST 72
18112#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_LEN 1
18113/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
18114 * CTPIO is not mapped.
18115 */
18116#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_8K 0x0
18117/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
18118#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_16K 0x1
18119/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
18120#define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_64K 0x2
18121/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
18122 * (SF-115995-SW) in the present configuration of firmware and port mode.
18123 */
18124#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
18125#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
18126/* Number of buffers per adapter that can be used for VFIFO Stuffing
18127 * (SF-115995-SW) in the present configuration of firmware and port mode.
18128 */
18129#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
18130#define MC_CMD_GET_CAPABILITIES_V10_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
18131/* Entry count in the MAC stats array, including the final GENERATION_END
18132 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
18133 * hold at least this many 64-bit stats values, if they wish to receive all
18134 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
18135 * stats array returned will be truncated.
18136 */
18137#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_NUM_STATS_OFST 76
18138#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAC_STATS_NUM_STATS_LEN 2
18139/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
18140 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
18141 */
18142#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_MAX_OFST 80
18143#define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_MAX_LEN 4
18144/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
18145 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
18146 * they create an RX queue. Due to hardware limitations, only a small number of
18147 * different buffer sizes may be available concurrently. Nonzero entries in
18148 * this array are the sizes of buffers which the system guarantees will be
18149 * available for use. If the list is empty, there are no limitations on
18150 * concurrent buffer sizes.
18151 */
18152#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
18153#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
18154#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
18155/* Third word of flags. Not present on older firmware (check the length). */
18156#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS3_OFST 148
18157#define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS3_LEN 4
18158#define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_OFST 148
18159#define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_LBN 0
18160#define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_WIDTH 1
18161#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_OFST 148
18162#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_LBN 1
18163#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_EVEN_SPREADING_WIDTH 1
18164#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
18165#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
18166#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
18167#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_OFST 148
18168#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_LBN 3
18169#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_SUPPORTED_WIDTH 1
18170#define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_OFST 148
18171#define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_LBN 4
18172#define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_WIDTH 1
18173#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
18174#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
18175#define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
18176#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
18177#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
18178#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
18179#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
18180#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
18181#define MC_CMD_GET_CAPABILITIES_V10_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
18182#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
18183#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
18184#define MC_CMD_GET_CAPABILITIES_V10_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
18185#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
18186#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
18187#define MC_CMD_GET_CAPABILITIES_V10_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
18188#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
18189#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
18190#define MC_CMD_GET_CAPABILITIES_V10_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
18191#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
18192#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
18193#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
18194#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
18195#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
18196#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
18197#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148
18198#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13
18199#define MC_CMD_GET_CAPABILITIES_V10_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1
18200#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
18201#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
18202#define MC_CMD_GET_CAPABILITIES_V10_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
18203#define MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_OFST 148
18204#define MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_LBN 15
18205#define MC_CMD_GET_CAPABILITIES_V10_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
18206#define MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
18207#define MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
18208#define MC_CMD_GET_CAPABILITIES_V10_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
18209#define MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_OFST 148
18210#define MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_LBN 17
18211#define MC_CMD_GET_CAPABILITIES_V10_OUT_CXL_CONFIG_ENABLE_WIDTH 1
18212/* These bits are reserved for communicating test-specific capabilities to
18213 * host-side test software. All production drivers should treat this field as
18214 * opaque.
18215 */
18216#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_OFST 152
18217#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LEN 8
18218#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_OFST 152
18219#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LEN 4
18220#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LBN 1216
18221#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_WIDTH 32
18222#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_OFST 156
18223#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LEN 4
18224#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LBN 1248
18225#define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_WIDTH 32
18226/* The minimum size (in table entries) of indirection table to be allocated
18227 * from the pool for an RSS context. Note that the table size used must be a
18228 * power of 2.
18229 */
18230#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
18231#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
18232/* The maximum size (in table entries) of indirection table to be allocated
18233 * from the pool for an RSS context. Note that the table size used must be a
18234 * power of 2.
18235 */
18236#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
18237#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
18238/* The maximum number of queues that can be used by an RSS context in exclusive
18239 * mode. In exclusive mode the context has a configurable indirection table and
18240 * a configurable RSS key.
18241 */
18242#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
18243#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
18244/* The maximum number of queues that can be used by an RSS context in even-
18245 * spreading mode. In even-spreading mode the context has no indirection table
18246 * but it does have a configurable RSS key.
18247 */
18248#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
18249#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
18250/* The total number of RSS contexts supported. Note that the number of
18251 * available contexts using indirection tables is also limited by the
18252 * availability of indirection table space allocated from a common pool.
18253 */
18254#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_NUM_CONTEXTS_OFST 176
18255#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_NUM_CONTEXTS_LEN 4
18256/* The total amount of indirection table space that can be shared between RSS
18257 * contexts.
18258 */
18259#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_TABLE_POOL_SIZE_OFST 180
18260#define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_TABLE_POOL_SIZE_LEN 4
18261/* A bitmap of the queue sizes the device can provide, where bit N being set
18262 * indicates that 2**N is a valid size. The device may be limited in the number
18263 * of different queue sizes that can exist simultaneously, so a bit being set
18264 * here does not guarantee that an attempt to create a queue of that size will
18265 * succeed.
18266 */
18267#define MC_CMD_GET_CAPABILITIES_V10_OUT_SUPPORTED_QUEUE_SIZES_OFST 184
18268#define MC_CMD_GET_CAPABILITIES_V10_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
18269/* A bitmap of queue sizes that are always available, in the same format as
18270 * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes
18271 * will never fail due to unavailability of the requested size.
18272 */
18273#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_OFST 188
18274#define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
18275
18276/* MC_CMD_GET_CAPABILITIES_V11_OUT msgresponse */
18277#define MC_CMD_GET_CAPABILITIES_V11_OUT_LEN 196
18278/* First word of flags. */
18279#define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS1_OFST 0
18280#define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS1_LEN 4
18281#define MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_OFST 0
18282#define MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_LBN 3
18283#define MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_WIDTH 1
18284#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_OFST 0
18285#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_LBN 4
18286#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_WIDTH 1
18287#define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_OFST 0
18288#define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_LBN 5
18289#define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_WIDTH 1
18290#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
18291#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
18292#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
18293#define MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_OFST 0
18294#define MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_LBN 7
18295#define MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
18296#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_OFST 0
18297#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_LBN 8
18298#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
18299#define MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_OFST 0
18300#define MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_LBN 9
18301#define MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_WIDTH 1
18302#define MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
18303#define MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
18304#define MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
18305#define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
18306#define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
18307#define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
18308#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
18309#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
18310#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
18311#define MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_OFST 0
18312#define MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_LBN 13
18313#define MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
18314#define MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_OFST 0
18315#define MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_LBN 14
18316#define MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_WIDTH 1
18317#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
18318#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
18319#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
18320#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_OFST 0
18321#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_LBN 16
18322#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_WIDTH 1
18323#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_OFST 0
18324#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_LBN 17
18325#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_WIDTH 1
18326#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_OFST 0
18327#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_LBN 18
18328#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_WIDTH 1
18329#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_OFST 0
18330#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_LBN 19
18331#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_WIDTH 1
18332#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_OFST 0
18333#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_LBN 20
18334#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_WIDTH 1
18335#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_OFST 0
18336#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_LBN 21
18337#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_WIDTH 1
18338#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_OFST 0
18339#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_LBN 22
18340#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_WIDTH 1
18341#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_OFST 0
18342#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_LBN 23
18343#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_WIDTH 1
18344#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_OFST 0
18345#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_LBN 24
18346#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_WIDTH 1
18347#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_OFST 0
18348#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_LBN 25
18349#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_WIDTH 1
18350#define MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_OFST 0
18351#define MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_LBN 26
18352#define MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_WIDTH 1
18353#define MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_OFST 0
18354#define MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_LBN 27
18355#define MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
18356#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_OFST 0
18357#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_LBN 28
18358#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_WIDTH 1
18359#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
18360#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
18361#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
18362#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_OFST 0
18363#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_LBN 30
18364#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_WIDTH 1
18365#define MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_OFST 0
18366#define MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_LBN 31
18367#define MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_WIDTH 1
18368/* RxDPCPU firmware id. */
18369#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DPCPU_FW_ID_OFST 4
18370#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DPCPU_FW_ID_LEN 2
18371/* enum: Standard RXDP firmware */
18372#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP 0x0
18373/* enum: Low latency RXDP firmware */
18374#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_LOW_LATENCY 0x1
18375/* enum: Packed stream RXDP firmware */
18376#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_PACKED_STREAM 0x2
18377/* enum: Rules engine RXDP firmware */
18378#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_RULES_ENGINE 0x5
18379/* enum: DPDK RXDP firmware */
18380#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_DPDK 0x6
18381/* enum: BIST RXDP firmware */
18382#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_BIST 0x10a
18383/* enum: RXDP Test firmware image 1 */
18384#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
18385/* enum: RXDP Test firmware image 2 */
18386#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
18387/* enum: RXDP Test firmware image 3 */
18388#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
18389/* enum: RXDP Test firmware image 4 */
18390#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
18391/* enum: RXDP Test firmware image 5 */
18392#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_BACKPRESSURE 0x105
18393/* enum: RXDP Test firmware image 6 */
18394#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
18395/* enum: RXDP Test firmware image 7 */
18396#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
18397/* enum: RXDP Test firmware image 8 */
18398#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
18399/* enum: RXDP Test firmware image 9 */
18400#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
18401/* enum: RXDP Test firmware image 10 */
18402#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_SLOW 0x10c
18403/* TxDPCPU firmware id. */
18404#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DPCPU_FW_ID_OFST 6
18405#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DPCPU_FW_ID_LEN 2
18406/* enum: Standard TXDP firmware */
18407#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP 0x0
18408/* enum: Low latency TXDP firmware */
18409#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_LOW_LATENCY 0x1
18410/* enum: High packet rate TXDP firmware */
18411#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_HIGH_PACKET_RATE 0x3
18412/* enum: Rules engine TXDP firmware */
18413#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_RULES_ENGINE 0x5
18414/* enum: DPDK TXDP firmware */
18415#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_DPDK 0x6
18416/* enum: BIST TXDP firmware */
18417#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_BIST 0x12d
18418/* enum: TXDP Test firmware image 1 */
18419#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
18420/* enum: TXDP Test firmware image 2 */
18421#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
18422/* enum: TXDP CSR bus test firmware */
18423#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_CSR 0x103
18424#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_OFST 8
18425#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_LEN 2
18426#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_OFST 8
18427#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_LBN 0
18428#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_WIDTH 12
18429#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_OFST 8
18430#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_LBN 12
18431#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
18432/* enum: reserved value - do not use (may indicate alternative interpretation
18433 * of REV field in future)
18434 */
18435#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_RESERVED 0x0
18436/* enum: Trivial RX PD firmware for early Huntington development (Huntington
18437 * development only)
18438 */
18439#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
18440/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
18441 */
18442#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
18443/* enum: RX PD firmware with approximately Siena-compatible behaviour
18444 * (Huntington development only)
18445 */
18446#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
18447/* enum: Full featured RX PD production firmware */
18448#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
18449/* enum: (deprecated original name for the FULL_FEATURED variant) */
18450#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_VSWITCH 0x3
18451/* enum: siena_compat variant RX PD firmware using PM rather than MAC
18452 * (Huntington development only)
18453 */
18454#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
18455/* enum: Low latency RX PD production firmware */
18456#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
18457/* enum: Packed stream RX PD production firmware */
18458#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
18459/* enum: RX PD firmware handling layer 2 only for high packet rate performance
18460 * tests (Medford development only)
18461 */
18462#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
18463/* enum: Rules engine RX PD production firmware */
18464#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
18465/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
18466#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_L3XUDP 0x9
18467/* enum: DPDK RX PD production firmware */
18468#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_DPDK 0xa
18469/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
18470#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
18471/* enum: RX PD firmware parsing but not filtering network overlay tunnel
18472 * encapsulations (Medford development only)
18473 */
18474#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
18475#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_OFST 10
18476#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_LEN 2
18477#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_OFST 10
18478#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_LBN 0
18479#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_WIDTH 12
18480#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_OFST 10
18481#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_LBN 12
18482#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
18483/* enum: reserved value - do not use (may indicate alternative interpretation
18484 * of REV field in future)
18485 */
18486#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_RESERVED 0x0
18487/* enum: Trivial TX PD firmware for early Huntington development (Huntington
18488 * development only)
18489 */
18490#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
18491/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
18492 */
18493#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
18494/* enum: TX PD firmware with approximately Siena-compatible behaviour
18495 * (Huntington development only)
18496 */
18497#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
18498/* enum: Full featured TX PD production firmware */
18499#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
18500/* enum: (deprecated original name for the FULL_FEATURED variant) */
18501#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_VSWITCH 0x3
18502/* enum: siena_compat variant TX PD firmware using PM rather than MAC
18503 * (Huntington development only)
18504 */
18505#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
18506#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
18507/* enum: TX PD firmware handling layer 2 only for high packet rate performance
18508 * tests (Medford development only)
18509 */
18510#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
18511/* enum: Rules engine TX PD production firmware */
18512#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
18513/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
18514#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_L3XUDP 0x9
18515/* enum: DPDK TX PD production firmware */
18516#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_DPDK 0xa
18517/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
18518#define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
18519/* Hardware capabilities of NIC */
18520#define MC_CMD_GET_CAPABILITIES_V11_OUT_HW_CAPABILITIES_OFST 12
18521#define MC_CMD_GET_CAPABILITIES_V11_OUT_HW_CAPABILITIES_LEN 4
18522/* Licensed capabilities */
18523#define MC_CMD_GET_CAPABILITIES_V11_OUT_LICENSE_CAPABILITIES_OFST 16
18524#define MC_CMD_GET_CAPABILITIES_V11_OUT_LICENSE_CAPABILITIES_LEN 4
18525/* Second word of flags. Not present on older firmware (check the length). */
18526#define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS2_OFST 20
18527#define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS2_LEN 4
18528#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_OFST 20
18529#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_LBN 0
18530#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_WIDTH 1
18531#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_OFST 20
18532#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_LBN 1
18533#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_ENCAP_WIDTH 1
18534#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_OFST 20
18535#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_LBN 2
18536#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVQ_TIMER_CTRL_WIDTH 1
18537#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_OFST 20
18538#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_LBN 3
18539#define MC_CMD_GET_CAPABILITIES_V11_OUT_EVENT_CUT_THROUGH_WIDTH 1
18540#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_OFST 20
18541#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_LBN 4
18542#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_WIDTH 1
18543#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_OFST 20
18544#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_LBN 5
18545#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
18546#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
18547#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
18548#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
18549#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
18550#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
18551#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
18552#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_OFST 20
18553#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_LBN 7
18554#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_EVQ_V2_WIDTH 1
18555#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_OFST 20
18556#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_LBN 8
18557#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
18558#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_OFST 20
18559#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_LBN 9
18560#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TIMESTAMP_WIDTH 1
18561#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_OFST 20
18562#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_LBN 10
18563#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_SNIFF_WIDTH 1
18564#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_OFST 20
18565#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_LBN 11
18566#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_SNIFF_WIDTH 1
18567#define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
18568#define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
18569#define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
18570#define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_OFST 20
18571#define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_LBN 13
18572#define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_BACKGROUND_WIDTH 1
18573#define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_OFST 20
18574#define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_LBN 14
18575#define MC_CMD_GET_CAPABILITIES_V11_OUT_MCDI_DB_RETURN_WIDTH 1
18576#define MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_OFST 20
18577#define MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_LBN 15
18578#define MC_CMD_GET_CAPABILITIES_V11_OUT_CTPIO_WIDTH 1
18579#define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_OFST 20
18580#define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_LBN 16
18581#define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_SUPPORT_WIDTH 1
18582#define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_OFST 20
18583#define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_LBN 17
18584#define MC_CMD_GET_CAPABILITIES_V11_OUT_TSA_BOUND_WIDTH 1
18585#define MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
18586#define MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
18587#define MC_CMD_GET_CAPABILITIES_V11_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
18588#define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_OFST 20
18589#define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_LBN 19
18590#define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_FLAG_WIDTH 1
18591#define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_OFST 20
18592#define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_LBN 20
18593#define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_WIDTH 1
18594#define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
18595#define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
18596#define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
18597#define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
18598#define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
18599#define MC_CMD_GET_CAPABILITIES_V11_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
18600#define MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_OFST 20
18601#define MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_LBN 22
18602#define MC_CMD_GET_CAPABILITIES_V11_OUT_L3XUDP_SUPPORT_WIDTH 1
18603#define MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
18604#define MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
18605#define MC_CMD_GET_CAPABILITIES_V11_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
18606#define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_OFST 20
18607#define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_LBN 24
18608#define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_SPREADING_WIDTH 1
18609#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_OFST 20
18610#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_LBN 25
18611#define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_HLB_IDLE_WIDTH 1
18612#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
18613#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
18614#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
18615#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
18616#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
18617#define MC_CMD_GET_CAPABILITIES_V11_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
18618#define MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_OFST 20
18619#define MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_LBN 28
18620#define MC_CMD_GET_CAPABILITIES_V11_OUT_BUNDLE_UPDATE_WIDTH 1
18621#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_OFST 20
18622#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_LBN 29
18623#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V3_WIDTH 1
18624#define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_OFST 20
18625#define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_LBN 30
18626#define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_SENSORS_WIDTH 1
18627#define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
18628#define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
18629#define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
18630/* Number of FATSOv2 contexts per datapath supported by this NIC (when
18631 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
18632 */
18633#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
18634#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
18635/* One byte per PF containing the number of the external port assigned to this
18636 * PF, indexed by PF number. Special values indicate that a PF is either not
18637 * present or not assigned.
18638 */
18639#define MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
18640#define MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
18641#define MC_CMD_GET_CAPABILITIES_V11_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
18642/* enum: The caller is not permitted to access information on this PF. */
18643#define MC_CMD_GET_CAPABILITIES_V11_OUT_ACCESS_NOT_PERMITTED 0xff
18644/* enum: PF does not exist. */
18645#define MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_PRESENT 0xfe
18646/* enum: PF does exist but is not assigned to any external port. */
18647#define MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_ASSIGNED 0xfd
18648/* enum: This value indicates that PF is assigned, but it cannot be expressed
18649 * in this field. It is intended for a possible future situation where a more
18650 * complex scheme of PFs to ports mapping is being used. The future driver
18651 * should look for a new field supporting the new scheme. The current/old
18652 * driver should treat this value as PF_NOT_ASSIGNED.
18653 */
18654#define MC_CMD_GET_CAPABILITIES_V11_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
18655/* One byte per PF containing the number of its VFs, indexed by PF number. A
18656 * special value indicates that a PF is not present.
18657 */
18658#define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_OFST 42
18659#define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_LEN 1
18660#define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VFS_PER_PF_NUM 16
18661/* enum: The caller is not permitted to access information on this PF. */
18662/* MC_CMD_GET_CAPABILITIES_V11_OUT_ACCESS_NOT_PERMITTED 0xff */
18663/* enum: PF does not exist. */
18664/* MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_PRESENT 0xfe */
18665/* Number of VIs available for external ports 0-3. For devices with more than
18666 * four ports, the remainder are in NUM_VIS_PER_PORT2 in
18667 * GET_CAPABILITIES_V12_OUT.
18668 */
18669#define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_OFST 58
18670#define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_LEN 2
18671#define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_NUM 4
18672/* Size of RX descriptor cache expressed as binary logarithm The actual size
18673 * equals (2 ^ RX_DESC_CACHE_SIZE)
18674 */
18675#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DESC_CACHE_SIZE_OFST 66
18676#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DESC_CACHE_SIZE_LEN 1
18677/* Size of TX descriptor cache expressed as binary logarithm The actual size
18678 * equals (2 ^ TX_DESC_CACHE_SIZE)
18679 */
18680#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DESC_CACHE_SIZE_OFST 67
18681#define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_DESC_CACHE_SIZE_LEN 1
18682/* Total number of available PIO buffers */
18683#define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_PIO_BUFFS_OFST 68
18684#define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_PIO_BUFFS_LEN 2
18685/* Size of a single PIO buffer */
18686#define MC_CMD_GET_CAPABILITIES_V11_OUT_SIZE_PIO_BUFF_OFST 70
18687#define MC_CMD_GET_CAPABILITIES_V11_OUT_SIZE_PIO_BUFF_LEN 2
18688/* On chips later than Medford the amount of address space assigned to each VI
18689 * is configurable. This is a global setting that the driver must query to
18690 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
18691 * with 8k VI windows.
18692 */
18693#define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_OFST 72
18694#define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_LEN 1
18695/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
18696 * CTPIO is not mapped.
18697 */
18698#define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_8K 0x0
18699/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
18700#define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_16K 0x1
18701/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
18702#define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_64K 0x2
18703/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
18704 * (SF-115995-SW) in the present configuration of firmware and port mode.
18705 */
18706#define MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
18707#define MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
18708/* Number of buffers per adapter that can be used for VFIFO Stuffing
18709 * (SF-115995-SW) in the present configuration of firmware and port mode.
18710 */
18711#define MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
18712#define MC_CMD_GET_CAPABILITIES_V11_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
18713/* Entry count in the MAC stats array, including the final GENERATION_END
18714 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
18715 * hold at least this many 64-bit stats values, if they wish to receive all
18716 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
18717 * stats array returned will be truncated.
18718 */
18719#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_NUM_STATS_OFST 76
18720#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAC_STATS_NUM_STATS_LEN 2
18721/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
18722 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
18723 */
18724#define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_MAX_OFST 80
18725#define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_MAX_LEN 4
18726/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
18727 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
18728 * they create an RX queue. Due to hardware limitations, only a small number of
18729 * different buffer sizes may be available concurrently. Nonzero entries in
18730 * this array are the sizes of buffers which the system guarantees will be
18731 * available for use. If the list is empty, there are no limitations on
18732 * concurrent buffer sizes.
18733 */
18734#define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
18735#define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
18736#define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
18737/* Third word of flags. Not present on older firmware (check the length). */
18738#define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS3_OFST 148
18739#define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS3_LEN 4
18740#define MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_OFST 148
18741#define MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_LBN 0
18742#define MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_WIDTH 1
18743#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_OFST 148
18744#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_LBN 1
18745#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_EVEN_SPREADING_WIDTH 1
18746#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
18747#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
18748#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
18749#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_OFST 148
18750#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_LBN 3
18751#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_SUPPORTED_WIDTH 1
18752#define MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_OFST 148
18753#define MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_LBN 4
18754#define MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_WIDTH 1
18755#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
18756#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
18757#define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
18758#define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
18759#define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
18760#define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
18761#define MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
18762#define MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
18763#define MC_CMD_GET_CAPABILITIES_V11_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
18764#define MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
18765#define MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
18766#define MC_CMD_GET_CAPABILITIES_V11_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
18767#define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
18768#define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
18769#define MC_CMD_GET_CAPABILITIES_V11_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
18770#define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
18771#define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
18772#define MC_CMD_GET_CAPABILITIES_V11_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
18773#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
18774#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
18775#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
18776#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
18777#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
18778#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
18779#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148
18780#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13
18781#define MC_CMD_GET_CAPABILITIES_V11_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1
18782#define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
18783#define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
18784#define MC_CMD_GET_CAPABILITIES_V11_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
18785#define MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_OFST 148
18786#define MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_LBN 15
18787#define MC_CMD_GET_CAPABILITIES_V11_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
18788#define MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
18789#define MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
18790#define MC_CMD_GET_CAPABILITIES_V11_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
18791#define MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_OFST 148
18792#define MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_LBN 17
18793#define MC_CMD_GET_CAPABILITIES_V11_OUT_CXL_CONFIG_ENABLE_WIDTH 1
18794/* These bits are reserved for communicating test-specific capabilities to
18795 * host-side test software. All production drivers should treat this field as
18796 * opaque.
18797 */
18798#define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_OFST 152
18799#define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LEN 8
18800#define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_OFST 152
18801#define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_LEN 4
18802#define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_LBN 1216
18803#define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_WIDTH 32
18804#define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_OFST 156
18805#define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_LEN 4
18806#define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_LBN 1248
18807#define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_WIDTH 32
18808/* The minimum size (in table entries) of indirection table to be allocated
18809 * from the pool for an RSS context. Note that the table size used must be a
18810 * power of 2.
18811 */
18812#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
18813#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
18814/* The maximum size (in table entries) of indirection table to be allocated
18815 * from the pool for an RSS context. Note that the table size used must be a
18816 * power of 2.
18817 */
18818#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
18819#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
18820/* The maximum number of queues that can be used by an RSS context in exclusive
18821 * mode. In exclusive mode the context has a configurable indirection table and
18822 * a configurable RSS key.
18823 */
18824#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
18825#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
18826/* The maximum number of queues that can be used by an RSS context in even-
18827 * spreading mode. In even-spreading mode the context has no indirection table
18828 * but it does have a configurable RSS key.
18829 */
18830#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
18831#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
18832/* The total number of RSS contexts supported. Note that the number of
18833 * available contexts using indirection tables is also limited by the
18834 * availability of indirection table space allocated from a common pool.
18835 */
18836#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_NUM_CONTEXTS_OFST 176
18837#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_NUM_CONTEXTS_LEN 4
18838/* The total amount of indirection table space that can be shared between RSS
18839 * contexts.
18840 */
18841#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_TABLE_POOL_SIZE_OFST 180
18842#define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_TABLE_POOL_SIZE_LEN 4
18843/* A bitmap of the queue sizes the device can provide, where bit N being set
18844 * indicates that 2**N is a valid size. The device may be limited in the number
18845 * of different queue sizes that can exist simultaneously, so a bit being set
18846 * here does not guarantee that an attempt to create a queue of that size will
18847 * succeed.
18848 */
18849#define MC_CMD_GET_CAPABILITIES_V11_OUT_SUPPORTED_QUEUE_SIZES_OFST 184
18850#define MC_CMD_GET_CAPABILITIES_V11_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
18851/* A bitmap of queue sizes that are always available, in the same format as
18852 * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes
18853 * will never fail due to unavailability of the requested size.
18854 */
18855#define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_QUEUE_SIZES_OFST 188
18856#define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
18857/* Number of available indirect memory maps. */
18858#define MC_CMD_GET_CAPABILITIES_V11_OUT_INDIRECT_MAP_INDEX_COUNT_OFST 192
18859#define MC_CMD_GET_CAPABILITIES_V11_OUT_INDIRECT_MAP_INDEX_COUNT_LEN 4
18860
18861/* MC_CMD_GET_CAPABILITIES_V12_OUT msgresponse */
18862#define MC_CMD_GET_CAPABILITIES_V12_OUT_LEN 204
18863/* First word of flags. */
18864#define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS1_OFST 0
18865#define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS1_LEN 4
18866#define MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_OFST 0
18867#define MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_LBN 3
18868#define MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_WIDTH 1
18869#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_OFST 0
18870#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_LBN 4
18871#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_WIDTH 1
18872#define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_OFST 0
18873#define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_LBN 5
18874#define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_WIDTH 1
18875#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
18876#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
18877#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
18878#define MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_OFST 0
18879#define MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_LBN 7
18880#define MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
18881#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_OFST 0
18882#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_LBN 8
18883#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
18884#define MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_OFST 0
18885#define MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_LBN 9
18886#define MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_WIDTH 1
18887#define MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
18888#define MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
18889#define MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
18890#define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
18891#define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
18892#define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
18893#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
18894#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
18895#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
18896#define MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_OFST 0
18897#define MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_LBN 13
18898#define MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
18899#define MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_OFST 0
18900#define MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_LBN 14
18901#define MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_WIDTH 1
18902#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
18903#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
18904#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
18905#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_OFST 0
18906#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_LBN 16
18907#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_WIDTH 1
18908#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_OFST 0
18909#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_LBN 17
18910#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_WIDTH 1
18911#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_OFST 0
18912#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_LBN 18
18913#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_WIDTH 1
18914#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_OFST 0
18915#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_LBN 19
18916#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_WIDTH 1
18917#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_OFST 0
18918#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_LBN 20
18919#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_WIDTH 1
18920#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_OFST 0
18921#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_LBN 21
18922#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_WIDTH 1
18923#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_OFST 0
18924#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_LBN 22
18925#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_WIDTH 1
18926#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_OFST 0
18927#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_LBN 23
18928#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_WIDTH 1
18929#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_OFST 0
18930#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_LBN 24
18931#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_WIDTH 1
18932#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_OFST 0
18933#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_LBN 25
18934#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_WIDTH 1
18935#define MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_OFST 0
18936#define MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_LBN 26
18937#define MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_WIDTH 1
18938#define MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_OFST 0
18939#define MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_LBN 27
18940#define MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
18941#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_OFST 0
18942#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_LBN 28
18943#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_WIDTH 1
18944#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
18945#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
18946#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
18947#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_OFST 0
18948#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_LBN 30
18949#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_WIDTH 1
18950#define MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_OFST 0
18951#define MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_LBN 31
18952#define MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_WIDTH 1
18953/* RxDPCPU firmware id. */
18954#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DPCPU_FW_ID_OFST 4
18955#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DPCPU_FW_ID_LEN 2
18956/* enum: Standard RXDP firmware */
18957#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP 0x0
18958/* enum: Low latency RXDP firmware */
18959#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_LOW_LATENCY 0x1
18960/* enum: Packed stream RXDP firmware */
18961#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_PACKED_STREAM 0x2
18962/* enum: Rules engine RXDP firmware */
18963#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_RULES_ENGINE 0x5
18964/* enum: DPDK RXDP firmware */
18965#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_DPDK 0x6
18966/* enum: BIST RXDP firmware */
18967#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_BIST 0x10a
18968/* enum: RXDP Test firmware image 1 */
18969#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
18970/* enum: RXDP Test firmware image 2 */
18971#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
18972/* enum: RXDP Test firmware image 3 */
18973#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
18974/* enum: RXDP Test firmware image 4 */
18975#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
18976/* enum: RXDP Test firmware image 5 */
18977#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_BACKPRESSURE 0x105
18978/* enum: RXDP Test firmware image 6 */
18979#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
18980/* enum: RXDP Test firmware image 7 */
18981#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
18982/* enum: RXDP Test firmware image 8 */
18983#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
18984/* enum: RXDP Test firmware image 9 */
18985#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
18986/* enum: RXDP Test firmware image 10 */
18987#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_SLOW 0x10c
18988/* TxDPCPU firmware id. */
18989#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DPCPU_FW_ID_OFST 6
18990#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DPCPU_FW_ID_LEN 2
18991/* enum: Standard TXDP firmware */
18992#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP 0x0
18993/* enum: Low latency TXDP firmware */
18994#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_LOW_LATENCY 0x1
18995/* enum: High packet rate TXDP firmware */
18996#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_HIGH_PACKET_RATE 0x3
18997/* enum: Rules engine TXDP firmware */
18998#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_RULES_ENGINE 0x5
18999/* enum: DPDK TXDP firmware */
19000#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_DPDK 0x6
19001/* enum: BIST TXDP firmware */
19002#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_BIST 0x12d
19003/* enum: TXDP Test firmware image 1 */
19004#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
19005/* enum: TXDP Test firmware image 2 */
19006#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
19007/* enum: TXDP CSR bus test firmware */
19008#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_CSR 0x103
19009#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_OFST 8
19010#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_LEN 2
19011#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_OFST 8
19012#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_LBN 0
19013#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_WIDTH 12
19014#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_OFST 8
19015#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_LBN 12
19016#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
19017/* enum: reserved value - do not use (may indicate alternative interpretation
19018 * of REV field in future)
19019 */
19020#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_RESERVED 0x0
19021/* enum: Trivial RX PD firmware for early Huntington development (Huntington
19022 * development only)
19023 */
19024#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
19025/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
19026 */
19027#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
19028/* enum: RX PD firmware with approximately Siena-compatible behaviour
19029 * (Huntington development only)
19030 */
19031#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
19032/* enum: Full featured RX PD production firmware */
19033#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
19034/* enum: (deprecated original name for the FULL_FEATURED variant) */
19035#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_VSWITCH 0x3
19036/* enum: siena_compat variant RX PD firmware using PM rather than MAC
19037 * (Huntington development only)
19038 */
19039#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
19040/* enum: Low latency RX PD production firmware */
19041#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
19042/* enum: Packed stream RX PD production firmware */
19043#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
19044/* enum: RX PD firmware handling layer 2 only for high packet rate performance
19045 * tests (Medford development only)
19046 */
19047#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
19048/* enum: Rules engine RX PD production firmware */
19049#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
19050/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
19051#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_L3XUDP 0x9
19052/* enum: DPDK RX PD production firmware */
19053#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_DPDK 0xa
19054/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
19055#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
19056/* enum: RX PD firmware parsing but not filtering network overlay tunnel
19057 * encapsulations (Medford development only)
19058 */
19059#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
19060#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_OFST 10
19061#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_LEN 2
19062#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_OFST 10
19063#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_LBN 0
19064#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_WIDTH 12
19065#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_OFST 10
19066#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_LBN 12
19067#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
19068/* enum: reserved value - do not use (may indicate alternative interpretation
19069 * of REV field in future)
19070 */
19071#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_RESERVED 0x0
19072/* enum: Trivial TX PD firmware for early Huntington development (Huntington
19073 * development only)
19074 */
19075#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
19076/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
19077 */
19078#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
19079/* enum: TX PD firmware with approximately Siena-compatible behaviour
19080 * (Huntington development only)
19081 */
19082#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
19083/* enum: Full featured TX PD production firmware */
19084#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
19085/* enum: (deprecated original name for the FULL_FEATURED variant) */
19086#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_VSWITCH 0x3
19087/* enum: siena_compat variant TX PD firmware using PM rather than MAC
19088 * (Huntington development only)
19089 */
19090#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
19091#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
19092/* enum: TX PD firmware handling layer 2 only for high packet rate performance
19093 * tests (Medford development only)
19094 */
19095#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
19096/* enum: Rules engine TX PD production firmware */
19097#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
19098/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
19099#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_L3XUDP 0x9
19100/* enum: DPDK TX PD production firmware */
19101#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_DPDK 0xa
19102/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
19103#define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
19104/* Hardware capabilities of NIC */
19105#define MC_CMD_GET_CAPABILITIES_V12_OUT_HW_CAPABILITIES_OFST 12
19106#define MC_CMD_GET_CAPABILITIES_V12_OUT_HW_CAPABILITIES_LEN 4
19107/* Licensed capabilities */
19108#define MC_CMD_GET_CAPABILITIES_V12_OUT_LICENSE_CAPABILITIES_OFST 16
19109#define MC_CMD_GET_CAPABILITIES_V12_OUT_LICENSE_CAPABILITIES_LEN 4
19110/* Second word of flags. Not present on older firmware (check the length). */
19111#define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS2_OFST 20
19112#define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS2_LEN 4
19113#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_OFST 20
19114#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_LBN 0
19115#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_WIDTH 1
19116#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_OFST 20
19117#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_LBN 1
19118#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_ENCAP_WIDTH 1
19119#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_OFST 20
19120#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_LBN 2
19121#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVQ_TIMER_CTRL_WIDTH 1
19122#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_OFST 20
19123#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_LBN 3
19124#define MC_CMD_GET_CAPABILITIES_V12_OUT_EVENT_CUT_THROUGH_WIDTH 1
19125#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_OFST 20
19126#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_LBN 4
19127#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_WIDTH 1
19128#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_OFST 20
19129#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_LBN 5
19130#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
19131#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
19132#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
19133#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
19134#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
19135#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
19136#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
19137#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_OFST 20
19138#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_LBN 7
19139#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_EVQ_V2_WIDTH 1
19140#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_OFST 20
19141#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_LBN 8
19142#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
19143#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_OFST 20
19144#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_LBN 9
19145#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TIMESTAMP_WIDTH 1
19146#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_OFST 20
19147#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_LBN 10
19148#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_SNIFF_WIDTH 1
19149#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_OFST 20
19150#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_LBN 11
19151#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_SNIFF_WIDTH 1
19152#define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
19153#define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
19154#define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
19155#define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_OFST 20
19156#define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_LBN 13
19157#define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_BACKGROUND_WIDTH 1
19158#define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_OFST 20
19159#define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_LBN 14
19160#define MC_CMD_GET_CAPABILITIES_V12_OUT_MCDI_DB_RETURN_WIDTH 1
19161#define MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_OFST 20
19162#define MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_LBN 15
19163#define MC_CMD_GET_CAPABILITIES_V12_OUT_CTPIO_WIDTH 1
19164#define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_OFST 20
19165#define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_LBN 16
19166#define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_SUPPORT_WIDTH 1
19167#define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_OFST 20
19168#define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_LBN 17
19169#define MC_CMD_GET_CAPABILITIES_V12_OUT_TSA_BOUND_WIDTH 1
19170#define MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
19171#define MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
19172#define MC_CMD_GET_CAPABILITIES_V12_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
19173#define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_OFST 20
19174#define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_LBN 19
19175#define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_FLAG_WIDTH 1
19176#define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_OFST 20
19177#define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_LBN 20
19178#define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_WIDTH 1
19179#define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
19180#define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
19181#define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
19182#define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
19183#define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
19184#define MC_CMD_GET_CAPABILITIES_V12_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
19185#define MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_OFST 20
19186#define MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_LBN 22
19187#define MC_CMD_GET_CAPABILITIES_V12_OUT_L3XUDP_SUPPORT_WIDTH 1
19188#define MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
19189#define MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
19190#define MC_CMD_GET_CAPABILITIES_V12_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
19191#define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_OFST 20
19192#define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_LBN 24
19193#define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_SPREADING_WIDTH 1
19194#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_OFST 20
19195#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_LBN 25
19196#define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_HLB_IDLE_WIDTH 1
19197#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
19198#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
19199#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
19200#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
19201#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
19202#define MC_CMD_GET_CAPABILITIES_V12_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
19203#define MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_OFST 20
19204#define MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_LBN 28
19205#define MC_CMD_GET_CAPABILITIES_V12_OUT_BUNDLE_UPDATE_WIDTH 1
19206#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_OFST 20
19207#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_LBN 29
19208#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V3_WIDTH 1
19209#define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_OFST 20
19210#define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_LBN 30
19211#define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_SENSORS_WIDTH 1
19212#define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
19213#define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
19214#define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
19215/* Number of FATSOv2 contexts per datapath supported by this NIC (when
19216 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
19217 */
19218#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
19219#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
19220/* One byte per PF containing the number of the external port assigned to this
19221 * PF, indexed by PF number. Special values indicate that a PF is either not
19222 * present or not assigned.
19223 */
19224#define MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
19225#define MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
19226#define MC_CMD_GET_CAPABILITIES_V12_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
19227/* enum: The caller is not permitted to access information on this PF. */
19228#define MC_CMD_GET_CAPABILITIES_V12_OUT_ACCESS_NOT_PERMITTED 0xff
19229/* enum: PF does not exist. */
19230#define MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_PRESENT 0xfe
19231/* enum: PF does exist but is not assigned to any external port. */
19232#define MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_ASSIGNED 0xfd
19233/* enum: This value indicates that PF is assigned, but it cannot be expressed
19234 * in this field. It is intended for a possible future situation where a more
19235 * complex scheme of PFs to ports mapping is being used. The future driver
19236 * should look for a new field supporting the new scheme. The current/old
19237 * driver should treat this value as PF_NOT_ASSIGNED.
19238 */
19239#define MC_CMD_GET_CAPABILITIES_V12_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
19240/* One byte per PF containing the number of its VFs, indexed by PF number. A
19241 * special value indicates that a PF is not present.
19242 */
19243#define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_OFST 42
19244#define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_LEN 1
19245#define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VFS_PER_PF_NUM 16
19246/* enum: The caller is not permitted to access information on this PF. */
19247/* MC_CMD_GET_CAPABILITIES_V12_OUT_ACCESS_NOT_PERMITTED 0xff */
19248/* enum: PF does not exist. */
19249/* MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_PRESENT 0xfe */
19250/* Number of VIs available for external ports 0-3. For devices with more than
19251 * four ports, the remainder are in NUM_VIS_PER_PORT2 in
19252 * GET_CAPABILITIES_V12_OUT.
19253 */
19254#define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_OFST 58
19255#define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_LEN 2
19256#define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_NUM 4
19257/* Size of RX descriptor cache expressed as binary logarithm The actual size
19258 * equals (2 ^ RX_DESC_CACHE_SIZE)
19259 */
19260#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DESC_CACHE_SIZE_OFST 66
19261#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DESC_CACHE_SIZE_LEN 1
19262/* Size of TX descriptor cache expressed as binary logarithm The actual size
19263 * equals (2 ^ TX_DESC_CACHE_SIZE)
19264 */
19265#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DESC_CACHE_SIZE_OFST 67
19266#define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_DESC_CACHE_SIZE_LEN 1
19267/* Total number of available PIO buffers */
19268#define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_PIO_BUFFS_OFST 68
19269#define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_PIO_BUFFS_LEN 2
19270/* Size of a single PIO buffer */
19271#define MC_CMD_GET_CAPABILITIES_V12_OUT_SIZE_PIO_BUFF_OFST 70
19272#define MC_CMD_GET_CAPABILITIES_V12_OUT_SIZE_PIO_BUFF_LEN 2
19273/* On chips later than Medford the amount of address space assigned to each VI
19274 * is configurable. This is a global setting that the driver must query to
19275 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
19276 * with 8k VI windows.
19277 */
19278#define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_OFST 72
19279#define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_LEN 1
19280/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
19281 * CTPIO is not mapped.
19282 */
19283#define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_8K 0x0
19284/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
19285#define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_16K 0x1
19286/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
19287#define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_64K 0x2
19288/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
19289 * (SF-115995-SW) in the present configuration of firmware and port mode.
19290 */
19291#define MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
19292#define MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
19293/* Number of buffers per adapter that can be used for VFIFO Stuffing
19294 * (SF-115995-SW) in the present configuration of firmware and port mode.
19295 */
19296#define MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
19297#define MC_CMD_GET_CAPABILITIES_V12_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
19298/* Entry count in the MAC stats array, including the final GENERATION_END
19299 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
19300 * hold at least this many 64-bit stats values, if they wish to receive all
19301 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
19302 * stats array returned will be truncated.
19303 */
19304#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_NUM_STATS_OFST 76
19305#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAC_STATS_NUM_STATS_LEN 2
19306/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
19307 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
19308 */
19309#define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_MAX_OFST 80
19310#define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_MAX_LEN 4
19311/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
19312 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
19313 * they create an RX queue. Due to hardware limitations, only a small number of
19314 * different buffer sizes may be available concurrently. Nonzero entries in
19315 * this array are the sizes of buffers which the system guarantees will be
19316 * available for use. If the list is empty, there are no limitations on
19317 * concurrent buffer sizes.
19318 */
19319#define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
19320#define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
19321#define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
19322/* Third word of flags. Not present on older firmware (check the length). */
19323#define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS3_OFST 148
19324#define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS3_LEN 4
19325#define MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_OFST 148
19326#define MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_LBN 0
19327#define MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_WIDTH 1
19328#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_OFST 148
19329#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_LBN 1
19330#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_EVEN_SPREADING_WIDTH 1
19331#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
19332#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
19333#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
19334#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_OFST 148
19335#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_LBN 3
19336#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_SUPPORTED_WIDTH 1
19337#define MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_OFST 148
19338#define MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_LBN 4
19339#define MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_WIDTH 1
19340#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
19341#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
19342#define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
19343#define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
19344#define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
19345#define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
19346#define MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
19347#define MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
19348#define MC_CMD_GET_CAPABILITIES_V12_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
19349#define MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_OFST 148
19350#define MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_LBN 8
19351#define MC_CMD_GET_CAPABILITIES_V12_OUT_ENCAPSULATED_MCDI_SUPPORTED_WIDTH 1
19352#define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_OFST 148
19353#define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_LBN 9
19354#define MC_CMD_GET_CAPABILITIES_V12_OUT_EXTERNAL_MAE_SUPPORTED_WIDTH 1
19355#define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_OFST 148
19356#define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_LBN 10
19357#define MC_CMD_GET_CAPABILITIES_V12_OUT_NVRAM_UPDATE_ABORT_SUPPORTED_WIDTH 1
19358#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_OFST 148
19359#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_LBN 11
19360#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V2_SUPPORTED_WIDTH 1
19361#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_OFST 148
19362#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_LBN 12
19363#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_STEER_ON_OUTER_SUPPORTED_WIDTH 1
19364#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_OFST 148
19365#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_LBN 13
19366#define MC_CMD_GET_CAPABILITIES_V12_OUT_MAE_ACTION_SET_ALLOC_V3_SUPPORTED_WIDTH 1
19367#define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_OFST 148
19368#define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_LBN 14
19369#define MC_CMD_GET_CAPABILITIES_V12_OUT_DYNAMIC_MPORT_JOURNAL_WIDTH 1
19370#define MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_OFST 148
19371#define MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_LBN 15
19372#define MC_CMD_GET_CAPABILITIES_V12_OUT_CLIENT_CMD_VF_PROXY_WIDTH 1
19373#define MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_OFST 148
19374#define MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_LBN 16
19375#define MC_CMD_GET_CAPABILITIES_V12_OUT_LL_RX_EVENT_SUPPRESSION_SUPPORTED_WIDTH 1
19376#define MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_OFST 148
19377#define MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_LBN 17
19378#define MC_CMD_GET_CAPABILITIES_V12_OUT_CXL_CONFIG_ENABLE_WIDTH 1
19379/* These bits are reserved for communicating test-specific capabilities to
19380 * host-side test software. All production drivers should treat this field as
19381 * opaque.
19382 */
19383#define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_OFST 152
19384#define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LEN 8
19385#define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_OFST 152
19386#define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_LEN 4
19387#define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_LBN 1216
19388#define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_WIDTH 32
19389#define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_OFST 156
19390#define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_LEN 4
19391#define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_LBN 1248
19392#define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_WIDTH 32
19393/* The minimum size (in table entries) of indirection table to be allocated
19394 * from the pool for an RSS context. Note that the table size used must be a
19395 * power of 2.
19396 */
19397#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
19398#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
19399/* The maximum size (in table entries) of indirection table to be allocated
19400 * from the pool for an RSS context. Note that the table size used must be a
19401 * power of 2.
19402 */
19403#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
19404#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
19405/* The maximum number of queues that can be used by an RSS context in exclusive
19406 * mode. In exclusive mode the context has a configurable indirection table and
19407 * a configurable RSS key.
19408 */
19409#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
19410#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
19411/* The maximum number of queues that can be used by an RSS context in even-
19412 * spreading mode. In even-spreading mode the context has no indirection table
19413 * but it does have a configurable RSS key.
19414 */
19415#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
19416#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
19417/* The total number of RSS contexts supported. Note that the number of
19418 * available contexts using indirection tables is also limited by the
19419 * availability of indirection table space allocated from a common pool.
19420 */
19421#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_NUM_CONTEXTS_OFST 176
19422#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_NUM_CONTEXTS_LEN 4
19423/* The total amount of indirection table space that can be shared between RSS
19424 * contexts.
19425 */
19426#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_TABLE_POOL_SIZE_OFST 180
19427#define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_TABLE_POOL_SIZE_LEN 4
19428/* A bitmap of the queue sizes the device can provide, where bit N being set
19429 * indicates that 2**N is a valid size. The device may be limited in the number
19430 * of different queue sizes that can exist simultaneously, so a bit being set
19431 * here does not guarantee that an attempt to create a queue of that size will
19432 * succeed.
19433 */
19434#define MC_CMD_GET_CAPABILITIES_V12_OUT_SUPPORTED_QUEUE_SIZES_OFST 184
19435#define MC_CMD_GET_CAPABILITIES_V12_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
19436/* A bitmap of queue sizes that are always available, in the same format as
19437 * SUPPORTED_QUEUE_SIZES. Attempting to create a queue with one of these sizes
19438 * will never fail due to unavailability of the requested size.
19439 */
19440#define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_QUEUE_SIZES_OFST 188
19441#define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
19442/* Number of available indirect memory maps. */
19443#define MC_CMD_GET_CAPABILITIES_V12_OUT_INDIRECT_MAP_INDEX_COUNT_OFST 192
19444#define MC_CMD_GET_CAPABILITIES_V12_OUT_INDIRECT_MAP_INDEX_COUNT_LEN 4
19445/* Number of VIs available for external ports 4-7. Information for ports 0-3 is
19446 * in NUM_VIS_PER_PORT in GET_CAPABILITIES_V2_OUT.
19447 */
19448#define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_OFST 196
19449#define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_LEN 2
19450#define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_NUM 4
19451
19452
19453/***********************************/
19454/* MC_CMD_V2_EXTN
19455 * Encapsulation for a v2 extended command
19456 */
19457#define MC_CMD_V2_EXTN 0x7f
19458
19459/* MC_CMD_V2_EXTN_IN msgrequest */
19460#define MC_CMD_V2_EXTN_IN_LEN 4
19461/* the extended command number */
19462#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
19463#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
19464#define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
19465#define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
19466/* the actual length of the encapsulated command (which is not in the v1
19467 * header)
19468 */
19469#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
19470#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
19471#define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
19472#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2
19473/* Type of command/response */
19474#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28
19475#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
19476/* enum: MCDI command directed to or response originating from the MC. */
19477#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
19478/* enum: MCDI command directed to a TSA controller. MCDI responses of this type
19479 * are not defined.
19480 */
19481#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
19482/* enum: MCDI command used for platform management. Typically, these commands
19483 * are used for low-level operations directed at the platform as a whole (e.g.
19484 * MMIO device enumeration) rather than individual functions and use a
19485 * dedicated comms channel (e.g. RPmsg/IPI). May be handled by the same or
19486 * different CPU as MCDI_MESSAGE_TYPE_MC.
19487 */
19488#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_PLATFORM 0x2
19489
19490
19491/***********************************/
19492/* MC_CMD_LINK_PIOBUF
19493 * Link a push I/O buffer to a TxQ
19494 */
19495#define MC_CMD_LINK_PIOBUF 0x92
19496#undef MC_CMD_0x92_PRIVILEGE_CTG
19497
19498#define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
19499
19500/* MC_CMD_LINK_PIOBUF_IN msgrequest */
19501#define MC_CMD_LINK_PIOBUF_IN_LEN 8
19502/* Handle for allocated push I/O buffer. */
19503#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
19504#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
19505/* Function Local Instance (VI) number which has a TxQ allocated to it. */
19506#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
19507#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
19508
19509/* MC_CMD_LINK_PIOBUF_OUT msgresponse */
19510#define MC_CMD_LINK_PIOBUF_OUT_LEN 0
19511
19512
19513/***********************************/
19514/* MC_CMD_UNLINK_PIOBUF
19515 * Unlink a push I/O buffer from a TxQ
19516 */
19517#define MC_CMD_UNLINK_PIOBUF 0x93
19518#undef MC_CMD_0x93_PRIVILEGE_CTG
19519
19520#define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
19521
19522/* MC_CMD_UNLINK_PIOBUF_IN msgrequest */
19523#define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
19524/* Function Local Instance (VI) number. */
19525#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
19526#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
19527
19528/* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */
19529#define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
19530
19531
19532/***********************************/
19533/* MC_CMD_VSWITCH_ALLOC
19534 * allocate and initialise a v-switch.
19535 */
19536#define MC_CMD_VSWITCH_ALLOC 0x94
19537#undef MC_CMD_0x94_PRIVILEGE_CTG
19538
19539#define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19540
19541/* MC_CMD_VSWITCH_ALLOC_IN msgrequest */
19542#define MC_CMD_VSWITCH_ALLOC_IN_LEN 16
19543/* The port to connect to the v-switch's upstream port. */
19544#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19545#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19546/* The type of v-switch to create. */
19547#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
19548#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
19549/* enum: VLAN */
19550#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
19551/* enum: VEB */
19552#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
19553/* enum: VEPA (obsolete) */
19554#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
19555/* enum: MUX */
19556#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
19557/* enum: Snapper specific; semantics TBD */
19558#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
19559/* Flags controlling v-port creation */
19560#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8
19561#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
19562#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_OFST 8
19563#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
19564#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
19565/* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
19566 * this must be one or greated, and the attached v-ports must have exactly this
19567 * number of tags. For other v-switch types, this must be zero of greater, and
19568 * is an upper limit on the number of VLAN tags for attached v-ports. An error
19569 * will be returned if existing configuration means we can't support attached
19570 * v-ports with this number of tags.
19571 */
19572#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
19573#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
19574
19575/* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */
19576#define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
19577
19578
19579/***********************************/
19580/* MC_CMD_VSWITCH_FREE
19581 * de-allocate a v-switch.
19582 */
19583#define MC_CMD_VSWITCH_FREE 0x95
19584#undef MC_CMD_0x95_PRIVILEGE_CTG
19585
19586#define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19587
19588/* MC_CMD_VSWITCH_FREE_IN msgrequest */
19589#define MC_CMD_VSWITCH_FREE_IN_LEN 4
19590/* The port to which the v-switch is connected. */
19591#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
19592#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4
19593
19594/* MC_CMD_VSWITCH_FREE_OUT msgresponse */
19595#define MC_CMD_VSWITCH_FREE_OUT_LEN 0
19596
19597
19598/***********************************/
19599/* MC_CMD_VPORT_ALLOC
19600 * allocate a v-port.
19601 */
19602#define MC_CMD_VPORT_ALLOC 0x96
19603#undef MC_CMD_0x96_PRIVILEGE_CTG
19604
19605#define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19606
19607/* MC_CMD_VPORT_ALLOC_IN msgrequest */
19608#define MC_CMD_VPORT_ALLOC_IN_LEN 20
19609/* The port to which the v-switch is connected. */
19610#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19611#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19612/* The type of the new v-port. */
19613#define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
19614#define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
19615/* enum: VLAN (obsolete) */
19616#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
19617/* enum: VEB (obsolete) */
19618#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
19619/* enum: VEPA (obsolete) */
19620#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
19621/* enum: A normal v-port receives packets which match a specified MAC and/or
19622 * VLAN.
19623 */
19624#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
19625/* enum: An expansion v-port packets traffic which don't match any other
19626 * v-port.
19627 */
19628#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
19629/* enum: An test v-port receives packets which match any filters installed by
19630 * its downstream components.
19631 */
19632#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
19633/* Flags controlling v-port creation */
19634#define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8
19635#define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
19636#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_OFST 8
19637#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
19638#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
19639#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_OFST 8
19640#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1
19641#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1
19642/* The number of VLAN tags to insert/remove. An error will be returned if
19643 * incompatible with the number of VLAN tags specified for the upstream
19644 * v-switch.
19645 */
19646#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
19647#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
19648/* The actual VLAN tags to insert/remove */
19649#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16
19650#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
19651#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_OFST 16
19652#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
19653#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16
19654#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_OFST 16
19655#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16
19656#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16
19657
19658/* MC_CMD_VPORT_ALLOC_OUT msgresponse */
19659#define MC_CMD_VPORT_ALLOC_OUT_LEN 4
19660/* The handle of the new v-port */
19661#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
19662#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4
19663
19664
19665/***********************************/
19666/* MC_CMD_VPORT_FREE
19667 * de-allocate a v-port.
19668 */
19669#define MC_CMD_VPORT_FREE 0x97
19670#undef MC_CMD_0x97_PRIVILEGE_CTG
19671
19672#define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19673
19674/* MC_CMD_VPORT_FREE_IN msgrequest */
19675#define MC_CMD_VPORT_FREE_IN_LEN 4
19676/* The handle of the v-port */
19677#define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
19678#define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4
19679
19680/* MC_CMD_VPORT_FREE_OUT msgresponse */
19681#define MC_CMD_VPORT_FREE_OUT_LEN 0
19682
19683
19684/***********************************/
19685/* MC_CMD_VADAPTOR_ALLOC
19686 * allocate a v-adaptor.
19687 */
19688#define MC_CMD_VADAPTOR_ALLOC 0x98
19689#undef MC_CMD_0x98_PRIVILEGE_CTG
19690
19691#define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19692
19693/* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */
19694#define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30
19695/* The port to connect to the v-adaptor's port. */
19696#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19697#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19698/* Flags controlling v-adaptor creation */
19699#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8
19700#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
19701#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_OFST 8
19702#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
19703#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
19704#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 8
19705#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1
19706#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
19707/* The number of VLAN tags to strip on receive */
19708#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12
19709#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4
19710/* The number of VLAN tags to transparently insert/remove. */
19711#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16
19712#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
19713/* The actual VLAN tags to insert/remove */
19714#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20
19715#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
19716#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_OFST 20
19717#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
19718#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16
19719#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_OFST 20
19720#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16
19721#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16
19722/* The MAC address to assign to this v-adaptor */
19723#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24
19724#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6
19725/* enum: Derive the MAC address from the upstream port */
19726#define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
19727
19728/* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */
19729#define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
19730
19731
19732/***********************************/
19733/* MC_CMD_VADAPTOR_FREE
19734 * de-allocate a v-adaptor.
19735 */
19736#define MC_CMD_VADAPTOR_FREE 0x99
19737#undef MC_CMD_0x99_PRIVILEGE_CTG
19738
19739#define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19740
19741/* MC_CMD_VADAPTOR_FREE_IN msgrequest */
19742#define MC_CMD_VADAPTOR_FREE_IN_LEN 4
19743/* The port to which the v-adaptor is connected. */
19744#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
19745#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4
19746
19747/* MC_CMD_VADAPTOR_FREE_OUT msgresponse */
19748#define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
19749
19750
19751/***********************************/
19752/* MC_CMD_VADAPTOR_SET_MAC
19753 * assign a new MAC address to a v-adaptor.
19754 */
19755#define MC_CMD_VADAPTOR_SET_MAC 0x5d
19756#undef MC_CMD_0x5d_PRIVILEGE_CTG
19757
19758#define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19759
19760/* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */
19761#define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10
19762/* The port to which the v-adaptor is connected. */
19763#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
19764#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
19765/* The new MAC address to assign to this v-adaptor */
19766#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
19767#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6
19768
19769/* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */
19770#define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
19771
19772
19773/***********************************/
19774/* MC_CMD_VADAPTOR_QUERY
19775 * read some config of v-adaptor.
19776 */
19777#define MC_CMD_VADAPTOR_QUERY 0x61
19778#undef MC_CMD_0x61_PRIVILEGE_CTG
19779
19780#define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19781
19782/* MC_CMD_VADAPTOR_QUERY_IN msgrequest */
19783#define MC_CMD_VADAPTOR_QUERY_IN_LEN 4
19784/* The port to which the v-adaptor is connected. */
19785#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
19786#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
19787
19788/* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */
19789#define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12
19790/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
19791#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
19792#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4
19793/* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
19794#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
19795#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4
19796/* The number of VLAN tags that may still be added */
19797#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8
19798#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
19799
19800
19801/***********************************/
19802/* MC_CMD_EVB_PORT_ASSIGN
19803 * assign a port to a PCI function.
19804 */
19805#define MC_CMD_EVB_PORT_ASSIGN 0x9a
19806#undef MC_CMD_0x9a_PRIVILEGE_CTG
19807
19808#define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19809
19810/* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */
19811#define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8
19812/* The port to assign. */
19813#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
19814#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4
19815/* The target function to modify. */
19816#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
19817#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
19818#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 4
19819#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
19820#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16
19821#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 4
19822#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16
19823#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16
19824
19825/* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */
19826#define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
19827
19828
19829/***********************************/
19830/* MC_CMD_RSS_CONTEXT_ALLOC
19831 * Allocate an RSS context.
19832 */
19833#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
19834#undef MC_CMD_0x9e_PRIVILEGE_CTG
19835
19836#define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19837
19838/* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */
19839#define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12
19840/* The handle of the owning upstream port */
19841#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19842#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19843/* The type of context to allocate */
19844#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
19845#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4
19846/* enum: Allocate a context for exclusive use. The key and indirection table
19847 * must be explicitly configured.
19848 */
19849#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
19850/* enum: Allocate a context for shared use; this will spread across a range of
19851 * queues, but the key and indirection table are pre-configured and may not be
19852 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
19853 */
19854#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
19855/* enum: Allocate a context to spread evenly across an arbitrary number of
19856 * queues. No indirection table space is allocated for this context. (EF100 and
19857 * later)
19858 */
19859#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x2
19860/* Number of queues spanned by this context. For exclusive contexts this must
19861 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
19862 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if
19863 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in
19864 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19865 * spreading contexts this must be in the range 1 to
19866 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note
19867 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
19868 * be useful as a way of obtaining the Toeplitz hash.
19869 */
19870#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8
19871#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
19872
19873/* MC_CMD_RSS_CONTEXT_ALLOC_V2_IN msgrequest */
19874#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_LEN 16
19875/* The handle of the owning upstream port */
19876#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 0
19877#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 4
19878/* The type of context to allocate */
19879#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 4
19880#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 4
19881/* enum: Allocate a context for exclusive use. The key and indirection table
19882 * must be explicitly configured.
19883 */
19884#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x0
19885/* enum: Allocate a context for shared use; this will spread across a range of
19886 * queues, but the key and indirection table are pre-configured and may not be
19887 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
19888 */
19889#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x1
19890/* enum: Allocate a context to spread evenly across an arbitrary number of
19891 * queues. No indirection table space is allocated for this context. (EF100 and
19892 * later)
19893 */
19894#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x2
19895/* Number of queues spanned by this context. For exclusive contexts this must
19896 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
19897 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if
19898 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in
19899 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19900 * spreading contexts this must be in the range 1 to
19901 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note
19902 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
19903 * be useful as a way of obtaining the Toeplitz hash.
19904 */
19905#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_OFST 8
19906#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 4
19907/* Size of indirection table to be allocated to this context from the pool.
19908 * Must be a power of 2. The minimum and maximum table size can be queried
19909 * using MC_CMD_GET_CAPABILITIES_V9. If there is not enough space remaining in
19910 * the common pool to allocate the requested table size, due to allocating
19911 * table space to other RSS contexts, then the command will fail with
19912 * MC_CMD_ERR_ENOSPC.
19913 */
19914#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_OFST 12
19915#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 4
19916
19917/* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */
19918#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
19919/* The handle of the new RSS context. This should be considered opaque to the
19920 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
19921 * handle.
19922 */
19923#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
19924#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
19925/* enum: guaranteed invalid RSS context handle value */
19926#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
19927
19928
19929/***********************************/
19930/* MC_CMD_RSS_CONTEXT_FREE
19931 * Free an RSS context.
19932 */
19933#define MC_CMD_RSS_CONTEXT_FREE 0x9f
19934#undef MC_CMD_0x9f_PRIVILEGE_CTG
19935
19936#define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19937
19938/* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */
19939#define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
19940/* The handle of the RSS context */
19941#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
19942#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4
19943
19944/* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */
19945#define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
19946
19947
19948/***********************************/
19949/* MC_CMD_RSS_CONTEXT_SET_KEY
19950 * Set the Toeplitz hash key for an RSS context.
19951 */
19952#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
19953#undef MC_CMD_0xa0_PRIVILEGE_CTG
19954
19955#define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19956
19957/* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */
19958#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44
19959/* The handle of the RSS context */
19960#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
19961#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4
19962/* The 40-byte Toeplitz hash key (TBD endianness issues?) */
19963#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
19964#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40
19965
19966/* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */
19967#define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
19968
19969
19970/***********************************/
19971/* MC_CMD_RSS_CONTEXT_GET_KEY
19972 * Get the Toeplitz hash key for an RSS context.
19973 */
19974#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
19975#undef MC_CMD_0xa1_PRIVILEGE_CTG
19976
19977#define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
19978
19979/* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */
19980#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
19981/* The handle of the RSS context */
19982#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
19983#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4
19984
19985/* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */
19986#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44
19987/* The 40-byte Toeplitz hash key (TBD endianness issues?) */
19988#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
19989#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40
19990
19991
19992/***********************************/
19993/* MC_CMD_RSS_CONTEXT_SET_TABLE
19994 * Set the indirection table for an RSS context. This command should only be
19995 * used with indirection tables containing 128 entries, which is the default
19996 * when the RSS context is allocated without specifying a table size.
19997 */
19998#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
19999#undef MC_CMD_0xa2_PRIVILEGE_CTG
20000
20001#define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20002
20003/* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */
20004#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132
20005/* The handle of the RSS context */
20006#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
20007#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
20008/* The 128-byte indirection table (1 byte per entry) */
20009#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
20010#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128
20011
20012/* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */
20013#define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
20014
20015
20016/***********************************/
20017/* MC_CMD_RSS_CONTEXT_GET_TABLE
20018 * Get the indirection table for an RSS context. This command should only be
20019 * used with indirection tables containing 128 entries, which is the default
20020 * when the RSS context is allocated without specifying a table size.
20021 */
20022#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
20023#undef MC_CMD_0xa3_PRIVILEGE_CTG
20024
20025#define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20026
20027/* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */
20028#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
20029/* The handle of the RSS context */
20030#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
20031#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
20032
20033/* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */
20034#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132
20035/* The 128-byte indirection table (1 byte per entry) */
20036#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
20037#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128
20038
20039
20040/***********************************/
20041/* MC_CMD_RSS_CONTEXT_SET_FLAGS
20042 * Set various control flags for an RSS context.
20043 */
20044#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
20045#undef MC_CMD_0xe1_PRIVILEGE_CTG
20046
20047#define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20048
20049/* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */
20050#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8
20051/* The handle of the RSS context */
20052#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
20053#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
20054/* Hash control flags. The _EN bits are always supported, but new modes are
20055 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES:
20056 * in this case, the MODE fields may be set to non-zero values, and will take
20057 * effect regardless of the settings of the _EN flags. See the RSS_MODE
20058 * structure for the meaning of the mode bits. Drivers must check the
20059 * capability before trying to set any _MODE fields, as older firmware will
20060 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
20061 * the case where all the _MODE flags are zero, the _EN flags take effect,
20062 * providing backward compatibility for existing drivers. (Setting all _MODE
20063 * *and* all _EN flags to zero is valid, to disable RSS spreading for that
20064 * particular packet type.)
20065 */
20066#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
20067#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
20068#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 4
20069#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
20070#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
20071#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 4
20072#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
20073#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
20074#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 4
20075#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2
20076#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
20077#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 4
20078#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3
20079#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
20080#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 4
20081#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
20082#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
20083#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 4
20084#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8
20085#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
20086#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 4
20087#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12
20088#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
20089#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 4
20090#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16
20091#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
20092#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 4
20093#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20
20094#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
20095#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 4
20096#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24
20097#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
20098#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 4
20099#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28
20100#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
20101
20102/* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */
20103#define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
20104
20105
20106/***********************************/
20107/* MC_CMD_RSS_CONTEXT_GET_FLAGS
20108 * Get various control flags for an RSS context.
20109 */
20110#define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
20111#undef MC_CMD_0xe2_PRIVILEGE_CTG
20112
20113#define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20114
20115/* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */
20116#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
20117/* The handle of the RSS context */
20118#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
20119#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
20120
20121/* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */
20122#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8
20123/* Hash control flags. If all _MODE bits are zero (which will always be true
20124 * for older firmware which does not report the ADDITIONAL_RSS_MODES
20125 * capability), the _EN bits report the state. If any _MODE bits are non-zero
20126 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES)
20127 * then the _EN bits should be disregarded, although the _MODE flags are
20128 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
20129 * context and in the case where the _EN flags were used in the SET. This
20130 * provides backward compatibility: old drivers will not be attempting to
20131 * derive any meaning from the _MODE bits (and can never set them to any value
20132 * not representable by the _EN bits); new drivers can always determine the
20133 * mode by looking only at the _MODE bits; the value returned by a GET can
20134 * always be used for a SET regardless of old/new driver vs. old/new firmware.
20135 */
20136#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
20137#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
20138#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 4
20139#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
20140#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
20141#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 4
20142#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
20143#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
20144#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 4
20145#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2
20146#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
20147#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 4
20148#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3
20149#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
20150#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 4
20151#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
20152#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
20153#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 4
20154#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8
20155#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
20156#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 4
20157#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12
20158#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
20159#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 4
20160#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16
20161#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
20162#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 4
20163#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20
20164#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
20165#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 4
20166#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24
20167#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
20168#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4
20169#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28
20170#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
20171
20172
20173/***********************************/
20174/* MC_CMD_VPORT_ADD_MAC_ADDRESS
20175 * Add a MAC address to a v-port
20176 */
20177#define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
20178#undef MC_CMD_0xa8_PRIVILEGE_CTG
20179
20180#define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20181
20182/* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */
20183#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10
20184/* The handle of the v-port */
20185#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
20186#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4
20187/* MAC address to add */
20188#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
20189#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6
20190
20191/* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */
20192#define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
20193
20194
20195/***********************************/
20196/* MC_CMD_VPORT_DEL_MAC_ADDRESS
20197 * Delete a MAC address from a v-port
20198 */
20199#define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
20200#undef MC_CMD_0xa9_PRIVILEGE_CTG
20201
20202#define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20203
20204/* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */
20205#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10
20206/* The handle of the v-port */
20207#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
20208#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4
20209/* MAC address to add */
20210#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
20211#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6
20212
20213/* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */
20214#define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
20215
20216
20217/***********************************/
20218/* MC_CMD_VPORT_GET_MAC_ADDRESSES
20219 * Delete a MAC address from a v-port
20220 */
20221#define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
20222#undef MC_CMD_0xaa_PRIVILEGE_CTG
20223
20224#define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20225
20226/* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */
20227#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
20228/* The handle of the v-port */
20229#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
20230#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4
20231
20232/* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */
20233#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
20234#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250
20235#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1018
20236#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
20237#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6)
20238/* The number of MAC addresses returned */
20239#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
20240#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
20241/* Array of MAC addresses */
20242#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
20243#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6
20244#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
20245#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41
20246#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM_MCDI2 169
20247
20248
20249/***********************************/
20250/* MC_CMD_VPORT_RECONFIGURE
20251 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
20252 * has already been passed to another function (v-port's user), then that
20253 * function will be reset before applying the changes.
20254 */
20255#define MC_CMD_VPORT_RECONFIGURE 0xeb
20256#undef MC_CMD_0xeb_PRIVILEGE_CTG
20257
20258#define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20259
20260/* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */
20261#define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44
20262/* The handle of the v-port */
20263#define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
20264#define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4
20265/* Flags requesting what should be changed. */
20266#define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
20267#define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
20268#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 4
20269#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
20270#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1
20271#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 4
20272#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1
20273#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1
20274/* The number of VLAN tags to insert/remove. An error will be returned if
20275 * incompatible with the number of VLAN tags specified for the upstream
20276 * v-switch.
20277 */
20278#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8
20279#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4
20280/* The actual VLAN tags to insert/remove */
20281#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12
20282#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
20283#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_OFST 12
20284#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
20285#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16
20286#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_OFST 12
20287#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16
20288#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16
20289/* The number of MAC addresses to add */
20290#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16
20291#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4
20292/* MAC addresses to add */
20293#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20
20294#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6
20295#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
20296
20297/* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */
20298#define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
20299#define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
20300#define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
20301#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_OFST 0
20302#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
20303#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1
20304
20305
20306/***********************************/
20307/* MC_CMD_GET_CLOCK
20308 * Return the system and PDCPU clock frequencies.
20309 */
20310#define MC_CMD_GET_CLOCK 0xac
20311#undef MC_CMD_0xac_PRIVILEGE_CTG
20312
20313#define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20314
20315/* MC_CMD_GET_CLOCK_IN msgrequest */
20316#define MC_CMD_GET_CLOCK_IN_LEN 0
20317
20318/* MC_CMD_GET_CLOCK_OUT msgresponse */
20319#define MC_CMD_GET_CLOCK_OUT_LEN 8
20320/* System frequency, MHz */
20321#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
20322#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4
20323/* DPCPU frequency, MHz */
20324#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
20325#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4
20326
20327
20328/***********************************/
20329/* MC_CMD_TRIGGER_INTERRUPT
20330 * Trigger an interrupt by prodding the BIU.
20331 */
20332#define MC_CMD_TRIGGER_INTERRUPT 0xe3
20333#undef MC_CMD_0xe3_PRIVILEGE_CTG
20334
20335#define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20336
20337/* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */
20338#define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
20339/* Interrupt level relative to base for function. */
20340#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
20341#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4
20342
20343/* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */
20344#define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
20345
20346
20347/***********************************/
20348/* MC_CMD_DUMP_DO
20349 * Take a dump of the DUT state
20350 */
20351#define MC_CMD_DUMP_DO 0xe8
20352#undef MC_CMD_0xe8_PRIVILEGE_CTG
20353
20354#define MC_CMD_0xe8_PRIVILEGE_CTG SRIOV_CTG_INSECURE
20355
20356/* MC_CMD_DUMP_DO_IN msgrequest */
20357#define MC_CMD_DUMP_DO_IN_LEN 52
20358#define MC_CMD_DUMP_DO_IN_PADDING_OFST 0
20359#define MC_CMD_DUMP_DO_IN_PADDING_LEN 4
20360#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
20361#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4
20362#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
20363#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
20364#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
20365#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
20366#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
20367#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
20368#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
20369#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
20370#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
20371#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20372#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
20373#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
20374#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
20375#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20376#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
20377#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20378#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
20379#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20380#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
20381#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
20382#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20383#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
20384#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20385#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
20386#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
20387#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
20388/* enum: The uart port this command was received over (if using a uart
20389 * transport)
20390 */
20391#define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
20392#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
20393#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
20394#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28
20395#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4
20396#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
20397#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
20398#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
20399#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
20400/* Enum values, see field(s): */
20401/* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
20402#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
20403#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20404#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
20405#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
20406#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
20407#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20408#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
20409#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20410#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
20411#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20412#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
20413#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20414#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
20415#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20416#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
20417#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
20418#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
20419#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
20420
20421/* MC_CMD_DUMP_DO_OUT msgresponse */
20422#define MC_CMD_DUMP_DO_OUT_LEN 4
20423#define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
20424#define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4
20425
20426
20427/***********************************/
20428/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED
20429 * Configure unsolicited dumps
20430 */
20431#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
20432#undef MC_CMD_0xe9_PRIVILEGE_CTG
20433
20434#define MC_CMD_0xe9_PRIVILEGE_CTG SRIOV_CTG_INSECURE
20435
20436/* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */
20437#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52
20438#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
20439#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4
20440#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
20441#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4
20442/* Enum values, see field(s): */
20443/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */
20444#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
20445#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
20446/* Enum values, see field(s): */
20447/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
20448#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
20449#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20450#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
20451#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
20452#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
20453#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20454#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
20455#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20456#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
20457#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20458#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
20459#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20460#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
20461#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20462#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
20463#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
20464#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
20465#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
20466#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28
20467#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4
20468/* Enum values, see field(s): */
20469/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */
20470#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
20471#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
20472/* Enum values, see field(s): */
20473/* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
20474#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
20475#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20476#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
20477#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
20478#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
20479#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20480#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
20481#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20482#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
20483#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20484#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
20485#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20486#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
20487#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20488#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
20489#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
20490#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
20491#define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
20492
20493
20494/***********************************/
20495/* MC_CMD_GET_FUNCTION_INFO
20496 * Get function information. PF and VF number.
20497 */
20498#define MC_CMD_GET_FUNCTION_INFO 0xec
20499#undef MC_CMD_0xec_PRIVILEGE_CTG
20500
20501#define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
20502
20503/* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */
20504#define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
20505
20506/* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */
20507#define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8
20508#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
20509#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4
20510#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
20511#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4
20512
20513/* MC_CMD_GET_FUNCTION_INFO_OUT_V2 msgresponse */
20514#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_LEN 12
20515#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_PF_OFST 0
20516#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_PF_LEN 4
20517#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_VF_OFST 4
20518#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_VF_LEN 4
20519/* Values from PCIE_INTERFACE enumeration. For NICs with a single interface, or
20520 * in the case of a V1 response, this should be HOST_PRIMARY.
20521 */
20522#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_INTF_OFST 8
20523#define MC_CMD_GET_FUNCTION_INFO_OUT_V2_INTF_LEN 4
20524
20525
20526/***********************************/
20527/* MC_CMD_ENABLE_OFFLINE_BIST
20528 * Enters offline BIST mode. All queues are torn down, chip enters quiescent
20529 * mode, calling function gets exclusive MCDI ownership. The only way out is
20530 * reboot.
20531 */
20532#define MC_CMD_ENABLE_OFFLINE_BIST 0xed
20533#undef MC_CMD_0xed_PRIVILEGE_CTG
20534
20535#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
20536
20537/* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */
20538#define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
20539
20540/* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */
20541#define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
20542
20543
20544/***********************************/
20545/* MC_CMD_KR_TUNE
20546 * Get or set KR Serdes RXEQ and TX Driver settings
20547 */
20548#define MC_CMD_KR_TUNE 0xf1
20549#undef MC_CMD_0xf1_PRIVILEGE_CTG
20550
20551#define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND
20552
20553/* MC_CMD_KR_TUNE_IN msgrequest */
20554#define MC_CMD_KR_TUNE_IN_LENMIN 4
20555#define MC_CMD_KR_TUNE_IN_LENMAX 252
20556#define MC_CMD_KR_TUNE_IN_LENMAX_MCDI2 1020
20557#define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
20558#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_NUM(len) (((len)-4)/4)
20559/* Requested operation */
20560#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
20561#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
20562/* enum: Get current RXEQ settings */
20563#define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
20564/* enum: Override RXEQ settings */
20565#define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
20566/* enum: Get current TX Driver settings */
20567#define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
20568/* enum: Override TX Driver settings */
20569#define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
20570/* enum: Force KR Serdes reset / recalibration */
20571#define MC_CMD_KR_TUNE_IN_RECAL 0x4
20572/* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid
20573 * signal.
20574 */
20575#define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
20576/* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The
20577 * caller should call this command repeatedly after starting eye plot, until no
20578 * more data is returned.
20579 */
20580#define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
20581/* enum: Read Figure Of Merit (eye quality, higher is better). */
20582#define MC_CMD_KR_TUNE_IN_READ_FOM 0x7
20583/* enum: Start/stop link training frames */
20584#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8
20585/* enum: Issue KR link training command (control training coefficients) */
20586#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9
20587/* Align the arguments to 32 bits */
20588#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
20589#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3
20590/* Arguments specific to the operation */
20591#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
20592#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
20593#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
20594#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62
20595#define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM_MCDI2 254
20596
20597/* MC_CMD_KR_TUNE_OUT msgresponse */
20598#define MC_CMD_KR_TUNE_OUT_LEN 0
20599
20600/* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */
20601#define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
20602/* Requested operation */
20603#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
20604#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1
20605/* Align the arguments to 32 bits */
20606#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
20607#define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
20608
20609/* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */
20610#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
20611#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252
20612#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX_MCDI2 1020
20613#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
20614#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20615/* RXEQ Parameter */
20616#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
20617#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
20618#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
20619#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
20620#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255
20621#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0
20622#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
20623#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
20624/* enum: Attenuation (0-15, Huntington) */
20625#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
20626/* enum: CTLE Boost (0-15, Huntington) */
20627#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
20628/* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
20629 * positive, Medford - 0-31)
20630 */
20631#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
20632/* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
20633 * positive, Medford - 0-31)
20634 */
20635#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
20636/* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
20637 * positive, Medford - 0-16)
20638 */
20639#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
20640/* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
20641 * positive, Medford - 0-16)
20642 */
20643#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
20644/* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
20645 * positive, Medford - 0-16)
20646 */
20647#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
20648/* enum: Edge DFE DLEV (0-128 for Medford) */
20649#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
20650/* enum: Variable Gain Amplifier (0-15, Medford) */
20651#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
20652/* enum: CTLE EQ Capacitor (0-15, Medford) */
20653#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
20654/* enum: CTLE EQ Resistor (0-7, Medford) */
20655#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
20656/* enum: CTLE gain (0-31, Medford2) */
20657#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb
20658/* enum: CTLE pole (0-31, Medford2) */
20659#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc
20660/* enum: CTLE peaking (0-31, Medford2) */
20661#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd
20662/* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */
20663#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe
20664/* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */
20665#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf
20666/* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */
20667#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10
20668/* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */
20669#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11
20670/* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */
20671#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12
20672/* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */
20673#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13
20674/* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */
20675#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14
20676/* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */
20677#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15
20678/* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */
20679#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16
20680/* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */
20681#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17
20682/* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */
20683#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18
20684/* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */
20685#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19
20686/* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */
20687#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a
20688/* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */
20689#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b
20690/* enum: Negative h1 polarity data sampler offset calibration code, even path
20691 * (Medford2 - 6 bit signed (-29 - +29)))
20692 */
20693#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c
20694/* enum: Negative h1 polarity data sampler offset calibration code, odd path
20695 * (Medford2 - 6 bit signed (-29 - +29)))
20696 */
20697#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d
20698/* enum: Positive h1 polarity data sampler offset calibration code, even path
20699 * (Medford2 - 6 bit signed (-29 - +29)))
20700 */
20701#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e
20702/* enum: Positive h1 polarity data sampler offset calibration code, odd path
20703 * (Medford2 - 6 bit signed (-29 - +29)))
20704 */
20705#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f
20706/* enum: CDR calibration loop code (Medford2) */
20707#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20
20708/* enum: CDR integral loop code (Medford2) */
20709#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21
20710/* enum: CTLE Boost stages - retimer lineside (Medford2 with DS250x retimer - 4
20711 * stages, 2 bits per stage)
20712 */
20713#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_LS 0x22
20714/* enum: DFE Tap1 - retimer lineside (Medford2 with DS250x retimer (-31 - 31))
20715 */
20716#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_LS 0x23
20717/* enum: DFE Tap2 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20718 */
20719#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_LS 0x24
20720/* enum: DFE Tap3 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20721 */
20722#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_LS 0x25
20723/* enum: DFE Tap4 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20724 */
20725#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_LS 0x26
20726/* enum: DFE Tap5 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20727 */
20728#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_LS 0x27
20729/* enum: CTLE Boost stages - retimer hostside (Medford2 with DS250x retimer - 4
20730 * stages, 2 bits per stage)
20731 */
20732#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_HS 0x28
20733/* enum: DFE Tap1 - retimer hostside (Medford2 with DS250x retimer (-31 - 31))
20734 */
20735#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_HS 0x29
20736/* enum: DFE Tap2 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20737 */
20738#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_HS 0x2a
20739/* enum: DFE Tap3 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20740 */
20741#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_HS 0x2b
20742/* enum: DFE Tap4 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20743 */
20744#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_HS 0x2c
20745/* enum: DFE Tap5 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20746 */
20747#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_HS 0x2d
20748#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0
20749#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
20750#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3
20751#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
20752#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
20753#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
20754#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
20755#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
20756#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0
20757#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11
20758#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
20759#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0
20760#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
20761#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
20762#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_OFST 0
20763#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16
20764#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
20765#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0
20766#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
20767#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
20768
20769/* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */
20770#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8
20771#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252
20772#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX_MCDI2 1020
20773#define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
20774#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
20775/* Requested operation */
20776#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
20777#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
20778/* Align the arguments to 32 bits */
20779#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
20780#define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
20781/* RXEQ Parameter */
20782#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
20783#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
20784#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
20785#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
20786#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254
20787#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
20788#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
20789#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
20790/* Enum values, see field(s): */
20791/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */
20792#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
20793#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
20794#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3
20795/* Enum values, see field(s): */
20796/* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */
20797#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
20798#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11
20799#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
20800#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
20801#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12
20802#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
20803#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
20804#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
20805#define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
20806#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
20807#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
20808#define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
20809
20810/* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */
20811#define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
20812
20813/* MC_CMD_KR_TUNE_TXEQ_GET_IN msgrequest */
20814#define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4
20815/* Requested operation */
20816#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0
20817#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_LEN 1
20818/* Align the arguments to 32 bits */
20819#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
20820#define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
20821
20822/* MC_CMD_KR_TUNE_TXEQ_GET_OUT msgresponse */
20823#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
20824#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX 252
20825#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMAX_MCDI2 1020
20826#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
20827#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20828/* TXEQ Parameter */
20829#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
20830#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
20831#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
20832#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
20833#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM_MCDI2 255
20834#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0
20835#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
20836#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
20837/* enum: TX Amplitude (Huntington, Medford, Medford2) */
20838#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
20839/* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
20840#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
20841/* enum: De-Emphasis Tap1 Fine */
20842#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
20843/* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
20844#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
20845/* enum: De-Emphasis Tap2 Fine (Huntington) */
20846#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
20847/* enum: Pre-Emphasis Magnitude (Huntington) */
20848#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
20849/* enum: Pre-Emphasis Fine (Huntington) */
20850#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
20851/* enum: TX Slew Rate Coarse control (Huntington) */
20852#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
20853/* enum: TX Slew Rate Fine control (Huntington) */
20854#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
20855/* enum: TX Termination Impedance control (Huntington) */
20856#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
20857/* enum: TX Amplitude Fine control (Medford) */
20858#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
20859/* enum: Pre-cursor Tap (Medford, Medford2) */
20860#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
20861/* enum: Post-cursor Tap (Medford, Medford2) */
20862#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
20863/* enum: TX Amplitude (Retimer Lineside) */
20864#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_LS 0xd
20865/* enum: Pre-cursor Tap (Retimer Lineside) */
20866#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_LS 0xe
20867/* enum: Post-cursor Tap (Retimer Lineside) */
20868#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_LS 0xf
20869/* enum: TX Amplitude (Retimer Hostside) */
20870#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_HS 0x10
20871/* enum: Pre-cursor Tap (Retimer Hostside) */
20872#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_HS 0x11
20873/* enum: Post-cursor Tap (Retimer Hostside) */
20874#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_HS 0x12
20875#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0
20876#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
20877#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3
20878#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
20879#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
20880#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
20881#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
20882#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
20883#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0
20884#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11
20885#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5
20886#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_OFST 0
20887#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16
20888#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
20889#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_OFST 0
20890#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_LBN 24
20891#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_WIDTH 8
20892
20893/* MC_CMD_KR_TUNE_TXEQ_SET_IN msgrequest */
20894#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMIN 8
20895#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX 252
20896#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LENMAX_MCDI2 1020
20897#define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
20898#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
20899/* Requested operation */
20900#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
20901#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_LEN 1
20902/* Align the arguments to 32 bits */
20903#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
20904#define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
20905/* TXEQ Parameter */
20906#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4
20907#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
20908#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MINNUM 1
20909#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM 62
20910#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_MAXNUM_MCDI2 254
20911#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_OFST 4
20912#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
20913#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_WIDTH 8
20914/* Enum values, see field(s): */
20915/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_ID */
20916#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_OFST 4
20917#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_LBN 8
20918#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_WIDTH 3
20919/* Enum values, see field(s): */
20920/* MC_CMD_KR_TUNE_TXEQ_GET_OUT/PARAM_LANE */
20921#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_OFST 4
20922#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_LBN 11
20923#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_WIDTH 5
20924#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_OFST 4
20925#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_LBN 16
20926#define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
20927#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_OFST 4
20928#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_LBN 24
20929#define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_WIDTH 8
20930
20931/* MC_CMD_KR_TUNE_TXEQ_SET_OUT msgresponse */
20932#define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0
20933
20934/* MC_CMD_KR_TUNE_RECAL_IN msgrequest */
20935#define MC_CMD_KR_TUNE_RECAL_IN_LEN 4
20936/* Requested operation */
20937#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
20938#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1
20939/* Align the arguments to 32 bits */
20940#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1
20941#define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3
20942
20943/* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */
20944#define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
20945
20946/* MC_CMD_KR_TUNE_START_EYE_PLOT_IN msgrequest */
20947#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LEN 8
20948/* Requested operation */
20949#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
20950#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
20951/* Align the arguments to 32 bits */
20952#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
20953#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
20954/* Port-relative lane to scan eye on */
20955#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
20956#define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
20957
20958/* MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN msgrequest */
20959#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LEN 12
20960/* Requested operation */
20961#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0
20962#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_LEN 1
20963/* Align the arguments to 32 bits */
20964#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_OFST 1
20965#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_RSVD_LEN 3
20966#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4
20967#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4
20968#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_OFST 4
20969#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0
20970#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_WIDTH 8
20971#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_OFST 4
20972#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_LBN 31
20973#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_WIDTH 1
20974/* Scan duration / cycle count */
20975#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_OFST 8
20976#define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4
20977
20978/* MC_CMD_KR_TUNE_START_EYE_PLOT_OUT msgresponse */
20979#define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0
20980
20981/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN msgrequest */
20982#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4
20983/* Requested operation */
20984#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
20985#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_LEN 1
20986/* Align the arguments to 32 bits */
20987#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_OFST 1
20988#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_RSVD_LEN 3
20989
20990/* MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT msgresponse */
20991#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
20992#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX 252
20993#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMAX_MCDI2 1020
20994#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
20995#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
20996#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
20997#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_LEN 2
20998#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
20999#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
21000#define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MAXNUM_MCDI2 510
21001
21002/* MC_CMD_KR_TUNE_READ_FOM_IN msgrequest */
21003#define MC_CMD_KR_TUNE_READ_FOM_IN_LEN 8
21004/* Requested operation */
21005#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0
21006#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_LEN 1
21007/* Align the arguments to 32 bits */
21008#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_OFST 1
21009#define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_RSVD_LEN 3
21010#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
21011#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4
21012#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_OFST 4
21013#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0
21014#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_WIDTH 8
21015#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_OFST 4
21016#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_LBN 31
21017#define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_WIDTH 1
21018
21019/* MC_CMD_KR_TUNE_READ_FOM_OUT msgresponse */
21020#define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4
21021#define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0
21022#define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4
21023
21024/* MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN msgrequest */
21025#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_LEN 8
21026/* Requested operation */
21027#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0
21028#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_LEN 1
21029/* Align the arguments to 32 bits */
21030#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_OFST 1
21031#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_LEN 3
21032#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4
21033#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4
21034#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
21035#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */
21036
21037/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN msgrequest */
21038#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LEN 28
21039/* Requested operation */
21040#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0
21041#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_LEN 1
21042/* Align the arguments to 32 bits */
21043#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_OFST 1
21044#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_RSVD_LEN 3
21045#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4
21046#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4
21047/* Set INITIALIZE state */
21048#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_OFST 8
21049#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4
21050/* Set PRESET state */
21051#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_OFST 12
21052#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4
21053/* C(-1) request */
21054#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_OFST 16
21055#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4
21056#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
21057#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
21058#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
21059/* C(0) request */
21060#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_OFST 20
21061#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4
21062/* Enum values, see field(s): */
21063/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
21064/* C(+1) request */
21065#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_OFST 24
21066#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4
21067/* Enum values, see field(s): */
21068/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
21069
21070/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT msgresponse */
21071#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_LEN 24
21072/* C(-1) status */
21073#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0
21074#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4
21075#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
21076#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
21077#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
21078#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
21079/* C(0) status */
21080#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4
21081#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4
21082/* Enum values, see field(s): */
21083/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
21084/* C(+1) status */
21085#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_OFST 8
21086#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4
21087/* Enum values, see field(s): */
21088/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN/CM1 */
21089/* C(-1) value */
21090#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_OFST 12
21091#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4
21092/* C(0) value */
21093#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_OFST 16
21094#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4
21095/* C(+1) status */
21096#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_OFST 20
21097#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4
21098
21099
21100/***********************************/
21101/* MC_CMD_LICENSING
21102 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
21103 * - not used for V3 licensing
21104 */
21105#define MC_CMD_LICENSING 0xf3
21106#undef MC_CMD_0xf3_PRIVILEGE_CTG
21107
21108#define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21109
21110/* MC_CMD_LICENSING_IN msgrequest */
21111#define MC_CMD_LICENSING_IN_LEN 4
21112/* identifies the type of operation requested */
21113#define MC_CMD_LICENSING_IN_OP_OFST 0
21114#define MC_CMD_LICENSING_IN_OP_LEN 4
21115/* enum: re-read and apply licenses after a license key partition update; note
21116 * that this operation returns a zero-length response
21117 */
21118#define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
21119/* enum: report counts of installed licenses */
21120#define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
21121
21122/* MC_CMD_LICENSING_OUT msgresponse */
21123#define MC_CMD_LICENSING_OUT_LEN 28
21124/* count of application keys which are valid */
21125#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
21126#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4
21127/* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with
21128 * MC_CMD_FC_OP_LICENSE)
21129 */
21130#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
21131#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4
21132/* count of application keys which are invalid due to being blacklisted */
21133#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8
21134#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4
21135/* count of application keys which are invalid due to being unverifiable */
21136#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12
21137#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4
21138/* count of application keys which are invalid due to being for the wrong node
21139 */
21140#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16
21141#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4
21142/* licensing state (for diagnostics; the exact meaning of the bits in this
21143 * field are private to the firmware)
21144 */
21145#define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20
21146#define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4
21147/* licensing subsystem self-test report (for manftest) */
21148#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24
21149#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
21150/* enum: licensing subsystem self-test failed */
21151#define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
21152/* enum: licensing subsystem self-test passed */
21153#define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
21154
21155
21156/***********************************/
21157/* MC_CMD_LICENSING_V3
21158 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
21159 * - V3 licensing (Medford)
21160 */
21161#define MC_CMD_LICENSING_V3 0xd0
21162#undef MC_CMD_0xd0_PRIVILEGE_CTG
21163
21164#define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21165
21166/* MC_CMD_LICENSING_V3_IN msgrequest */
21167#define MC_CMD_LICENSING_V3_IN_LEN 4
21168/* identifies the type of operation requested */
21169#define MC_CMD_LICENSING_V3_IN_OP_OFST 0
21170#define MC_CMD_LICENSING_V3_IN_OP_LEN 4
21171/* enum: re-read and apply licenses after a license key partition update; note
21172 * that this operation returns a zero-length response
21173 */
21174#define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
21175/* enum: report counts of installed licenses Returns EAGAIN if license
21176 * processing (updating) has been started but not yet completed.
21177 */
21178#define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
21179
21180/* MC_CMD_LICENSING_V3_OUT msgresponse */
21181#define MC_CMD_LICENSING_V3_OUT_LEN 88
21182/* count of keys which are valid */
21183#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
21184#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4
21185/* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with
21186 * MC_CMD_FC_OP_LICENSE)
21187 */
21188#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
21189#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4
21190/* count of keys which are invalid due to being unverifiable */
21191#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8
21192#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4
21193/* count of keys which are invalid due to being for the wrong node */
21194#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12
21195#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4
21196/* licensing state (for diagnostics; the exact meaning of the bits in this
21197 * field are private to the firmware)
21198 */
21199#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16
21200#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4
21201/* licensing subsystem self-test report (for manftest) */
21202#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20
21203#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
21204/* enum: licensing subsystem self-test failed */
21205#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
21206/* enum: licensing subsystem self-test passed */
21207#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
21208/* bitmask of licensed applications */
21209#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24
21210#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8
21211#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24
21212#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LEN 4
21213#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LBN 192
21214#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_WIDTH 32
21215#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28
21216#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LEN 4
21217#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LBN 224
21218#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_WIDTH 32
21219/* reserved for future use */
21220#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32
21221#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24
21222/* bitmask of licensed features */
21223#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56
21224#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8
21225#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56
21226#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LEN 4
21227#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LBN 448
21228#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_WIDTH 32
21229#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60
21230#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LEN 4
21231#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LBN 480
21232#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_WIDTH 32
21233/* reserved for future use */
21234#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64
21235#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24
21236
21237
21238/***********************************/
21239/* MC_CMD_GET_LICENSED_APP_STATE
21240 * Query the state of an individual licensed application. (Note that the actual
21241 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation
21242 * or a reboot of the MC.) Not used for V3 licensing
21243 */
21244#define MC_CMD_GET_LICENSED_APP_STATE 0xf5
21245#undef MC_CMD_0xf5_PRIVILEGE_CTG
21246
21247#define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21248
21249/* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */
21250#define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
21251/* application ID to query (LICENSED_APP_ID_xxx) */
21252#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
21253#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4
21254
21255/* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */
21256#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
21257/* state of this application */
21258#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
21259#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
21260/* enum: no (or invalid) license is present for the application */
21261#define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
21262/* enum: a valid license is present for the application */
21263#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
21264
21265
21266/***********************************/
21267/* MC_CMD_SET_PARSER_DISP_CONFIG
21268 * Change configuration related to the parser-dispatcher subsystem.
21269 */
21270#define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
21271#undef MC_CMD_0xf9_PRIVILEGE_CTG
21272
21273#define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21274
21275/* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */
21276#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12
21277#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252
21278#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX_MCDI2 1020
21279#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
21280#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4)
21281/* the type of configuration setting to change */
21282#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
21283#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
21284/* enum: Per-TXQ enable for multicast UDP destination lookup for possible
21285 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.)
21286 */
21287#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
21288/* enum: Per-v-adaptor enable for suppression of self-transmissions on the
21289 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single
21290 * boolean.)
21291 */
21292#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
21293/* handle for the entity to update: queue handle, EVB port ID, etc. depending
21294 * on the type of configuration setting being changed
21295 */
21296#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
21297#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
21298/* new value: the details depend on the type of configuration setting being
21299 * changed
21300 */
21301#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8
21302#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
21303#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1
21304#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61
21305#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM_MCDI2 253
21306
21307/* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */
21308#define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
21309
21310
21311/***********************************/
21312/* MC_CMD_GET_WORKAROUNDS
21313 * Read the list of all implemented and all currently enabled workarounds. The
21314 * enums here must correspond with those in MC_CMD_WORKAROUND.
21315 */
21316#define MC_CMD_GET_WORKAROUNDS 0x59
21317#undef MC_CMD_0x59_PRIVILEGE_CTG
21318
21319#define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21320
21321/* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */
21322#define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8
21323/* Each workaround is represented by a single bit according to the enums below.
21324 */
21325#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
21326#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4
21327#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
21328#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4
21329/* enum: Bug 17230 work around. */
21330#define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
21331/* enum: Bug 35388 work around (unsafe EVQ writes). */
21332#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
21333/* enum: Bug35017 workaround (A64 tables must be identity map) */
21334#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
21335/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
21336#define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
21337/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
21338 * - before adding code that queries this workaround, remember that there's
21339 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
21340 * and will hence (incorrectly) report that the bug doesn't exist.
21341 */
21342#define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
21343/* enum: Bug 26807 features present in firmware (multicast filter chaining) */
21344#define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
21345/* enum: Bug 61265 work around (broken EVQ TMR writes). */
21346#define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
21347
21348
21349/***********************************/
21350/* MC_CMD_PRIVILEGE_MASK
21351 * Read/set privileges of an arbitrary PCIe function
21352 */
21353#define MC_CMD_PRIVILEGE_MASK 0x5a
21354#undef MC_CMD_0x5a_PRIVILEGE_CTG
21355
21356#define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21357
21358/* MC_CMD_PRIVILEGE_MASK_IN msgrequest */
21359#define MC_CMD_PRIVILEGE_MASK_IN_LEN 8
21360/* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
21361 * 1,3 = 0x00030001
21362 */
21363#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
21364#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
21365#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_OFST 0
21366#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
21367#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16
21368#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_OFST 0
21369#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16
21370#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16
21371#define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
21372/* New privilege mask to be set. The mask will only be changed if the MSB is
21373 * set to 1.
21374 */
21375#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
21376#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
21377#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
21378#define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
21379#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
21380#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
21381#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
21382/* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */
21383#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
21384#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
21385#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
21386#define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
21387#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
21388#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
21389/* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC
21390 * adress.
21391 */
21392#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
21393/* enum: Privilege that allows a Function to change the MAC address configured
21394 * in its associated vAdapter/vPort.
21395 */
21396#define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
21397/* enum: Privilege that allows a Function to install filters that specify VLANs
21398 * that are not in the permit list for the associated vPort. This privilege is
21399 * primarily to support ESX where vPorts are created that restrict traffic to
21400 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT.
21401 */
21402#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
21403/* enum: Privilege for insecure commands. Commands that belong to this group
21404 * are not permitted on secure adapters regardless of the privilege mask.
21405 */
21406#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
21407/* enum: Trusted Server Adapter (TSA) / ServerLock. Privilege for
21408 * administrator-level operations that are not allowed from the local host once
21409 * an adapter has Bound to a remote ServerLock Controller (see doxbox
21410 * SF-117064-DG for background).
21411 */
21412#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
21413/* enum: Control the Match-Action Engine if present. See mcdi_mae.yml. */
21414#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE 0x10000
21415/* enum: This Function/client may call MC_CMD_CLIENT_ALLOC to create new
21416 * dynamic client children of itself.
21417 */
21418#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALLOC_CLIENT 0x20000
21419/* enum: A dynamic client with this privilege may perform all the same DMA
21420 * operations as the function client from which it is descended.
21421 */
21422#define MC_CMD_PRIVILEGE_MASK_IN_GRP_FUNC_DMA 0x40000
21423/* enum: A client with this privilege may perform DMA as any PCIe function on
21424 * the device and to on-device DDR. It allows clients to use TX-DESC2CMPT-DESC
21425 * descriptors, and to use TX-SEG-DESC and TX-MEM2MEM-DESC with an address
21426 * space override (i.e. with the ADDR_SPC_EN bit set).
21427 */
21428#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ARBITRARY_DMA 0x80000
21429/* enum: Set this bit to indicate that a new privilege mask is to be set,
21430 * otherwise the command will only read the existing mask.
21431 */
21432#define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
21433
21434/* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */
21435#define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
21436/* For an admin function, always all the privileges are reported. */
21437#define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
21438#define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4
21439
21440
21441/***********************************/
21442/* MC_CMD_LINK_STATE_MODE
21443 * Read/set link state mode of a VF
21444 */
21445#define MC_CMD_LINK_STATE_MODE 0x5c
21446#undef MC_CMD_0x5c_PRIVILEGE_CTG
21447
21448#define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21449
21450/* MC_CMD_LINK_STATE_MODE_IN msgrequest */
21451#define MC_CMD_LINK_STATE_MODE_IN_LEN 8
21452/* The target function to have its link state mode read or set, must be a VF
21453 * e.g. VF 1,3 = 0x00030001
21454 */
21455#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
21456#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
21457#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_OFST 0
21458#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
21459#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16
21460#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_OFST 0
21461#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16
21462#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16
21463/* New link state mode to be set */
21464#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
21465#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
21466#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
21467#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
21468#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
21469/* enum: Use this value to just read the existing setting without modifying it.
21470 */
21471#define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
21472
21473/* MC_CMD_LINK_STATE_MODE_OUT msgresponse */
21474#define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
21475#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
21476#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4
21477
21478/* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */
21479#define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
21480/* UDP port (the standard ports are named below but any port may be used) */
21481#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
21482#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2
21483/* enum: the IANA allocated UDP port for VXLAN */
21484#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
21485/* enum: the IANA allocated UDP port for Geneve */
21486#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
21487#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
21488#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16
21489/* tunnel encapsulation protocol (only those named below are supported) */
21490#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2
21491#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2
21492/* enum: This port will be used for VXLAN on both IPv4 and IPv6 */
21493#define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
21494/* enum: This port will be used for Geneve on both IPv4 and IPv6 */
21495#define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
21496#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16
21497#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16
21498
21499
21500/***********************************/
21501/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS
21502 * Configure UDP ports for tunnel encapsulation hardware acceleration. The
21503 * parser-dispatcher will attempt to parse traffic on these ports as tunnel
21504 * encapsulation PDUs and filter them using the tunnel encapsulation filter
21505 * chain rather than the standard filter chain. Note that this command can
21506 * cause all functions to see a reset. (Available on Medford only.)
21507 */
21508#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
21509#undef MC_CMD_0x117_PRIVILEGE_CTG
21510
21511#define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
21512
21513/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */
21514#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
21515#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68
21516#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX_MCDI2 68
21517#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
21518#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4)
21519/* Flags */
21520#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
21521#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2
21522#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_OFST 0
21523#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
21524#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1
21525/* The number of entries in the ENTRIES array */
21526#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2
21527#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2
21528/* Entries defining the UDP port to protocol mapping, each laid out as a
21529 * TUNNEL_ENCAP_UDP_PORT_ENTRY
21530 */
21531#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
21532#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
21533#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
21534#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16
21535#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM_MCDI2 16
21536
21537/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */
21538#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2
21539/* Flags */
21540#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
21541#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2
21542#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 0
21543#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
21544#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1
21545
21546
21547/***********************************/
21548/* MC_CMD_SET_EVQ_TMR
21549 * Update the timer load, timer reload and timer mode values for a given EVQ.
21550 * The requested timer values (in TMR_LOAD_REQ_NS and TMR_RELOAD_REQ_NS) will
21551 * be rounded up to the granularity supported by the hardware, then truncated
21552 * to the range supported by the hardware. The resulting value after the
21553 * rounding and truncation will be returned to the caller (in TMR_LOAD_ACT_NS
21554 * and TMR_RELOAD_ACT_NS).
21555 */
21556#define MC_CMD_SET_EVQ_TMR 0x120
21557#undef MC_CMD_0x120_PRIVILEGE_CTG
21558
21559#define MC_CMD_0x120_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21560
21561/* MC_CMD_SET_EVQ_TMR_IN msgrequest */
21562#define MC_CMD_SET_EVQ_TMR_IN_LEN 16
21563/* Function-relative queue instance */
21564#define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0
21565#define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4
21566/* Requested value for timer load (in nanoseconds) */
21567#define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4
21568#define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4
21569/* Requested value for timer reload (in nanoseconds) */
21570#define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_OFST 8
21571#define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4
21572/* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */
21573#define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12
21574#define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4
21575#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
21576#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
21577#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
21578#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
21579
21580/* MC_CMD_SET_EVQ_TMR_OUT msgresponse */
21581#define MC_CMD_SET_EVQ_TMR_OUT_LEN 8
21582/* Actual value for timer load (in nanoseconds) */
21583#define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0
21584#define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4
21585/* Actual value for timer reload (in nanoseconds) */
21586#define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4
21587#define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4
21588
21589
21590/***********************************/
21591/* MC_CMD_GET_EVQ_TMR_PROPERTIES
21592 * Query properties about the event queue timers.
21593 */
21594#define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
21595#undef MC_CMD_0x122_PRIVILEGE_CTG
21596
21597#define MC_CMD_0x122_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21598
21599/* MC_CMD_GET_EVQ_TMR_PROPERTIES_IN msgrequest */
21600#define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0
21601
21602/* MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT msgresponse */
21603#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN 36
21604/* Reserved for future use. */
21605#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0
21606#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4
21607/* For timers updated via writes to EVQ_TMR_REG, this is the time interval (in
21608 * nanoseconds) for each increment of the timer load/reload count. The
21609 * requested duration of a timer is this value multiplied by the timer
21610 * load/reload count.
21611 */
21612#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4
21613#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4
21614/* For timers updated via writes to EVQ_TMR_REG, this is the maximum value
21615 * allowed for timer load/reload counts.
21616 */
21617#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_OFST 8
21618#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4
21619/* For timers updated via writes to EVQ_TMR_REG, timer load/reload counts not a
21620 * multiple of this step size will be rounded in an implementation defined
21621 * manner.
21622 */
21623#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_OFST 12
21624#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4
21625/* Maximum timer duration (in nanoseconds) for timers updated via MCDI. Only
21626 * meaningful if MC_CMD_SET_EVQ_TMR is implemented.
21627 */
21628#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_OFST 16
21629#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4
21630/* Timer durations requested via MCDI that are not a multiple of this step size
21631 * will be rounded up. Only meaningful if MC_CMD_SET_EVQ_TMR is implemented.
21632 */
21633#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_OFST 20
21634#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4
21635/* For timers updated using the bug35388 workaround, this is the time interval
21636 * (in nanoseconds) for each increment of the timer load/reload count. The
21637 * requested duration of a timer is this value multiplied by the timer
21638 * load/reload count. This field is only meaningful if the bug35388 workaround
21639 * is enabled.
21640 */
21641#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_OFST 24
21642#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4
21643/* For timers updated using the bug35388 workaround, this is the maximum value
21644 * allowed for timer load/reload counts. This field is only meaningful if the
21645 * bug35388 workaround is enabled.
21646 */
21647#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_OFST 28
21648#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4
21649/* For timers updated using the bug35388 workaround, timer load/reload counts
21650 * not a multiple of this step size will be rounded in an implementation
21651 * defined manner. This field is only meaningful if the bug35388 workaround is
21652 * enabled.
21653 */
21654#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32
21655#define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4
21656
21657/* CLIENT_HANDLE structuredef: A client is an abstract entity that can make
21658 * requests of the device and that can own resources managed by the device.
21659 * Examples of clients include PCIe functions and dynamic clients. A client
21660 * handle is a 32b opaque value used to refer to a client. Further details can
21661 * be found within XN-200418-TC.
21662 */
21663#define CLIENT_HANDLE_LEN 4
21664#define CLIENT_HANDLE_OPAQUE_OFST 0
21665#define CLIENT_HANDLE_OPAQUE_LEN 4
21666/* enum: A client handle guaranteed never to refer to a real client. */
21667#define CLIENT_HANDLE_NULL 0xffffffff
21668/* enum: Used to refer to the calling client. */
21669#define CLIENT_HANDLE_SELF 0xfffffffe
21670#define CLIENT_HANDLE_OPAQUE_LBN 0
21671#define CLIENT_HANDLE_OPAQUE_WIDTH 32
21672
21673/* SCHED_CREDIT_CHECK_RESULT structuredef */
21674#define SCHED_CREDIT_CHECK_RESULT_LEN 16
21675/* The instance of the scheduler. Refer to XN-200389-AW (snic/hnic) and
21676 * XN-200425-TC (cdx) for the location of these schedulers in the hardware.
21677 */
21678#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_OFST 0
21679#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LEN 1
21680#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_A 0x0 /* enum */
21681#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_A 0x1 /* enum */
21682#define SCHED_CREDIT_CHECK_RESULT_HUB_B 0x2 /* enum */
21683#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_C 0x3 /* enum */
21684#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_TX 0x4 /* enum */
21685#define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_D 0x5 /* enum */
21686#define SCHED_CREDIT_CHECK_RESULT_HUB_REPLAY 0x6 /* enum */
21687#define SCHED_CREDIT_CHECK_RESULT_DMAC_H2C 0x7 /* enum */
21688#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_B 0x8 /* enum */
21689#define SCHED_CREDIT_CHECK_RESULT_HUB_NET_REPLAY 0x9 /* enum */
21690#define SCHED_CREDIT_CHECK_RESULT_ADAPTER_C2H_C 0xa /* enum */
21691#define SCHED_CREDIT_CHECK_RESULT_A2_H2C_C 0xb /* enum */
21692#define SCHED_CREDIT_CHECK_RESULT_A3_SOFT_ADAPTOR_C 0xc /* enum */
21693#define SCHED_CREDIT_CHECK_RESULT_A4_DPU_WRITE_C 0xd /* enum */
21694#define SCHED_CREDIT_CHECK_RESULT_JRC_RRU 0xe /* enum */
21695#define SCHED_CREDIT_CHECK_RESULT_CDM_SINK 0xf /* enum */
21696#define SCHED_CREDIT_CHECK_RESULT_PCIE_SINK 0x10 /* enum */
21697#define SCHED_CREDIT_CHECK_RESULT_UPORT_SINK 0x11 /* enum */
21698#define SCHED_CREDIT_CHECK_RESULT_PSX_SINK 0x12 /* enum */
21699#define SCHED_CREDIT_CHECK_RESULT_A5_DPU_READ_C 0x13 /* enum */
21700#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LBN 0
21701#define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_WIDTH 8
21702/* The type of node that this result refers to. */
21703#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_OFST 1
21704#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LEN 1
21705/* enum: Destination node */
21706#define SCHED_CREDIT_CHECK_RESULT_DEST 0x0
21707/* enum: Source node */
21708#define SCHED_CREDIT_CHECK_RESULT_SOURCE 0x1
21709/* enum: Destination node credit type 1 (new to the Keystone schedulers, see
21710 * SF-120268-TC)
21711 */
21712#define SCHED_CREDIT_CHECK_RESULT_DEST_CREDIT1 0x2
21713#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_LBN 8
21714#define SCHED_CREDIT_CHECK_RESULT_NODE_TYPE_WIDTH 8
21715/* Level of node in scheduler hierarchy (level 0 is the bottom of the
21716 * hierarchy, increasing towards the root node).
21717 */
21718#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_OFST 2
21719#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LEN 2
21720#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_LBN 16
21721#define SCHED_CREDIT_CHECK_RESULT_NODE_LEVEL_WIDTH 16
21722/* Node index */
21723#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_OFST 4
21724#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LEN 4
21725#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LBN 32
21726#define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_WIDTH 32
21727/* The number of credits the node is expected to have. */
21728#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_OFST 8
21729#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LEN 4
21730#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LBN 64
21731#define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_WIDTH 32
21732/* The number of credits the node actually had. */
21733#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_OFST 12
21734#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LEN 4
21735#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LBN 96
21736#define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_WIDTH 32
21737
21738
21739/***********************************/
21740/* MC_CMD_GET_DESC_ADDR_INFO
21741 * Returns a description of the mapping from DESC_ADDR to TRGT_ADDR for the calling function's address space.
21742 */
21743#define MC_CMD_GET_DESC_ADDR_INFO 0x1b7
21744#undef MC_CMD_0x1b7_PRIVILEGE_CTG
21745
21746#define MC_CMD_0x1b7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21747
21748/* MC_CMD_GET_DESC_ADDR_INFO_IN msgrequest */
21749#define MC_CMD_GET_DESC_ADDR_INFO_IN_LEN 0
21750
21751/* MC_CMD_GET_DESC_ADDR_INFO_OUT msgresponse */
21752#define MC_CMD_GET_DESC_ADDR_INFO_OUT_LEN 4
21753/* The type of mapping; see SF-nnnnnn-xx (EF100 driver writer's guide, once
21754 * written) for details of each type.
21755 */
21756#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_OFST 0
21757#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_LEN 4
21758/* enum: TRGT_ADDR = DESC_ADDR */
21759#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_FLAT 0x0
21760/* enum: DESC_ADDR has one or more regions that map into TRGT_ADDR. The base
21761 * TRGT_ADDR for each region is programmable via MCDI.
21762 */
21763#define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_REGIONED 0x1
21764
21765
21766/***********************************/
21767/* MC_CMD_GET_DESC_ADDR_REGIONS
21768 * Returns a list of the DESC_ADDR regions for the calling function's address space. Only valid if that function's address space has the REGIONED mapping from DESC_ADDR to TRGT_ADDR.
21769 */
21770#define MC_CMD_GET_DESC_ADDR_REGIONS 0x1b8
21771#undef MC_CMD_0x1b8_PRIVILEGE_CTG
21772
21773#define MC_CMD_0x1b8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21774
21775/* MC_CMD_GET_DESC_ADDR_REGIONS_IN msgrequest */
21776#define MC_CMD_GET_DESC_ADDR_REGIONS_IN_LEN 0
21777
21778/* MC_CMD_GET_DESC_ADDR_REGIONS_OUT msgresponse */
21779#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMIN 32
21780#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX 224
21781#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LENMAX_MCDI2 992
21782#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LEN(num) (0+32*(num))
21783#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_NUM(len) (((len)-0)/32)
21784/* An array of DESC_ADDR_REGION strutures. The number of entries in the array
21785 * indicates the number of available regions.
21786 */
21787#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_OFST 0
21788#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_LEN 32
21789#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MINNUM 1
21790#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM 7
21791#define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_MAXNUM_MCDI2 31
21792
21793
21794/***********************************/
21795/* MC_CMD_SET_DESC_ADDR_REGIONS
21796 * Set the base TRGT_ADDR for a set of DESC_ADDR regions for the calling function's address space. Only valid if that function's address space had the REGIONED mapping from DESC_ADDR to TRGT_ADDR.
21797 */
21798#define MC_CMD_SET_DESC_ADDR_REGIONS 0x1b9
21799#undef MC_CMD_0x1b9_PRIVILEGE_CTG
21800
21801#define MC_CMD_0x1b9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21802
21803/* MC_CMD_SET_DESC_ADDR_REGIONS_IN msgrequest */
21804#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMIN 16
21805#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX 248
21806#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LENMAX_MCDI2 1016
21807#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_LEN(num) (8+8*(num))
21808#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_NUM(len) (((len)-8)/8)
21809/* A bitmask indicating which regions should have their base TRGT_ADDR updated.
21810 * To update the base TRGR_ADDR for a DESC_ADDR region, the corresponding bit
21811 * should be set to 1.
21812 */
21813#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_OFST 0
21814#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_LEN 4
21815/* Reserved field; must be set to zero. */
21816#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_OFST 4
21817#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_LEN 4
21818/* An array of values used to updated the base TRGT_ADDR for DESC_ADDR regions.
21819 * Array indices corresponding to region numbers (i.e. the array is sparse, and
21820 * included entries for regions even if the corresponding SET_REGION_MASK bit
21821 * is zero).
21822 */
21823#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_OFST 8
21824#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LEN 8
21825#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_OFST 8
21826#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LEN 4
21827#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LBN 64
21828#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_WIDTH 32
21829#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_OFST 12
21830#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LEN 4
21831#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LBN 96
21832#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_WIDTH 32
21833#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MINNUM 1
21834#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM 30
21835#define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_MAXNUM_MCDI2 126
21836
21837/* MC_CMD_SET_DESC_ADDR_REGIONS_OUT msgresponse */
21838#define MC_CMD_SET_DESC_ADDR_REGIONS_OUT_LEN 0
21839
21840
21841/***********************************/
21842/* MC_CMD_CLIENT_CMD
21843 * Execute an arbitrary MCDI command on behalf of a different client. The
21844 * consequences of the command (e.g. ownership of any resources created) apply
21845 * to the indicated client rather than the function client which actually sent
21846 * this command. All inherent permission checks are also performed on the
21847 * indicated client. The given client must be a descendant of the requestor.
21848 * The command to be proxied follows immediately afterward in the host buffer
21849 * (or on the UART). Chaining multiple MC_CMD_CLIENT_CMD is unnecessary and not
21850 * supported. New dynamic clients may be created with MC_CMD_CLIENT_ALLOC.
21851 */
21852#define MC_CMD_CLIENT_CMD 0x1ba
21853#undef MC_CMD_0x1ba_PRIVILEGE_CTG
21854
21855#define MC_CMD_0x1ba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21856
21857/* MC_CMD_CLIENT_CMD_IN msgrequest */
21858#define MC_CMD_CLIENT_CMD_IN_LEN 4
21859/* The client as which to execute the following command. */
21860#define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_OFST 0
21861#define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_LEN 4
21862
21863/* MC_CMD_CLIENT_CMD_OUT msgresponse */
21864#define MC_CMD_CLIENT_CMD_OUT_LEN 0
21865
21866
21867/***********************************/
21868/* MC_CMD_CLIENT_ALLOC
21869 * Create a new client object. Clients are a system for delineating NIC
21870 * resource ownership, such that groups of resources may be torn down as a
21871 * unit. See also MC_CMD_CLIENT_CMD. See XN-200265-TC for background, concepts
21872 * and a glossary. Clients created by this command are known as "dynamic
21873 * clients". The newly-created client is a child of the client which sent this
21874 * command. The caller must have the GRP_ALLOC_CLIENT privilege. The new client
21875 * initially has no permission to do anything; see
21876 * MC_CMD_DEVEL_CLIENT_PRIVILEGE_MODIFY.
21877 */
21878#define MC_CMD_CLIENT_ALLOC 0x1bb
21879#undef MC_CMD_0x1bb_PRIVILEGE_CTG
21880
21881#define MC_CMD_0x1bb_PRIVILEGE_CTG SRIOV_CTG_ALLOC_CLIENT
21882
21883/* MC_CMD_CLIENT_ALLOC_IN msgrequest */
21884#define MC_CMD_CLIENT_ALLOC_IN_LEN 0
21885
21886/* MC_CMD_CLIENT_ALLOC_OUT msgresponse */
21887#define MC_CMD_CLIENT_ALLOC_OUT_LEN 4
21888/* The ID of the new client object which has been created. */
21889#define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_OFST 0
21890#define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_LEN 4
21891
21892
21893/***********************************/
21894/* MC_CMD_CLIENT_FREE
21895 * Destroy and release an existing client object. All resources owned by that
21896 * client (including its child clients, and thus all resources owned by the
21897 * entire family tree) are freed.
21898 */
21899#define MC_CMD_CLIENT_FREE 0x1bc
21900#undef MC_CMD_0x1bc_PRIVILEGE_CTG
21901
21902#define MC_CMD_0x1bc_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21903
21904/* MC_CMD_CLIENT_FREE_IN msgrequest */
21905#define MC_CMD_CLIENT_FREE_IN_LEN 4
21906/* The ID of the client to be freed. This client must be a descendant of the
21907 * requestor. A client cannot free itself.
21908 */
21909#define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_OFST 0
21910#define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_LEN 4
21911
21912/* MC_CMD_CLIENT_FREE_OUT msgresponse */
21913#define MC_CMD_CLIENT_FREE_OUT_LEN 0
21914
21915
21916/***********************************/
21917/* MC_CMD_SET_VI_USER
21918 * Assign partial rights over this VI to another client. VIs have an 'owner'
21919 * and a 'user'. The owner is the client which allocated the VI
21920 * (MC_CMD_ALLOC_VIS) and cannot be changed. The user is the client which has
21921 * permission to create queues and other resources on that VI. Initially
21922 * user==owner, but the user can be changed by this command; the resources thus
21923 * created are then owned by the user-client. Only the VI owner can call this
21924 * command, and the request will fail if there are any outstanding child
21925 * resources (e.g. queues) currently allocated from this VI.
21926 */
21927#define MC_CMD_SET_VI_USER 0x1be
21928#undef MC_CMD_0x1be_PRIVILEGE_CTG
21929
21930#define MC_CMD_0x1be_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21931
21932/* MC_CMD_SET_VI_USER_IN msgrequest */
21933#define MC_CMD_SET_VI_USER_IN_LEN 8
21934/* Function-relative VI number to modify. */
21935#define MC_CMD_SET_VI_USER_IN_INSTANCE_OFST 0
21936#define MC_CMD_SET_VI_USER_IN_INSTANCE_LEN 4
21937/* Client ID to become the new user. This must be a descendant of the owning
21938 * client, the owning client itself, or the special value MC_CMD_CLIENT_ID_SELF
21939 * which is synonymous with the owning client.
21940 */
21941#define MC_CMD_SET_VI_USER_IN_CLIENT_ID_OFST 4
21942#define MC_CMD_SET_VI_USER_IN_CLIENT_ID_LEN 4
21943
21944/* MC_CMD_SET_VI_USER_OUT msgresponse */
21945#define MC_CMD_SET_VI_USER_OUT_LEN 0
21946
21947
21948/***********************************/
21949/* MC_CMD_GET_CLIENT_MAC_ADDRESSES
21950 * A device reports a set of MAC addresses for each client to use, known as the
21951 * "permanent MAC addresses". Those MAC addresses are provided by the client's
21952 * administrator, e.g. via MC_CMD_SET_CLIENT_MAC_ADDRESSES, and are intended as
21953 * a hint to that client which MAC address its administrator would like to use
21954 * to identity itself. This API exists solely to allow communication of MAC
21955 * address from administrator to adminstree, and has no inherent interaction
21956 * with switching within the device. There is no guarantee that a client will
21957 * be able to send traffic with a source MAC address taken from the list of MAC
21958 * address reported, nor is there a guarantee that a client will be able to
21959 * resource traffic with a destination MAC taken from the list of MAC
21960 * addresses. Likewise, there is no guarantee that a client will not be able to
21961 * use a MAC address not present in the list. Restrictions on switching are
21962 * controlled either through the EVB API if operating in EVB mode, or via MAE
21963 * rules if host software is directly managing the MAE. In order to allow
21964 * tenants to use this API whilst a provider is using the EVB API, the MAC
21965 * addresses reported by MC_CMD_GET_CLIENT_MAC_ADDRESSES will be augmented with
21966 * any MAC addresses associated with the vPort assigned to the caller. In order
21967 * to allow tenants to use the EVB API whilst a provider is using this API, if
21968 * a client queries the MAC addresses for a vPort using the host_evb_port_id
21969 * EVB_PORT_ASSIGNED, that list of MAC addresses will be augmented with the MAC
21970 * addresses assigned to the calling client. This query can either be explicit
21971 * (i.e. MC_CMD_VPORT_GET_MAC_ADDRESSES) or implicit (e.g. creation of a
21972 * vAdaptor with a NULL/automatic MAC address). Changing the MAC address on a
21973 * vAdaptor only affects VNIC steering filters; it has no effect on the MAC
21974 * addresses assigned to the vAdaptor's owner. VirtIO clients behave as EVB
21975 * clients. On VirtIO device reset, a vAdaptor is created with an automatic MAC
21976 * address. Querying the VirtIO device's MAC address queries the underlying
21977 * vAdaptor's MAC address. Setting the VirtIO device's MAC address sets the
21978 * underlying vAdaptor's MAC addresses.
21979 */
21980#define MC_CMD_GET_CLIENT_MAC_ADDRESSES 0x1c4
21981#undef MC_CMD_0x1c4_PRIVILEGE_CTG
21982
21983#define MC_CMD_0x1c4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
21984
21985/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN msgrequest */
21986#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN 4
21987/* A handle for the client for whom MAC address should be obtained. Use
21988 * CLIENT_HANDLE_SELF to obtain the MAC addresses assigned to the calling
21989 * client.
21990 */
21991#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
21992#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
21993
21994/* MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT msgresponse */
21995#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMIN 0
21996#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX 252
21997#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1020
21998#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(num) (0+6*(num))
21999#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_NUM(len) (((len)-0)/6)
22000/* An array of MAC addresses assigned to the client. */
22001#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_OFST 0
22002#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_LEN 6
22003#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MINNUM 0
22004#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM 42
22005#define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MAXNUM_MCDI2 170
22006
22007
22008/***********************************/
22009/* MC_CMD_SET_CLIENT_MAC_ADDRESSES
22010 * Set the permanent MAC addresses for a client. The caller must by an
22011 * administrator of the target client. See MC_CMD_GET_CLIENT_MAC_ADDRESSES for
22012 * additional detail.
22013 */
22014#define MC_CMD_SET_CLIENT_MAC_ADDRESSES 0x1c5
22015#undef MC_CMD_0x1c5_PRIVILEGE_CTG
22016
22017#define MC_CMD_0x1c5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22018
22019/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN msgrequest */
22020#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMIN 4
22021#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX 250
22022#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMAX_MCDI2 1018
22023#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LEN(num) (4+6*(num))
22024#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_NUM(len) (((len)-4)/6)
22025/* A handle for the client for whom MAC addresses should be set */
22026#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
22027#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
22028/* An array of MAC addresses to assign to the client. */
22029#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_OFST 4
22030#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_LEN 6
22031#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MINNUM 0
22032#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM 41
22033#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MAXNUM_MCDI2 169
22034
22035/* MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT msgresponse */
22036#define MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT_LEN 0
22037
22038
22039/***********************************/
22040/* MC_CMD_CHECK_SCHEDULER_CREDITS
22041 * For debugging purposes. For each source and destination node in the hardware
22042 * schedulers, check whether the number of credits is as it should be. This
22043 * should only be used when the NIC is idle, because collection is not atomic
22044 * and because the expected credit counts are only meaningful when no traffic
22045 * is flowing.
22046 */
22047#define MC_CMD_CHECK_SCHEDULER_CREDITS 0x1c8
22048#undef MC_CMD_0x1c8_PRIVILEGE_CTG
22049
22050#define MC_CMD_0x1c8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
22051
22052/* MC_CMD_CHECK_SCHEDULER_CREDITS_IN msgrequest */
22053#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_LEN 8
22054/* Flags for the request */
22055#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_OFST 0
22056#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_LEN 4
22057#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_OFST 0
22058#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_LBN 0
22059#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_WIDTH 1
22060/* If there are too many results to fit into an MCDI response, they're split
22061 * into pages. This field specifies which (0-indexed) page to request. A
22062 * request with PAGE=0 will snapshot the results, and subsequent requests with
22063 * PAGE>0 will return data from the most recent snapshot. The GENERATION field
22064 * in the response allows callers to verify that all responses correspond to
22065 * the same snapshot.
22066 */
22067#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_OFST 4
22068#define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_LEN 4
22069
22070/* MC_CMD_CHECK_SCHEDULER_CREDITS_OUT msgresponse */
22071#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMIN 16
22072#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX 240
22073#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LENMAX_MCDI2 1008
22074#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_LEN(num) (16+16*(num))
22075#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_NUM(len) (((len)-16)/16)
22076/* The total number of results (across all pages). */
22077#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_OFST 0
22078#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_LEN 4
22079/* The number of pages that the response is split across. */
22080#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_OFST 4
22081#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_LEN 4
22082/* The number of results in this response. */
22083#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_OFST 8
22084#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_LEN 4
22085/* Result generation count. Incremented any time a request is made with PAGE=0.
22086 */
22087#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_OFST 12
22088#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_LEN 4
22089/* The results, as an array of SCHED_CREDIT_CHECK_RESULT structures. */
22090#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_OFST 16
22091#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_LEN 16
22092#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MINNUM 0
22093#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM 14
22094#define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MAXNUM_MCDI2 62
22095
22096
22097/***********************************/
22098/* MC_CMD_VIRTIO_GET_FEATURES
22099 * Get a list of the virtio features supported by the device.
22100 */
22101#define MC_CMD_VIRTIO_GET_FEATURES 0x168
22102#undef MC_CMD_0x168_PRIVILEGE_CTG
22103
22104#define MC_CMD_0x168_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22105
22106/* MC_CMD_VIRTIO_GET_FEATURES_IN msgrequest */
22107#define MC_CMD_VIRTIO_GET_FEATURES_IN_LEN 4
22108/* Type of device to get features for. Matches the device id as defined by the
22109 * virtio spec.
22110 */
22111#define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_OFST 0
22112#define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_LEN 4
22113/* enum: Reserved. Do not use. */
22114#define MC_CMD_VIRTIO_GET_FEATURES_IN_RESERVED 0x0
22115/* enum: Net device. */
22116#define MC_CMD_VIRTIO_GET_FEATURES_IN_NET 0x1
22117/* enum: Block device. */
22118#define MC_CMD_VIRTIO_GET_FEATURES_IN_BLOCK 0x2
22119
22120/* MC_CMD_VIRTIO_GET_FEATURES_OUT msgresponse */
22121#define MC_CMD_VIRTIO_GET_FEATURES_OUT_LEN 8
22122/* Features supported by the device. The result is a bitfield in the format of
22123 * the feature bits of the specified device type as defined in the virtIO 1.1
22124 * specification ( https://docs.oasis-
22125 * open.org/virtio/virtio/v1.1/csprd01/virtio-v1.1-csprd01.pdf )
22126 */
22127#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0
22128#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LEN 8
22129#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0
22130#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LEN 4
22131#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LBN 0
22132#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_WIDTH 32
22133#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4
22134#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LEN 4
22135#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LBN 32
22136#define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_WIDTH 32
22137
22138
22139/***********************************/
22140/* MC_CMD_VIRTIO_TEST_FEATURES
22141 * Query whether a given set of features is supported. Fails with ENOSUP if the
22142 * driver requests a feature the device doesn't support. Fails with EINVAL if
22143 * the driver fails to request a feature which the device requires.
22144 */
22145#define MC_CMD_VIRTIO_TEST_FEATURES 0x169
22146#undef MC_CMD_0x169_PRIVILEGE_CTG
22147
22148#define MC_CMD_0x169_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22149
22150/* MC_CMD_VIRTIO_TEST_FEATURES_IN msgrequest */
22151#define MC_CMD_VIRTIO_TEST_FEATURES_IN_LEN 16
22152/* Type of device to test features for. Matches the device id as defined by the
22153 * virtio spec.
22154 */
22155#define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_OFST 0
22156#define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_LEN 4
22157/* Enum values, see field(s): */
22158/* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */
22159#define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_OFST 4
22160#define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_LEN 4
22161/* Features requested. Same format as the returned value from
22162 * MC_CMD_VIRTIO_GET_FEATURES.
22163 */
22164#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_OFST 8
22165#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LEN 8
22166#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_OFST 8
22167#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LEN 4
22168#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LBN 64
22169#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_WIDTH 32
22170#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_OFST 12
22171#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LEN 4
22172#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LBN 96
22173#define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_WIDTH 32
22174
22175/* MC_CMD_VIRTIO_TEST_FEATURES_OUT msgresponse */
22176#define MC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0
22177
22178
22179/***********************************/
22180/* MC_CMD_VIRTIO_INIT_QUEUE
22181 * Create a virtio virtqueue. Fails with EALREADY if the queue already exists.
22182 * Fails with ENOSUP if a feature is requested that isn't supported. Fails with
22183 * EINVAL if a required feature isn't requested, or any other parameter is
22184 * invalid.
22185 */
22186#define MC_CMD_VIRTIO_INIT_QUEUE 0x16a
22187#undef MC_CMD_0x16a_PRIVILEGE_CTG
22188
22189#define MC_CMD_0x16a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22190
22191/* MC_CMD_VIRTIO_INIT_QUEUE_REQ msgrequest */
22192#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_LEN 68
22193/* Type of virtqueue to create. A network rxq and a txq can exist at the same
22194 * time on a single VI.
22195 */
22196#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_OFST 0
22197#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_LEN 1
22198/* enum: A network device receive queue */
22199#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_RXQ 0x0
22200/* enum: A network device transmit queue */
22201#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_TXQ 0x1
22202/* enum: A block device request queue */
22203#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_BLOCK 0x2
22204#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_OFST 1
22205#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED_LEN 1
22206/* If the calling function is a PF and this field is not VF_NULL, create the
22207 * queue on the specified child VF instead of on the PF.
22208 */
22209#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_TARGET_VF_OFST 2
22210#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_TARGET_VF_LEN 2
22211/* enum: No VF, create queue on the PF. */
22212#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_VF_NULL 0xffff
22213/* Desired instance. This is the function-local index of the associated VI, not
22214 * the virtqueue number as counted by the virtqueue spec.
22215 */
22216#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_OFST 4
22217#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_LEN 4
22218/* Queue size, in entries. Must be a power of two. */
22219#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_OFST 8
22220#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_LEN 4
22221/* Flags */
22222#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_OFST 12
22223#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_LEN 4
22224#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_OFST 12
22225#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_LBN 0
22226#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_WIDTH 1
22227/* Address of the descriptor table in the virtqueue. */
22228#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_OFST 16
22229#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LEN 8
22230#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_OFST 16
22231#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LEN 4
22232#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LBN 128
22233#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_WIDTH 32
22234#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_OFST 20
22235#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LEN 4
22236#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LBN 160
22237#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_WIDTH 32
22238/* Address of the available ring in the virtqueue. */
22239#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_OFST 24
22240#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LEN 8
22241#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_OFST 24
22242#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LEN 4
22243#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LBN 192
22244#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_WIDTH 32
22245#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_OFST 28
22246#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LEN 4
22247#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LBN 224
22248#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_WIDTH 32
22249/* Address of the used ring in the virtqueue. */
22250#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_OFST 32
22251#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LEN 8
22252#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_OFST 32
22253#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LEN 4
22254#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LBN 256
22255#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_WIDTH 32
22256#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_OFST 36
22257#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LEN 4
22258#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LBN 288
22259#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_WIDTH 32
22260/* PASID to use on PCIe transactions involving this queue. Ignored if the
22261 * USE_PASID flag is not set.
22262 */
22263#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_OFST 40
22264#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_LEN 4
22265/* Which MSIX vector to use for this virtqueue, or NO_VECTOR if MSIX should not
22266 * be used.
22267 */
22268#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MSIX_VECTOR_OFST 44
22269#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MSIX_VECTOR_LEN 2
22270/* enum: Do not enable interrupts for this virtqueue */
22271#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NO_VECTOR 0xffff
22272#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED2_OFST 46
22273#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_RESERVED2_LEN 2
22274/* Virtio features to apply to this queue. Same format as the in the virtio
22275 * spec and in the return from MC_CMD_VIRTIO_GET_FEATURES. Must be a subset of
22276 * the features returned from MC_CMD_VIRTIO_GET_FEATURES. Features are per-
22277 * queue because with vDPA multiple queues on the same function can be passed
22278 * through to different virtual hosts as independent devices.
22279 */
22280#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_OFST 48
22281#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LEN 8
22282#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_OFST 48
22283#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LEN 4
22284#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LBN 384
22285#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_WIDTH 32
22286#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_OFST 52
22287#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LEN 4
22288#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LBN 416
22289#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_WIDTH 32
22290/* Enum values, see field(s): */
22291/* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_OUT/FEATURES */
22292/* The initial available index for this virtqueue. If this queue is being
22293 * created to be migrated into, this should be the FINAL_AVAIL_IDX value
22294 * returned by MC_CMD_VIRTIO_FINI_QUEUE of the queue being migrated from (or
22295 * equivalent if the original queue was on a thirdparty device). Otherwise, it
22296 * should be zero.
22297 */
22298#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_AVAIL_IDX_OFST 56
22299#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_AVAIL_IDX_LEN 4
22300/* Alias of INITIAL_AVAIL_IDX, kept for compatibility. */
22301#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_OFST 56
22302#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_LEN 4
22303/* The initial used index for this virtqueue. If this queue is being created to
22304 * be migrated into, this should be the FINAL_USED_IDX value returned by
22305 * MC_CMD_VIRTIO_FINI_QUEUE of the queue being migrated from (or equivalent if
22306 * the original queue was on a thirdparty device). Otherwise, it should be
22307 * zero.
22308 */
22309#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_USED_IDX_OFST 60
22310#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_USED_IDX_LEN 4
22311/* Alias of INITIAL_USED_IDX, kept for compatibility. */
22312#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_OFST 60
22313#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_LEN 4
22314/* A MAE_MPORT_SELECTOR defining which mport this queue should be associated
22315 * with. Use MAE_MPORT_SELECTOR_ASSIGNED to request the default mport for the
22316 * function this queue is being created on.
22317 */
22318#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_OFST 64
22319#define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_LEN 4
22320
22321/* MC_CMD_VIRTIO_INIT_QUEUE_RESP msgresponse */
22322#define MC_CMD_VIRTIO_INIT_QUEUE_RESP_LEN 0
22323
22324
22325/***********************************/
22326/* MC_CMD_VIRTIO_FINI_QUEUE
22327 * Destroy a virtio virtqueue
22328 */
22329#define MC_CMD_VIRTIO_FINI_QUEUE 0x16b
22330#undef MC_CMD_0x16b_PRIVILEGE_CTG
22331
22332#define MC_CMD_0x16b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22333
22334/* MC_CMD_VIRTIO_FINI_QUEUE_REQ msgrequest */
22335#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_LEN 8
22336/* Type of virtqueue to destroy. */
22337#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_OFST 0
22338#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_LEN 1
22339/* Enum values, see field(s): */
22340/* MC_CMD_VIRTIO_INIT_QUEUE/MC_CMD_VIRTIO_INIT_QUEUE_REQ/QUEUE_TYPE */
22341#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_OFST 1
22342#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_RESERVED_LEN 1
22343/* If the calling function is a PF and this field is not VF_NULL, destroy the
22344 * queue on the specified child VF instead of on the PF.
22345 */
22346#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_TARGET_VF_OFST 2
22347#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_TARGET_VF_LEN 2
22348/* enum: No VF, destroy the queue on the PF. */
22349#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_VF_NULL 0xffff
22350/* Instance to destroy */
22351#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_OFST 4
22352#define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_LEN 4
22353
22354/* MC_CMD_VIRTIO_FINI_QUEUE_RESP msgresponse */
22355#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_LEN 8
22356/* The available index of the virtqueue when the queue was stopped. */
22357#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_AVAIL_IDX_OFST 0
22358#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_AVAIL_IDX_LEN 4
22359/* Alias of FINAL_AVAIL_IDX, kept for compatibility. */
22360#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_OFST 0
22361#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_LEN 4
22362/* The used index of the virtqueue when the queue was stopped. */
22363#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_USED_IDX_OFST 4
22364#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_USED_IDX_LEN 4
22365/* Alias of FINAL_USED_IDX, kept for compatibility. */
22366#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_OFST 4
22367#define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_LEN 4
22368
22369
22370/***********************************/
22371/* MC_CMD_VIRTIO_GET_DOORBELL_OFFSET
22372 * Get the offset in the BAR of the doorbells for a VI. Doesn't require the
22373 * queue(s) to be allocated.
22374 */
22375#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c
22376#undef MC_CMD_0x16c_PRIVILEGE_CTG
22377
22378#define MC_CMD_0x16c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22379
22380/* MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ msgrequest */
22381#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_LEN 8
22382/* Type of device to get information for. Matches the device id as defined by
22383 * the virtio spec.
22384 */
22385#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_OFST 0
22386#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_LEN 1
22387/* Enum values, see field(s): */
22388/* MC_CMD_VIRTIO_GET_FEATURES/MC_CMD_VIRTIO_GET_FEATURES_IN/DEVICE_ID */
22389#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_OFST 1
22390#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_RESERVED_LEN 1
22391/* If the calling function is a PF and this field is not VF_NULL, query the VI
22392 * on the specified child VF instead of on the PF.
22393 */
22394#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_TARGET_VF_OFST 2
22395#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_TARGET_VF_LEN 2
22396/* enum: No VF, query the PF. */
22397#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_VF_NULL 0xffff
22398/* VI instance to query */
22399#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_OFST 4
22400#define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_LEN 4
22401
22402/* MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP msgresponse */
22403#define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_LEN 8
22404/* Offset of RX doorbell in BAR */
22405#define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_OFST 0
22406#define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_LEN 4
22407/* Offset of TX doorbell in BAR */
22408#define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_OFST 4
22409#define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_LEN 4
22410
22411/* MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP msgresponse */
22412#define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_LEN 4
22413/* Offset of request doorbell in BAR */
22414#define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_OFST 0
22415#define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_LEN 4
22416
22417/* PCIE_FUNCTION structuredef: Structure representing a PCIe function ID
22418 * (interface/PF/VF tuple)
22419 */
22420#define PCIE_FUNCTION_LEN 8
22421/* PCIe PF function number */
22422#define PCIE_FUNCTION_PF_OFST 0
22423#define PCIE_FUNCTION_PF_LEN 2
22424/* enum: Wildcard value representing any available function (e.g in resource
22425 * allocation requests)
22426 */
22427#define PCIE_FUNCTION_PF_ANY 0xfffe
22428/* enum: Value representing invalid (null) function */
22429#define PCIE_FUNCTION_PF_NULL 0xffff
22430#define PCIE_FUNCTION_PF_LBN 0
22431#define PCIE_FUNCTION_PF_WIDTH 16
22432/* PCIe VF Function number (PF relative) */
22433#define PCIE_FUNCTION_VF_OFST 2
22434#define PCIE_FUNCTION_VF_LEN 2
22435/* enum: Wildcard value representing any available function (e.g in resource
22436 * allocation requests)
22437 */
22438#define PCIE_FUNCTION_VF_ANY 0xfffe
22439/* enum: Function is a PF (when PF != PF_NULL) or invalid function (when PF ==
22440 * PF_NULL)
22441 */
22442#define PCIE_FUNCTION_VF_NULL 0xffff
22443#define PCIE_FUNCTION_VF_LBN 16
22444#define PCIE_FUNCTION_VF_WIDTH 16
22445/* PCIe interface of the function. Values should be taken from the
22446 * PCIE_INTERFACE enum
22447 */
22448#define PCIE_FUNCTION_INTF_OFST 4
22449#define PCIE_FUNCTION_INTF_LEN 4
22450/* enum: Host PCIe interface. (Alias for HOST_PRIMARY, provided for backwards
22451 * compatibility)
22452 */
22453#define PCIE_FUNCTION_INTF_HOST 0x0
22454/* enum: Application Processor interface (alias for NIC_EMBEDDED, provided for
22455 * backwards compatibility)
22456 */
22457#define PCIE_FUNCTION_INTF_AP 0x1
22458#define PCIE_FUNCTION_INTF_LBN 32
22459#define PCIE_FUNCTION_INTF_WIDTH 32
22460
22461
22462/***********************************/
22463/* MC_CMD_GET_CLIENT_HANDLE
22464 * Obtain a handle for a client given a description of that client. N.B. this
22465 * command is subject to change given the open discussion about how PCIe
22466 * functions should be referenced on an iEP (integrated endpoint: functions
22467 * span multiple buses) and multihost (multiple PCIe interfaces) system.
22468 */
22469#define MC_CMD_GET_CLIENT_HANDLE 0x1c3
22470#undef MC_CMD_0x1c3_PRIVILEGE_CTG
22471
22472#define MC_CMD_0x1c3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
22473
22474/* MC_CMD_GET_CLIENT_HANDLE_IN msgrequest */
22475#define MC_CMD_GET_CLIENT_HANDLE_IN_LEN 12
22476/* Type of client to get a client handle for */
22477#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_OFST 0
22478#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_LEN 4
22479/* enum: Obtain a client handle for a PCIe function-type client. */
22480#define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_FUNC 0x0
22481/* PCIe Function ID (as struct PCIE_FUNCTION). Valid when TYPE==FUNC. Use: -
22482 * INTF=CALLER, PF=PF_NULL, VF=VF_NULL to refer to the calling function -
22483 * INTF=CALLER, PF=PF_NULL, VF=... to refer to a VF child of the calling PF or
22484 * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer
22485 * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a
22486 * VF on the calling interface - INTF=..., PF=PF_NULL, VF=VF_NULL to refer to
22487 * the named interface itself - INTF=..., PF=..., VF=VF_NULL to refer to a PF
22488 * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named
22489 * interface where ... refers to a small integer for the VF/PF fields, and to
22490 * values from the PCIE_INTERFACE enum for for the INTF field. It's only
22491 * meaningful to use INTF=CALLER within a structure that's an argument to
22492 * MC_CMD_DEVEL_GET_CLIENT_HANDLE.
22493 */
22494#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_OFST 4
22495#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LEN 8
22496#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_OFST 4
22497#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LEN 4
22498#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LBN 32
22499#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_WIDTH 32
22500#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_OFST 8
22501#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LEN 4
22502#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LBN 64
22503#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_WIDTH 32
22504/* enum: NULL value for the INTF field of struct PCIE_FUNCTION. Provided for
22505 * backwards compatibility only, callers should use PCIE_INTERFACE_CALLER.
22506 */
22507#define MC_CMD_GET_CLIENT_HANDLE_IN_PCIE_FUNCTION_INTF_NULL 0xffffffff
22508/* See structuredef: PCIE_FUNCTION */
22509#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_OFST 4
22510#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_LEN 2
22511#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_OFST 6
22512#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_VF_LEN 2
22513#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_OFST 8
22514#define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_LEN 4
22515
22516/* MC_CMD_GET_CLIENT_HANDLE_OUT msgresponse */
22517#define MC_CMD_GET_CLIENT_HANDLE_OUT_LEN 4
22518#define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_OFST 0
22519#define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_LEN 4
22520
22521/* MAE_FIELD_FLAGS structuredef */
22522#define MAE_FIELD_FLAGS_LEN 4
22523#define MAE_FIELD_FLAGS_FLAT_OFST 0
22524#define MAE_FIELD_FLAGS_FLAT_LEN 4
22525#define MAE_FIELD_FLAGS_SUPPORT_STATUS_OFST 0
22526#define MAE_FIELD_FLAGS_SUPPORT_STATUS_LBN 0
22527#define MAE_FIELD_FLAGS_SUPPORT_STATUS_WIDTH 6
22528#define MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_OFST 0
22529#define MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_LBN 6
22530#define MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_WIDTH 1
22531#define MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_OFST 0
22532#define MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_LBN 7
22533#define MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_WIDTH 1
22534#define MAE_FIELD_FLAGS_FLAT_LBN 0
22535#define MAE_FIELD_FLAGS_FLAT_WIDTH 32
22536
22537/* MAE_ENC_FIELD_PAIRS structuredef: Mask and value pairs for all fields that
22538 * it makes sense to use to determine the encapsulation type of a packet. Its
22539 * intended use is to keep a common packing of fields across multiple MCDI
22540 * commands, keeping things inherently sychronised and allowing code shared. To
22541 * use in an MCDI command, the command should end with a variable length byte
22542 * array populated with this structure. Do not extend this structure. Instead,
22543 * create _Vx versions with the necessary fields appended. That way, the
22544 * existing semantics for extending MCDI commands are preserved.
22545 */
22546#define MAE_ENC_FIELD_PAIRS_LEN 156
22547#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0
22548#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4
22549#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0
22550#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_WIDTH 32
22551#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4
22552#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4
22553#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LBN 32
22554#define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_WIDTH 32
22555#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_OFST 8
22556#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_LEN 2
22557#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_LBN 64
22558#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_WIDTH 16
22559#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_OFST 10
22560#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_LEN 2
22561#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_LBN 80
22562#define MAE_ENC_FIELD_PAIRS_ENC_ETHER_TYPE_BE_MASK_WIDTH 16
22563#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_OFST 12
22564#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_LEN 2
22565#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_LBN 96
22566#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_WIDTH 16
22567#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_OFST 14
22568#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_LEN 2
22569#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_LBN 112
22570#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_TCI_BE_MASK_WIDTH 16
22571#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_OFST 16
22572#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_LEN 2
22573#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_LBN 128
22574#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_WIDTH 16
22575#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_OFST 18
22576#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LEN 2
22577#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LBN 144
22578#define MAE_ENC_FIELD_PAIRS_ENC_VLAN0_PROTO_BE_MASK_WIDTH 16
22579#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_OFST 20
22580#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_LEN 2
22581#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_LBN 160
22582#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_WIDTH 16
22583#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_OFST 22
22584#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_LEN 2
22585#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_LBN 176
22586#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_TCI_BE_MASK_WIDTH 16
22587#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_OFST 24
22588#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_LEN 2
22589#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_LBN 192
22590#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_WIDTH 16
22591#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_OFST 26
22592#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LEN 2
22593#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LBN 208
22594#define MAE_ENC_FIELD_PAIRS_ENC_VLAN1_PROTO_BE_MASK_WIDTH 16
22595#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_OFST 28
22596#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_LEN 6
22597#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_LBN 224
22598#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_WIDTH 48
22599#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_OFST 34
22600#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_LEN 6
22601#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_LBN 272
22602#define MAE_ENC_FIELD_PAIRS_ENC_ETH_SADDR_BE_MASK_WIDTH 48
22603#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_OFST 40
22604#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_LEN 6
22605#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_LBN 320
22606#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_WIDTH 48
22607#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_OFST 46
22608#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_LEN 6
22609#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_LBN 368
22610#define MAE_ENC_FIELD_PAIRS_ENC_ETH_DADDR_BE_MASK_WIDTH 48
22611#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_OFST 52
22612#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_LEN 4
22613#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_LBN 416
22614#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_WIDTH 32
22615#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_OFST 56
22616#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4
22617#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_LBN 448
22618#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_WIDTH 32
22619#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_OFST 60
22620#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_LEN 16
22621#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_LBN 480
22622#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_WIDTH 128
22623#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_OFST 76
22624#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_LEN 16
22625#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_LBN 608
22626#define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP6_BE_MASK_WIDTH 128
22627#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_OFST 92
22628#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_LEN 4
22629#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_LBN 736
22630#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_WIDTH 32
22631#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_OFST 96
22632#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4
22633#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_LBN 768
22634#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_WIDTH 32
22635#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_OFST 100
22636#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_LEN 16
22637#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_LBN 800
22638#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_WIDTH 128
22639#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_OFST 116
22640#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_LEN 16
22641#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_LBN 928
22642#define MAE_ENC_FIELD_PAIRS_ENC_DST_IP6_BE_MASK_WIDTH 128
22643#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_OFST 132
22644#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_LEN 1
22645#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_LBN 1056
22646#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_WIDTH 8
22647#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_OFST 133
22648#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_LEN 1
22649#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_LBN 1064
22650#define MAE_ENC_FIELD_PAIRS_ENC_IP_PROTO_MASK_WIDTH 8
22651#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_OFST 134
22652#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_LEN 1
22653#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_LBN 1072
22654#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_WIDTH 8
22655#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_OFST 135
22656#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_LEN 1
22657#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_LBN 1080
22658#define MAE_ENC_FIELD_PAIRS_ENC_IP_TOS_MASK_WIDTH 8
22659#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_OFST 136
22660#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_LEN 1
22661#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_LBN 1088
22662#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_WIDTH 8
22663#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_OFST 137
22664#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LEN 1
22665#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_LBN 1096
22666#define MAE_ENC_FIELD_PAIRS_ENC_IP_TTL_MASK_WIDTH 8
22667/* Deprecated in favour of ENC_FLAGS alias. */
22668#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_OFST 138
22669#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LEN 1
22670#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_OFST 138
22671#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_LBN 0
22672#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_WIDTH 1
22673#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_OFST 138
22674#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_LBN 1
22675#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_WIDTH 1
22676#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_OFST 138
22677#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_LBN 2
22678#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_WIDTH 1
22679#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_LBN 1104
22680#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_WIDTH 8
22681/* More generic alias for ENC_VLAN_FLAGS. */
22682#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_OFST 138
22683#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_LEN 1
22684#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_LBN 1104
22685#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_WIDTH 8
22686/* Deprecated in favour of ENC_FLAGS_MASK alias. */
22687#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_OFST 139
22688#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LEN 1
22689#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_OFST 139
22690#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_LBN 0
22691#define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_WIDTH 1
22692#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_OFST 139
22693#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_LBN 1
22694#define MAE_ENC_FIELD_PAIRS_ENC_HAS_IVLAN_MASK_WIDTH 1
22695#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_OFST 139
22696#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_LBN 2
22697#define MAE_ENC_FIELD_PAIRS_ENC_IP_FRAG_MASK_WIDTH 1
22698#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_LBN 1112
22699#define MAE_ENC_FIELD_PAIRS_ENC_VLAN_FLAGS_MASK_WIDTH 8
22700/* More generic alias for ENC_FLAGS_MASK. */
22701#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_OFST 139
22702#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LEN 1
22703#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_LBN 1112
22704#define MAE_ENC_FIELD_PAIRS_ENC_FLAGS_MASK_WIDTH 8
22705#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_OFST 140
22706#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LEN 4
22707#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LBN 1120
22708#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_WIDTH 32
22709#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_OFST 144
22710#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4
22711#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_LBN 1152
22712#define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_WIDTH 32
22713#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_OFST 148
22714#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_LEN 2
22715#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_LBN 1184
22716#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_WIDTH 16
22717#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_OFST 150
22718#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_LEN 2
22719#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_LBN 1200
22720#define MAE_ENC_FIELD_PAIRS_ENC_L4_SPORT_BE_MASK_WIDTH 16
22721#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_OFST 152
22722#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_LEN 2
22723#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_LBN 1216
22724#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_WIDTH 16
22725#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_OFST 154
22726#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_LEN 2
22727#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_LBN 1232
22728#define MAE_ENC_FIELD_PAIRS_ENC_L4_DPORT_BE_MASK_WIDTH 16
22729
22730/* MAE_FIELD_MASK_VALUE_PAIRS structuredef: Mask and value pairs for all fields
22731 * currently defined. Same semantics as MAE_ENC_FIELD_PAIRS.
22732 */
22733#define MAE_FIELD_MASK_VALUE_PAIRS_LEN 344
22734#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0
22735#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4
22736#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0
22737#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_WIDTH 32
22738#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4
22739#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4
22740#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LBN 32
22741#define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_WIDTH 32
22742#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_OFST 8
22743#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_LEN 4
22744#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_LBN 64
22745#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_WIDTH 32
22746#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_OFST 12
22747#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_LEN 4
22748#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_LBN 96
22749#define MAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_WIDTH 32
22750#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_OFST 16
22751#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_LEN 2
22752#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_LBN 128
22753#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_WIDTH 16
22754#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_OFST 18
22755#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_LEN 2
22756#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_LBN 144
22757#define MAE_FIELD_MASK_VALUE_PAIRS_ETHER_TYPE_BE_MASK_WIDTH 16
22758#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_OFST 20
22759#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_LEN 2
22760#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_LBN 160
22761#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_WIDTH 16
22762#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_OFST 22
22763#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_LEN 2
22764#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_LBN 176
22765#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_TCI_BE_MASK_WIDTH 16
22766#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_OFST 24
22767#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_LEN 2
22768#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_LBN 192
22769#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_WIDTH 16
22770#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_OFST 26
22771#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_LEN 2
22772#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_LBN 208
22773#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN0_PROTO_BE_MASK_WIDTH 16
22774#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_OFST 28
22775#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_LEN 2
22776#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_LBN 224
22777#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_WIDTH 16
22778#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_OFST 30
22779#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_LEN 2
22780#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_LBN 240
22781#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_TCI_BE_MASK_WIDTH 16
22782#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_OFST 32
22783#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_LEN 2
22784#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_LBN 256
22785#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_WIDTH 16
22786#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_OFST 34
22787#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_LEN 2
22788#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_LBN 272
22789#define MAE_FIELD_MASK_VALUE_PAIRS_VLAN1_PROTO_BE_MASK_WIDTH 16
22790#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_OFST 36
22791#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_LEN 6
22792#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_LBN 288
22793#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_WIDTH 48
22794#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_OFST 42
22795#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_LEN 6
22796#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_LBN 336
22797#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_SADDR_BE_MASK_WIDTH 48
22798#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_OFST 48
22799#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_LEN 6
22800#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_LBN 384
22801#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_WIDTH 48
22802#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_OFST 54
22803#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_LEN 6
22804#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_LBN 432
22805#define MAE_FIELD_MASK_VALUE_PAIRS_ETH_DADDR_BE_MASK_WIDTH 48
22806#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_OFST 60
22807#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_LEN 4
22808#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_LBN 480
22809#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_WIDTH 32
22810#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_OFST 64
22811#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_LEN 4
22812#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_LBN 512
22813#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_WIDTH 32
22814#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_OFST 68
22815#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_LEN 16
22816#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_LBN 544
22817#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_WIDTH 128
22818#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_OFST 84
22819#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_LEN 16
22820#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_LBN 672
22821#define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP6_BE_MASK_WIDTH 128
22822#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_OFST 100
22823#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_LEN 4
22824#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_LBN 800
22825#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_WIDTH 32
22826#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_OFST 104
22827#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_LEN 4
22828#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_LBN 832
22829#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_WIDTH 32
22830#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_OFST 108
22831#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_LEN 16
22832#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_LBN 864
22833#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_WIDTH 128
22834#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_OFST 124
22835#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_LEN 16
22836#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_LBN 992
22837#define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP6_BE_MASK_WIDTH 128
22838#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_OFST 140
22839#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_LEN 1
22840#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_LBN 1120
22841#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_WIDTH 8
22842#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_OFST 141
22843#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_LEN 1
22844#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_LBN 1128
22845#define MAE_FIELD_MASK_VALUE_PAIRS_IP_PROTO_MASK_WIDTH 8
22846#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_OFST 142
22847#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_LEN 1
22848#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_LBN 1136
22849#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_WIDTH 8
22850#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_OFST 143
22851#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_LEN 1
22852#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_LBN 1144
22853#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TOS_MASK_WIDTH 8
22854/* Due to hardware limitations, firmware may return
22855 * MC_CMD_ERR_EINVAL(BAD_IP_TTL) when attempting to match on an IP_TTL value
22856 * other than 1.
22857 */
22858#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_OFST 144
22859#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_LEN 1
22860#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_LBN 1152
22861#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_WIDTH 8
22862#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_OFST 145
22863#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_LEN 1
22864#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_LBN 1160
22865#define MAE_FIELD_MASK_VALUE_PAIRS_IP_TTL_MASK_WIDTH 8
22866#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_OFST 148
22867#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_LEN 4
22868#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_LBN 1184
22869#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_WIDTH 32
22870#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_OFST 152
22871#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_LEN 4
22872#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_LBN 1216
22873#define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_WIDTH 32
22874#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_OFST 156
22875#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_LEN 2
22876#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_LBN 1248
22877#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_WIDTH 16
22878#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_OFST 158
22879#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_LEN 2
22880#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_LBN 1264
22881#define MAE_FIELD_MASK_VALUE_PAIRS_L4_SPORT_BE_MASK_WIDTH 16
22882#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_OFST 160
22883#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_LEN 2
22884#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_LBN 1280
22885#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_WIDTH 16
22886#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_OFST 162
22887#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_LEN 2
22888#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_LBN 1296
22889#define MAE_FIELD_MASK_VALUE_PAIRS_L4_DPORT_BE_MASK_WIDTH 16
22890#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_OFST 164
22891#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_LEN 2
22892#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_LBN 1312
22893#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_WIDTH 16
22894#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_OFST 166
22895#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_LEN 2
22896#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_LBN 1328
22897#define MAE_FIELD_MASK_VALUE_PAIRS_TCP_FLAGS_BE_MASK_WIDTH 16
22898#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_OFST 168
22899#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_LEN 4
22900#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_LBN 1344
22901#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_WIDTH 32
22902#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_OFST 172
22903#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_LEN 4
22904#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_LBN 1376
22905#define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_WIDTH 32
22906#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_OFST 176
22907#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_LEN 4
22908#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_LBN 1408
22909#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_WIDTH 32
22910#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_OFST 180
22911#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_LEN 4
22912#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_LBN 1440
22913#define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_WIDTH 32
22914#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_OFST 184
22915#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_LEN 2
22916#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_LBN 1472
22917#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_WIDTH 16
22918#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_OFST 188
22919#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_LEN 2
22920#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_LBN 1504
22921#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETHER_TYPE_BE_MASK_WIDTH 16
22922#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_OFST 192
22923#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_LEN 2
22924#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_LBN 1536
22925#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_WIDTH 16
22926#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_OFST 194
22927#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_LEN 2
22928#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_LBN 1552
22929#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_TCI_BE_MASK_WIDTH 16
22930#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_OFST 196
22931#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_LEN 2
22932#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_LBN 1568
22933#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_WIDTH 16
22934#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_OFST 198
22935#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LEN 2
22936#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_LBN 1584
22937#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN0_PROTO_BE_MASK_WIDTH 16
22938#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_OFST 200
22939#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_LEN 2
22940#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_LBN 1600
22941#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_WIDTH 16
22942#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_OFST 202
22943#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_LEN 2
22944#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_LBN 1616
22945#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_TCI_BE_MASK_WIDTH 16
22946#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_OFST 204
22947#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_LEN 2
22948#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_LBN 1632
22949#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_WIDTH 16
22950#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_OFST 206
22951#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LEN 2
22952#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_LBN 1648
22953#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VLAN1_PROTO_BE_MASK_WIDTH 16
22954#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_OFST 208
22955#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_LEN 6
22956#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_LBN 1664
22957#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_WIDTH 48
22958#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_OFST 214
22959#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_LEN 6
22960#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_LBN 1712
22961#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_SADDR_BE_MASK_WIDTH 48
22962#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_OFST 220
22963#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_LEN 6
22964#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_LBN 1760
22965#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_WIDTH 48
22966#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_OFST 226
22967#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_LEN 6
22968#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_LBN 1808
22969#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_ETH_DADDR_BE_MASK_WIDTH 48
22970#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_OFST 232
22971#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_LEN 4
22972#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_LBN 1856
22973#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_WIDTH 32
22974#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_OFST 236
22975#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4
22976#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_LBN 1888
22977#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_WIDTH 32
22978#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_OFST 240
22979#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_LEN 16
22980#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_LBN 1920
22981#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_WIDTH 128
22982#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_OFST 256
22983#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_LEN 16
22984#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_LBN 2048
22985#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP6_BE_MASK_WIDTH 128
22986#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_OFST 272
22987#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_LEN 4
22988#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_LBN 2176
22989#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_WIDTH 32
22990#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_OFST 276
22991#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4
22992#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_LBN 2208
22993#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_WIDTH 32
22994#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_OFST 280
22995#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_LEN 16
22996#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_LBN 2240
22997#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_WIDTH 128
22998#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_OFST 296
22999#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_LEN 16
23000#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_LBN 2368
23001#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP6_BE_MASK_WIDTH 128
23002#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_OFST 312
23003#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_LEN 1
23004#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_LBN 2496
23005#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_WIDTH 8
23006#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_OFST 313
23007#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_LEN 1
23008#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_LBN 2504
23009#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_PROTO_MASK_WIDTH 8
23010#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_OFST 314
23011#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_LEN 1
23012#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_LBN 2512
23013#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_WIDTH 8
23014#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_OFST 315
23015#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_LEN 1
23016#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_LBN 2520
23017#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TOS_MASK_WIDTH 8
23018#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_OFST 316
23019#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_LEN 1
23020#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_LBN 2528
23021#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_WIDTH 8
23022#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_OFST 317
23023#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_LEN 1
23024#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_LBN 2536
23025#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_TTL_MASK_WIDTH 8
23026#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_OFST 320
23027#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_LEN 4
23028#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_LBN 2560
23029#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_WIDTH 32
23030#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_OFST 324
23031#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4
23032#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_LBN 2592
23033#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_WIDTH 32
23034#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_OFST 328
23035#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_LEN 2
23036#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_LBN 2624
23037#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_WIDTH 16
23038#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_OFST 330
23039#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_LEN 2
23040#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_LBN 2640
23041#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_SPORT_BE_MASK_WIDTH 16
23042#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_OFST 332
23043#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_LEN 2
23044#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_LBN 2656
23045#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_WIDTH 16
23046#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_OFST 334
23047#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_LEN 2
23048#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_LBN 2672
23049#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_L4_DPORT_BE_MASK_WIDTH 16
23050#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_OFST 336
23051#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_LEN 4
23052#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_LBN 2688
23053#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_WIDTH 32
23054#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_OFST 340
23055#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_LEN 4
23056#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_LBN 2720
23057#define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_WIDTH 32
23058
23059/* MAE_FIELD_MASK_VALUE_PAIRS_V2 structuredef */
23060#define MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN 372
23061#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_OFST 0
23062#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LEN 4
23063#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LBN 0
23064#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_WIDTH 32
23065#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_OFST 4
23066#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_LEN 4
23067#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_LBN 32
23068#define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_WIDTH 32
23069#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_OFST 8
23070#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_LEN 4
23071#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_LBN 64
23072#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_WIDTH 32
23073#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_OFST 12
23074#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_LEN 4
23075#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_LBN 96
23076#define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_WIDTH 32
23077#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_OFST 16
23078#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_LEN 2
23079#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_LBN 128
23080#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_WIDTH 16
23081#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_OFST 18
23082#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_LEN 2
23083#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_LBN 144
23084#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETHER_TYPE_BE_MASK_WIDTH 16
23085#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_OFST 20
23086#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_LEN 2
23087#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_LBN 160
23088#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_WIDTH 16
23089#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_OFST 22
23090#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_LEN 2
23091#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_LBN 176
23092#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_TCI_BE_MASK_WIDTH 16
23093#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_OFST 24
23094#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_LEN 2
23095#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_LBN 192
23096#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_WIDTH 16
23097#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_OFST 26
23098#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_LEN 2
23099#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_LBN 208
23100#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN0_PROTO_BE_MASK_WIDTH 16
23101#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_OFST 28
23102#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_LEN 2
23103#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_LBN 224
23104#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_WIDTH 16
23105#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_OFST 30
23106#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_LEN 2
23107#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_LBN 240
23108#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_TCI_BE_MASK_WIDTH 16
23109#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_OFST 32
23110#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_LEN 2
23111#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_LBN 256
23112#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_WIDTH 16
23113#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_OFST 34
23114#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_LEN 2
23115#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_LBN 272
23116#define MAE_FIELD_MASK_VALUE_PAIRS_V2_VLAN1_PROTO_BE_MASK_WIDTH 16
23117#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_OFST 36
23118#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_LEN 6
23119#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_LBN 288
23120#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_WIDTH 48
23121#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_OFST 42
23122#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_LEN 6
23123#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_LBN 336
23124#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_SADDR_BE_MASK_WIDTH 48
23125#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_OFST 48
23126#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_LEN 6
23127#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_LBN 384
23128#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_WIDTH 48
23129#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_OFST 54
23130#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_LEN 6
23131#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_LBN 432
23132#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ETH_DADDR_BE_MASK_WIDTH 48
23133#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_OFST 60
23134#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_LEN 4
23135#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_LBN 480
23136#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_WIDTH 32
23137#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_OFST 64
23138#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_LEN 4
23139#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_LBN 512
23140#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_WIDTH 32
23141#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_OFST 68
23142#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_LEN 16
23143#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_LBN 544
23144#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_WIDTH 128
23145#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_OFST 84
23146#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_LEN 16
23147#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_LBN 672
23148#define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP6_BE_MASK_WIDTH 128
23149#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_OFST 100
23150#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_LEN 4
23151#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_LBN 800
23152#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_WIDTH 32
23153#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_OFST 104
23154#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_LEN 4
23155#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_LBN 832
23156#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_WIDTH 32
23157#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_OFST 108
23158#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_LEN 16
23159#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_LBN 864
23160#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_WIDTH 128
23161#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_OFST 124
23162#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_LEN 16
23163#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_LBN 992
23164#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP6_BE_MASK_WIDTH 128
23165#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_OFST 140
23166#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_LEN 1
23167#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_LBN 1120
23168#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_WIDTH 8
23169#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_OFST 141
23170#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_LEN 1
23171#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_LBN 1128
23172#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_PROTO_MASK_WIDTH 8
23173#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_OFST 142
23174#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_LEN 1
23175#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_LBN 1136
23176#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_WIDTH 8
23177#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_OFST 143
23178#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_LEN 1
23179#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_LBN 1144
23180#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TOS_MASK_WIDTH 8
23181/* Due to hardware limitations, firmware may return
23182 * MC_CMD_ERR_EINVAL(BAD_IP_TTL) when attempting to match on an IP_TTL value
23183 * other than 1.
23184 */
23185#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_OFST 144
23186#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_LEN 1
23187#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_LBN 1152
23188#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_WIDTH 8
23189#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_OFST 145
23190#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_LEN 1
23191#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_LBN 1160
23192#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_TTL_MASK_WIDTH 8
23193#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_OFST 148
23194#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_LEN 4
23195#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_LBN 1184
23196#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_WIDTH 32
23197#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_OFST 152
23198#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_LEN 4
23199#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_LBN 1216
23200#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_WIDTH 32
23201#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_OFST 156
23202#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_LEN 2
23203#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_LBN 1248
23204#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_WIDTH 16
23205#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_OFST 158
23206#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_LEN 2
23207#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_LBN 1264
23208#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_SPORT_BE_MASK_WIDTH 16
23209#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_OFST 160
23210#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_LEN 2
23211#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_LBN 1280
23212#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_WIDTH 16
23213#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_OFST 162
23214#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_LEN 2
23215#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_LBN 1296
23216#define MAE_FIELD_MASK_VALUE_PAIRS_V2_L4_DPORT_BE_MASK_WIDTH 16
23217#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_OFST 164
23218#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_LEN 2
23219#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_LBN 1312
23220#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_WIDTH 16
23221#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_OFST 166
23222#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_LEN 2
23223#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_LBN 1328
23224#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_FLAGS_BE_MASK_WIDTH 16
23225#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_OFST 168
23226#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_LEN 4
23227#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_LBN 1344
23228#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_WIDTH 32
23229#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_OFST 172
23230#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_LEN 4
23231#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_LBN 1376
23232#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_WIDTH 32
23233#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_OFST 176
23234#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_LEN 4
23235#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_LBN 1408
23236#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_WIDTH 32
23237#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_OFST 180
23238#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_LEN 4
23239#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_LBN 1440
23240#define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_WIDTH 32
23241#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_OFST 184
23242#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_LEN 2
23243#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_LBN 1472
23244#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_WIDTH 16
23245#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_OFST 188
23246#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_LEN 2
23247#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_LBN 1504
23248#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETHER_TYPE_BE_MASK_WIDTH 16
23249#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_OFST 192
23250#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_LEN 2
23251#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_LBN 1536
23252#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_WIDTH 16
23253#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_OFST 194
23254#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_LEN 2
23255#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_LBN 1552
23256#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_TCI_BE_MASK_WIDTH 16
23257#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_OFST 196
23258#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_LEN 2
23259#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_LBN 1568
23260#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_WIDTH 16
23261#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_OFST 198
23262#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_LEN 2
23263#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_LBN 1584
23264#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN0_PROTO_BE_MASK_WIDTH 16
23265#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_OFST 200
23266#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_LEN 2
23267#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_LBN 1600
23268#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_WIDTH 16
23269#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_OFST 202
23270#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_LEN 2
23271#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_LBN 1616
23272#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_TCI_BE_MASK_WIDTH 16
23273#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_OFST 204
23274#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_LEN 2
23275#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_LBN 1632
23276#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_WIDTH 16
23277#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_OFST 206
23278#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_LEN 2
23279#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_LBN 1648
23280#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VLAN1_PROTO_BE_MASK_WIDTH 16
23281#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_OFST 208
23282#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_LEN 6
23283#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_LBN 1664
23284#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_WIDTH 48
23285#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_OFST 214
23286#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_LEN 6
23287#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_LBN 1712
23288#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_SADDR_BE_MASK_WIDTH 48
23289#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_OFST 220
23290#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_LEN 6
23291#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_LBN 1760
23292#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_WIDTH 48
23293#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_OFST 226
23294#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_LEN 6
23295#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_LBN 1808
23296#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_ETH_DADDR_BE_MASK_WIDTH 48
23297#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_OFST 232
23298#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_LEN 4
23299#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_LBN 1856
23300#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_WIDTH 32
23301#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_OFST 236
23302#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_LEN 4
23303#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_LBN 1888
23304#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_WIDTH 32
23305#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_OFST 240
23306#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_LEN 16
23307#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_LBN 1920
23308#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_WIDTH 128
23309#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_OFST 256
23310#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_LEN 16
23311#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_LBN 2048
23312#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP6_BE_MASK_WIDTH 128
23313#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_OFST 272
23314#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_LEN 4
23315#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_LBN 2176
23316#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_WIDTH 32
23317#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_OFST 276
23318#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_LEN 4
23319#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_LBN 2208
23320#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_WIDTH 32
23321#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_OFST 280
23322#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_LEN 16
23323#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_LBN 2240
23324#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_WIDTH 128
23325#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_OFST 296
23326#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_LEN 16
23327#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_LBN 2368
23328#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP6_BE_MASK_WIDTH 128
23329#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_OFST 312
23330#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_LEN 1
23331#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_LBN 2496
23332#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_WIDTH 8
23333#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_OFST 313
23334#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_LEN 1
23335#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_LBN 2504
23336#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_PROTO_MASK_WIDTH 8
23337#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_OFST 314
23338#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_LEN 1
23339#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_LBN 2512
23340#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_WIDTH 8
23341#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_OFST 315
23342#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_LEN 1
23343#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_LBN 2520
23344#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TOS_MASK_WIDTH 8
23345#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_OFST 316
23346#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_LEN 1
23347#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_LBN 2528
23348#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_WIDTH 8
23349#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_OFST 317
23350#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_LEN 1
23351#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_LBN 2536
23352#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_TTL_MASK_WIDTH 8
23353#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_OFST 320
23354#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_LEN 4
23355#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_LBN 2560
23356#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_WIDTH 32
23357#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_OFST 324
23358#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_LEN 4
23359#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_LBN 2592
23360#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_WIDTH 32
23361#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_OFST 328
23362#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_LEN 2
23363#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_LBN 2624
23364#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_WIDTH 16
23365#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_OFST 330
23366#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_LEN 2
23367#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_LBN 2640
23368#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_SPORT_BE_MASK_WIDTH 16
23369#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_OFST 332
23370#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_LEN 2
23371#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_LBN 2656
23372#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_WIDTH 16
23373#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_OFST 334
23374#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_LEN 2
23375#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_LBN 2672
23376#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_L4_DPORT_BE_MASK_WIDTH 16
23377#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_OFST 336
23378#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_LEN 4
23379#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_LBN 2688
23380#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_WIDTH 32
23381#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_OFST 340
23382#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_LEN 4
23383#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_LBN 2720
23384#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_WIDTH 32
23385#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_OFST 344
23386#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LEN 4
23387#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_OFST 344
23388#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_LBN 0
23389#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_WIDTH 1
23390#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DO_CT_OFST 344
23391#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DO_CT_LBN 1
23392#define MAE_FIELD_MASK_VALUE_PAIRS_V2_DO_CT_WIDTH 1
23393#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_HIT_OFST 344
23394#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_HIT_LBN 2
23395#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_HIT_WIDTH 1
23396#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_OFST 344
23397#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_LBN 3
23398#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_FROM_NETWORK_WIDTH 1
23399#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_OFST 344
23400#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_LBN 4
23401#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_WIDTH 1
23402#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_OFST 344
23403#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_LBN 5
23404#define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_IVLAN_WIDTH 1
23405#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_OFST 344
23406#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_LBN 6
23407#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_OVLAN_WIDTH 1
23408#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_OFST 344
23409#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_LBN 7
23410#define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_HAS_IVLAN_WIDTH 1
23411#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_OFST 344
23412#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_LBN 8
23413#define MAE_FIELD_MASK_VALUE_PAIRS_V2_TCP_SYN_FIN_RST_WIDTH 1
23414#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_OFST 344
23415#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_LBN 9
23416#define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FIRST_FRAG_WIDTH 1
23417#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LBN 2752
23418#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_WIDTH 32
23419#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST 348
23420#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_LEN 4
23421#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_LBN 2784
23422#define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_WIDTH 32
23423#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_OFST 352
23424#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_LEN 2
23425#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_LBN 2816
23426#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_WIDTH 16
23427#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_OFST 354
23428#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_LEN 2
23429#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_LBN 2832
23430#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_DOMAIN_MASK_WIDTH 16
23431#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_OFST 356
23432#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_LEN 4
23433#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_LBN 2848
23434#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_WIDTH 32
23435#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_OFST 360
23436#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_LEN 4
23437#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_LBN 2880
23438#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_WIDTH 32
23439#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_OFST 364
23440#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_LEN 1
23441#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_LBN 2912
23442#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_WIDTH 8
23443/* Set to zero. */
23444#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_OFST 365
23445#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_LEN 1
23446#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_LBN 2920
23447#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD2_WIDTH 8
23448#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_OFST 366
23449#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_LEN 1
23450#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_LBN 2928
23451#define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_PRIVATE_FLAGS_MASK_WIDTH 8
23452/* Set to zero. */
23453#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_OFST 367
23454#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_LEN 1
23455#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_LBN 2936
23456#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD3_WIDTH 8
23457#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_OFST 368
23458#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_LEN 1
23459#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_LBN 2944
23460#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_WIDTH 8
23461/* Set to zero */
23462#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_OFST 369
23463#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_LEN 1
23464#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_LBN 2952
23465#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD4_WIDTH 8
23466#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_OFST 370
23467#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_LEN 1
23468#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_LBN 2960
23469#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RECIRC_ID_MASK_WIDTH 8
23470/* Set to zero */
23471#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_OFST 371
23472#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_LEN 1
23473#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_LBN 2968
23474#define MAE_FIELD_MASK_VALUE_PAIRS_V2_RSVD5_WIDTH 8
23475
23476/* MAE_MPORT_SELECTOR structuredef: MPORTS are identified by an opaque unsigned
23477 * integer value (mport_id) that is guaranteed to be representable within
23478 * 32-bits or within any NIC interface field that needs store the value
23479 * (whichever is narrower). This selector structure provides a stable way to
23480 * refer to m-ports.
23481 */
23482#define MAE_MPORT_SELECTOR_LEN 4
23483/* Used to force the tools to output bitfield-style defines for this structure.
23484 */
23485#define MAE_MPORT_SELECTOR_FLAT_OFST 0
23486#define MAE_MPORT_SELECTOR_FLAT_LEN 4
23487/* enum: An m-port selector value that is guaranteed never to represent a real
23488 * mport
23489 */
23490#define MAE_MPORT_SELECTOR_NULL 0x0
23491/* enum: The m-port assigned to the calling client. */
23492#define MAE_MPORT_SELECTOR_ASSIGNED 0x1000000
23493#define MAE_MPORT_SELECTOR_TYPE_OFST 0
23494#define MAE_MPORT_SELECTOR_TYPE_LBN 24
23495#define MAE_MPORT_SELECTOR_TYPE_WIDTH 8
23496/* enum: The MPORT connected to a given physical port */
23497#define MAE_MPORT_SELECTOR_TYPE_PPORT 0x2
23498/* enum: The MPORT assigned to a given PCIe function. Deprecated in favour of
23499 * MH_FUNC.
23500 */
23501#define MAE_MPORT_SELECTOR_TYPE_FUNC 0x3
23502/* enum: An mport_id */
23503#define MAE_MPORT_SELECTOR_TYPE_MPORT_ID 0x4
23504/* enum: The MPORT assigned to a given PCIe function (see also FWRIVERHD-1108)
23505 */
23506#define MAE_MPORT_SELECTOR_TYPE_MH_FUNC 0x5
23507/* enum: This is guaranteed never to be a valid selector type */
23508#define MAE_MPORT_SELECTOR_TYPE_INVALID 0xff
23509#define MAE_MPORT_SELECTOR_MPORT_ID_OFST 0
23510#define MAE_MPORT_SELECTOR_MPORT_ID_LBN 0
23511#define MAE_MPORT_SELECTOR_MPORT_ID_WIDTH 24
23512#define MAE_MPORT_SELECTOR_PPORT_ID_OFST 0
23513#define MAE_MPORT_SELECTOR_PPORT_ID_LBN 0
23514#define MAE_MPORT_SELECTOR_PPORT_ID_WIDTH 4
23515#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_OFST 0
23516#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_LBN 20
23517#define MAE_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
23518#define MAE_MPORT_SELECTOR_HOST_PRIMARY 0x1 /* enum */
23519#define MAE_MPORT_SELECTOR_NIC_EMBEDDED 0x2 /* enum */
23520/* enum: Deprecated, use CALLER_INTF instead. */
23521#define MAE_MPORT_SELECTOR_CALLER 0xf
23522#define MAE_MPORT_SELECTOR_CALLER_INTF 0xf /* enum */
23523#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_OFST 0
23524#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_LBN 16
23525#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
23526#define MAE_MPORT_SELECTOR_FUNC_PF_ID_OFST 0
23527#define MAE_MPORT_SELECTOR_FUNC_PF_ID_LBN 16
23528#define MAE_MPORT_SELECTOR_FUNC_PF_ID_WIDTH 8
23529#define MAE_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
23530#define MAE_MPORT_SELECTOR_FUNC_VF_ID_LBN 0
23531#define MAE_MPORT_SELECTOR_FUNC_VF_ID_WIDTH 16
23532/* enum: Used for VF_ID to indicate a physical function. */
23533#define MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL 0xffff
23534/* enum: Used for PF_ID to indicate the physical function of the calling
23535 * client. - When used by a PF with VF_ID == VF_ID_NULL, the mport selector
23536 * relates to the calling function. (For clarity, it is recommended that
23537 * clients use ASSIGNED to achieve this behaviour). - When used by a PF with
23538 * VF_ID != VF_ID_NULL, the mport selector relates to a VF child of the calling
23539 * function. - When used by a VF with VF_ID == VF_ID_NULL, the mport selector
23540 * relates to the PF owning the calling function. - When used by a VF with
23541 * VF_ID != VF_ID_NULL, the mport selector relates to a sibling VF of the
23542 * calling function. - Not meaningful used by a client that is not a PCIe
23543 * function.
23544 */
23545#define MAE_MPORT_SELECTOR_FUNC_PF_ID_CALLER 0xff
23546/* enum: Same as PF_ID_CALLER, but for use in the smaller MH_PF_ID field. Only
23547 * valid if FUNC_INTF_ID is CALLER.
23548 */
23549#define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_CALLER 0xf
23550#define MAE_MPORT_SELECTOR_FLAT_LBN 0
23551#define MAE_MPORT_SELECTOR_FLAT_WIDTH 32
23552
23553/* MAE_LINK_ENDPOINT_SELECTOR structuredef: Structure that identifies a real or
23554 * virtual network port by MAE port and link end. Intended to be used by
23555 * network port MCDI commands. Setting FLAT to MAE_LINK_ENDPOINT_COMPAT is
23556 * equivalent to using the previous version of the command. Not all possible
23557 * combinations of MPORT_END and MPORT_SELECTOR in MAE_LINK_ENDPOINT_SELECTOR
23558 * will work in all circumstances. 1. Some will always work (e.g. a VF can
23559 * always address its logical MAC using MPORT_SELECTOR=ASSIGNED,LINK_END=VNIC),
23560 * 2. Some are not meaningful and will always fail with EINVAL (e.g. attempting
23561 * to address the VNIC end of a link to a physical port), 3. Some are
23562 * meaningful but require the MCDI client to have the required permission and
23563 * fail with EPERM otherwise (e.g. trying to set the MAC on a VF the caller
23564 * cannot administer), and 4. Some could be implementation-specific and fail
23565 * with ENOTSUP if not available (no examples exist right now). See
23566 * SF-123581-TC section 4.3 for more details.
23567 */
23568#define MAE_LINK_ENDPOINT_SELECTOR_LEN 8
23569/* Identifier for the MAE MPORT of interest */
23570#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_OFST 0
23571#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LEN 4
23572#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LBN 0
23573#define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_WIDTH 32
23574/* Which end of the link identified by MPORT to consider */
23575#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_OFST 4
23576#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LEN 4
23577/* Enum values, see field(s): */
23578/* MAE_MPORT_END */
23579#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LBN 32
23580#define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_WIDTH 32
23581/* A field for accessing the endpoint selector as a collection of bits */
23582#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_OFST 0
23583#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LEN 8
23584#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_OFST 0
23585#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LEN 4
23586#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LBN 0
23587#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_WIDTH 32
23588#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_OFST 4
23589#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LEN 4
23590#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LBN 32
23591#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_WIDTH 32
23592/* enum: Set FLAT to this value to obtain backward-compatible behaviour in
23593 * commands that have been extended to take a MAE_LINK_ENDPOINT_SELECTOR
23594 * argument. New commands that are designed to take such an argument from the
23595 * start will not support this.
23596 */
23597#define MAE_LINK_ENDPOINT_SELECTOR_MAE_LINK_ENDPOINT_COMPAT 0x0
23598#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LBN 0
23599#define MAE_LINK_ENDPOINT_SELECTOR_FLAT_WIDTH 64
23600
23601
23602/***********************************/
23603/* MC_CMD_MAE_GET_CAPS
23604 * Describes capabilities of the MAE (Match-Action Engine)
23605 */
23606#define MC_CMD_MAE_GET_CAPS 0x140
23607#undef MC_CMD_0x140_PRIVILEGE_CTG
23608
23609#define MC_CMD_0x140_PRIVILEGE_CTG SRIOV_CTG_GENERAL
23610
23611/* MC_CMD_MAE_GET_CAPS_IN msgrequest */
23612#define MC_CMD_MAE_GET_CAPS_IN_LEN 0
23613
23614/* MC_CMD_MAE_GET_CAPS_OUT msgresponse */
23615#define MC_CMD_MAE_GET_CAPS_OUT_LEN 52
23616/* The number of field IDs that the NIC supports. Any field with a ID greater
23617 * than or equal to the value returned in this field must be treated as having
23618 * a support level of MAE_FIELD_UNSUPPORTED in all requests.
23619 */
23620#define MC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_OFST 0
23621#define MC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_LEN 4
23622#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
23623#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
23624#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_OFST 4
23625#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_LBN 0
23626#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
23627#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_OFST 4
23628#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_LBN 1
23629#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
23630#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_OFST 4
23631#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_LBN 2
23632#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
23633#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_OFST 4
23634#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_LBN 3
23635#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
23636/* Deprecated alias for AR_COUNTERS. */
23637#define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_OFST 8
23638#define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_LEN 4
23639/* The total number of AR counters available to allocate. */
23640#define MC_CMD_MAE_GET_CAPS_OUT_AR_COUNTERS_OFST 8
23641#define MC_CMD_MAE_GET_CAPS_OUT_AR_COUNTERS_LEN 4
23642/* The total number of counters lists available to allocate. A value of zero
23643 * indicates that counter lists are not supported by the NIC. (But single
23644 * counters may still be.)
23645 */
23646#define MC_CMD_MAE_GET_CAPS_OUT_COUNTER_LISTS_OFST 12
23647#define MC_CMD_MAE_GET_CAPS_OUT_COUNTER_LISTS_LEN 4
23648/* The total number of encap header structures available to allocate. */
23649#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_HEADER_LIMIT_OFST 16
23650#define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_HEADER_LIMIT_LEN 4
23651/* Reserved. Should be zero. */
23652#define MC_CMD_MAE_GET_CAPS_OUT_RSVD_OFST 20
23653#define MC_CMD_MAE_GET_CAPS_OUT_RSVD_LEN 4
23654/* The total number of action sets available to allocate. */
23655#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SETS_OFST 24
23656#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SETS_LEN 4
23657/* The total number of action set lists available to allocate. */
23658#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SET_LISTS_OFST 28
23659#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SET_LISTS_LEN 4
23660/* The total number of outer rules available to allocate. */
23661#define MC_CMD_MAE_GET_CAPS_OUT_OUTER_RULES_OFST 32
23662#define MC_CMD_MAE_GET_CAPS_OUT_OUTER_RULES_LEN 4
23663/* The total number of action rules available to allocate. */
23664#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_RULES_OFST 36
23665#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_RULES_LEN 4
23666/* The number of priorities available for ACTION_RULE filters. It is invalid to
23667 * install a MATCH_ACTION filter with a priority number >= ACTION_PRIOS.
23668 */
23669#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_PRIOS_OFST 40
23670#define MC_CMD_MAE_GET_CAPS_OUT_ACTION_PRIOS_LEN 4
23671/* The number of priorities available for OUTER_RULE filters. It is invalid to
23672 * install an OUTER_RULE filter with a priority number >= OUTER_PRIOS.
23673 */
23674#define MC_CMD_MAE_GET_CAPS_OUT_OUTER_PRIOS_OFST 44
23675#define MC_CMD_MAE_GET_CAPS_OUT_OUTER_PRIOS_LEN 4
23676/* MAE API major version. Currently 1. If this field is not present in the
23677 * response (i.e. response shorter than 384 bits), then its value is zero. If
23678 * the value does not match the client's expectations, the client should raise
23679 * a fatal error.
23680 */
23681#define MC_CMD_MAE_GET_CAPS_OUT_API_VER_OFST 48
23682#define MC_CMD_MAE_GET_CAPS_OUT_API_VER_LEN 4
23683
23684/* MC_CMD_MAE_GET_CAPS_V2_OUT msgresponse */
23685#define MC_CMD_MAE_GET_CAPS_V2_OUT_LEN 60
23686/* The number of field IDs that the NIC supports. Any field with a ID greater
23687 * than or equal to the value returned in this field must be treated as having
23688 * a support level of MAE_FIELD_UNSUPPORTED in all requests.
23689 */
23690#define MC_CMD_MAE_GET_CAPS_V2_OUT_MATCH_FIELD_COUNT_OFST 0
23691#define MC_CMD_MAE_GET_CAPS_V2_OUT_MATCH_FIELD_COUNT_LEN 4
23692#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
23693#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
23694#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_OFST 4
23695#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_LBN 0
23696#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
23697#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_NVGRE_OFST 4
23698#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_NVGRE_LBN 1
23699#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
23700#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_GENEVE_OFST 4
23701#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_GENEVE_LBN 2
23702#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
23703#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_L2GRE_OFST 4
23704#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_L2GRE_LBN 3
23705#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
23706/* Deprecated alias for AR_COUNTERS. */
23707#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTERS_OFST 8
23708#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTERS_LEN 4
23709/* The total number of AR counters available to allocate. */
23710#define MC_CMD_MAE_GET_CAPS_V2_OUT_AR_COUNTERS_OFST 8
23711#define MC_CMD_MAE_GET_CAPS_V2_OUT_AR_COUNTERS_LEN 4
23712/* The total number of counters lists available to allocate. A value of zero
23713 * indicates that counter lists are not supported by the NIC. (But single
23714 * counters may still be.)
23715 */
23716#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_LISTS_OFST 12
23717#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_LISTS_LEN 4
23718/* The total number of encap header structures available to allocate. */
23719#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_HEADER_LIMIT_OFST 16
23720#define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_HEADER_LIMIT_LEN 4
23721/* Reserved. Should be zero. */
23722#define MC_CMD_MAE_GET_CAPS_V2_OUT_RSVD_OFST 20
23723#define MC_CMD_MAE_GET_CAPS_V2_OUT_RSVD_LEN 4
23724/* The total number of action sets available to allocate. */
23725#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SETS_OFST 24
23726#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SETS_LEN 4
23727/* The total number of action set lists available to allocate. */
23728#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SET_LISTS_OFST 28
23729#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SET_LISTS_LEN 4
23730/* The total number of outer rules available to allocate. */
23731#define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_RULES_OFST 32
23732#define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_RULES_LEN 4
23733/* The total number of action rules available to allocate. */
23734#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_RULES_OFST 36
23735#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_RULES_LEN 4
23736/* The number of priorities available for ACTION_RULE filters. It is invalid to
23737 * install a MATCH_ACTION filter with a priority number >= ACTION_PRIOS.
23738 */
23739#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_PRIOS_OFST 40
23740#define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_PRIOS_LEN 4
23741/* The number of priorities available for OUTER_RULE filters. It is invalid to
23742 * install an OUTER_RULE filter with a priority number >= OUTER_PRIOS.
23743 */
23744#define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_PRIOS_OFST 44
23745#define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_PRIOS_LEN 4
23746/* MAE API major version. Currently 1. If this field is not present in the
23747 * response (i.e. response shorter than 384 bits), then its value is zero. If
23748 * the value does not match the client's expectations, the client should raise
23749 * a fatal error.
23750 */
23751#define MC_CMD_MAE_GET_CAPS_V2_OUT_API_VER_OFST 48
23752#define MC_CMD_MAE_GET_CAPS_V2_OUT_API_VER_LEN 4
23753/* Mask of supported counter types. Each bit position corresponds to a value of
23754 * the MAE_COUNTER_TYPE enum. If this field is missing (i.e. V1 response),
23755 * clients must assume that only AR counters are supported (i.e.
23756 * COUNTER_TYPES_SUPPORTED==0x1). See also
23757 * MC_CMD_MAE_COUNTERS_STREAM_START/COUNTER_TYPES_MASK.
23758 */
23759#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_TYPES_SUPPORTED_OFST 52
23760#define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_TYPES_SUPPORTED_LEN 4
23761/* The total number of conntrack counters available to allocate. */
23762#define MC_CMD_MAE_GET_CAPS_V2_OUT_CT_COUNTERS_OFST 56
23763#define MC_CMD_MAE_GET_CAPS_V2_OUT_CT_COUNTERS_LEN 4
23764
23765/* MC_CMD_MAE_GET_CAPS_V3_OUT msgresponse */
23766#define MC_CMD_MAE_GET_CAPS_V3_OUT_LEN 64
23767/* The number of field IDs that the NIC supports. Any field with a ID greater
23768 * than or equal to the value returned in this field must be treated as having
23769 * a support level of MAE_FIELD_UNSUPPORTED in all requests.
23770 */
23771#define MC_CMD_MAE_GET_CAPS_V3_OUT_MATCH_FIELD_COUNT_OFST 0
23772#define MC_CMD_MAE_GET_CAPS_V3_OUT_MATCH_FIELD_COUNT_LEN 4
23773#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
23774#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
23775#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_OFST 4
23776#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_LBN 0
23777#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_WIDTH 1
23778#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_NVGRE_OFST 4
23779#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_NVGRE_LBN 1
23780#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_NVGRE_WIDTH 1
23781#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_GENEVE_OFST 4
23782#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_GENEVE_LBN 2
23783#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_GENEVE_WIDTH 1
23784#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_L2GRE_OFST 4
23785#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_L2GRE_LBN 3
23786#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_L2GRE_WIDTH 1
23787/* Deprecated alias for AR_COUNTERS. */
23788#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTERS_OFST 8
23789#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTERS_LEN 4
23790/* The total number of AR counters available to allocate. */
23791#define MC_CMD_MAE_GET_CAPS_V3_OUT_AR_COUNTERS_OFST 8
23792#define MC_CMD_MAE_GET_CAPS_V3_OUT_AR_COUNTERS_LEN 4
23793/* The total number of counters lists available to allocate. A value of zero
23794 * indicates that counter lists are not supported by the NIC. (But single
23795 * counters may still be.)
23796 */
23797#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_LISTS_OFST 12
23798#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_LISTS_LEN 4
23799/* The total number of encap header structures available to allocate. */
23800#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_HEADER_LIMIT_OFST 16
23801#define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_HEADER_LIMIT_LEN 4
23802/* Reserved. Should be zero. */
23803#define MC_CMD_MAE_GET_CAPS_V3_OUT_RSVD_OFST 20
23804#define MC_CMD_MAE_GET_CAPS_V3_OUT_RSVD_LEN 4
23805/* The total number of action sets available to allocate. */
23806#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SETS_OFST 24
23807#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SETS_LEN 4
23808/* The total number of action set lists available to allocate. */
23809#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SET_LISTS_OFST 28
23810#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SET_LISTS_LEN 4
23811/* The total number of outer rules available to allocate. */
23812#define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_RULES_OFST 32
23813#define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_RULES_LEN 4
23814/* The total number of action rules available to allocate. */
23815#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_RULES_OFST 36
23816#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_RULES_LEN 4
23817/* The number of priorities available for ACTION_RULE filters. It is invalid to
23818 * install a MATCH_ACTION filter with a priority number >= ACTION_PRIOS.
23819 */
23820#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_PRIOS_OFST 40
23821#define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_PRIOS_LEN 4
23822/* The number of priorities available for OUTER_RULE filters. It is invalid to
23823 * install an OUTER_RULE filter with a priority number >= OUTER_PRIOS.
23824 */
23825#define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_PRIOS_OFST 44
23826#define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_PRIOS_LEN 4
23827/* MAE API major version. Currently 1. If this field is not present in the
23828 * response (i.e. response shorter than 384 bits), then its value is zero. If
23829 * the value does not match the client's expectations, the client should raise
23830 * a fatal error.
23831 */
23832#define MC_CMD_MAE_GET_CAPS_V3_OUT_API_VER_OFST 48
23833#define MC_CMD_MAE_GET_CAPS_V3_OUT_API_VER_LEN 4
23834/* Mask of supported counter types. Each bit position corresponds to a value of
23835 * the MAE_COUNTER_TYPE enum. If this field is missing (i.e. V1 response),
23836 * clients must assume that only AR counters are supported (i.e.
23837 * COUNTER_TYPES_SUPPORTED==0x1). See also
23838 * MC_CMD_MAE_COUNTERS_STREAM_START/COUNTER_TYPES_MASK.
23839 */
23840#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_TYPES_SUPPORTED_OFST 52
23841#define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_TYPES_SUPPORTED_LEN 4
23842/* The total number of conntrack counters available to allocate. */
23843#define MC_CMD_MAE_GET_CAPS_V3_OUT_CT_COUNTERS_OFST 56
23844#define MC_CMD_MAE_GET_CAPS_V3_OUT_CT_COUNTERS_LEN 4
23845/* The total number of Outer Rule counters available to allocate. */
23846#define MC_CMD_MAE_GET_CAPS_V3_OUT_OR_COUNTERS_OFST 60
23847#define MC_CMD_MAE_GET_CAPS_V3_OUT_OR_COUNTERS_LEN 4
23848
23849
23850/***********************************/
23851/* MC_CMD_MAE_GET_AR_CAPS
23852 * Get a level of support for match fields when used in match-action rules
23853 */
23854#define MC_CMD_MAE_GET_AR_CAPS 0x141
23855#undef MC_CMD_0x141_PRIVILEGE_CTG
23856
23857#define MC_CMD_0x141_PRIVILEGE_CTG SRIOV_CTG_MAE
23858
23859/* MC_CMD_MAE_GET_AR_CAPS_IN msgrequest */
23860#define MC_CMD_MAE_GET_AR_CAPS_IN_LEN 0
23861
23862/* MC_CMD_MAE_GET_AR_CAPS_OUT msgresponse */
23863#define MC_CMD_MAE_GET_AR_CAPS_OUT_LENMIN 4
23864#define MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX 252
23865#define MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2 1020
23866#define MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(num) (4+4*(num))
23867#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)
23868/* Number of fields actually returned in FIELD_FLAGS. */
23869#define MC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_OFST 0
23870#define MC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_LEN 4
23871/* Array of values indicating the NIC's support for a given field, indexed by
23872 * field id. The driver must ensure space for
23873 * MC_CMD_MAE_GET_CAPS.MATCH_FIELD_COUNT entries in the array..
23874 */
23875#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_OFST 4
23876#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_LEN 4
23877#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MINNUM 0
23878#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MAXNUM 62
23879#define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MAXNUM_MCDI2 254
23880
23881
23882/***********************************/
23883/* MC_CMD_MAE_GET_OR_CAPS
23884 * Get a level of support for fields used in outer rule keys.
23885 */
23886#define MC_CMD_MAE_GET_OR_CAPS 0x142
23887#undef MC_CMD_0x142_PRIVILEGE_CTG
23888
23889#define MC_CMD_0x142_PRIVILEGE_CTG SRIOV_CTG_MAE
23890
23891/* MC_CMD_MAE_GET_OR_CAPS_IN msgrequest */
23892#define MC_CMD_MAE_GET_OR_CAPS_IN_LEN 0
23893
23894/* MC_CMD_MAE_GET_OR_CAPS_OUT msgresponse */
23895#define MC_CMD_MAE_GET_OR_CAPS_OUT_LENMIN 4
23896#define MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX 252
23897#define MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2 1020
23898#define MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(num) (4+4*(num))
23899#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)
23900/* Number of fields actually returned in FIELD_FLAGS. */
23901#define MC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_OFST 0
23902#define MC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_LEN 4
23903/* Same semantics as MC_CMD_MAE_GET_AR_CAPS.MAE_FIELD_FLAGS */
23904#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_OFST 4
23905#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_LEN 4
23906#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MINNUM 0
23907#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MAXNUM 62
23908#define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MAXNUM_MCDI2 254
23909
23910
23911/***********************************/
23912/* MC_CMD_MAE_COUNTER_ALLOC
23913 * Allocate match-action-engine counters, which can be referenced in various
23914 * tables.
23915 */
23916#define MC_CMD_MAE_COUNTER_ALLOC 0x143
23917#undef MC_CMD_0x143_PRIVILEGE_CTG
23918
23919#define MC_CMD_0x143_PRIVILEGE_CTG SRIOV_CTG_MAE
23920
23921/* MC_CMD_MAE_COUNTER_ALLOC_IN msgrequest: Using this is equivalent to using V2
23922 * with COUNTER_TYPE=AR.
23923 */
23924#define MC_CMD_MAE_COUNTER_ALLOC_IN_LEN 4
23925/* The number of counters that the driver would like allocated */
23926#define MC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_OFST 0
23927#define MC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_LEN 4
23928
23929/* MC_CMD_MAE_COUNTER_ALLOC_V2_IN msgrequest */
23930#define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_LEN 8
23931/* The number of counters that the driver would like allocated */
23932#define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_REQUESTED_COUNT_OFST 0
23933#define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_REQUESTED_COUNT_LEN 4
23934/* Which type of counter to allocate. */
23935#define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_COUNTER_TYPE_OFST 4
23936#define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_COUNTER_TYPE_LEN 4
23937/* Enum values, see field(s): */
23938/* MAE_COUNTER_TYPE */
23939
23940/* MC_CMD_MAE_COUNTER_ALLOC_OUT msgresponse */
23941#define MC_CMD_MAE_COUNTER_ALLOC_OUT_LENMIN 12
23942#define MC_CMD_MAE_COUNTER_ALLOC_OUT_LENMAX 252
23943#define MC_CMD_MAE_COUNTER_ALLOC_OUT_LENMAX_MCDI2 1020
23944#define MC_CMD_MAE_COUNTER_ALLOC_OUT_LEN(num) (8+4*(num))
23945#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NUM(len) (((len)-8)/4)
23946/* Generation count. Packets with generation count >= GENERATION_COUNT will
23947 * contain valid counter values for counter IDs allocated in this call, unless
23948 * the counter values are zero and zero squash is enabled. Note that there is
23949 * an independent GENERATION_COUNT object per counter type, and that generation
23950 * counts wrap from 0xffffffff to 1.
23951 */
23952#define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_OFST 0
23953#define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_LEN 4
23954/* enum: Generation counter 0 is reserved and unused. */
23955#define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_INVALID 0x0
23956/* The number of counter IDs that the NIC allocated. It is never less than 1;
23957 * failure to allocate a single counter will cause an error to be returned. It
23958 * is never greater than REQUESTED_COUNT, but may be less.
23959 */
23960#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_OFST 4
23961#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_LEN 4
23962/* An array containing the IDs for the counters allocated. */
23963#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_OFST 8
23964#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4
23965#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 1
23966#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 61
23967#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM_MCDI2 253
23968/* enum: A counter ID that is guaranteed never to represent a real counter */
23969#define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NULL 0xffffffff
23970/* Other enum values, see field(s): */
23971/* MAE_COUNTER_ID */
23972
23973
23974/***********************************/
23975/* MC_CMD_MAE_COUNTER_FREE
23976 * Free match-action-engine counters
23977 */
23978#define MC_CMD_MAE_COUNTER_FREE 0x144
23979#undef MC_CMD_0x144_PRIVILEGE_CTG
23980
23981#define MC_CMD_0x144_PRIVILEGE_CTG SRIOV_CTG_MAE
23982
23983/* MC_CMD_MAE_COUNTER_FREE_IN msgrequest: Using this is equivalent to using V2
23984 * with COUNTER_TYPE=AR.
23985 */
23986#define MC_CMD_MAE_COUNTER_FREE_IN_LENMIN 8
23987#define MC_CMD_MAE_COUNTER_FREE_IN_LENMAX 132
23988#define MC_CMD_MAE_COUNTER_FREE_IN_LENMAX_MCDI2 132
23989#define MC_CMD_MAE_COUNTER_FREE_IN_LEN(num) (4+4*(num))
23990#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_NUM(len) (((len)-4)/4)
23991/* The number of counter IDs to be freed. */
23992#define MC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_OFST 0
23993#define MC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_LEN 4
23994/* An array containing the counter IDs to be freed. */
23995#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_OFST 4
23996#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_LEN 4
23997#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MINNUM 1
23998#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MAXNUM 32
23999#define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MAXNUM_MCDI2 32
24000
24001/* MC_CMD_MAE_COUNTER_FREE_V2_IN msgrequest */
24002#define MC_CMD_MAE_COUNTER_FREE_V2_IN_LEN 136
24003/* The number of counter IDs to be freed. */
24004#define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_ID_COUNT_OFST 0
24005#define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_ID_COUNT_LEN 4
24006/* An array containing the counter IDs to be freed. */
24007#define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_OFST 4
24008#define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_LEN 4
24009#define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_MINNUM 1
24010#define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_MAXNUM 32
24011#define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_MAXNUM_MCDI2 32
24012/* Which type of counter to free. */
24013#define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_TYPE_OFST 132
24014#define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_TYPE_LEN 4
24015/* Enum values, see field(s): */
24016/* MAE_COUNTER_TYPE */
24017
24018/* MC_CMD_MAE_COUNTER_FREE_OUT msgresponse */
24019#define MC_CMD_MAE_COUNTER_FREE_OUT_LENMIN 12
24020#define MC_CMD_MAE_COUNTER_FREE_OUT_LENMAX 136
24021#define MC_CMD_MAE_COUNTER_FREE_OUT_LENMAX_MCDI2 136
24022#define MC_CMD_MAE_COUNTER_FREE_OUT_LEN(num) (8+4*(num))
24023#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_NUM(len) (((len)-8)/4)
24024/* Generation count. A packet with generation count == GENERATION_COUNT will
24025 * contain the final values for these counter IDs, unless the counter values
24026 * are zero and zero squash is enabled. Note that the GENERATION_COUNT value is
24027 * specific to the COUNTER_TYPE (IDENTIFIER field in packet header). Receiving
24028 * a packet with generation count > GENERATION_COUNT guarantees that no more
24029 * values will be written for these counters. If values for these counter IDs
24030 * are present, the counter ID has been reallocated. A counter ID will not be
24031 * reallocated within a single read cycle as this would merge increments from
24032 * the 'old' and 'new' counters. GENERATION_COUNT_INVALID is reserved and
24033 * unused.
24034 */
24035#define MC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_OFST 0
24036#define MC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_LEN 4
24037/* The number of counter IDs actually freed. It is never less than 1; failure
24038 * to free a single counter will cause an error to be returned. It is never
24039 * greater than the number that were requested to be freed, but may be less if
24040 * counters could not be freed.
24041 */
24042#define MC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_OFST 4
24043#define MC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_LEN 4
24044/* An array containing the IDs for the counters to that were freed. Note,
24045 * failure to free a counter can only occur on incorrect driver behaviour, so
24046 * asserting that the expected counters were freed is reasonable. When
24047 * debugging, attempting to free a single counter at a time will provide a
24048 * reason for the failure to free said counter.
24049 */
24050#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_OFST 8
24051#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_LEN 4
24052#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_MINNUM 1
24053#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_MAXNUM 32
24054#define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_MAXNUM_MCDI2 32
24055
24056
24057/***********************************/
24058/* MC_CMD_MAE_COUNTERS_STREAM_START
24059 * Start streaming counter values, specifying an RxQ to deliver packets to.
24060 * Counters allocated to the calling function will be written in a round robin
24061 * at a fixed cycle rate, assuming sufficient credits are available. The driver
24062 * may cause the counter values to be written at a slower rate by constraining
24063 * the availability of credits. Note that if the driver wishes to deliver
24064 * packets to a different queue, it must call MAE_COUNTERS_STREAM_STOP to stop
24065 * delivering packets to the current queue first.
24066 */
24067#define MC_CMD_MAE_COUNTERS_STREAM_START 0x151
24068#undef MC_CMD_0x151_PRIVILEGE_CTG
24069
24070#define MC_CMD_0x151_PRIVILEGE_CTG SRIOV_CTG_MAE
24071
24072/* MC_CMD_MAE_COUNTERS_STREAM_START_IN msgrequest: Using V1 is equivalent to V2
24073 * with COUNTER_TYPES_MASK=0x1 (i.e. AR counters only).
24074 */
24075#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_LEN 8
24076/* The RxQ to write packets to. */
24077#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_QID_OFST 0
24078#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_QID_LEN 2
24079/* Maximum size in bytes of packets that may be written to the RxQ. */
24080#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_PACKET_SIZE_OFST 2
24081#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_PACKET_SIZE_LEN 2
24082/* Optional flags. */
24083#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_OFST 4
24084#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_LEN 4
24085#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_OFST 4
24086#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_LBN 0
24087#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_WIDTH 1
24088#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_OFST 4
24089#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_LBN 1
24090#define MC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_WIDTH 1
24091
24092/* MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN msgrequest */
24093#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_LEN 12
24094/* The RxQ to write packets to. */
24095#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_QID_OFST 0
24096#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_QID_LEN 2
24097/* Maximum size in bytes of packets that may be written to the RxQ. */
24098#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_PACKET_SIZE_OFST 2
24099#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_PACKET_SIZE_LEN 2
24100/* Optional flags. */
24101#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_FLAGS_OFST 4
24102#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_FLAGS_LEN 4
24103#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_OFST 4
24104#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_LBN 0
24105#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_WIDTH 1
24106#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_STALL_EN_OFST 4
24107#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_STALL_EN_LBN 1
24108#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_STALL_EN_WIDTH 1
24109/* Mask of which counter types should be reported. Each bit position
24110 * corresponds to a value of the MAE_COUNTER_TYPE enum. For example a value of
24111 * 0x3 requests both AR and CT counters. A value of zero is invalid. Counter
24112 * types not selected by the mask value won't be included in the stream. If a
24113 * client wishes to change which counter types are reported, it must first call
24114 * MAE_COUNTERS_STREAM_STOP, then restart it with the new mask value.
24115 * Requesting a counter type which isn't supported by firmware (reported in
24116 * MC_CMD_MAE_GET_CAPS/COUNTER_TYPES_SUPPORTED) will result in ENOTSUP.
24117 */
24118#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_TYPES_MASK_OFST 8
24119#define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_TYPES_MASK_LEN 4
24120
24121/* MC_CMD_MAE_COUNTERS_STREAM_START_OUT msgresponse */
24122#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_LEN 4
24123#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_OFST 0
24124#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_LEN 4
24125#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_OFST 0
24126#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_LBN 0
24127#define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_WIDTH 1
24128
24129
24130/***********************************/
24131/* MC_CMD_MAE_COUNTERS_STREAM_STOP
24132 * Stop streaming counter values to the specified RxQ.
24133 */
24134#define MC_CMD_MAE_COUNTERS_STREAM_STOP 0x152
24135#undef MC_CMD_0x152_PRIVILEGE_CTG
24136
24137#define MC_CMD_0x152_PRIVILEGE_CTG SRIOV_CTG_MAE
24138
24139/* MC_CMD_MAE_COUNTERS_STREAM_STOP_IN msgrequest */
24140#define MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_LEN 2
24141/* The RxQ to stop writing packets to. */
24142#define MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_QID_OFST 0
24143#define MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_QID_LEN 2
24144
24145/* MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT msgresponse */
24146#define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_LEN 4
24147/* Generation count for AR counters. The final set of AR counter values will be
24148 * written out in packets with count == GENERATION_COUNT. An empty packet with
24149 * count > GENERATION_COUNT indicates that no more counter values of this type
24150 * will be written to this stream. GENERATION_COUNT_INVALID is reserved and
24151 * unused.
24152 */
24153#define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_OFST 0
24154#define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_LEN 4
24155
24156/* MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT msgresponse */
24157#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LENMIN 4
24158#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LENMAX 32
24159#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LENMAX_MCDI2 32
24160#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LEN(num) (0+4*(num))
24161#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_NUM(len) (((len)-0)/4)
24162/* Array of generation counts, indexed by MAE_COUNTER_TYPE. Note that since
24163 * MAE_COUNTER_TYPE_AR==0, this response is backwards-compatible with V1. The
24164 * final set of counter values will be written out in packets with count ==
24165 * GENERATION_COUNT. An empty packet with count > GENERATION_COUNT indicates
24166 * that no more counter values of this type will be written to this stream.
24167 * GENERATION_COUNT_INVALID is reserved and unused.
24168 */
24169#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_OFST 0
24170#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_LEN 4
24171#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_MINNUM 1
24172#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_MAXNUM 8
24173#define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_MAXNUM_MCDI2 8
24174
24175
24176/***********************************/
24177/* MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS
24178 * Give a number of credits to the packetiser. Each credit received allows the
24179 * MC to write one packet to the RxQ, therefore for each credit the driver must
24180 * have written sufficient descriptors for a packet of length
24181 * MAE_COUNTERS_PACKETISER_STREAM_START/PACKET_SIZE and rung the doorbell.
24182 */
24183#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153
24184#undef MC_CMD_0x153_PRIVILEGE_CTG
24185
24186#define MC_CMD_0x153_PRIVILEGE_CTG SRIOV_CTG_MAE
24187
24188/* MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN msgrequest */
24189#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_LEN 4
24190/* Number of credits to give to the packetiser. */
24191#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_OFST 0
24192#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_LEN 4
24193
24194/* MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_OUT msgresponse */
24195#define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_OUT_LEN 0
24196
24197
24198/***********************************/
24199/* MC_CMD_MAE_ENCAP_HEADER_ALLOC
24200 * Allocate an encapsulation header to be used in an Action Rule response. The
24201 * header must be constructed as a valid packet with 0-length payload.
24202 * Specifically, the L3/L4 lengths & checksums will only be incrementally fixed
24203 * by the NIC, rather than recomputed entirely. Currently only IPv4, IPv6 and
24204 * UDP are supported. If the maximum number of headers have already been
24205 * allocated then the command will fail with MC_CMD_ERR_ENOSPC.
24206 */
24207#define MC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148
24208#undef MC_CMD_0x148_PRIVILEGE_CTG
24209
24210#define MC_CMD_0x148_PRIVILEGE_CTG SRIOV_CTG_MAE
24211
24212/* MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN msgrequest */
24213#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMIN 4
24214#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMAX 252
24215#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMAX_MCDI2 1020
24216#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LEN(num) (4+1*(num))
24217#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_NUM(len) (((len)-4)/1)
24218#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_OFST 0
24219#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_LEN 4
24220#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_OFST 4
24221#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_LEN 1
24222#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MINNUM 0
24223#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MAXNUM 248
24224#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MAXNUM_MCDI2 1016
24225
24226/* MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT msgresponse */
24227#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_LEN 4
24228#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_OFST 0
24229#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_LEN 4
24230/* enum: An encap metadata ID that is guaranteed never to represent real encap
24231 * metadata
24232 */
24233#define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_NULL 0xffffffff
24234
24235
24236/***********************************/
24237/* MC_CMD_MAE_ENCAP_HEADER_UPDATE
24238 * Update encap action metadata. See comments for MAE_ENCAP_HEADER_ALLOC.
24239 */
24240#define MC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149
24241#undef MC_CMD_0x149_PRIVILEGE_CTG
24242
24243#define MC_CMD_0x149_PRIVILEGE_CTG SRIOV_CTG_MAE
24244
24245/* MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN msgrequest */
24246#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LENMIN 8
24247#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LENMAX 252
24248#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LENMAX_MCDI2 1020
24249#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LEN(num) (8+1*(num))
24250#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_NUM(len) (((len)-8)/1)
24251#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_OFST 0
24252#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_LEN 4
24253#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_OFST 4
24254#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_LEN 4
24255#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_OFST 8
24256#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_LEN 1
24257#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MINNUM 0
24258#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MAXNUM 244
24259#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MAXNUM_MCDI2 1012
24260
24261/* MC_CMD_MAE_ENCAP_HEADER_UPDATE_OUT msgresponse */
24262#define MC_CMD_MAE_ENCAP_HEADER_UPDATE_OUT_LEN 0
24263
24264
24265/***********************************/
24266/* MC_CMD_MAE_ENCAP_HEADER_FREE
24267 * Free encap action metadata
24268 */
24269#define MC_CMD_MAE_ENCAP_HEADER_FREE 0x14a
24270#undef MC_CMD_0x14a_PRIVILEGE_CTG
24271
24272#define MC_CMD_0x14a_PRIVILEGE_CTG SRIOV_CTG_MAE
24273
24274/* MC_CMD_MAE_ENCAP_HEADER_FREE_IN msgrequest */
24275#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMIN 4
24276#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMAX 128
24277#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMAX_MCDI2 128
24278#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LEN(num) (0+4*(num))
24279#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_NUM(len) (((len)-0)/4)
24280/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
24281#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_OFST 0
24282#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_LEN 4
24283#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_MINNUM 1
24284#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_MAXNUM 32
24285#define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_MAXNUM_MCDI2 32
24286
24287/* MC_CMD_MAE_ENCAP_HEADER_FREE_OUT msgresponse */
24288#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMIN 4
24289#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMAX 128
24290#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMAX_MCDI2 128
24291#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LEN(num) (0+4*(num))
24292#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_NUM(len) (((len)-0)/4)
24293/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
24294#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_OFST 0
24295#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_LEN 4
24296#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_MINNUM 1
24297#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_MAXNUM 32
24298#define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_MAXNUM_MCDI2 32
24299
24300
24301/***********************************/
24302/* MC_CMD_MAE_MAC_ADDR_ALLOC
24303 * Allocate MAC address. Hardware implementations have MAC addresses programmed
24304 * into an indirection table, and clients should take care not to allocate the
24305 * same MAC address twice (but instead reuse its ID). If the maximum number of
24306 * MAC addresses have already been allocated then the command will fail with
24307 * MC_CMD_ERR_ENOSPC.
24308 */
24309#define MC_CMD_MAE_MAC_ADDR_ALLOC 0x15e
24310#undef MC_CMD_0x15e_PRIVILEGE_CTG
24311
24312#define MC_CMD_0x15e_PRIVILEGE_CTG SRIOV_CTG_MAE
24313
24314/* MC_CMD_MAE_MAC_ADDR_ALLOC_IN msgrequest */
24315#define MC_CMD_MAE_MAC_ADDR_ALLOC_IN_LEN 6
24316/* MAC address as bytes in network order. */
24317#define MC_CMD_MAE_MAC_ADDR_ALLOC_IN_MAC_ADDR_OFST 0
24318#define MC_CMD_MAE_MAC_ADDR_ALLOC_IN_MAC_ADDR_LEN 6
24319
24320/* MC_CMD_MAE_MAC_ADDR_ALLOC_OUT msgresponse */
24321#define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_LEN 4
24322#define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_OFST 0
24323#define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_LEN 4
24324/* enum: An MAC address ID that is guaranteed never to represent a real MAC
24325 * address.
24326 */
24327#define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL 0xffffffff
24328
24329
24330/***********************************/
24331/* MC_CMD_MAE_MAC_ADDR_FREE
24332 * Free MAC address.
24333 */
24334#define MC_CMD_MAE_MAC_ADDR_FREE 0x15f
24335#undef MC_CMD_0x15f_PRIVILEGE_CTG
24336
24337#define MC_CMD_0x15f_PRIVILEGE_CTG SRIOV_CTG_MAE
24338
24339/* MC_CMD_MAE_MAC_ADDR_FREE_IN msgrequest */
24340#define MC_CMD_MAE_MAC_ADDR_FREE_IN_LENMIN 4
24341#define MC_CMD_MAE_MAC_ADDR_FREE_IN_LENMAX 128
24342#define MC_CMD_MAE_MAC_ADDR_FREE_IN_LENMAX_MCDI2 128
24343#define MC_CMD_MAE_MAC_ADDR_FREE_IN_LEN(num) (0+4*(num))
24344#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_NUM(len) (((len)-0)/4)
24345/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
24346#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_OFST 0
24347#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_LEN 4
24348#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_MINNUM 1
24349#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_MAXNUM 32
24350#define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_MAXNUM_MCDI2 32
24351
24352/* MC_CMD_MAE_MAC_ADDR_FREE_OUT msgresponse */
24353#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMIN 4
24354#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMAX 128
24355#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMAX_MCDI2 128
24356#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LEN(num) (0+4*(num))
24357#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_NUM(len) (((len)-0)/4)
24358/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
24359#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_OFST 0
24360#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_LEN 4
24361#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_MINNUM 1
24362#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_MAXNUM 32
24363#define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_MAXNUM_MCDI2 32
24364
24365
24366/***********************************/
24367/* MC_CMD_MAE_ACTION_SET_ALLOC
24368 * Allocate an action set, which can be referenced either in response to an
24369 * Action Rule, or as part of an Action Set List. If the maxmimum number of
24370 * action sets have already been allocated then the command will fail with
24371 * MC_CMD_ERR_ENOSPC.
24372 */
24373#define MC_CMD_MAE_ACTION_SET_ALLOC 0x14d
24374#undef MC_CMD_0x14d_PRIVILEGE_CTG
24375
24376#define MC_CMD_0x14d_PRIVILEGE_CTG SRIOV_CTG_MAE
24377
24378/* MC_CMD_MAE_ACTION_SET_ALLOC_IN msgrequest */
24379#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN 44
24380#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_OFST 0
24381#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_LEN 4
24382#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_OFST 0
24383#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_LBN 0
24384#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_WIDTH 2
24385#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_OFST 0
24386#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_LBN 4
24387#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_WIDTH 2
24388#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_OFST 0
24389#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_LBN 8
24390#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_WIDTH 1
24391#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_OFST 0
24392#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_LBN 9
24393#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_WIDTH 1
24394#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_OFST 0
24395#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_LBN 10
24396#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_WIDTH 1
24397#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_OFST 0
24398#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_LBN 11
24399#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_WIDTH 1
24400#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_OFST 0
24401#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_LBN 12
24402#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_WIDTH 1
24403#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_OFST 0
24404#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_LBN 13
24405#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_WIDTH 1
24406#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_OFST 0
24407#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_LBN 14
24408#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
24409#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_C_PL_OFST 0
24410#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_C_PL_LBN 15
24411#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_C_PL_WIDTH 1
24412#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_D_PL_OFST 0
24413#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_D_PL_LBN 16
24414#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_D_PL_WIDTH 1
24415#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_OFST 0
24416#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_LBN 17
24417#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_WIDTH 1
24418#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_NET_CHAN_OFST 0
24419#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_NET_CHAN_LBN 18
24420#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_NET_CHAN_WIDTH 1
24421#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_PLUGIN_OFST 0
24422#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_PLUGIN_LBN 19
24423#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_PLUGIN_WIDTH 1
24424#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_INC_L4_OFST 0
24425#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_INC_L4_LBN 20
24426#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_INC_L4_WIDTH 1
24427/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
24428#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_OFST 4
24429#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_LEN 2
24430/* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */
24431#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE_OFST 6
24432#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE_LEN 2
24433/* If VLAN_PUSH == 2, inner TCI value to be inserted. */
24434#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE_OFST 8
24435#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE_LEN 2
24436/* If VLAN_PUSH == 2, inner TPID value to be inserted. */
24437#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE_OFST 10
24438#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE_LEN 2
24439/* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
24440#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_RSVD_OFST 12
24441#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_RSVD_LEN 4
24442/* Set to ENCAP_HEADER_ID_NULL to request no encap action */
24443#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID_OFST 16
24444#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID_LEN 4
24445/* An m-port selector identifying the m-port that the modified packet should be
24446 * delivered to. Set to MPORT_SELECTOR_NULL to request no delivery of the
24447 * packet.
24448 */
24449#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DELIVER_OFST 20
24450#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DELIVER_LEN 4
24451/* Allows an action set to trigger several counter updates. Set to
24452 * MAE_COUNTER_ID_NULL to request no counter action.
24453 */
24454#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID_OFST 24
24455#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID_LEN 4
24456/* Enum values, see field(s): */
24457/* MAE_COUNTER_ID */
24458/* If a driver only wished to update one counter within this action set, then
24459 * it can supply a COUNTER_ID instead of allocating a single-element counter
24460 * list. The ID must have been allocated with COUNTER_TYPE=AR. This field
24461 * should be set to MAE_COUNTER_ID_NULL if this behaviour is not required. It
24462 * is not valid to supply a non-NULL value for both COUNTER_LIST_ID and
24463 * COUNTER_ID.
24464 */
24465#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_ID_OFST 28
24466#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_ID_LEN 4
24467/* Enum values, see field(s): */
24468/* MAE_COUNTER_ID */
24469#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_VALUE_OFST 32
24470#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_VALUE_LEN 4
24471/* Set to MAC_ID_NULL to request no source MAC replacement. */
24472#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID_OFST 36
24473#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID_LEN 4
24474/* Set to MAC_ID_NULL to request no destination MAC replacement. */
24475#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_OFST 40
24476#define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_LEN 4
24477
24478/* MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN msgrequest: Only supported if
24479 * MAE_ACTION_SET_ALLOC_V2_SUPPORTED is advertised in
24480 * MC_CMD_GET_CAPABILITIES_V7_OUT.
24481 */
24482#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LEN 51
24483#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_OFST 0
24484#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_LEN 4
24485#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_OFST 0
24486#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_LBN 0
24487#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_WIDTH 2
24488#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_OFST 0
24489#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_LBN 4
24490#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_WIDTH 2
24491#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_OFST 0
24492#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_LBN 8
24493#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_WIDTH 1
24494#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_OFST 0
24495#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_LBN 9
24496#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_WIDTH 1
24497#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_OFST 0
24498#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_LBN 10
24499#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_WIDTH 1
24500#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_OFST 0
24501#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_LBN 11
24502#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_WIDTH 1
24503#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_OFST 0
24504#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_LBN 12
24505#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_WIDTH 1
24506#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_OFST 0
24507#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_LBN 13
24508#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_WIDTH 1
24509#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_OFST 0
24510#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_LBN 14
24511#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
24512#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_C_PL_OFST 0
24513#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_C_PL_LBN 15
24514#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_C_PL_WIDTH 1
24515#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_D_PL_OFST 0
24516#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_D_PL_LBN 16
24517#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_D_PL_WIDTH 1
24518#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_OFST 0
24519#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_LBN 17
24520#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_WIDTH 1
24521#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_NET_CHAN_OFST 0
24522#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_NET_CHAN_LBN 18
24523#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_NET_CHAN_WIDTH 1
24524#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_PLUGIN_OFST 0
24525#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_PLUGIN_LBN 19
24526#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_PLUGIN_WIDTH 1
24527#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_INC_L4_OFST 0
24528#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_INC_L4_LBN 20
24529#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_INC_L4_WIDTH 1
24530/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
24531#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_OFST 4
24532#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_LEN 2
24533/* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */
24534#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_OFST 6
24535#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_PROTO_BE_LEN 2
24536/* If VLAN_PUSH == 2, inner TCI value to be inserted. */
24537#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_OFST 8
24538#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_TCI_BE_LEN 2
24539/* If VLAN_PUSH == 2, inner TPID value to be inserted. */
24540#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_OFST 10
24541#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN1_PROTO_BE_LEN 2
24542/* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
24543#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_OFST 12
24544#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_LEN 4
24545/* Set to ENCAP_HEADER_ID_NULL to request no encap action */
24546#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_OFST 16
24547#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_LEN 4
24548/* An m-port selector identifying the m-port that the modified packet should be
24549 * delivered to. Set to MPORT_SELECTOR_NULL to request no delivery of the
24550 * packet.
24551 */
24552#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_OFST 20
24553#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_LEN 4
24554/* Allows an action set to trigger several counter updates. Set to
24555 * MAE_COUNTER_ID_NULL to request no counter action.
24556 */
24557#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_OFST 24
24558#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_LEN 4
24559/* Enum values, see field(s): */
24560/* MAE_COUNTER_ID */
24561/* If a driver only wished to update one counter within this action set, then
24562 * it can supply a COUNTER_ID instead of allocating a single-element counter
24563 * list. The ID must have been allocated with COUNTER_TYPE=AR. This field
24564 * should be set to MAE_COUNTER_ID_NULL if this behaviour is not required. It
24565 * is not valid to supply a non-NULL value for both COUNTER_LIST_ID and
24566 * COUNTER_ID.
24567 */
24568#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_OFST 28
24569#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_LEN 4
24570/* Enum values, see field(s): */
24571/* MAE_COUNTER_ID */
24572#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_OFST 32
24573#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_LEN 4
24574/* Set to MAC_ID_NULL to request no source MAC replacement. */
24575#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_OFST 36
24576#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_LEN 4
24577/* Set to MAC_ID_NULL to request no destination MAC replacement. */
24578#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_OFST 40
24579#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_LEN 4
24580/* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */
24581#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_OFST 44
24582#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_LEN 4
24583/* Actions for modifying the Differentiated Services Code-Point (DSCP) bits
24584 * within IPv4 and IPv6 headers.
24585 */
24586#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_OFST 48
24587#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_CONTROL_LEN 2
24588#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_OFST 48
24589#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_LBN 0
24590#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_WIDTH 1
24591#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_OFST 48
24592#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_LBN 1
24593#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_DECAP_COPY_WIDTH 1
24594#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_OFST 48
24595#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_LBN 2
24596#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_DSCP_WIDTH 1
24597#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_OFST 48
24598#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_LBN 3
24599#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DSCP_VALUE_WIDTH 6
24600/* Actions for modifying the Explicit Congestion Notification (ECN) bits within
24601 * IPv4 and IPv6 headers.
24602 */
24603#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_OFST 50
24604#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_CONTROL_LEN 1
24605#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_OFST 50
24606#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_LBN 0
24607#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_WIDTH 1
24608#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_OFST 50
24609#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_LBN 1
24610#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_DECAP_COPY_WIDTH 1
24611#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_OFST 50
24612#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_LBN 2
24613#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_ECN_WIDTH 1
24614#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_OFST 50
24615#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_LBN 3
24616#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_VALUE_WIDTH 2
24617#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_OFST 50
24618#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_LBN 5
24619#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_0_TO_CE_WIDTH 1
24620#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_OFST 50
24621#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_LBN 6
24622#define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ECN_ECT_1_TO_CE_WIDTH 1
24623
24624/* MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN msgrequest: Only supported if
24625 * MAE_ACTION_SET_ALLOC_V3_SUPPORTED is advertised in
24626 * MC_CMD_GET_CAPABILITIES_V10_OUT.
24627 */
24628#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LEN 53
24629#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAGS_OFST 0
24630#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAGS_LEN 4
24631#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_PUSH_OFST 0
24632#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_PUSH_LBN 0
24633#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_PUSH_WIDTH 2
24634#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_POP_OFST 0
24635#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_POP_LBN 4
24636#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_POP_WIDTH 2
24637#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DECAP_OFST 0
24638#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DECAP_LBN 8
24639#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DECAP_WIDTH 1
24640#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_OFST 0
24641#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_LBN 9
24642#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_WIDTH 1
24643#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAG_OFST 0
24644#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAG_LBN 10
24645#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAG_WIDTH 1
24646#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_NAT_OFST 0
24647#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_NAT_LBN 11
24648#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_NAT_WIDTH 1
24649#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DECR_IP_TTL_OFST 0
24650#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DECR_IP_TTL_LBN 12
24651#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DECR_IP_TTL_WIDTH 1
24652#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_SRC_MPORT_OFST 0
24653#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_SRC_MPORT_LBN 13
24654#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_SRC_MPORT_WIDTH 1
24655#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SUPPRESS_SELF_DELIVERY_OFST 0
24656#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SUPPRESS_SELF_DELIVERY_LBN 14
24657#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SUPPRESS_SELF_DELIVERY_WIDTH 1
24658#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_C_PL_OFST 0
24659#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_C_PL_LBN 15
24660#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_C_PL_WIDTH 1
24661#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_D_PL_OFST 0
24662#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_D_PL_LBN 16
24663#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_D_PL_WIDTH 1
24664#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_OFST 0
24665#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_LBN 17
24666#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_WIDTH 1
24667#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_NET_CHAN_OFST 0
24668#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_NET_CHAN_LBN 18
24669#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_NET_CHAN_WIDTH 1
24670#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_PLUGIN_OFST 0
24671#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_PLUGIN_LBN 19
24672#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_PLUGIN_WIDTH 1
24673#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_INC_L4_OFST 0
24674#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_INC_L4_LBN 20
24675#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_INC_L4_WIDTH 1
24676/* If VLAN_PUSH >= 1, TCI value to be inserted as outermost VLAN. */
24677#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN0_TCI_BE_OFST 4
24678#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN0_TCI_BE_LEN 2
24679/* If VLAN_PUSH >= 1, TPID value to be inserted as outermost VLAN. */
24680#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN0_PROTO_BE_OFST 6
24681#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN0_PROTO_BE_LEN 2
24682/* If VLAN_PUSH == 2, inner TCI value to be inserted. */
24683#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN1_TCI_BE_OFST 8
24684#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN1_TCI_BE_LEN 2
24685/* If VLAN_PUSH == 2, inner TPID value to be inserted. */
24686#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN1_PROTO_BE_OFST 10
24687#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN1_PROTO_BE_LEN 2
24688/* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
24689#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RSVD_OFST 12
24690#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RSVD_LEN 4
24691/* Set to ENCAP_HEADER_ID_NULL to request no encap action */
24692#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ENCAP_HEADER_ID_OFST 16
24693#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ENCAP_HEADER_ID_LEN 4
24694/* An m-port selector identifying the m-port that the modified packet should be
24695 * delivered to. Set to MPORT_SELECTOR_NULL to request no delivery of the
24696 * packet.
24697 */
24698#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DELIVER_OFST 20
24699#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DELIVER_LEN 4
24700/* Allows an action set to trigger several counter updates. Set to
24701 * MAE_COUNTER_ID_NULL to request no counter action.
24702 */
24703#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_COUNTER_LIST_ID_OFST 24
24704#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_COUNTER_LIST_ID_LEN 4
24705/* Enum values, see field(s): */
24706/* MAE_COUNTER_ID */
24707/* If a driver only wished to update one counter within this action set, then
24708 * it can supply a COUNTER_ID instead of allocating a single-element counter
24709 * list. The ID must have been allocated with COUNTER_TYPE=AR. This field
24710 * should be set to MAE_COUNTER_ID_NULL if this behaviour is not required. It
24711 * is not valid to supply a non-NULL value for both COUNTER_LIST_ID and
24712 * COUNTER_ID.
24713 */
24714#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_COUNTER_ID_OFST 28
24715#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_COUNTER_ID_LEN 4
24716/* Enum values, see field(s): */
24717/* MAE_COUNTER_ID */
24718#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_VALUE_OFST 32
24719#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_VALUE_LEN 4
24720/* Set to MAC_ID_NULL to request no source MAC replacement. */
24721#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SRC_MAC_ID_OFST 36
24722#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SRC_MAC_ID_LEN 4
24723/* Set to MAC_ID_NULL to request no destination MAC replacement. */
24724#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DST_MAC_ID_OFST 40
24725#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DST_MAC_ID_LEN 4
24726/* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */
24727#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_REPORTED_SRC_MPORT_OFST 44
24728#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_REPORTED_SRC_MPORT_LEN 4
24729/* Actions for modifying the Differentiated Services Code-Point (DSCP) bits
24730 * within IPv4 and IPv6 headers.
24731 */
24732#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DSCP_CONTROL_OFST 48
24733#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DSCP_CONTROL_LEN 2
24734#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_ENCAP_COPY_OFST 48
24735#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_ENCAP_COPY_LBN 0
24736#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_ENCAP_COPY_WIDTH 1
24737#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_DECAP_COPY_OFST 48
24738#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_DECAP_COPY_LBN 1
24739#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_DECAP_COPY_WIDTH 1
24740#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_DSCP_OFST 48
24741#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_DSCP_LBN 2
24742#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_DSCP_WIDTH 1
24743#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DSCP_VALUE_OFST 48
24744#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DSCP_VALUE_LBN 3
24745#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DSCP_VALUE_WIDTH 6
24746/* Actions for modifying the Explicit Congestion Notification (ECN) bits within
24747 * IPv4 and IPv6 headers.
24748 */
24749#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_CONTROL_OFST 50
24750#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_CONTROL_LEN 1
24751#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_ENCAP_COPY_OFST 50
24752#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_ENCAP_COPY_LBN 0
24753#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_ENCAP_COPY_WIDTH 1
24754#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_DECAP_COPY_OFST 50
24755#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_DECAP_COPY_LBN 1
24756#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_DECAP_COPY_WIDTH 1
24757#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_ECN_OFST 50
24758#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_ECN_LBN 2
24759#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_ECN_WIDTH 1
24760#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_VALUE_OFST 50
24761#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_VALUE_LBN 3
24762#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_VALUE_WIDTH 2
24763#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_0_TO_CE_OFST 50
24764#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_0_TO_CE_LBN 5
24765#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_0_TO_CE_WIDTH 1
24766#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_1_TO_CE_OFST 50
24767#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_1_TO_CE_LBN 6
24768#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ECN_ECT_1_TO_CE_WIDTH 1
24769/* Actions for overwriting CH_ROUTE subfields. */
24770#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_OVERWRITE_OFST 51
24771#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_OVERWRITE_LEN 1
24772#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_C_PL_OFST 51
24773#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_C_PL_LBN 0
24774#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_C_PL_WIDTH 1
24775#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_D_PL_OFST 51
24776#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_D_PL_LBN 1
24777#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_D_PL_WIDTH 1
24778#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_PL_CHAN_OFST 51
24779#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_PL_CHAN_LBN 2
24780#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_PL_CHAN_WIDTH 1
24781#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_OUT_HOST_CHAN_OFST 51
24782#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_OUT_HOST_CHAN_LBN 3
24783#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_OUT_HOST_CHAN_WIDTH 1
24784/* Override outgoing CH_VC to network port for DO_SET_NET_CHAN action. Cannot
24785 * be used in conjunction with DO_SET_SRC_MPORT action.
24786 */
24787#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_NET_CHAN_OFST 52
24788#define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_NET_CHAN_LEN 1
24789
24790/* MC_CMD_MAE_ACTION_SET_ALLOC_OUT msgresponse */
24791#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN 4
24792/* The MSB of the AS_ID is guaranteed to be clear if the ID is not
24793 * ACTION_SET_ID_NULL. This allows an AS_ID to be distinguished from an ASL_ID
24794 * returned from MC_CMD_MAE_ACTION_SET_LIST_ALLOC.
24795 */
24796#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_OFST 0
24797#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_LEN 4
24798/* enum: An action set ID that is guaranteed never to represent an action set
24799 */
24800#define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_ACTION_SET_ID_NULL 0xffffffff
24801
24802
24803/***********************************/
24804/* MC_CMD_MAE_ACTION_SET_FREE
24805 */
24806#define MC_CMD_MAE_ACTION_SET_FREE 0x14e
24807#undef MC_CMD_0x14e_PRIVILEGE_CTG
24808
24809#define MC_CMD_0x14e_PRIVILEGE_CTG SRIOV_CTG_MAE
24810
24811/* MC_CMD_MAE_ACTION_SET_FREE_IN msgrequest */
24812#define MC_CMD_MAE_ACTION_SET_FREE_IN_LENMIN 4
24813#define MC_CMD_MAE_ACTION_SET_FREE_IN_LENMAX 128
24814#define MC_CMD_MAE_ACTION_SET_FREE_IN_LENMAX_MCDI2 128
24815#define MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(num) (0+4*(num))
24816#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_NUM(len) (((len)-0)/4)
24817/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
24818#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_OFST 0
24819#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_LEN 4
24820#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_MINNUM 1
24821#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_MAXNUM 32
24822#define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_MAXNUM_MCDI2 32
24823
24824/* MC_CMD_MAE_ACTION_SET_FREE_OUT msgresponse */
24825#define MC_CMD_MAE_ACTION_SET_FREE_OUT_LENMIN 4
24826#define MC_CMD_MAE_ACTION_SET_FREE_OUT_LENMAX 128
24827#define MC_CMD_MAE_ACTION_SET_FREE_OUT_LENMAX_MCDI2 128
24828#define MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(num) (0+4*(num))
24829#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_NUM(len) (((len)-0)/4)
24830/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
24831#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_OFST 0
24832#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_LEN 4
24833#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_MINNUM 1
24834#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_MAXNUM 32
24835#define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_MAXNUM_MCDI2 32
24836
24837
24838/***********************************/
24839/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC
24840 * Allocate an action set list (ASL) that can be referenced by an ID. The ASL
24841 * ID can be used when inserting an action rule, so that for each packet
24842 * matching the rule every action set in the list is applied. If the maximum
24843 * number of ASLs have already been allocated then the command will fail with
24844 * MC_CMD_ERR_ENOSPC.
24845 */
24846#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f
24847#undef MC_CMD_0x14f_PRIVILEGE_CTG
24848
24849#define MC_CMD_0x14f_PRIVILEGE_CTG SRIOV_CTG_MAE
24850
24851/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN msgrequest */
24852#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LENMIN 8
24853#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LENMAX 252
24854#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LENMAX_MCDI2 1020
24855#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LEN(num) (4+4*(num))
24856#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_NUM(len) (((len)-4)/4)
24857/* Number of elements in the AS_IDS field. */
24858#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_OFST 0
24859#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_LEN 4
24860/* The IDs of the action sets in this list. The last element of this list may
24861 * be the ID of an already allocated ASL. In this case the action sets from the
24862 * already allocated ASL will be applied after the action sets supplied by this
24863 * request. This mechanism can be used to reduce resource usage in the case
24864 * where one ASL is a sublist of another ASL. The sublist should be allocated
24865 * first, then the superlist should be allocated by supplying all required
24866 * action set IDs that are not in the sublist followed by the ID of the
24867 * sublist. One sublist can be referenced by multiple superlists.
24868 */
24869#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_OFST 4
24870#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_LEN 4
24871#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_MINNUM 1
24872#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_MAXNUM 62
24873#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_MAXNUM_MCDI2 254
24874
24875/* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT msgresponse */
24876#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_LEN 4
24877/* The MSB of the ASL_ID is guaranteed to be set. This allows an ASL_ID to be
24878 * distinguished from an AS_ID returned from MC_CMD_MAE_ACTION_SET_ALLOC.
24879 */
24880#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_OFST 0
24881#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_LEN 4
24882/* enum: An action set list ID that is guaranteed never to represent an action
24883 * set list
24884 */
24885#define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ACTION_SET_LIST_ID_NULL 0xffffffff
24886
24887
24888/***********************************/
24889/* MC_CMD_MAE_ACTION_SET_LIST_FREE
24890 * Free match-action-engine redirect_lists
24891 */
24892#define MC_CMD_MAE_ACTION_SET_LIST_FREE 0x150
24893#undef MC_CMD_0x150_PRIVILEGE_CTG
24894
24895#define MC_CMD_0x150_PRIVILEGE_CTG SRIOV_CTG_MAE
24896
24897/* MC_CMD_MAE_ACTION_SET_LIST_FREE_IN msgrequest */
24898#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMIN 4
24899#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMAX 128
24900#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMAX_MCDI2 128
24901#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LEN(num) (0+4*(num))
24902#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_NUM(len) (((len)-0)/4)
24903/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
24904#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_OFST 0
24905#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_LEN 4
24906#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_MINNUM 1
24907#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_MAXNUM 32
24908#define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_MAXNUM_MCDI2 32
24909
24910/* MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT msgresponse */
24911#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMIN 4
24912#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMAX 128
24913#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMAX_MCDI2 128
24914#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LEN(num) (0+4*(num))
24915#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_NUM(len) (((len)-0)/4)
24916/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
24917#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_OFST 0
24918#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_LEN 4
24919#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_MINNUM 1
24920#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_MAXNUM 32
24921#define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_MAXNUM_MCDI2 32
24922
24923
24924/***********************************/
24925/* MC_CMD_MAE_OUTER_RULE_INSERT
24926 * Inserts an Outer Rule, which controls encapsulation parsing, and may
24927 * influence the Lookup Sequence. If the maximum number of rules have already
24928 * been inserted then the command will fail with MC_CMD_ERR_ENOSPC.
24929 */
24930#define MC_CMD_MAE_OUTER_RULE_INSERT 0x15a
24931#undef MC_CMD_0x15a_PRIVILEGE_CTG
24932
24933#define MC_CMD_0x15a_PRIVILEGE_CTG SRIOV_CTG_MAE
24934
24935/* MC_CMD_MAE_OUTER_RULE_INSERT_IN msgrequest */
24936#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMIN 16
24937#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX 252
24938#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2 1020
24939#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LEN(num) (16+1*(num))
24940#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_NUM(len) (((len)-16)/1)
24941/* Packets matching the rule will be parsed with this encapsulation. */
24942#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_OFST 0
24943#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_LEN 4
24944/* Enum values, see field(s): */
24945/* MAE_MCDI_ENCAP_TYPE */
24946/* Match priority. Lower values have higher priority. Must be less than
24947 * MC_CMD_MAE_GET_CAPS_OUT.ENCAP_PRIOS If a packet matches two filters with
24948 * equal priority then it is unspecified which takes priority.
24949 */
24950#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_OFST 4
24951#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_LEN 4
24952/* Deprecated alias for ACTION_CONTROL. */
24953#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LOOKUP_CONTROL_OFST 8
24954#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LOOKUP_CONTROL_LEN 4
24955#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_OFST 8
24956#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_LBN 0
24957#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_WIDTH 1
24958#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_VNI_MODE_OFST 8
24959#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_VNI_MODE_LBN 1
24960#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_VNI_MODE_WIDTH 2
24961/* Enum values, see field(s): */
24962/* MAE_CT_VNI_MODE */
24963#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_COUNT_OFST 8
24964#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_COUNT_LBN 3
24965#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_COUNT_WIDTH 1
24966#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_TCP_FLAGS_INHIBIT_OFST 8
24967#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_TCP_FLAGS_INHIBIT_LBN 4
24968#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_TCP_FLAGS_INHIBIT_WIDTH 1
24969#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_RECIRC_ID_OFST 8
24970#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_RECIRC_ID_LBN 8
24971#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_RECIRC_ID_WIDTH 8
24972#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_DOMAIN_OFST 8
24973#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_DOMAIN_LBN 16
24974#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_DOMAIN_WIDTH 16
24975/* This field controls the actions that are performed when a rule is hit. */
24976#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ACTION_CONTROL_OFST 8
24977#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ACTION_CONTROL_LEN 4
24978/* ID of counter to increment when the rule is hit. Only used if the DO_COUNT
24979 * flag is set. The ID must have been allocated with COUNTER_TYPE=OR.
24980 */
24981#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_COUNTER_ID_OFST 12
24982#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_COUNTER_ID_LEN 4
24983/* Structure of the format MAE_ENC_FIELD_PAIRS. */
24984#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST 16
24985#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_LEN 1
24986#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MINNUM 0
24987#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MAXNUM 236
24988#define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MAXNUM_MCDI2 1004
24989
24990/* MC_CMD_MAE_OUTER_RULE_INSERT_OUT msgresponse */
24991#define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN 4
24992#define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_OFST 0
24993#define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN 4
24994/* enum: An outer match ID that is guaranteed never to represent an outer match
24995 */
24996#define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL 0xffffffff
24997
24998
24999/***********************************/
25000/* MC_CMD_MAE_OUTER_RULE_REMOVE
25001 */
25002#define MC_CMD_MAE_OUTER_RULE_REMOVE 0x15b
25003#undef MC_CMD_0x15b_PRIVILEGE_CTG
25004
25005#define MC_CMD_0x15b_PRIVILEGE_CTG SRIOV_CTG_MAE
25006
25007/* MC_CMD_MAE_OUTER_RULE_REMOVE_IN msgrequest */
25008#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMIN 4
25009#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMAX 128
25010#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMAX_MCDI2 128
25011#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(num) (0+4*(num))
25012#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_NUM(len) (((len)-0)/4)
25013/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
25014#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_OFST 0
25015#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_LEN 4
25016#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_MINNUM 1
25017#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_MAXNUM 32
25018#define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_MAXNUM_MCDI2 32
25019
25020/* MC_CMD_MAE_OUTER_RULE_REMOVE_OUT msgresponse */
25021#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMIN 4
25022#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMAX 128
25023#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMAX_MCDI2 128
25024#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(num) (0+4*(num))
25025#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_NUM(len) (((len)-0)/4)
25026/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
25027#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_OFST 0
25028#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_LEN 4
25029#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MINNUM 1
25030#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MAXNUM 32
25031#define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_MAXNUM_MCDI2 32
25032
25033/* MAE_ACTION_RULE_RESPONSE structuredef */
25034#define MAE_ACTION_RULE_RESPONSE_LEN 16
25035#define MAE_ACTION_RULE_RESPONSE_ASL_ID_OFST 0
25036#define MAE_ACTION_RULE_RESPONSE_ASL_ID_LEN 4
25037#define MAE_ACTION_RULE_RESPONSE_ASL_ID_LBN 0
25038#define MAE_ACTION_RULE_RESPONSE_ASL_ID_WIDTH 32
25039/* Only one of ASL_ID or AS_ID may have a non-NULL value. */
25040#define MAE_ACTION_RULE_RESPONSE_AS_ID_OFST 4
25041#define MAE_ACTION_RULE_RESPONSE_AS_ID_LEN 4
25042#define MAE_ACTION_RULE_RESPONSE_AS_ID_LBN 32
25043#define MAE_ACTION_RULE_RESPONSE_AS_ID_WIDTH 32
25044/* Controls lookup flow when this rule is hit. See sub-fields for details. More
25045 * info on the lookup sequence can be found in SF-122976-TC. It is an error to
25046 * set both DO_CT and DO_RECIRC.
25047 */
25048#define MAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_OFST 8
25049#define MAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_LEN 4
25050#define MAE_ACTION_RULE_RESPONSE_DO_CT_OFST 8
25051#define MAE_ACTION_RULE_RESPONSE_DO_CT_LBN 0
25052#define MAE_ACTION_RULE_RESPONSE_DO_CT_WIDTH 1
25053#define MAE_ACTION_RULE_RESPONSE_DO_RECIRC_OFST 8
25054#define MAE_ACTION_RULE_RESPONSE_DO_RECIRC_LBN 1
25055#define MAE_ACTION_RULE_RESPONSE_DO_RECIRC_WIDTH 1
25056#define MAE_ACTION_RULE_RESPONSE_CT_VNI_MODE_OFST 8
25057#define MAE_ACTION_RULE_RESPONSE_CT_VNI_MODE_LBN 2
25058#define MAE_ACTION_RULE_RESPONSE_CT_VNI_MODE_WIDTH 2
25059/* Enum values, see field(s): */
25060/* MAE_CT_VNI_MODE */
25061#define MAE_ACTION_RULE_RESPONSE_RECIRC_ID_OFST 8
25062#define MAE_ACTION_RULE_RESPONSE_RECIRC_ID_LBN 8
25063#define MAE_ACTION_RULE_RESPONSE_RECIRC_ID_WIDTH 8
25064#define MAE_ACTION_RULE_RESPONSE_CT_DOMAIN_OFST 8
25065#define MAE_ACTION_RULE_RESPONSE_CT_DOMAIN_LBN 16
25066#define MAE_ACTION_RULE_RESPONSE_CT_DOMAIN_WIDTH 16
25067#define MAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_LBN 64
25068#define MAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_WIDTH 32
25069/* Counter ID to increment if DO_CT or DO_RECIRC is set. Must be set to
25070 * COUNTER_ID_NULL otherwise. Counter ID must have been allocated with
25071 * COUNTER_TYPE=AR.
25072 */
25073#define MAE_ACTION_RULE_RESPONSE_COUNTER_ID_OFST 12
25074#define MAE_ACTION_RULE_RESPONSE_COUNTER_ID_LEN 4
25075#define MAE_ACTION_RULE_RESPONSE_COUNTER_ID_LBN 96
25076#define MAE_ACTION_RULE_RESPONSE_COUNTER_ID_WIDTH 32
25077
25078
25079/***********************************/
25080/* MC_CMD_MAE_ACTION_RULE_INSERT
25081 * Insert a rule specify that packets matching a filter be processed according
25082 * to a previous allocated action. Masks can be set as indicated by
25083 * MC_CMD_MAE_GET_MATCH_FIELD_CAPABILITIES. If the maximum number of rules have
25084 * already been inserted then the command will fail with MC_CMD_ERR_ENOSPC.
25085 */
25086#define MC_CMD_MAE_ACTION_RULE_INSERT 0x15c
25087#undef MC_CMD_0x15c_PRIVILEGE_CTG
25088
25089#define MC_CMD_0x15c_PRIVILEGE_CTG SRIOV_CTG_MAE
25090
25091/* MC_CMD_MAE_ACTION_RULE_INSERT_IN msgrequest */
25092#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMIN 28
25093#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX 252
25094#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2 1020
25095#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_LEN(num) (28+1*(num))
25096#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_NUM(len) (((len)-28)/1)
25097/* See MC_CMD_MAE_OUTER_RULE_REGISTER_IN/PRIO. */
25098#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_OFST 0
25099#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_LEN 4
25100/* Structure of the format MAE_ACTION_RULE_RESPONSE */
25101#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST 4
25102#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN 20
25103/* Reserved for future use. Must be set to zero. */
25104#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RSVD_OFST 24
25105#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RSVD_LEN 4
25106/* Structure of the format MAE_FIELD_MASK_VALUE_PAIRS */
25107#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST 28
25108#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_LEN 1
25109#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MINNUM 0
25110#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MAXNUM 224
25111#define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MAXNUM_MCDI2 992
25112
25113/* MC_CMD_MAE_ACTION_RULE_INSERT_OUT msgresponse */
25114#define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN 4
25115#define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_OFST 0
25116#define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN 4
25117/* enum: An action rule ID that is guaranteed never to represent an action rule
25118 */
25119#define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL 0xffffffff
25120
25121
25122/***********************************/
25123/* MC_CMD_MAE_ACTION_RULE_UPDATE
25124 * Atomically change the response of an action rule. Firmware may return
25125 * ENOTSUP, in which case the driver should DELETE/INSERT.
25126 */
25127#define MC_CMD_MAE_ACTION_RULE_UPDATE 0x15d
25128#undef MC_CMD_0x15d_PRIVILEGE_CTG
25129
25130#define MC_CMD_0x15d_PRIVILEGE_CTG SRIOV_CTG_MAE
25131
25132/* MC_CMD_MAE_ACTION_RULE_UPDATE_IN msgrequest */
25133#define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_LEN 24
25134/* ID of action rule to update */
25135#define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_OFST 0
25136#define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_LEN 4
25137/* Structure of the format MAE_ACTION_RULE_RESPONSE */
25138#define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_RESPONSE_OFST 4
25139#define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_RESPONSE_LEN 20
25140
25141/* MC_CMD_MAE_ACTION_RULE_UPDATE_OUT msgresponse */
25142#define MC_CMD_MAE_ACTION_RULE_UPDATE_OUT_LEN 0
25143
25144
25145/***********************************/
25146/* MC_CMD_MAE_ACTION_RULE_DELETE
25147 */
25148#define MC_CMD_MAE_ACTION_RULE_DELETE 0x155
25149#undef MC_CMD_0x155_PRIVILEGE_CTG
25150
25151#define MC_CMD_0x155_PRIVILEGE_CTG SRIOV_CTG_MAE
25152
25153/* MC_CMD_MAE_ACTION_RULE_DELETE_IN msgrequest */
25154#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMIN 4
25155#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMAX 128
25156#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMAX_MCDI2 128
25157#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(num) (0+4*(num))
25158#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_NUM(len) (((len)-0)/4)
25159/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
25160#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_OFST 0
25161#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_LEN 4
25162#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_MINNUM 1
25163#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_MAXNUM 32
25164#define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_MAXNUM_MCDI2 32
25165
25166/* MC_CMD_MAE_ACTION_RULE_DELETE_OUT msgresponse */
25167#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMIN 4
25168#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMAX 128
25169#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMAX_MCDI2 128
25170#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(num) (0+4*(num))
25171#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_NUM(len) (((len)-0)/4)
25172/* Same semantics as MC_CMD_MAE_COUNTER_FREE */
25173#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_OFST 0
25174#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_LEN 4
25175#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_MINNUM 1
25176#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_MAXNUM 32
25177#define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_MAXNUM_MCDI2 32
25178
25179
25180/***********************************/
25181/* MC_CMD_MAE_MPORT_LOOKUP
25182 * Return the m-port corresponding to a selector.
25183 */
25184#define MC_CMD_MAE_MPORT_LOOKUP 0x160
25185#undef MC_CMD_0x160_PRIVILEGE_CTG
25186
25187#define MC_CMD_0x160_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25188
25189/* MC_CMD_MAE_MPORT_LOOKUP_IN msgrequest */
25190#define MC_CMD_MAE_MPORT_LOOKUP_IN_LEN 4
25191#define MC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_OFST 0
25192#define MC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_LEN 4
25193
25194/* MC_CMD_MAE_MPORT_LOOKUP_OUT msgresponse */
25195#define MC_CMD_MAE_MPORT_LOOKUP_OUT_LEN 4
25196#define MC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_OFST 0
25197#define MC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_LEN 4
25198
25199
25200/***********************************/
25201/* MC_CMD_MAE_MPORT_ALLOC
25202 * Allocates a m-port, which can subsequently be used in action rules as a
25203 * match or delivery argument.
25204 */
25205#define MC_CMD_MAE_MPORT_ALLOC 0x163
25206#undef MC_CMD_0x163_PRIVILEGE_CTG
25207
25208#define MC_CMD_0x163_PRIVILEGE_CTG SRIOV_CTG_MAE
25209
25210/* MC_CMD_MAE_MPORT_ALLOC_IN msgrequest */
25211#define MC_CMD_MAE_MPORT_ALLOC_IN_LEN 20
25212/* The type of m-port to allocate. Firmware may return ENOTSUP for certain
25213 * types.
25214 */
25215#define MC_CMD_MAE_MPORT_ALLOC_IN_TYPE_OFST 0
25216#define MC_CMD_MAE_MPORT_ALLOC_IN_TYPE_LEN 4
25217/* enum: Traffic can be sent to this type of m-port using an override
25218 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
25219 * nominated m-port, and will be delivered with metadata identifying the alias
25220 * m-port.
25221 */
25222#define MC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_ALIAS 0x1
25223/* enum: This type of m-port has a VNIC attached. Queues can be created on this
25224 * VNIC by specifying the created m-port as an m-port selector at queue
25225 * creation time.
25226 */
25227#define MC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_VNIC 0x2
25228/* 128-bit value for use by the driver. */
25229#define MC_CMD_MAE_MPORT_ALLOC_IN_UUID_OFST 4
25230#define MC_CMD_MAE_MPORT_ALLOC_IN_UUID_LEN 16
25231
25232/* MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN msgrequest */
25233#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_LEN 24
25234/* The type of m-port to allocate. Firmware may return ENOTSUP for certain
25235 * types.
25236 */
25237#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_OFST 0
25238#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_LEN 4
25239/* enum: Traffic can be sent to this type of m-port using an override
25240 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
25241 * nominated m-port, and will be delivered with metadata identifying the alias
25242 * m-port.
25243 */
25244#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_ALIAS 0x1
25245/* enum: This type of m-port has a VNIC attached. Queues can be created on this
25246 * VNIC by specifying the created m-port as an m-port selector at queue
25247 * creation time.
25248 */
25249#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_VNIC 0x2
25250/* 128-bit value for use by the driver. */
25251#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_UUID_OFST 4
25252#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_UUID_LEN 16
25253/* An m-port selector identifying the VNIC to which traffic should be
25254 * delivered. This must currently be set to MAE_MPORT_SELECTOR_ASSIGNED (i.e.
25255 * the m-port assigned to the calling client).
25256 */
25257#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_DELIVER_MPORT_OFST 20
25258#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_DELIVER_MPORT_LEN 4
25259
25260/* MC_CMD_MAE_MPORT_ALLOC_VNIC_IN msgrequest */
25261#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_LEN 20
25262/* The type of m-port to allocate. Firmware may return ENOTSUP for certain
25263 * types.
25264 */
25265#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_OFST 0
25266#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_LEN 4
25267/* enum: Traffic can be sent to this type of m-port using an override
25268 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
25269 * nominated m-port, and will be delivered with metadata identifying the alias
25270 * m-port.
25271 */
25272#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_ALIAS 0x1
25273/* enum: This type of m-port has a VNIC attached. Queues can be created on this
25274 * VNIC by specifying the created m-port as an m-port selector at queue
25275 * creation time.
25276 */
25277#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_VNIC 0x2
25278/* 128-bit value for use by the driver. */
25279#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_UUID_OFST 4
25280#define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_UUID_LEN 16
25281
25282/* MC_CMD_MAE_MPORT_ALLOC_OUT msgresponse */
25283#define MC_CMD_MAE_MPORT_ALLOC_OUT_LEN 4
25284/* ID of newly-allocated m-port. */
25285#define MC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_OFST 0
25286#define MC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_LEN 4
25287
25288/* MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT msgrequest */
25289#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LEN 24
25290/* ID of newly-allocated m-port. */
25291#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_OFST 0
25292#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_LEN 4
25293/* A value that will appear in the packet metadata for any packets delivered
25294 * using an alias type m-port. This value is guaranteed unique on the VNIC
25295 * being delivered to, and is guaranteed not to exceed the range of values
25296 * representable in the relevant metadata field.
25297 */
25298#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LABEL_OFST 20
25299#define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LABEL_LEN 4
25300
25301/* MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT msgrequest */
25302#define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_LEN 4
25303/* ID of newly-allocated m-port. */
25304#define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_OFST 0
25305#define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_LEN 4
25306
25307
25308/***********************************/
25309/* MC_CMD_MAE_MPORT_FREE
25310 * Free a m-port which was previously allocated by the driver.
25311 */
25312#define MC_CMD_MAE_MPORT_FREE 0x164
25313#undef MC_CMD_0x164_PRIVILEGE_CTG
25314
25315#define MC_CMD_0x164_PRIVILEGE_CTG SRIOV_CTG_MAE
25316
25317/* MC_CMD_MAE_MPORT_FREE_IN msgrequest */
25318#define MC_CMD_MAE_MPORT_FREE_IN_LEN 4
25319/* MPORT_ID as returned by MC_CMD_MAE_MPORT_ALLOC. */
25320#define MC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_OFST 0
25321#define MC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_LEN 4
25322
25323/* MC_CMD_MAE_MPORT_FREE_OUT msgresponse */
25324#define MC_CMD_MAE_MPORT_FREE_OUT_LEN 0
25325
25326/* MAE_MPORT_DESC structuredef */
25327#define MAE_MPORT_DESC_LEN 52
25328#define MAE_MPORT_DESC_MPORT_ID_OFST 0
25329#define MAE_MPORT_DESC_MPORT_ID_LEN 4
25330#define MAE_MPORT_DESC_MPORT_ID_LBN 0
25331#define MAE_MPORT_DESC_MPORT_ID_WIDTH 32
25332/* Reserved for future purposes, contains information independent of caller */
25333#define MAE_MPORT_DESC_FLAGS_OFST 4
25334#define MAE_MPORT_DESC_FLAGS_LEN 4
25335#define MAE_MPORT_DESC_FLAGS_LBN 32
25336#define MAE_MPORT_DESC_FLAGS_WIDTH 32
25337#define MAE_MPORT_DESC_CALLER_FLAGS_OFST 8
25338#define MAE_MPORT_DESC_CALLER_FLAGS_LEN 4
25339#define MAE_MPORT_DESC_CAN_RECEIVE_ON_OFST 8
25340#define MAE_MPORT_DESC_CAN_RECEIVE_ON_LBN 0
25341#define MAE_MPORT_DESC_CAN_RECEIVE_ON_WIDTH 1
25342#define MAE_MPORT_DESC_CAN_DELIVER_TO_OFST 8
25343#define MAE_MPORT_DESC_CAN_DELIVER_TO_LBN 1
25344#define MAE_MPORT_DESC_CAN_DELIVER_TO_WIDTH 1
25345#define MAE_MPORT_DESC_CAN_DELETE_OFST 8
25346#define MAE_MPORT_DESC_CAN_DELETE_LBN 2
25347#define MAE_MPORT_DESC_CAN_DELETE_WIDTH 1
25348#define MAE_MPORT_DESC_IS_ZOMBIE_OFST 8
25349#define MAE_MPORT_DESC_IS_ZOMBIE_LBN 3
25350#define MAE_MPORT_DESC_IS_ZOMBIE_WIDTH 1
25351#define MAE_MPORT_DESC_CALLER_FLAGS_LBN 64
25352#define MAE_MPORT_DESC_CALLER_FLAGS_WIDTH 32
25353/* Not the ideal name; it's really the type of thing connected to the m-port */
25354#define MAE_MPORT_DESC_MPORT_TYPE_OFST 12
25355#define MAE_MPORT_DESC_MPORT_TYPE_LEN 4
25356/* enum: Connected to a MAC... */
25357#define MAE_MPORT_DESC_MPORT_TYPE_NET_PORT 0x0
25358/* enum: Adds metadata and delivers to another m-port */
25359#define MAE_MPORT_DESC_MPORT_TYPE_ALIAS 0x1
25360/* enum: Connected to a VNIC. */
25361#define MAE_MPORT_DESC_MPORT_TYPE_VNIC 0x2
25362#define MAE_MPORT_DESC_MPORT_TYPE_LBN 96
25363#define MAE_MPORT_DESC_MPORT_TYPE_WIDTH 32
25364/* 128-bit value available to drivers for m-port identification. */
25365#define MAE_MPORT_DESC_UUID_OFST 16
25366#define MAE_MPORT_DESC_UUID_LEN 16
25367#define MAE_MPORT_DESC_UUID_LBN 128
25368#define MAE_MPORT_DESC_UUID_WIDTH 128
25369/* Big wadge of space reserved for other common properties */
25370#define MAE_MPORT_DESC_RESERVED_OFST 32
25371#define MAE_MPORT_DESC_RESERVED_LEN 8
25372#define MAE_MPORT_DESC_RESERVED_LO_OFST 32
25373#define MAE_MPORT_DESC_RESERVED_LO_LEN 4
25374#define MAE_MPORT_DESC_RESERVED_LO_LBN 256
25375#define MAE_MPORT_DESC_RESERVED_LO_WIDTH 32
25376#define MAE_MPORT_DESC_RESERVED_HI_OFST 36
25377#define MAE_MPORT_DESC_RESERVED_HI_LEN 4
25378#define MAE_MPORT_DESC_RESERVED_HI_LBN 288
25379#define MAE_MPORT_DESC_RESERVED_HI_WIDTH 32
25380#define MAE_MPORT_DESC_RESERVED_LBN 256
25381#define MAE_MPORT_DESC_RESERVED_WIDTH 64
25382/* Logical port index. Only valid when type NET Port. */
25383#define MAE_MPORT_DESC_NET_PORT_IDX_OFST 40
25384#define MAE_MPORT_DESC_NET_PORT_IDX_LEN 4
25385#define MAE_MPORT_DESC_NET_PORT_IDX_LBN 320
25386#define MAE_MPORT_DESC_NET_PORT_IDX_WIDTH 32
25387/* The m-port delivered to */
25388#define MAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_OFST 40
25389#define MAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_LEN 4
25390#define MAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_LBN 320
25391#define MAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_WIDTH 32
25392/* The type of thing that owns the VNIC */
25393#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_OFST 40
25394#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_LEN 4
25395#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_FUNCTION 0x1 /* enum */
25396#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_PLUGIN 0x2 /* enum */
25397#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_LBN 320
25398#define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_WIDTH 32
25399/* The PCIe interface on which the function lives. CJK: We need an enumeration
25400 * of interfaces that we extend as new interface (types) appear. This belongs
25401 * elsewhere and should be referenced from here
25402 */
25403#define MAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_OFST 44
25404#define MAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_LEN 4
25405#define MAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_LBN 352
25406#define MAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_WIDTH 32
25407#define MAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_OFST 48
25408#define MAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_LEN 2
25409#define MAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_LBN 384
25410#define MAE_MPORT_DESC_VNIC_FUNCTION_PF_IDX_WIDTH 16
25411#define MAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_OFST 50
25412#define MAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_LEN 2
25413/* enum: Indicates that the function is a PF */
25414#define MAE_MPORT_DESC_VF_IDX_NULL 0xffff
25415#define MAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_LBN 400
25416#define MAE_MPORT_DESC_VNIC_FUNCTION_VF_IDX_WIDTH 16
25417/* Reserved. Should be ignored for now. */
25418#define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_OFST 44
25419#define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_LEN 4
25420#define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_LBN 352
25421#define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_WIDTH 32
25422
25423
25424/***********************************/
25425/* MC_CMD_MAE_MPORT_READ_JOURNAL
25426 * Firmware maintains a per-client journal of mport creations and deletions.
25427 * This journal is clear-on-read, i.e. repeated calls of this command will
25428 * drain the buffer. Whenever the caller resets its function via FLR or
25429 * MC_CMD_ENTITY_RESET, the journal is regenerated from a blank start.
25430 */
25431#define MC_CMD_MAE_MPORT_READ_JOURNAL 0x147
25432#undef MC_CMD_0x147_PRIVILEGE_CTG
25433
25434#define MC_CMD_0x147_PRIVILEGE_CTG SRIOV_CTG_MAE
25435
25436/* MC_CMD_MAE_MPORT_READ_JOURNAL_IN msgrequest */
25437#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_LEN 4
25438/* Any unused flags are reserved and must be set to zero. */
25439#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_OFST 0
25440#define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_LEN 4
25441
25442/* MC_CMD_MAE_MPORT_READ_JOURNAL_OUT msgresponse */
25443#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMIN 12
25444#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX 252
25445#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LENMAX_MCDI2 1020
25446#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_LEN(num) (12+1*(num))
25447#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_NUM(len) (((len)-12)/1)
25448/* Any unused flags are reserved and must be ignored. */
25449#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_OFST 0
25450#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_LEN 4
25451#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_OFST 0
25452#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_LBN 0
25453#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_WIDTH 1
25454/* The number of MAE_MPORT_DESC structures in MPORT_DESC_DATA. May be zero. */
25455#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_OFST 4
25456#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_LEN 4
25457#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_OFST 8
25458#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_LEN 4
25459/* Any array of MAE_MPORT_DESC structures. The MAE_MPORT_DESC structure may
25460 * grow in future version of this command. Drivers should use a stride of
25461 * SIZEOF_MPORT_DESC. Fields beyond SIZEOF_MPORT_DESC are not present.
25462 */
25463#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_OFST 12
25464#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_LEN 1
25465#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MINNUM 0
25466#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM 240
25467#define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MAXNUM_MCDI2 1008
25468
25469/* TABLE_FIELD_DESCR structuredef: An individual table field descriptor. This
25470 * describes the location and properties of one N-bit field within a wider
25471 * M-bit key/mask/response value.
25472 */
25473#define TABLE_FIELD_DESCR_LEN 8
25474/* Identifier for this field. */
25475#define TABLE_FIELD_DESCR_FIELD_ID_OFST 0
25476#define TABLE_FIELD_DESCR_FIELD_ID_LEN 2
25477/* Enum values, see field(s): */
25478/* TABLE_FIELD_ID */
25479#define TABLE_FIELD_DESCR_FIELD_ID_LBN 0
25480#define TABLE_FIELD_DESCR_FIELD_ID_WIDTH 16
25481/* Lowest (least significant) bit number of the bits of this field. */
25482#define TABLE_FIELD_DESCR_LBN_OFST 2
25483#define TABLE_FIELD_DESCR_LBN_LEN 2
25484#define TABLE_FIELD_DESCR_LBN_LBN 16
25485#define TABLE_FIELD_DESCR_LBN_WIDTH 16
25486/* Width of this field in bits. */
25487#define TABLE_FIELD_DESCR_WIDTH_OFST 4
25488#define TABLE_FIELD_DESCR_WIDTH_LEN 2
25489#define TABLE_FIELD_DESCR_WIDTH_LBN 32
25490#define TABLE_FIELD_DESCR_WIDTH_WIDTH 16
25491/* The mask type for this field. (Note that masking is relevant to keys; fields
25492 * of responses are always reported with the EXACT type.)
25493 */
25494#define TABLE_FIELD_DESCR_MASK_TYPE_OFST 6
25495#define TABLE_FIELD_DESCR_MASK_TYPE_LEN 1
25496/* enum: Field must never be selected in the mask. */
25497#define TABLE_FIELD_DESCR_MASK_NEVER 0x0
25498/* enum: Exact match: field must always be selected in the mask. */
25499#define TABLE_FIELD_DESCR_MASK_EXACT 0x1
25500/* enum: Ternary match: arbitrary mask bits are allowed. */
25501#define TABLE_FIELD_DESCR_MASK_TERNARY 0x2
25502/* enum: Whole field match: mask must be all 1 bits, or all 0 bits. */
25503#define TABLE_FIELD_DESCR_MASK_WHOLE_FIELD 0x3
25504/* enum: Longest prefix match: mask must be 1 bit(s) followed by 0 bit(s). */
25505#define TABLE_FIELD_DESCR_MASK_LPM 0x4
25506#define TABLE_FIELD_DESCR_MASK_TYPE_LBN 48
25507#define TABLE_FIELD_DESCR_MASK_TYPE_WIDTH 8
25508/* A version code that allows field semantics to be extended. All fields
25509 * currently use version 0.
25510 */
25511#define TABLE_FIELD_DESCR_SCHEME_OFST 7
25512#define TABLE_FIELD_DESCR_SCHEME_LEN 1
25513#define TABLE_FIELD_DESCR_SCHEME_LBN 56
25514#define TABLE_FIELD_DESCR_SCHEME_WIDTH 8
25515
25516
25517/***********************************/
25518/* MC_CMD_TABLE_LIST
25519 * Return the list of tables which may be accessed via this table API.
25520 */
25521#define MC_CMD_TABLE_LIST 0x1c9
25522#undef MC_CMD_0x1c9_PRIVILEGE_CTG
25523
25524#define MC_CMD_0x1c9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25525
25526/* MC_CMD_TABLE_LIST_IN msgrequest */
25527#define MC_CMD_TABLE_LIST_IN_LEN 4
25528/* Index of the first item to be returned in the TABLE_ID sequence. (Set to 0
25529 * for the first call; further calls are only required if the whole sequence
25530 * does not fit within the maximum MCDI message size.)
25531 */
25532#define MC_CMD_TABLE_LIST_IN_FIRST_TABLE_ID_INDEX_OFST 0
25533#define MC_CMD_TABLE_LIST_IN_FIRST_TABLE_ID_INDEX_LEN 4
25534
25535/* MC_CMD_TABLE_LIST_OUT msgresponse */
25536#define MC_CMD_TABLE_LIST_OUT_LENMIN 4
25537#define MC_CMD_TABLE_LIST_OUT_LENMAX 252
25538#define MC_CMD_TABLE_LIST_OUT_LENMAX_MCDI2 1020
25539#define MC_CMD_TABLE_LIST_OUT_LEN(num) (4+4*(num))
25540#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_NUM(len) (((len)-4)/4)
25541/* The total number of tables. */
25542#define MC_CMD_TABLE_LIST_OUT_N_TABLES_OFST 0
25543#define MC_CMD_TABLE_LIST_OUT_N_TABLES_LEN 4
25544/* A sequence of table identifiers. If all N_TABLES items do not fit, further
25545 * items can be obtained by repeating the call with a non-zero
25546 * FIRST_TABLE_ID_INDEX.
25547 */
25548#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_OFST 4
25549#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_LEN 4
25550#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_MINNUM 0
25551#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_MAXNUM 62
25552#define MC_CMD_TABLE_LIST_OUT_TABLE_ID_MAXNUM_MCDI2 254
25553/* Enum values, see field(s): */
25554/* TABLE_ID */
25555
25556
25557/***********************************/
25558/* MC_CMD_TABLE_DESCRIPTOR
25559 * Request the table descriptor for a particular table. This describes
25560 * properties of the table and the format of the key and response. May return
25561 * EINVAL for unknown table ID.
25562 */
25563#define MC_CMD_TABLE_DESCRIPTOR 0x1ca
25564#undef MC_CMD_0x1ca_PRIVILEGE_CTG
25565
25566#define MC_CMD_0x1ca_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25567
25568/* MC_CMD_TABLE_DESCRIPTOR_IN msgrequest */
25569#define MC_CMD_TABLE_DESCRIPTOR_IN_LEN 8
25570/* Identifier for this field. */
25571#define MC_CMD_TABLE_DESCRIPTOR_IN_TABLE_ID_OFST 0
25572#define MC_CMD_TABLE_DESCRIPTOR_IN_TABLE_ID_LEN 4
25573/* Enum values, see field(s): */
25574/* TABLE_ID */
25575/* Index of the first item to be returned in the FIELDS sequence. (Set to 0 for
25576 * the first call; further calls are only required if the whole sequence does
25577 * not fit within the maximum MCDI message size.)
25578 */
25579#define MC_CMD_TABLE_DESCRIPTOR_IN_FIRST_FIELDS_INDEX_OFST 4
25580#define MC_CMD_TABLE_DESCRIPTOR_IN_FIRST_FIELDS_INDEX_LEN 4
25581
25582/* MC_CMD_TABLE_DESCRIPTOR_OUT msgresponse */
25583#define MC_CMD_TABLE_DESCRIPTOR_OUT_LENMIN 28
25584#define MC_CMD_TABLE_DESCRIPTOR_OUT_LENMAX 252
25585#define MC_CMD_TABLE_DESCRIPTOR_OUT_LENMAX_MCDI2 1020
25586#define MC_CMD_TABLE_DESCRIPTOR_OUT_LEN(num) (20+8*(num))
25587#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_NUM(len) (((len)-20)/8)
25588/* Maximum number of entries in this table. */
25589#define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_ENTRIES_OFST 0
25590#define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_ENTRIES_LEN 4
25591/* The type of table. (This is really just informational; the important
25592 * properties of a table that affect programming can be deduced from other
25593 * items in the table or field descriptor.)
25594 */
25595#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_OFST 4
25596#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_LEN 2
25597/* enum: Direct table (essentially just an array). Behaves like a BCAM for
25598 * programming purposes, where the fact that the key is actually used as an
25599 * array index is really just an implementation detail.
25600 */
25601#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_DIRECT 0x1
25602/* enum: BCAM (binary CAM) table: exact match on all key fields." */
25603#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_BCAM 0x2
25604/* enum: TCAM (ternary CAM) table: matches fields with a mask. Each entry may
25605 * have its own different mask.
25606 */
25607#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_TCAM 0x3
25608/* enum: STCAM (semi-TCAM) table: like a TCAM but entries shared a limited
25609 * number of unique masks.
25610 */
25611#define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_STCAM 0x4
25612/* Width of key (and corresponding mask, for TCAM or STCAM) in bits. */
25613#define MC_CMD_TABLE_DESCRIPTOR_OUT_KEY_WIDTH_OFST 6
25614#define MC_CMD_TABLE_DESCRIPTOR_OUT_KEY_WIDTH_LEN 2
25615/* Width of response in bits. */
25616#define MC_CMD_TABLE_DESCRIPTOR_OUT_RESP_WIDTH_OFST 8
25617#define MC_CMD_TABLE_DESCRIPTOR_OUT_RESP_WIDTH_LEN 2
25618/* The total number of fields in the key. */
25619#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_KEY_FIELDS_OFST 10
25620#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_KEY_FIELDS_LEN 2
25621/* The total number of fields in the response. */
25622#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_RESP_FIELDS_OFST 12
25623#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_RESP_FIELDS_LEN 2
25624/* Number of priorities for STCAM or TCAM; otherwise 0. The priority of a table
25625 * entry (relevant when more than one masked entry matches) ranges from
25626 * 0=highest to N_PRIORITIES-1=lowest.
25627 */
25628#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_PRIORITIES_OFST 14
25629#define MC_CMD_TABLE_DESCRIPTOR_OUT_N_PRIORITIES_LEN 2
25630/* Maximum number of masks for STCAM; otherwise 0. */
25631#define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_MASKS_OFST 16
25632#define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_MASKS_LEN 2
25633/* Flags. */
25634#define MC_CMD_TABLE_DESCRIPTOR_OUT_FLAGS_OFST 18
25635#define MC_CMD_TABLE_DESCRIPTOR_OUT_FLAGS_LEN 1
25636#define MC_CMD_TABLE_DESCRIPTOR_OUT_ALLOC_MASKS_OFST 18
25637#define MC_CMD_TABLE_DESCRIPTOR_OUT_ALLOC_MASKS_LBN 0
25638#define MC_CMD_TABLE_DESCRIPTOR_OUT_ALLOC_MASKS_WIDTH 1
25639/* Access scheme version code, allowing the method of accessing table entries
25640 * to change semantics in future. A client which does not understand the value
25641 * of this field should assume that it cannot program this table. Currently
25642 * always set to 0 indicating the original MC_CMD_TABLE_INSERT/UPDATE/DELETE
25643 * semantics.
25644 */
25645#define MC_CMD_TABLE_DESCRIPTOR_OUT_SCHEME_OFST 19
25646#define MC_CMD_TABLE_DESCRIPTOR_OUT_SCHEME_LEN 1
25647/* A sequence of TABLE_FIELD_DESCR structures: N_KEY_FIELDS items describing
25648 * the key, followed by N_RESP_FIELDS items describing the response. If all
25649 * N_KEY_FIELDS+N_RESP_FIELDS items do not fit, further items can be obtained
25650 * by repeating the call with a non-zero FIRST_FIELDS_INDEX.
25651 */
25652#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_OFST 20
25653#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LEN 8
25654#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LO_OFST 20
25655#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LO_LEN 4
25656#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LO_LBN 160
25657#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LO_WIDTH 32
25658#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_HI_OFST 24
25659#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_HI_LEN 4
25660#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_HI_LBN 192
25661#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_HI_WIDTH 32
25662#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_MINNUM 1
25663#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_MAXNUM 29
25664#define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_MAXNUM_MCDI2 125
25665
25666
25667/***********************************/
25668/* MC_CMD_TABLE_INSERT
25669 * Insert a new entry into a table. The entry must not currently exist. May
25670 * return EINVAL for unknown table ID or other bad request parameters, EEXIST
25671 * if the entry already exists, ENOSPC if there is no space or EPERM if the
25672 * operation is not permitted. In case of an error, the additional MCDI error
25673 * argument field returns the raw error code from the underlying CAM driver.
25674 */
25675#define MC_CMD_TABLE_INSERT 0x1cd
25676#undef MC_CMD_0x1cd_PRIVILEGE_CTG
25677
25678#define MC_CMD_0x1cd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25679
25680/* MC_CMD_TABLE_INSERT_IN msgrequest */
25681#define MC_CMD_TABLE_INSERT_IN_LENMIN 16
25682#define MC_CMD_TABLE_INSERT_IN_LENMAX 252
25683#define MC_CMD_TABLE_INSERT_IN_LENMAX_MCDI2 1020
25684#define MC_CMD_TABLE_INSERT_IN_LEN(num) (12+4*(num))
25685#define MC_CMD_TABLE_INSERT_IN_DATA_NUM(len) (((len)-12)/4)
25686/* Table identifier. */
25687#define MC_CMD_TABLE_INSERT_IN_TABLE_ID_OFST 0
25688#define MC_CMD_TABLE_INSERT_IN_TABLE_ID_LEN 4
25689/* Enum values, see field(s): */
25690/* TABLE_ID */
25691/* Width in bits of supplied key data (must match table properties). */
25692#define MC_CMD_TABLE_INSERT_IN_KEY_WIDTH_OFST 4
25693#define MC_CMD_TABLE_INSERT_IN_KEY_WIDTH_LEN 2
25694/* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
25695 * when allocated MASK_ID is used instead).
25696 */
25697#define MC_CMD_TABLE_INSERT_IN_MASK_WIDTH_OFST 6
25698#define MC_CMD_TABLE_INSERT_IN_MASK_WIDTH_LEN 2
25699/* Width in bits of supplied response data (for INSERT and UPDATE operations
25700 * this must match the table properties; for DELETE operations, no response
25701 * data is required and this must be 0).
25702 */
25703#define MC_CMD_TABLE_INSERT_IN_RESP_WIDTH_OFST 8
25704#define MC_CMD_TABLE_INSERT_IN_RESP_WIDTH_LEN 2
25705/* Mask ID for STCAM table - used instead of mask data if the table descriptor
25706 * reports ALLOC_MASKS==1. Otherwise set to 0.
25707 */
25708#define MC_CMD_TABLE_INSERT_IN_MASK_ID_OFST 6
25709#define MC_CMD_TABLE_INSERT_IN_MASK_ID_LEN 2
25710/* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
25711#define MC_CMD_TABLE_INSERT_IN_PRIORITY_OFST 8
25712#define MC_CMD_TABLE_INSERT_IN_PRIORITY_LEN 2
25713/* (32-bit alignment padding - set to 0) */
25714#define MC_CMD_TABLE_INSERT_IN_RESERVED_OFST 10
25715#define MC_CMD_TABLE_INSERT_IN_RESERVED_LEN 2
25716/* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
25717 * data values. Each of these items is logically treated as a single wide N-bit
25718 * value, in which the individual fields have been placed within that value per
25719 * the LBN and WIDTH information from the table field descriptors. The wide
25720 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
25721 * multiple of 32 bits. The value is then packed into this command as a
25722 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
25723 */
25724#define MC_CMD_TABLE_INSERT_IN_DATA_OFST 12
25725#define MC_CMD_TABLE_INSERT_IN_DATA_LEN 4
25726#define MC_CMD_TABLE_INSERT_IN_DATA_MINNUM 1
25727#define MC_CMD_TABLE_INSERT_IN_DATA_MAXNUM 60
25728#define MC_CMD_TABLE_INSERT_IN_DATA_MAXNUM_MCDI2 252
25729
25730/* MC_CMD_TABLE_INSERT_OUT msgresponse */
25731#define MC_CMD_TABLE_INSERT_OUT_LEN 0
25732
25733
25734/***********************************/
25735/* MC_CMD_TABLE_DELETE
25736 * Delete an existing entry in a table. May return EINVAL for unknown table ID
25737 * or other bad request parameters, ENOENT if the entry does not exist, or
25738 * EPERM if the operation is not permitted. In case of an error, the additional
25739 * MCDI error argument field returns the raw error code from the underlying CAM
25740 * driver.
25741 */
25742#define MC_CMD_TABLE_DELETE 0x1cf
25743#undef MC_CMD_0x1cf_PRIVILEGE_CTG
25744
25745#define MC_CMD_0x1cf_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25746
25747/* MC_CMD_TABLE_DELETE_IN msgrequest */
25748#define MC_CMD_TABLE_DELETE_IN_LENMIN 16
25749#define MC_CMD_TABLE_DELETE_IN_LENMAX 252
25750#define MC_CMD_TABLE_DELETE_IN_LENMAX_MCDI2 1020
25751#define MC_CMD_TABLE_DELETE_IN_LEN(num) (12+4*(num))
25752#define MC_CMD_TABLE_DELETE_IN_DATA_NUM(len) (((len)-12)/4)
25753/* Table identifier. */
25754#define MC_CMD_TABLE_DELETE_IN_TABLE_ID_OFST 0
25755#define MC_CMD_TABLE_DELETE_IN_TABLE_ID_LEN 4
25756/* Enum values, see field(s): */
25757/* TABLE_ID */
25758/* Width in bits of supplied key data (must match table properties). */
25759#define MC_CMD_TABLE_DELETE_IN_KEY_WIDTH_OFST 4
25760#define MC_CMD_TABLE_DELETE_IN_KEY_WIDTH_LEN 2
25761/* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
25762 * when allocated MASK_ID is used instead).
25763 */
25764#define MC_CMD_TABLE_DELETE_IN_MASK_WIDTH_OFST 6
25765#define MC_CMD_TABLE_DELETE_IN_MASK_WIDTH_LEN 2
25766/* Width in bits of supplied response data (for INSERT and UPDATE operations
25767 * this must match the table properties; for DELETE operations, no response
25768 * data is required and this must be 0).
25769 */
25770#define MC_CMD_TABLE_DELETE_IN_RESP_WIDTH_OFST 8
25771#define MC_CMD_TABLE_DELETE_IN_RESP_WIDTH_LEN 2
25772/* Mask ID for STCAM table - used instead of mask data if the table descriptor
25773 * reports ALLOC_MASKS==1. Otherwise set to 0.
25774 */
25775#define MC_CMD_TABLE_DELETE_IN_MASK_ID_OFST 6
25776#define MC_CMD_TABLE_DELETE_IN_MASK_ID_LEN 2
25777/* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
25778#define MC_CMD_TABLE_DELETE_IN_PRIORITY_OFST 8
25779#define MC_CMD_TABLE_DELETE_IN_PRIORITY_LEN 2
25780/* (32-bit alignment padding - set to 0) */
25781#define MC_CMD_TABLE_DELETE_IN_RESERVED_OFST 10
25782#define MC_CMD_TABLE_DELETE_IN_RESERVED_LEN 2
25783/* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
25784 * data values. Each of these items is logically treated as a single wide N-bit
25785 * value, in which the individual fields have been placed within that value per
25786 * the LBN and WIDTH information from the table field descriptors. The wide
25787 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
25788 * multiple of 32 bits. The value is then packed into this command as a
25789 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
25790 */
25791#define MC_CMD_TABLE_DELETE_IN_DATA_OFST 12
25792#define MC_CMD_TABLE_DELETE_IN_DATA_LEN 4
25793#define MC_CMD_TABLE_DELETE_IN_DATA_MINNUM 1
25794#define MC_CMD_TABLE_DELETE_IN_DATA_MAXNUM 60
25795#define MC_CMD_TABLE_DELETE_IN_DATA_MAXNUM_MCDI2 252
25796
25797/* MC_CMD_TABLE_DELETE_OUT msgresponse */
25798#define MC_CMD_TABLE_DELETE_OUT_LEN 0
25799
25800/* MC_CMD_QUEUE_HANDLE structuredef: On X4, to distinguish between full-
25801 * featured (X2-style) VIs and low-latency (X3-style) queues, we use the top
25802 * bits of the queue handle to specify the queue type in all MCDI calls which
25803 * refer to VIs/queues. These bits should be masked off when indexing into a
25804 * queue in the BAR.
25805 */
25806#define MC_CMD_QUEUE_HANDLE_LEN 4
25807/* Combined queue number and type. This is the ID returned by and passed into
25808 * MCDI calls that use queues.
25809 */
25810#define MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_OFST 0
25811#define MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_LEN 4
25812#define MC_CMD_QUEUE_HANDLE_QUEUE_NUM_OFST 0
25813#define MC_CMD_QUEUE_HANDLE_QUEUE_NUM_LBN 0
25814#define MC_CMD_QUEUE_HANDLE_QUEUE_NUM_WIDTH 24
25815#define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_OFST 0
25816#define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LBN 24
25817#define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_WIDTH 8
25818/* enum: Indicates that the queue instance is a full-featured VI */
25819#define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_FF_VI 0x0
25820/* enum: Indicates that the queue instance is a LL TXQ */
25821#define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_TXQ 0x1
25822/* enum: Indicates that the queue instance is a LL RXQ */
25823#define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_RXQ 0x2
25824/* enum: Indicates that the queue instance is a LL EVQ */
25825#define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_EVQ 0x3
25826#define MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_LBN 0
25827#define MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_WIDTH 32
25828
25829
25830/***********************************/
25831/* MC_CMD_ALLOC_LL_QUEUES
25832 * Allocate low latency (X3-style) queues for current PCI function. Can be
25833 * called more than once if desired to allocate more queues.
25834 */
25835#define MC_CMD_ALLOC_LL_QUEUES 0x1dd
25836#undef MC_CMD_0x1dd_PRIVILEGE_CTG
25837
25838#define MC_CMD_0x1dd_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25839
25840/* MC_CMD_ALLOC_LL_QUEUES_IN msgrequest */
25841#define MC_CMD_ALLOC_LL_QUEUES_IN_LEN 24
25842/* The minimum number of TXQs that is acceptable */
25843#define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_TXQ_COUNT_OFST 0
25844#define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_TXQ_COUNT_LEN 4
25845/* The maximum number of TXQs that would be useful */
25846#define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_TXQ_COUNT_OFST 4
25847#define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_TXQ_COUNT_LEN 4
25848/* The minimum number of RXQs that is acceptable */
25849#define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_RXQ_COUNT_OFST 8
25850#define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_RXQ_COUNT_LEN 4
25851/* The maximum number of RXQs that would be useful */
25852#define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_RXQ_COUNT_OFST 12
25853#define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_RXQ_COUNT_LEN 4
25854/* The minimum number of EVQs that is acceptable */
25855#define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_EVQ_COUNT_OFST 16
25856#define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_EVQ_COUNT_LEN 4
25857/* The maximum number of EVQs that would be useful */
25858#define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_EVQ_COUNT_OFST 20
25859#define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_EVQ_COUNT_LEN 4
25860
25861/* MC_CMD_ALLOC_LL_QUEUES_OUT msgresponse */
25862#define MC_CMD_ALLOC_LL_QUEUES_OUT_LENMIN 16
25863#define MC_CMD_ALLOC_LL_QUEUES_OUT_LENMAX 252
25864#define MC_CMD_ALLOC_LL_QUEUES_OUT_LENMAX_MCDI2 1020
25865#define MC_CMD_ALLOC_LL_QUEUES_OUT_LEN(num) (12+4*(num))
25866#define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_NUM(len) (((len)-12)/4)
25867/* The number of TXQs allocated in this request */
25868#define MC_CMD_ALLOC_LL_QUEUES_OUT_TXQ_COUNT_OFST 0
25869#define MC_CMD_ALLOC_LL_QUEUES_OUT_TXQ_COUNT_LEN 4
25870/* The number of RXQs allocated in this request */
25871#define MC_CMD_ALLOC_LL_QUEUES_OUT_RXQ_COUNT_OFST 4
25872#define MC_CMD_ALLOC_LL_QUEUES_OUT_RXQ_COUNT_LEN 4
25873/* The number of EVQs allocated in this request */
25874#define MC_CMD_ALLOC_LL_QUEUES_OUT_EVQ_COUNT_OFST 8
25875#define MC_CMD_ALLOC_LL_QUEUES_OUT_EVQ_COUNT_LEN 4
25876/* A list of allocated queues, returned as MC_CMD_QUEUE_HANDLEs, not
25877 * necessarily contiguous. TXQs are first in the list, followed by RXQs then
25878 * EVQs. The type of each queue is indicated by the top bits (see the
25879 * QUEUE_TYPE enum)
25880 */
25881#define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_OFST 12
25882#define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_LEN 4
25883#define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MINNUM 1
25884#define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MAXNUM 60
25885#define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_MAXNUM_MCDI2 252
25886
25887
25888/***********************************/
25889/* MC_CMD_FREE_LL_QUEUES
25890 * Free low latency (X3-style) queues for current PCI function.
25891 */
25892#define MC_CMD_FREE_LL_QUEUES 0x1de
25893#undef MC_CMD_0x1de_PRIVILEGE_CTG
25894
25895#define MC_CMD_0x1de_PRIVILEGE_CTG SRIOV_CTG_GENERAL
25896
25897/* MC_CMD_FREE_LL_QUEUES_IN msgrequest */
25898#define MC_CMD_FREE_LL_QUEUES_IN_LENMIN 8
25899#define MC_CMD_FREE_LL_QUEUES_IN_LENMAX 252
25900#define MC_CMD_FREE_LL_QUEUES_IN_LENMAX_MCDI2 1020
25901#define MC_CMD_FREE_LL_QUEUES_IN_LEN(num) (4+4*(num))
25902#define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_NUM(len) (((len)-4)/4)
25903/* The number of queues to free. */
25904#define MC_CMD_FREE_LL_QUEUES_IN_QUEUE_COUNT_OFST 0
25905#define MC_CMD_FREE_LL_QUEUES_IN_QUEUE_COUNT_LEN 4
25906/* A list of queues to free, as a list of MC_CMD_QUEUE_HANDLEs. They must have
25907 * all been previously allocated by MC_CMD_ALLOC_LL_QUEUES. The type of each
25908 * queue should be indicated by the top bits.
25909 */
25910#define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_OFST 4
25911#define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_LEN 4
25912#define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MINNUM 1
25913#define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MAXNUM 62
25914#define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_MAXNUM_MCDI2 254
25915
25916/* MC_CMD_FREE_LL_QUEUES_OUT msgresponse */
25917#define MC_CMD_FREE_LL_QUEUES_OUT_LEN 0
25918
25919
25920#endif /* MCDI_PCOL_H */
25921

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source code of linux/drivers/net/ethernet/sfc/mcdi_pcol.h