1/* SPDX-License-Identifier: GPL-2.0-only */
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
6 */
7
8
9#ifndef MCDI_PCOL_H
10#define MCDI_PCOL_H
11
12/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
13/* Power-on reset state */
14#define MC_FW_STATE_POR (1)
15/* If this is set in MC_RESET_STATE_REG then it should be
16 * possible to jump into IMEM without loading code from flash. */
17#define MC_FW_WARM_BOOT_OK (2)
18/* The MC main image has started to boot. */
19#define MC_FW_STATE_BOOTING (4)
20/* The Scheduler has started. */
21#define MC_FW_STATE_SCHED (8)
22/* If this is set in MC_RESET_STATE_REG then it should be
23 * possible to jump into IMEM without loading code from flash.
24 * Unlike a warm boot, assume DMEM has been reloaded, so that
25 * the MC persistent data must be reinitialised. */
26#define MC_FW_TEPID_BOOT_OK (16)
27/* We have entered the main firmware via recovery mode. This
28 * means that MC persistent data must be reinitialised, but that
29 * we shouldn't touch PCIe config. */
30#define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)
31/* BIST state has been initialized */
32#define MC_FW_BIST_INIT_OK (128)
33
34/* Siena MC shared memmory offsets */
35/* The 'doorbell' addresses are hard-wired to alert the MC when written */
36#define MC_SMEM_P0_DOORBELL_OFST 0x000
37#define MC_SMEM_P1_DOORBELL_OFST 0x004
38/* The rest of these are firmware-defined */
39#define MC_SMEM_P0_PDU_OFST 0x008
40#define MC_SMEM_P1_PDU_OFST 0x108
41#define MC_SMEM_PDU_LEN 0x100
42#define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
43#define MC_SMEM_P0_STATUS_OFST 0x7f8
44#define MC_SMEM_P1_STATUS_OFST 0x7fc
45
46/* Values to be written to the per-port status dword in shared
47 * memory on reboot and assert */
48#define MC_STATUS_DWORD_REBOOT (0xb007b007)
49#define MC_STATUS_DWORD_ASSERT (0xdeaddead)
50
51/* Check whether an mcfw version (in host order) belongs to a bootloader */
52#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
53
54/* The current version of the MCDI protocol.
55 *
56 * Note that the ROM burnt into the card only talks V0, so at the very
57 * least every driver must support version 0 and MCDI_PCOL_VERSION
58 */
59#define MCDI_PCOL_VERSION 2
60
61/* Unused commands: 0x23, 0x27, 0x30, 0x31 */
62
63/* MCDI version 1
64 *
65 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
66 * structure, filled in by the client.
67 *
68 * 0 7 8 16 20 22 23 24 31
69 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
70 * | | |
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
74 *
75 * The client writes it's request into MC shared memory, and rings the
76 * doorbell. Each request is completed by either by the MC writing
77 * back into shared memory, or by writing out an event.
78 *
79 * All MCDI commands support completion by shared memory response. Each
80 * request may also contain additional data (accounted for by HEADER.LEN),
81 * and some response's may also contain additional data (again, accounted
82 * for by HEADER.LEN).
83 *
84 * Some MCDI commands support completion by event, in which any associated
85 * response data is included in the event.
86 *
87 * The protocol requires one response to be delivered for every request, a
88 * request should not be sent unless the response for the previous request
89 * has been received (either by polling shared memory, or by receiving
90 * an event).
91 */
92
93/** Request/Response structure */
94#define MCDI_HEADER_OFST 0
95#define MCDI_HEADER_CODE_LBN 0
96#define MCDI_HEADER_CODE_WIDTH 7
97#define MCDI_HEADER_RESYNC_LBN 7
98#define MCDI_HEADER_RESYNC_WIDTH 1
99#define MCDI_HEADER_DATALEN_LBN 8
100#define MCDI_HEADER_DATALEN_WIDTH 8
101#define MCDI_HEADER_SEQ_LBN 16
102#define MCDI_HEADER_SEQ_WIDTH 4
103#define MCDI_HEADER_RSVD_LBN 20
104#define MCDI_HEADER_RSVD_WIDTH 1
105#define MCDI_HEADER_NOT_EPOCH_LBN 21
106#define MCDI_HEADER_NOT_EPOCH_WIDTH 1
107#define MCDI_HEADER_ERROR_LBN 22
108#define MCDI_HEADER_ERROR_WIDTH 1
109#define MCDI_HEADER_RESPONSE_LBN 23
110#define MCDI_HEADER_RESPONSE_WIDTH 1
111#define MCDI_HEADER_XFLAGS_LBN 24
112#define MCDI_HEADER_XFLAGS_WIDTH 8
113/* Request response using event */
114#define MCDI_HEADER_XFLAGS_EVREQ 0x01
115/* Request (and signal) early doorbell return */
116#define MCDI_HEADER_XFLAGS_DBRET 0x02
117
118/* Maximum number of payload bytes */
119#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
120#define MCDI_CTL_SDU_LEN_MAX_V2 0x400
121
122#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
123
124
125/* The MC can generate events for two reasons:
126 * - To advance a shared memory request if XFLAGS_EVREQ was set
127 * - As a notification (link state, i2c event), controlled
128 * via MC_CMD_LOG_CTRL
129 *
130 * Both events share a common structure:
131 *
132 * 0 32 33 36 44 52 60
133 * | Data | Cont | Level | Src | Code | Rsvd |
134 * |
135 * \ There is another event pending in this notification
136 *
137 * If Code==CMDDONE, then the fields are further interpreted as:
138 *
139 * - LEVEL==INFO Command succeeded
140 * - LEVEL==ERR Command failed
141 *
142 * 0 8 16 24 32
143 * | Seq | Datalen | Errno | Rsvd |
144 *
145 * These fields are taken directly out of the standard MCDI header, i.e.,
146 * LEVEL==ERR, Datalen == 0 => Reboot
147 *
148 * Events can be squirted out of the UART (using LOG_CTRL) without a
149 * MCDI header. An event can be distinguished from a MCDI response by
150 * examining the first byte which is 0xc0. This corresponds to the
151 * non-existent MCDI command MC_CMD_DEBUG_LOG.
152 *
153 * 0 7 8
154 * | command | Resync | = 0xc0
155 *
156 * Since the event is written in big-endian byte order, this works
157 * providing bits 56-63 of the event are 0xc0.
158 *
159 * 56 60 63
160 * | Rsvd | Code | = 0xc0
161 *
162 * Which means for convenience the event code is 0xc for all MC
163 * generated events.
164 */
165#define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
166
167
168/* Operation not permitted. */
169#define MC_CMD_ERR_EPERM 1
170/* Non-existent command target */
171#define MC_CMD_ERR_ENOENT 2
172/* assert() has killed the MC */
173#define MC_CMD_ERR_EINTR 4
174/* I/O failure */
175#define MC_CMD_ERR_EIO 5
176/* Already exists */
177#define MC_CMD_ERR_EEXIST 6
178/* Try again */
179#define MC_CMD_ERR_EAGAIN 11
180/* Out of memory */
181#define MC_CMD_ERR_ENOMEM 12
182/* Caller does not hold required locks */
183#define MC_CMD_ERR_EACCES 13
184/* Resource is currently unavailable (e.g. lock contention) */
185#define MC_CMD_ERR_EBUSY 16
186/* No such device */
187#define MC_CMD_ERR_ENODEV 19
188/* Invalid argument to target */
189#define MC_CMD_ERR_EINVAL 22
190/* Broken pipe */
191#define MC_CMD_ERR_EPIPE 32
192/* Read-only */
193#define MC_CMD_ERR_EROFS 30
194/* Out of range */
195#define MC_CMD_ERR_ERANGE 34
196/* Non-recursive resource is already acquired */
197#define MC_CMD_ERR_EDEADLK 35
198/* Operation not implemented */
199#define MC_CMD_ERR_ENOSYS 38
200/* Operation timed out */
201#define MC_CMD_ERR_ETIME 62
202/* Link has been severed */
203#define MC_CMD_ERR_ENOLINK 67
204/* Protocol error */
205#define MC_CMD_ERR_EPROTO 71
206/* Operation not supported */
207#define MC_CMD_ERR_ENOTSUP 95
208/* Address not available */
209#define MC_CMD_ERR_EADDRNOTAVAIL 99
210/* Not connected */
211#define MC_CMD_ERR_ENOTCONN 107
212/* Operation already in progress */
213#define MC_CMD_ERR_EALREADY 114
214
215/* Resource allocation failed. */
216#define MC_CMD_ERR_ALLOC_FAIL 0x1000
217/* V-adaptor not found. */
218#define MC_CMD_ERR_NO_VADAPTOR 0x1001
219/* EVB port not found. */
220#define MC_CMD_ERR_NO_EVB_PORT 0x1002
221/* V-switch not found. */
222#define MC_CMD_ERR_NO_VSWITCH 0x1003
223/* Too many VLAN tags. */
224#define MC_CMD_ERR_VLAN_LIMIT 0x1004
225/* Bad PCI function number. */
226#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
227/* Invalid VLAN mode. */
228#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
229/* Invalid v-switch type. */
230#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
231/* Invalid v-port type. */
232#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
233/* MAC address exists. */
234#define MC_CMD_ERR_MAC_EXIST 0x1009
235/* Slave core not present */
236#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
237/* The datapath is disabled. */
238#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
239/* The requesting client is not a function */
240#define MC_CMD_ERR_CLIENT_NOT_FN 0x100c
241/* The requested operation might require the
242 command to be passed between MCs, and the
243 transport doesn't support that. Should
244 only ever been seen over the UART. */
245#define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
246/* VLAN tag(s) exists */
247#define MC_CMD_ERR_VLAN_EXIST 0x100e
248/* No MAC address assigned to an EVB port */
249#define MC_CMD_ERR_NO_MAC_ADDR 0x100f
250/* Notifies the driver that the request has been relayed
251 * to an admin function for authorization. The driver should
252 * wait for a PROXY_RESPONSE event and then resend its request.
253 * This error code is followed by a 32-bit handle that
254 * helps matching it with the respective PROXY_RESPONSE event. */
255#define MC_CMD_ERR_PROXY_PENDING 0x1010
256#define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
257/* The request cannot be passed for authorization because
258 * another request from the same function is currently being
259 * authorized. The drvier should try again later. */
260#define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
261/* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function
262 * that has enabled proxying or BLOCK_INDEX points to a function that
263 * doesn't await an authorization. */
264#define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
265/* This code is currently only used internally in FW. Its meaning is that
266 * an operation failed due to lack of SR-IOV privilege.
267 * Normally it is translated to EPERM by send_cmd_err(),
268 * but it may also be used to trigger some special mechanism
269 * for handling such case, e.g. to relay the failed request
270 * to a designated admin function for authorization. */
271#define MC_CMD_ERR_NO_PRIVILEGE 0x1013
272/* Workaround 26807 could not be turned on/off because some functions
273 * have already installed filters. See the comment at
274 * MC_CMD_WORKAROUND_BUG26807.
275 * May also returned for other operations such as sub-variant switching. */
276#define MC_CMD_ERR_FILTERS_PRESENT 0x1014
277/* The clock whose frequency you've attempted to set
278 * doesn't exist on this NIC */
279#define MC_CMD_ERR_NO_CLOCK 0x1015
280/* Returned by MC_CMD_TESTASSERT if the action that should
281 * have caused an assertion failed to do so. */
282#define MC_CMD_ERR_UNREACHABLE 0x1016
283/* This command needs to be processed in the background but there were no
284 * resources to do so. Send it again after a command has completed. */
285#define MC_CMD_ERR_QUEUE_FULL 0x1017
286/* The operation could not be completed because the PCIe link has gone
287 * away. This error code is never expected to be returned over the TLP
288 * transport. */
289#define MC_CMD_ERR_NO_PCIE 0x1018
290/* The operation could not be completed because the datapath has gone
291 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
292 * datapath absence may be temporary*/
293#define MC_CMD_ERR_NO_DATAPATH 0x1019
294/* The operation could not complete because some VIs are allocated */
295#define MC_CMD_ERR_VIS_PRESENT 0x101a
296/* The operation could not complete because some PIO buffers are allocated */
297#define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
298
299#define MC_CMD_ERR_CODE_OFST 0
300
301/* We define 8 "escape" commands to allow
302 for command number space extension */
303
304#define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
305#define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
306#define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
307#define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
308#define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
309#define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
310#define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
311#define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
312
313/* Vectors in the boot ROM */
314/* Point to the copycode entry point. */
315#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
316#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
317#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
318/* Points to the recovery mode entry point. Misnamed but kept for compatibility. */
319#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
320#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
321#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
322/* Points to the recovery mode entry point. Same as above, but the right name. */
323#define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
324#define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
325#define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
326
327/* Points to noflash mode entry point. */
328#define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
329
330/* The command set exported by the boot ROM (MCDI v0) */
331#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \
332 (1 << MC_CMD_READ32) | \
333 (1 << MC_CMD_WRITE32) | \
334 (1 << MC_CMD_COPYCODE) | \
335 (1 << MC_CMD_GET_VERSION), \
336 0, 0, 0 }
337
338#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
339 (MC_CMD_SENSOR_ENTRY_OFST + (_x))
340
341#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \
342 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
343 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \
344 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
345
346#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \
347 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
348 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \
349 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
350
351#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \
352 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
353 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \
354 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
355
356/* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
357 * stack ID (which must be in the range 1-255) along with an EVB port ID.
358 */
359#define EVB_STACK_ID(n) (((n) & 0xff) << 16)
360
361
362/* Version 2 adds an optional argument to error returns: the errno value
363 * may be followed by the (0-based) number of the first argument that
364 * could not be processed.
365 */
366#define MC_CMD_ERR_ARG_OFST 4
367
368/* No space */
369#define MC_CMD_ERR_ENOSPC 28
370
371/* MCDI_EVENT structuredef */
372#define MCDI_EVENT_LEN 8
373#define MCDI_EVENT_CONT_LBN 32
374#define MCDI_EVENT_CONT_WIDTH 1
375#define MCDI_EVENT_LEVEL_LBN 33
376#define MCDI_EVENT_LEVEL_WIDTH 3
377/* enum: Info. */
378#define MCDI_EVENT_LEVEL_INFO 0x0
379/* enum: Warning. */
380#define MCDI_EVENT_LEVEL_WARN 0x1
381/* enum: Error. */
382#define MCDI_EVENT_LEVEL_ERR 0x2
383/* enum: Fatal. */
384#define MCDI_EVENT_LEVEL_FATAL 0x3
385#define MCDI_EVENT_DATA_OFST 0
386#define MCDI_EVENT_DATA_LEN 4
387#define MCDI_EVENT_CMDDONE_SEQ_OFST 0
388#define MCDI_EVENT_CMDDONE_SEQ_LBN 0
389#define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
390#define MCDI_EVENT_CMDDONE_DATALEN_OFST 0
391#define MCDI_EVENT_CMDDONE_DATALEN_LBN 8
392#define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
393#define MCDI_EVENT_CMDDONE_ERRNO_OFST 0
394#define MCDI_EVENT_CMDDONE_ERRNO_LBN 16
395#define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
396#define MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0
397#define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
398#define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
399#define MCDI_EVENT_LINKCHANGE_SPEED_OFST 0
400#define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
401#define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
402/* enum: Link is down or link speed could not be determined */
403#define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
404/* enum: 100Mbs */
405#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
406/* enum: 1Gbs */
407#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
408/* enum: 10Gbs */
409#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
410/* enum: 40Gbs */
411#define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
412/* enum: 25Gbs */
413#define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
414/* enum: 50Gbs */
415#define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
416/* enum: 100Gbs */
417#define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
418#define MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0
419#define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
420#define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
421#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0
422#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
423#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
424#define MCDI_EVENT_SENSOREVT_MONITOR_OFST 0
425#define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
426#define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
427#define MCDI_EVENT_SENSOREVT_STATE_OFST 0
428#define MCDI_EVENT_SENSOREVT_STATE_LBN 8
429#define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
430#define MCDI_EVENT_SENSOREVT_VALUE_OFST 0
431#define MCDI_EVENT_SENSOREVT_VALUE_LBN 16
432#define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
433#define MCDI_EVENT_FWALERT_DATA_OFST 0
434#define MCDI_EVENT_FWALERT_DATA_LBN 8
435#define MCDI_EVENT_FWALERT_DATA_WIDTH 24
436#define MCDI_EVENT_FWALERT_REASON_OFST 0
437#define MCDI_EVENT_FWALERT_REASON_LBN 0
438#define MCDI_EVENT_FWALERT_REASON_WIDTH 8
439/* enum: SRAM Access. */
440#define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
441#define MCDI_EVENT_FLR_VF_OFST 0
442#define MCDI_EVENT_FLR_VF_LBN 0
443#define MCDI_EVENT_FLR_VF_WIDTH 8
444#define MCDI_EVENT_TX_ERR_TXQ_OFST 0
445#define MCDI_EVENT_TX_ERR_TXQ_LBN 0
446#define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
447#define MCDI_EVENT_TX_ERR_TYPE_OFST 0
448#define MCDI_EVENT_TX_ERR_TYPE_LBN 12
449#define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
450/* enum: Descriptor loader reported failure */
451#define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
452/* enum: Descriptor ring empty and no EOP seen for packet */
453#define MCDI_EVENT_TX_ERR_NO_EOP 0x2
454/* enum: Overlength packet */
455#define MCDI_EVENT_TX_ERR_2BIG 0x3
456/* enum: Malformed option descriptor */
457#define MCDI_EVENT_TX_BAD_OPTDESC 0x5
458/* enum: Option descriptor part way through a packet */
459#define MCDI_EVENT_TX_OPT_IN_PKT 0x8
460/* enum: DMA or PIO data access error */
461#define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
462#define MCDI_EVENT_TX_ERR_INFO_OFST 0
463#define MCDI_EVENT_TX_ERR_INFO_LBN 16
464#define MCDI_EVENT_TX_ERR_INFO_WIDTH 16
465#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0
466#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
467#define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
468#define MCDI_EVENT_TX_FLUSH_TXQ_OFST 0
469#define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
470#define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
471#define MCDI_EVENT_PTP_ERR_TYPE_OFST 0
472#define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
473#define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
474/* enum: PLL lost lock */
475#define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
476/* enum: Filter overflow (PDMA) */
477#define MCDI_EVENT_PTP_ERR_FILTER 0x2
478/* enum: FIFO overflow (FPGA) */
479#define MCDI_EVENT_PTP_ERR_FIFO 0x3
480/* enum: Merge queue overflow */
481#define MCDI_EVENT_PTP_ERR_QUEUE 0x4
482#define MCDI_EVENT_AOE_ERR_TYPE_OFST 0
483#define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
484#define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
485/* enum: AOE failed to load - no valid image? */
486#define MCDI_EVENT_AOE_NO_LOAD 0x1
487/* enum: AOE FC reported an exception */
488#define MCDI_EVENT_AOE_FC_ASSERT 0x2
489/* enum: AOE FC watchdogged */
490#define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
491/* enum: AOE FC failed to start */
492#define MCDI_EVENT_AOE_FC_NO_START 0x4
493/* enum: Generic AOE fault - likely to have been reported via other means too
494 * but intended for use by aoex driver.
495 */
496#define MCDI_EVENT_AOE_FAULT 0x5
497/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
498#define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
499/* enum: AOE loaded successfully */
500#define MCDI_EVENT_AOE_LOAD 0x7
501/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
502#define MCDI_EVENT_AOE_DMA 0x8
503/* enum: AOE byteblaster connected/disconnected (Connection status in
504 * AOE_ERR_DATA)
505 */
506#define MCDI_EVENT_AOE_BYTEBLASTER 0x9
507/* enum: DDR ECC status update */
508#define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
509/* enum: PTP status update */
510#define MCDI_EVENT_AOE_PTP_STATUS 0xb
511/* enum: FPGA header incorrect */
512#define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
513/* enum: FPGA Powered Off due to error in powering up FPGA */
514#define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
515/* enum: AOE FPGA load failed due to MC to MUM communication failure */
516#define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
517/* enum: Notify that invalid flash type detected */
518#define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
519/* enum: Notify that the attempt to run FPGA Controller firmware timedout */
520#define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
521/* enum: Failure to probe one or more FPGA boot flash chips */
522#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
523/* enum: FPGA boot-flash contains an invalid image header */
524#define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
525/* enum: Failed to program clocks required by the FPGA */
526#define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
527/* enum: Notify that FPGA Controller is alive to serve MCDI requests */
528#define MCDI_EVENT_AOE_FC_RUNNING 0x14
529#define MCDI_EVENT_AOE_ERR_DATA_OFST 0
530#define MCDI_EVENT_AOE_ERR_DATA_LBN 8
531#define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
532#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0
533#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_LBN 8
534#define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_WIDTH 8
535/* enum: FC Assert happened, but the register information is not available */
536#define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
537/* enum: The register information for FC Assert is ready for readinng by driver
538 */
539#define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
540#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0
541#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_LBN 8
542#define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_WIDTH 8
543/* enum: Reading from NV failed */
544#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
545/* enum: Invalid Magic Number if FPGA header */
546#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
547/* enum: Invalid Silicon type detected in header */
548#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
549/* enum: Unsupported VRatio */
550#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
551/* enum: Unsupported DDR Type */
552#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
553/* enum: DDR Voltage out of supported range */
554#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
555/* enum: Unsupported DDR speed */
556#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
557/* enum: Unsupported DDR size */
558#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
559/* enum: Unsupported DDR rank */
560#define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
561#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0
562#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_LBN 8
563#define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_WIDTH 8
564/* enum: Primary boot flash */
565#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
566/* enum: Secondary boot flash */
567#define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
568#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0
569#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_LBN 8
570#define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_WIDTH 8
571#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0
572#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_LBN 8
573#define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_WIDTH 8
574#define MCDI_EVENT_RX_ERR_RXQ_OFST 0
575#define MCDI_EVENT_RX_ERR_RXQ_LBN 0
576#define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
577#define MCDI_EVENT_RX_ERR_TYPE_OFST 0
578#define MCDI_EVENT_RX_ERR_TYPE_LBN 12
579#define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
580#define MCDI_EVENT_RX_ERR_INFO_OFST 0
581#define MCDI_EVENT_RX_ERR_INFO_LBN 16
582#define MCDI_EVENT_RX_ERR_INFO_WIDTH 16
583#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0
584#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
585#define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
586#define MCDI_EVENT_RX_FLUSH_RXQ_OFST 0
587#define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
588#define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
589#define MCDI_EVENT_MC_REBOOT_COUNT_OFST 0
590#define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
591#define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
592#define MCDI_EVENT_MUM_ERR_TYPE_OFST 0
593#define MCDI_EVENT_MUM_ERR_TYPE_LBN 0
594#define MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8
595/* enum: MUM failed to load - no valid image? */
596#define MCDI_EVENT_MUM_NO_LOAD 0x1
597/* enum: MUM f/w reported an exception */
598#define MCDI_EVENT_MUM_ASSERT 0x2
599/* enum: MUM not kicking watchdog */
600#define MCDI_EVENT_MUM_WATCHDOG 0x3
601#define MCDI_EVENT_MUM_ERR_DATA_OFST 0
602#define MCDI_EVENT_MUM_ERR_DATA_LBN 8
603#define MCDI_EVENT_MUM_ERR_DATA_WIDTH 8
604#define MCDI_EVENT_DBRET_SEQ_OFST 0
605#define MCDI_EVENT_DBRET_SEQ_LBN 0
606#define MCDI_EVENT_DBRET_SEQ_WIDTH 8
607#define MCDI_EVENT_SUC_ERR_TYPE_OFST 0
608#define MCDI_EVENT_SUC_ERR_TYPE_LBN 0
609#define MCDI_EVENT_SUC_ERR_TYPE_WIDTH 8
610/* enum: Corrupted or bad SUC application. */
611#define MCDI_EVENT_SUC_BAD_APP 0x1
612/* enum: SUC application reported an assert. */
613#define MCDI_EVENT_SUC_ASSERT 0x2
614/* enum: SUC application reported an exception. */
615#define MCDI_EVENT_SUC_EXCEPTION 0x3
616/* enum: SUC watchdog timer expired. */
617#define MCDI_EVENT_SUC_WATCHDOG 0x4
618#define MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0
619#define MCDI_EVENT_SUC_ERR_ADDRESS_LBN 8
620#define MCDI_EVENT_SUC_ERR_ADDRESS_WIDTH 24
621#define MCDI_EVENT_SUC_ERR_DATA_OFST 0
622#define MCDI_EVENT_SUC_ERR_DATA_LBN 8
623#define MCDI_EVENT_SUC_ERR_DATA_WIDTH 24
624#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0
625#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0
626#define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_WIDTH 24
627#define MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0
628#define MCDI_EVENT_LINKCHANGE_V2_SPEED_LBN 24
629#define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4
630/* Enum values, see field(s): */
631/* MCDI_EVENT/LINKCHANGE_SPEED */
632#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0
633#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_LBN 28
634#define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_WIDTH 1
635#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0
636#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_LBN 29
637#define MCDI_EVENT_LINKCHANGE_V2_FCNTL_WIDTH 3
638/* Enum values, see field(s): */
639/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
640#define MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0
641#define MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0
642#define MCDI_EVENT_MODULECHANGE_LD_CAP_WIDTH 30
643#define MCDI_EVENT_MODULECHANGE_SEQ_OFST 0
644#define MCDI_EVENT_MODULECHANGE_SEQ_LBN 30
645#define MCDI_EVENT_MODULECHANGE_SEQ_WIDTH 2
646#define MCDI_EVENT_DATA_LBN 0
647#define MCDI_EVENT_DATA_WIDTH 32
648/* Alias for PTP_DATA. */
649#define MCDI_EVENT_SRC_LBN 36
650#define MCDI_EVENT_SRC_WIDTH 8
651/* Data associated with PTP events which doesn't fit into the main DATA field
652 */
653#define MCDI_EVENT_PTP_DATA_LBN 36
654#define MCDI_EVENT_PTP_DATA_WIDTH 8
655/* EF100 specific. Defined by QDMA. The phase bit, changes each time round the
656 * event ring
657 */
658#define MCDI_EVENT_EV_EVQ_PHASE_LBN 59
659#define MCDI_EVENT_EV_EVQ_PHASE_WIDTH 1
660#define MCDI_EVENT_EV_CODE_LBN 60
661#define MCDI_EVENT_EV_CODE_WIDTH 4
662#define MCDI_EVENT_CODE_LBN 44
663#define MCDI_EVENT_CODE_WIDTH 8
664/* enum: Event generated by host software */
665#define MCDI_EVENT_SW_EVENT 0x0
666/* enum: Bad assert. */
667#define MCDI_EVENT_CODE_BADSSERT 0x1
668/* enum: PM Notice. */
669#define MCDI_EVENT_CODE_PMNOTICE 0x2
670/* enum: Command done. */
671#define MCDI_EVENT_CODE_CMDDONE 0x3
672/* enum: Link change. */
673#define MCDI_EVENT_CODE_LINKCHANGE 0x4
674/* enum: Sensor Event. */
675#define MCDI_EVENT_CODE_SENSOREVT 0x5
676/* enum: Schedule error. */
677#define MCDI_EVENT_CODE_SCHEDERR 0x6
678/* enum: Reboot. */
679#define MCDI_EVENT_CODE_REBOOT 0x7
680/* enum: Mac stats DMA. */
681#define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
682/* enum: Firmware alert. */
683#define MCDI_EVENT_CODE_FWALERT 0x9
684/* enum: Function level reset. */
685#define MCDI_EVENT_CODE_FLR 0xa
686/* enum: Transmit error */
687#define MCDI_EVENT_CODE_TX_ERR 0xb
688/* enum: Tx flush has completed */
689#define MCDI_EVENT_CODE_TX_FLUSH 0xc
690/* enum: PTP packet received timestamp */
691#define MCDI_EVENT_CODE_PTP_RX 0xd
692/* enum: PTP NIC failure */
693#define MCDI_EVENT_CODE_PTP_FAULT 0xe
694/* enum: PTP PPS event */
695#define MCDI_EVENT_CODE_PTP_PPS 0xf
696/* enum: Rx flush has completed */
697#define MCDI_EVENT_CODE_RX_FLUSH 0x10
698/* enum: Receive error */
699#define MCDI_EVENT_CODE_RX_ERR 0x11
700/* enum: AOE fault */
701#define MCDI_EVENT_CODE_AOE 0x12
702/* enum: Network port calibration failed (VCAL). */
703#define MCDI_EVENT_CODE_VCAL_FAIL 0x13
704/* enum: HW PPS event */
705#define MCDI_EVENT_CODE_HW_PPS 0x14
706/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
707 * a different format)
708 */
709#define MCDI_EVENT_CODE_MC_REBOOT 0x15
710/* enum: the MC has detected a parity error */
711#define MCDI_EVENT_CODE_PAR_ERR 0x16
712/* enum: the MC has detected a correctable error */
713#define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
714/* enum: the MC has detected an uncorrectable error */
715#define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
716/* enum: The MC has entered offline BIST mode */
717#define MCDI_EVENT_CODE_MC_BIST 0x19
718/* enum: PTP tick event providing current NIC time */
719#define MCDI_EVENT_CODE_PTP_TIME 0x1a
720/* enum: MUM fault */
721#define MCDI_EVENT_CODE_MUM 0x1b
722/* enum: notify the designated PF of a new authorization request */
723#define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
724/* enum: notify a function that awaits an authorization that its request has
725 * been processed and it may now resend the command
726 */
727#define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
728/* enum: MCDI command accepted. New commands can be issued but this command is
729 * not done yet.
730 */
731#define MCDI_EVENT_CODE_DBRET 0x1e
732/* enum: The MC has detected a fault on the SUC */
733#define MCDI_EVENT_CODE_SUC 0x1f
734/* enum: Link change. This event is sent instead of LINKCHANGE if
735 * WANT_V2_LINKCHANGES was set on driver attach.
736 */
737#define MCDI_EVENT_CODE_LINKCHANGE_V2 0x20
738/* enum: This event is sent if WANT_V2_LINKCHANGES was set on driver attach
739 * when the local device capabilities changes. This will usually correspond to
740 * a module change.
741 */
742#define MCDI_EVENT_CODE_MODULECHANGE 0x21
743/* enum: Notification that the sensors have been added and/or removed from the
744 * sensor table. This event includes the new sensor table generation count, if
745 * this does not match the driver's local copy it is expected to call
746 * DYNAMIC_SENSORS_LIST to refresh it.
747 */
748#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22
749/* enum: Notification that a sensor has changed state as a result of a reading
750 * crossing a threshold. This is sent as two events, the first event contains
751 * the handle and the sensor's state (in the SRC field), and the second
752 * contains the value.
753 */
754#define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23
755/* enum: Notification that a descriptor proxy function configuration has been
756 * pushed to "live" status (visible to host). SRC field contains the handle of
757 * the affected descriptor proxy function. DATA field contains the generation
758 * count of configuration set applied. See MC_CMD_DESC_PROXY_FUNC_CONFIG_SET /
759 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.
760 */
761#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24
762/* enum: Notification that a descriptor proxy function has been reset. SRC
763 * field contains the handle of the affected descriptor proxy function. See
764 * SF-122927-TC for details.
765 */
766#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25
767/* enum: Notification that a driver attached to a descriptor proxy function.
768 * SRC field contains the handle of the affected descriptor proxy function. For
769 * Virtio proxy functions this message consists of two MCDI events, where the
770 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0
771 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy
772 * functions event length and meaning of DATA field is not yet defined. See
773 * SF-122927-TC for details.
774 */
775#define MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26
776/* enum: Artificial event generated by host and posted via MC for test
777 * purposes.
778 */
779#define MCDI_EVENT_CODE_TESTGEN 0xfa
780#define MCDI_EVENT_CMDDONE_DATA_OFST 0
781#define MCDI_EVENT_CMDDONE_DATA_LEN 4
782#define MCDI_EVENT_CMDDONE_DATA_LBN 0
783#define MCDI_EVENT_CMDDONE_DATA_WIDTH 32
784#define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
785#define MCDI_EVENT_LINKCHANGE_DATA_LEN 4
786#define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
787#define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
788#define MCDI_EVENT_SENSOREVT_DATA_OFST 0
789#define MCDI_EVENT_SENSOREVT_DATA_LEN 4
790#define MCDI_EVENT_SENSOREVT_DATA_LBN 0
791#define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
792#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
793#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
794#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
795#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
796#define MCDI_EVENT_TX_ERR_DATA_OFST 0
797#define MCDI_EVENT_TX_ERR_DATA_LEN 4
798#define MCDI_EVENT_TX_ERR_DATA_LBN 0
799#define MCDI_EVENT_TX_ERR_DATA_WIDTH 32
800/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of
801 * timestamp
802 */
803#define MCDI_EVENT_PTP_SECONDS_OFST 0
804#define MCDI_EVENT_PTP_SECONDS_LEN 4
805#define MCDI_EVENT_PTP_SECONDS_LBN 0
806#define MCDI_EVENT_PTP_SECONDS_WIDTH 32
807/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of
808 * timestamp
809 */
810#define MCDI_EVENT_PTP_MAJOR_OFST 0
811#define MCDI_EVENT_PTP_MAJOR_LEN 4
812#define MCDI_EVENT_PTP_MAJOR_LBN 0
813#define MCDI_EVENT_PTP_MAJOR_WIDTH 32
814/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field
815 * of timestamp
816 */
817#define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
818#define MCDI_EVENT_PTP_NANOSECONDS_LEN 4
819#define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
820#define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
821/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of
822 * timestamp
823 */
824#define MCDI_EVENT_PTP_MINOR_OFST 0
825#define MCDI_EVENT_PTP_MINOR_LEN 4
826#define MCDI_EVENT_PTP_MINOR_LBN 0
827#define MCDI_EVENT_PTP_MINOR_WIDTH 32
828/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
829 */
830#define MCDI_EVENT_PTP_UUID_OFST 0
831#define MCDI_EVENT_PTP_UUID_LEN 4
832#define MCDI_EVENT_PTP_UUID_LBN 0
833#define MCDI_EVENT_PTP_UUID_WIDTH 32
834#define MCDI_EVENT_RX_ERR_DATA_OFST 0
835#define MCDI_EVENT_RX_ERR_DATA_LEN 4
836#define MCDI_EVENT_RX_ERR_DATA_LBN 0
837#define MCDI_EVENT_RX_ERR_DATA_WIDTH 32
838#define MCDI_EVENT_PAR_ERR_DATA_OFST 0
839#define MCDI_EVENT_PAR_ERR_DATA_LEN 4
840#define MCDI_EVENT_PAR_ERR_DATA_LBN 0
841#define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
842#define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
843#define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
844#define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
845#define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
846#define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
847#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
848#define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
849#define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
850/* For CODE_PTP_TIME events, the major value of the PTP clock */
851#define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
852#define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
853#define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
854#define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32
855/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
856#define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36
857#define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8
858/* For CODE_PTP_TIME events, most significant bits of the minor value of the
859 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_19.
860 */
861#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_LBN 36
862#define MCDI_EVENT_PTP_TIME_MINOR_MS_8BITS_WIDTH 8
863/* For CODE_PTP_TIME events where report sync status is enabled, indicates
864 * whether the NIC clock has ever been set
865 */
866#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36
867#define MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
868/* For CODE_PTP_TIME events where report sync status is enabled, indicates
869 * whether the NIC and System clocks are in sync
870 */
871#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37
872#define MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
873/* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
874 * the minor value of the PTP clock
875 */
876#define MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38
877#define MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6
878/* For CODE_PTP_TIME events, most significant bits of the minor value of the
879 * PTP clock. This is a more generic equivalent of PTP_TIME_MINOR_26_21.
880 */
881#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_LBN 38
882#define MCDI_EVENT_PTP_TIME_MINOR_MS_6BITS_WIDTH 6
883#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
884#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
885#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
886#define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32
887#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
888#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
889#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
890#define MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32
891/* Zero means that the request has been completed or authorized, and the driver
892 * should resend it. A non-zero value means that the authorization has been
893 * denied, and gives the reason. Typically it will be EPERM.
894 */
895#define MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36
896#define MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8
897#define MCDI_EVENT_DBRET_DATA_OFST 0
898#define MCDI_EVENT_DBRET_DATA_LEN 4
899#define MCDI_EVENT_DBRET_DATA_LBN 0
900#define MCDI_EVENT_DBRET_DATA_WIDTH 32
901#define MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0
902#define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4
903#define MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0
904#define MCDI_EVENT_LINKCHANGE_V2_DATA_WIDTH 32
905#define MCDI_EVENT_MODULECHANGE_DATA_OFST 0
906#define MCDI_EVENT_MODULECHANGE_DATA_LEN 4
907#define MCDI_EVENT_MODULECHANGE_DATA_LBN 0
908#define MCDI_EVENT_MODULECHANGE_DATA_WIDTH 32
909/* The new generation count after a sensor has been added or deleted. */
910#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0
911#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4
912#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0
913#define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_WIDTH 32
914/* The handle of a dynamic sensor. */
915#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0
916#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4
917#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0
918#define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_WIDTH 32
919/* The current values of a sensor. */
920#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0
921#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4
922#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0
923#define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_WIDTH 32
924/* The current state of a sensor. */
925#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_LBN 36
926#define MCDI_EVENT_DYNAMIC_SENSORS_STATE_WIDTH 8
927#define MCDI_EVENT_DESC_PROXY_DATA_OFST 0
928#define MCDI_EVENT_DESC_PROXY_DATA_LEN 4
929#define MCDI_EVENT_DESC_PROXY_DATA_LBN 0
930#define MCDI_EVENT_DESC_PROXY_DATA_WIDTH 32
931/* Generation count of applied configuration set */
932#define MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0
933#define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4
934#define MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0
935#define MCDI_EVENT_DESC_PROXY_GENERATION_WIDTH 32
936/* Virtio features negotiated with the host driver. First event (CONT=1)
937 * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.
938 */
939#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0
940#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4
941#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0
942#define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_WIDTH 32
943
944/* FCDI_EVENT structuredef */
945#define FCDI_EVENT_LEN 8
946#define FCDI_EVENT_CONT_LBN 32
947#define FCDI_EVENT_CONT_WIDTH 1
948#define FCDI_EVENT_LEVEL_LBN 33
949#define FCDI_EVENT_LEVEL_WIDTH 3
950/* enum: Info. */
951#define FCDI_EVENT_LEVEL_INFO 0x0
952/* enum: Warning. */
953#define FCDI_EVENT_LEVEL_WARN 0x1
954/* enum: Error. */
955#define FCDI_EVENT_LEVEL_ERR 0x2
956/* enum: Fatal. */
957#define FCDI_EVENT_LEVEL_FATAL 0x3
958#define FCDI_EVENT_DATA_OFST 0
959#define FCDI_EVENT_DATA_LEN 4
960#define FCDI_EVENT_LINK_STATE_STATUS_OFST 0
961#define FCDI_EVENT_LINK_STATE_STATUS_LBN 0
962#define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
963#define FCDI_EVENT_LINK_DOWN 0x0 /* enum */
964#define FCDI_EVENT_LINK_UP 0x1 /* enum */
965#define FCDI_EVENT_DATA_LBN 0
966#define FCDI_EVENT_DATA_WIDTH 32
967#define FCDI_EVENT_SRC_LBN 36
968#define FCDI_EVENT_SRC_WIDTH 8
969#define FCDI_EVENT_EV_CODE_LBN 60
970#define FCDI_EVENT_EV_CODE_WIDTH 4
971#define FCDI_EVENT_CODE_LBN 44
972#define FCDI_EVENT_CODE_WIDTH 8
973/* enum: The FC was rebooted. */
974#define FCDI_EVENT_CODE_REBOOT 0x1
975/* enum: Bad assert. */
976#define FCDI_EVENT_CODE_ASSERT 0x2
977/* enum: DDR3 test result. */
978#define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
979/* enum: Link status. */
980#define FCDI_EVENT_CODE_LINK_STATE 0x4
981/* enum: A timed read is ready to be serviced. */
982#define FCDI_EVENT_CODE_TIMED_READ 0x5
983/* enum: One or more PPS IN events */
984#define FCDI_EVENT_CODE_PPS_IN 0x6
985/* enum: Tick event from PTP clock */
986#define FCDI_EVENT_CODE_PTP_TICK 0x7
987/* enum: ECC error counters */
988#define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
989/* enum: Current status of PTP */
990#define FCDI_EVENT_CODE_PTP_STATUS 0x9
991/* enum: Port id config to map MC-FC port idx */
992#define FCDI_EVENT_CODE_PORT_CONFIG 0xa
993/* enum: Boot result or error code */
994#define FCDI_EVENT_CODE_BOOT_RESULT 0xb
995#define FCDI_EVENT_REBOOT_SRC_LBN 36
996#define FCDI_EVENT_REBOOT_SRC_WIDTH 8
997#define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
998#define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
999#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
1000#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4
1001#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
1002#define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32
1003#define FCDI_EVENT_ASSERT_TYPE_LBN 36
1004#define FCDI_EVENT_ASSERT_TYPE_WIDTH 8
1005#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36
1006#define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8
1007#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
1008#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4
1009#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
1010#define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32
1011#define FCDI_EVENT_LINK_STATE_DATA_OFST 0
1012#define FCDI_EVENT_LINK_STATE_DATA_LEN 4
1013#define FCDI_EVENT_LINK_STATE_DATA_LBN 0
1014#define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32
1015#define FCDI_EVENT_PTP_STATE_OFST 0
1016#define FCDI_EVENT_PTP_STATE_LEN 4
1017#define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
1018#define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
1019#define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
1020#define FCDI_EVENT_PTP_STATE_LBN 0
1021#define FCDI_EVENT_PTP_STATE_WIDTH 32
1022#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36
1023#define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8
1024#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
1025#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4
1026#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
1027#define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32
1028/* Index of MC port being referred to */
1029#define FCDI_EVENT_PORT_CONFIG_SRC_LBN 36
1030#define FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8
1031/* FC Port index that matches the MC port index in SRC */
1032#define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
1033#define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4
1034#define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
1035#define FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32
1036#define FCDI_EVENT_BOOT_RESULT_OFST 0
1037#define FCDI_EVENT_BOOT_RESULT_LEN 4
1038/* Enum values, see field(s): */
1039/* MC_CMD_AOE/MC_CMD_AOE_OUT_INFO/FC_BOOT_RESULT */
1040#define FCDI_EVENT_BOOT_RESULT_LBN 0
1041#define FCDI_EVENT_BOOT_RESULT_WIDTH 32
1042
1043/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events
1044 * to the MC. Note that this structure | is overlayed over a normal FCDI event
1045 * such that bits 32-63 containing | event code, level, source etc remain the
1046 * same. In this case the data | field of the header is defined to be the
1047 * number of timestamps
1048 */
1049#define FCDI_EXTENDED_EVENT_PPS_LENMIN 16
1050#define FCDI_EXTENDED_EVENT_PPS_LENMAX 248
1051#define FCDI_EXTENDED_EVENT_PPS_LENMAX_MCDI2 1016
1052#define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
1053#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8)
1054/* Number of timestamps following */
1055#define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
1056#define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
1057#define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
1058#define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32
1059/* Seconds field of a timestamp record */
1060#define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8
1061#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4
1062#define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64
1063#define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32
1064/* Nanoseconds field of a timestamp record */
1065#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12
1066#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4
1067#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96
1068#define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32
1069/* Timestamp records comprising the event */
1070#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
1071#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
1072#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
1073#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12
1074#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1
1075#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30
1076#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM_MCDI2 126
1077#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64
1078#define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64
1079
1080/* MUM_EVENT structuredef */
1081#define MUM_EVENT_LEN 8
1082#define MUM_EVENT_CONT_LBN 32
1083#define MUM_EVENT_CONT_WIDTH 1
1084#define MUM_EVENT_LEVEL_LBN 33
1085#define MUM_EVENT_LEVEL_WIDTH 3
1086/* enum: Info. */
1087#define MUM_EVENT_LEVEL_INFO 0x0
1088/* enum: Warning. */
1089#define MUM_EVENT_LEVEL_WARN 0x1
1090/* enum: Error. */
1091#define MUM_EVENT_LEVEL_ERR 0x2
1092/* enum: Fatal. */
1093#define MUM_EVENT_LEVEL_FATAL 0x3
1094#define MUM_EVENT_DATA_OFST 0
1095#define MUM_EVENT_DATA_LEN 4
1096#define MUM_EVENT_SENSOR_ID_OFST 0
1097#define MUM_EVENT_SENSOR_ID_LBN 0
1098#define MUM_EVENT_SENSOR_ID_WIDTH 8
1099/* Enum values, see field(s): */
1100/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
1101#define MUM_EVENT_SENSOR_STATE_OFST 0
1102#define MUM_EVENT_SENSOR_STATE_LBN 8
1103#define MUM_EVENT_SENSOR_STATE_WIDTH 8
1104#define MUM_EVENT_PORT_PHY_READY_OFST 0
1105#define MUM_EVENT_PORT_PHY_READY_LBN 0
1106#define MUM_EVENT_PORT_PHY_READY_WIDTH 1
1107#define MUM_EVENT_PORT_PHY_LINK_UP_OFST 0
1108#define MUM_EVENT_PORT_PHY_LINK_UP_LBN 1
1109#define MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1
1110#define MUM_EVENT_PORT_PHY_TX_LOL_OFST 0
1111#define MUM_EVENT_PORT_PHY_TX_LOL_LBN 2
1112#define MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1
1113#define MUM_EVENT_PORT_PHY_RX_LOL_OFST 0
1114#define MUM_EVENT_PORT_PHY_RX_LOL_LBN 3
1115#define MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1
1116#define MUM_EVENT_PORT_PHY_TX_LOS_OFST 0
1117#define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
1118#define MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1
1119#define MUM_EVENT_PORT_PHY_RX_LOS_OFST 0
1120#define MUM_EVENT_PORT_PHY_RX_LOS_LBN 5
1121#define MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1
1122#define MUM_EVENT_PORT_PHY_TX_FAULT_OFST 0
1123#define MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6
1124#define MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1
1125#define MUM_EVENT_DATA_LBN 0
1126#define MUM_EVENT_DATA_WIDTH 32
1127#define MUM_EVENT_SRC_LBN 36
1128#define MUM_EVENT_SRC_WIDTH 8
1129#define MUM_EVENT_EV_CODE_LBN 60
1130#define MUM_EVENT_EV_CODE_WIDTH 4
1131#define MUM_EVENT_CODE_LBN 44
1132#define MUM_EVENT_CODE_WIDTH 8
1133/* enum: The MUM was rebooted. */
1134#define MUM_EVENT_CODE_REBOOT 0x1
1135/* enum: Bad assert. */
1136#define MUM_EVENT_CODE_ASSERT 0x2
1137/* enum: Sensor failure. */
1138#define MUM_EVENT_CODE_SENSOR 0x3
1139/* enum: Link fault has been asserted, or has cleared. */
1140#define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
1141#define MUM_EVENT_SENSOR_DATA_OFST 0
1142#define MUM_EVENT_SENSOR_DATA_LEN 4
1143#define MUM_EVENT_SENSOR_DATA_LBN 0
1144#define MUM_EVENT_SENSOR_DATA_WIDTH 32
1145#define MUM_EVENT_PORT_PHY_FLAGS_OFST 0
1146#define MUM_EVENT_PORT_PHY_FLAGS_LEN 4
1147#define MUM_EVENT_PORT_PHY_FLAGS_LBN 0
1148#define MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32
1149#define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
1150#define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4
1151#define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
1152#define MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32
1153#define MUM_EVENT_PORT_PHY_CAPS_OFST 0
1154#define MUM_EVENT_PORT_PHY_CAPS_LEN 4
1155#define MUM_EVENT_PORT_PHY_CAPS_LBN 0
1156#define MUM_EVENT_PORT_PHY_CAPS_WIDTH 32
1157#define MUM_EVENT_PORT_PHY_TECH_OFST 0
1158#define MUM_EVENT_PORT_PHY_TECH_LEN 4
1159#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
1160#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
1161#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
1162#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
1163#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
1164#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
1165#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
1166#define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
1167#define MUM_EVENT_PORT_PHY_TECH_LBN 0
1168#define MUM_EVENT_PORT_PHY_TECH_WIDTH 32
1169#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36
1170#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
1171#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
1172#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
1173#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
1174#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
1175#define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
1176#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40
1177#define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4
1178
1179
1180/***********************************/
1181/* MC_CMD_READ32
1182 * Read multiple 32byte words from MC memory. Note - this command really
1183 * belongs to INSECURE category but is required by shmboot. The command handler
1184 * has additional checks to reject insecure calls.
1185 */
1186#define MC_CMD_READ32 0x1
1187#undef MC_CMD_0x1_PRIVILEGE_CTG
1188
1189#define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1190
1191/* MC_CMD_READ32_IN msgrequest */
1192#define MC_CMD_READ32_IN_LEN 8
1193#define MC_CMD_READ32_IN_ADDR_OFST 0
1194#define MC_CMD_READ32_IN_ADDR_LEN 4
1195#define MC_CMD_READ32_IN_NUMWORDS_OFST 4
1196#define MC_CMD_READ32_IN_NUMWORDS_LEN 4
1197
1198/* MC_CMD_READ32_OUT msgresponse */
1199#define MC_CMD_READ32_OUT_LENMIN 4
1200#define MC_CMD_READ32_OUT_LENMAX 252
1201#define MC_CMD_READ32_OUT_LENMAX_MCDI2 1020
1202#define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1203#define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
1204#define MC_CMD_READ32_OUT_BUFFER_OFST 0
1205#define MC_CMD_READ32_OUT_BUFFER_LEN 4
1206#define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
1207#define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
1208#define MC_CMD_READ32_OUT_BUFFER_MAXNUM_MCDI2 255
1209
1210
1211/***********************************/
1212/* MC_CMD_WRITE32
1213 * Write multiple 32byte words to MC memory.
1214 */
1215#define MC_CMD_WRITE32 0x2
1216#undef MC_CMD_0x2_PRIVILEGE_CTG
1217
1218#define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1219
1220/* MC_CMD_WRITE32_IN msgrequest */
1221#define MC_CMD_WRITE32_IN_LENMIN 8
1222#define MC_CMD_WRITE32_IN_LENMAX 252
1223#define MC_CMD_WRITE32_IN_LENMAX_MCDI2 1020
1224#define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1225#define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)
1226#define MC_CMD_WRITE32_IN_ADDR_OFST 0
1227#define MC_CMD_WRITE32_IN_ADDR_LEN 4
1228#define MC_CMD_WRITE32_IN_BUFFER_OFST 4
1229#define MC_CMD_WRITE32_IN_BUFFER_LEN 4
1230#define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
1231#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
1232#define MC_CMD_WRITE32_IN_BUFFER_MAXNUM_MCDI2 254
1233
1234/* MC_CMD_WRITE32_OUT msgresponse */
1235#define MC_CMD_WRITE32_OUT_LEN 0
1236
1237
1238/***********************************/
1239/* MC_CMD_COPYCODE
1240 * Copy MC code between two locations and jump. Note - this command really
1241 * belongs to INSECURE category but is required by shmboot. The command handler
1242 * has additional checks to reject insecure calls.
1243 */
1244#define MC_CMD_COPYCODE 0x3
1245#undef MC_CMD_0x3_PRIVILEGE_CTG
1246
1247#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1248
1249/* MC_CMD_COPYCODE_IN msgrequest */
1250#define MC_CMD_COPYCODE_IN_LEN 16
1251/* Source address
1252 *
1253 * The main image should be entered via a copy of a single word from and to a
1254 * magic address, which controls various aspects of the boot. The magic address
1255 * is a bitfield, with each bit as documented below.
1256 */
1257#define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
1258#define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4
1259/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */
1260#define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
1261/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and
1262 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)
1263 */
1264#define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
1265/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,
1266 * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see
1267 * below)
1268 */
1269#define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
1270#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 0
1271#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17
1272#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1
1273#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 0
1274#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2
1275#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1
1276#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 0
1277#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3
1278#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1
1279#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 0
1280#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
1281#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1
1282#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 0
1283#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5
1284#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1
1285#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 0
1286#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_LBN 6
1287#define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_WIDTH 1
1288/* Destination address */
1289#define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
1290#define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4
1291#define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
1292#define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4
1293/* Address of where to jump after copy. */
1294#define MC_CMD_COPYCODE_IN_JUMP_OFST 12
1295#define MC_CMD_COPYCODE_IN_JUMP_LEN 4
1296/* enum: Control should return to the caller rather than jumping */
1297#define MC_CMD_COPYCODE_JUMP_NONE 0x1
1298
1299/* MC_CMD_COPYCODE_OUT msgresponse */
1300#define MC_CMD_COPYCODE_OUT_LEN 0
1301
1302
1303/***********************************/
1304/* MC_CMD_SET_FUNC
1305 * Select function for function-specific commands.
1306 */
1307#define MC_CMD_SET_FUNC 0x4
1308#undef MC_CMD_0x4_PRIVILEGE_CTG
1309
1310#define MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_INSECURE
1311
1312/* MC_CMD_SET_FUNC_IN msgrequest */
1313#define MC_CMD_SET_FUNC_IN_LEN 4
1314/* Set function */
1315#define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
1316#define MC_CMD_SET_FUNC_IN_FUNC_LEN 4
1317
1318/* MC_CMD_SET_FUNC_OUT msgresponse */
1319#define MC_CMD_SET_FUNC_OUT_LEN 0
1320
1321
1322/***********************************/
1323/* MC_CMD_GET_BOOT_STATUS
1324 * Get the instruction address from which the MC booted.
1325 */
1326#define MC_CMD_GET_BOOT_STATUS 0x5
1327#undef MC_CMD_0x5_PRIVILEGE_CTG
1328
1329#define MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1330
1331/* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
1332#define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
1333
1334/* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
1335#define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
1336/* ?? */
1337#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
1338#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
1339/* enum: indicates that the MC wasn't flash booted */
1340#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
1341#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
1342#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
1343#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4
1344#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
1345#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
1346#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4
1347#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
1348#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
1349#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4
1350#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
1351#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
1352
1353
1354/***********************************/
1355/* MC_CMD_GET_ASSERTS
1356 * Get (and optionally clear) the current assertion status. Only
1357 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other
1358 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
1359 */
1360#define MC_CMD_GET_ASSERTS 0x6
1361#undef MC_CMD_0x6_PRIVILEGE_CTG
1362
1363#define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
1364
1365/* MC_CMD_GET_ASSERTS_IN msgrequest */
1366#define MC_CMD_GET_ASSERTS_IN_LEN 4
1367/* Set to clear assertion */
1368#define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
1369#define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
1370
1371/* MC_CMD_GET_ASSERTS_OUT msgresponse */
1372#define MC_CMD_GET_ASSERTS_OUT_LEN 140
1373/* Assertion status flag. */
1374#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
1375#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
1376/* enum: No assertions have failed. */
1377#define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
1378/* enum: A system-level assertion has failed. */
1379#define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
1380/* enum: A thread-level assertion has failed. */
1381#define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
1382/* enum: The system was reset by the watchdog. */
1383#define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
1384/* enum: An illegal address trap stopped the system (huntington and later) */
1385#define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
1386/* Failing PC value */
1387#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
1388#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
1389/* Saved GP regs */
1390#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
1391#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
1392#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
1393/* enum: A magic value hinting that the value in this register at the time of
1394 * the failure has likely been lost.
1395 */
1396#define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
1397/* Failing thread address */
1398#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
1399#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
1400#define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
1401#define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
1402
1403/* MC_CMD_GET_ASSERTS_OUT_V2 msgresponse: Extended response for MicroBlaze CPUs
1404 * found on Riverhead designs
1405 */
1406#define MC_CMD_GET_ASSERTS_OUT_V2_LEN 240
1407/* Assertion status flag. */
1408#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0
1409#define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4
1410/* enum: No assertions have failed. */
1411/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
1412/* enum: A system-level assertion has failed. */
1413/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
1414/* enum: A thread-level assertion has failed. */
1415/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
1416/* enum: The system was reset by the watchdog. */
1417/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
1418/* enum: An illegal address trap stopped the system (huntington and later) */
1419/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
1420/* Failing PC value */
1421#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4
1422#define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4
1423/* Saved GP regs */
1424#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_OFST 8
1425#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4
1426#define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_NUM 31
1427/* enum: A magic value hinting that the value in this register at the time of
1428 * the failure has likely been lost.
1429 */
1430/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
1431/* Failing thread address */
1432#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_OFST 132
1433#define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4
1434#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_OFST 136
1435#define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4
1436/* Saved Special Function Registers */
1437#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_OFST 136
1438#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4
1439#define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_NUM 26
1440
1441/* MC_CMD_GET_ASSERTS_OUT_V3 msgresponse: Extended response with asserted
1442 * firmware version information
1443 */
1444#define MC_CMD_GET_ASSERTS_OUT_V3_LEN 360
1445/* Assertion status flag. */
1446#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0
1447#define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4
1448/* enum: No assertions have failed. */
1449/* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
1450/* enum: A system-level assertion has failed. */
1451/* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
1452/* enum: A thread-level assertion has failed. */
1453/* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
1454/* enum: The system was reset by the watchdog. */
1455/* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
1456/* enum: An illegal address trap stopped the system (huntington and later) */
1457/* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
1458/* Failing PC value */
1459#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4
1460#define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4
1461/* Saved GP regs */
1462#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_OFST 8
1463#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4
1464#define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_NUM 31
1465/* enum: A magic value hinting that the value in this register at the time of
1466 * the failure has likely been lost.
1467 */
1468/* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
1469/* Failing thread address */
1470#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_OFST 132
1471#define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4
1472#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_OFST 136
1473#define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4
1474/* Saved Special Function Registers */
1475#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_OFST 136
1476#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4
1477#define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_NUM 26
1478/* MC firmware unique build ID (as binary SHA-1 value) */
1479#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_OFST 240
1480#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_ID_LEN 20
1481/* MC firmware build date (as Unix timestamp) */
1482#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_OFST 260
1483#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LEN 8
1484#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_OFST 260
1485#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_OFST 264
1486/* MC firmware version number */
1487#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_OFST 268
1488#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LEN 8
1489#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_OFST 268
1490#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_OFST 272
1491/* MC firmware security level */
1492#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_OFST 276
1493#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
1494/* MC firmware extra version info (as null-terminated US-ASCII string) */
1495#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_OFST 280
1496#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_EXTRA_INFO_LEN 16
1497/* MC firmware build name (as null-terminated US-ASCII string) */
1498#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_OFST 296
1499#define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_NAME_LEN 64
1500
1501
1502/***********************************/
1503/* MC_CMD_LOG_CTRL
1504 * Configure the output stream for log events such as link state changes,
1505 * sensor notifications and MCDI completions
1506 */
1507#define MC_CMD_LOG_CTRL 0x7
1508#undef MC_CMD_0x7_PRIVILEGE_CTG
1509
1510#define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1511
1512/* MC_CMD_LOG_CTRL_IN msgrequest */
1513#define MC_CMD_LOG_CTRL_IN_LEN 8
1514/* Log destination */
1515#define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
1516#define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
1517/* enum: UART. */
1518#define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
1519/* enum: Event queue. */
1520#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
1521/* Legacy argument. Must be zero. */
1522#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
1523#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4
1524
1525/* MC_CMD_LOG_CTRL_OUT msgresponse */
1526#define MC_CMD_LOG_CTRL_OUT_LEN 0
1527
1528
1529/***********************************/
1530/* MC_CMD_GET_VERSION
1531 * Get version information about adapter components.
1532 */
1533#define MC_CMD_GET_VERSION 0x8
1534#undef MC_CMD_0x8_PRIVILEGE_CTG
1535
1536#define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1537
1538/* MC_CMD_GET_VERSION_IN msgrequest */
1539#define MC_CMD_GET_VERSION_IN_LEN 0
1540
1541/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */
1542#define MC_CMD_GET_VERSION_EXT_IN_LEN 4
1543/* placeholder, set to 0 */
1544#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
1545#define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
1546
1547/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */
1548#define MC_CMD_GET_VERSION_V0_OUT_LEN 4
1549#define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
1550#define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
1551/* enum: Reserved version number to indicate "any" version. */
1552#define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
1553/* enum: Bootrom version value for Siena. */
1554#define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
1555/* enum: Bootrom version value for Huntington. */
1556#define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
1557/* enum: Bootrom version value for Medford2. */
1558#define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
1559
1560/* MC_CMD_GET_VERSION_OUT msgresponse */
1561#define MC_CMD_GET_VERSION_OUT_LEN 32
1562/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1563/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1564/* Enum values, see field(s): */
1565/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1566#define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
1567#define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
1568/* 128bit mask of functions supported by the current firmware */
1569#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
1570#define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
1571#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
1572#define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
1573#define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
1574#define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
1575
1576/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
1577#define MC_CMD_GET_VERSION_EXT_OUT_LEN 48
1578/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1579/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1580/* Enum values, see field(s): */
1581/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1582#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
1583#define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
1584/* 128bit mask of functions supported by the current firmware */
1585#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8
1586#define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16
1587#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
1588#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
1589#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
1590#define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
1591/* extra info */
1592#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
1593#define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
1594
1595/* MC_CMD_GET_VERSION_V2_OUT msgresponse: Extended response providing version
1596 * information for all adapter components. For Riverhead based designs, base MC
1597 * firmware version fields refer to NMC firmware, while CMC firmware data is in
1598 * dedicated CMC fields. Flags indicate which data is present in the response
1599 * (depending on which components exist on a particular adapter)
1600 */
1601#define MC_CMD_GET_VERSION_V2_OUT_LEN 304
1602/* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
1603/* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
1604/* Enum values, see field(s): */
1605/* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
1606#define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4
1607#define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4
1608/* 128bit mask of functions supported by the current firmware */
1609#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_OFST 8
1610#define MC_CMD_GET_VERSION_V2_OUT_SUPPORTED_FUNCS_LEN 16
1611#define MC_CMD_GET_VERSION_V2_OUT_VERSION_OFST 24
1612#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LEN 8
1613#define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_OFST 24
1614#define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_OFST 28
1615/* extra info */
1616#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_OFST 32
1617#define MC_CMD_GET_VERSION_V2_OUT_EXTRA_LEN 16
1618/* Flags indicating which extended fields are valid */
1619#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_OFST 48
1620#define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4
1621#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_OFST 48
1622#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
1623#define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_WIDTH 1
1624#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_OFST 48
1625#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_LBN 1
1626#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_EXT_INFO_PRESENT_WIDTH 1
1627#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_OFST 48
1628#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_LBN 2
1629#define MC_CMD_GET_VERSION_V2_OUT_CMC_EXT_INFO_PRESENT_WIDTH 1
1630#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_OFST 48
1631#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_LBN 3
1632#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXT_INFO_PRESENT_WIDTH 1
1633#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_OFST 48
1634#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
1635#define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_WIDTH 1
1636/* MC firmware unique build ID (as binary SHA-1 value) */
1637#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_OFST 52
1638#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_ID_LEN 20
1639/* MC firmware security level */
1640#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_OFST 72
1641#define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4
1642/* MC firmware build name (as null-terminated US-ASCII string) */
1643#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_OFST 76
1644#define MC_CMD_GET_VERSION_V2_OUT_MCFW_BUILD_NAME_LEN 64
1645/* The SUC firmware version as four numbers - a.b.c.d */
1646#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_OFST 140
1647#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4
1648#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4
1649/* SUC firmware build date (as 64-bit Unix timestamp) */
1650#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_OFST 156
1651#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LEN 8
1652#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_OFST 156
1653#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_OFST 160
1654/* The ID of the SUC chip. This is specific to the platform but typically
1655 * indicates family, memory sizes etc. See SF-116728-SW for further details.
1656 */
1657#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_OFST 164
1658#define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4
1659/* The CMC firmware version as four numbers - a.b.c.d */
1660#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_OFST 168
1661#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4
1662#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4
1663/* CMC firmware build date (as 64-bit Unix timestamp) */
1664#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_OFST 184
1665#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LEN 8
1666#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_OFST 184
1667#define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_OFST 188
1668/* FPGA version as three numbers. On Riverhead based systems this field uses
1669 * the same encoding as hardware version ID registers (MC_FPGA_BUILD_HWRD_REG):
1670 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
1671 * => B, ...) FPGA_VERSION[2]: Sub-revision number
1672 */
1673#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_OFST 192
1674#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4
1675#define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_NUM 3
1676/* Extra FPGA revision information (as null-terminated US-ASCII string) */
1677#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_OFST 204
1678#define MC_CMD_GET_VERSION_V2_OUT_FPGA_EXTRA_LEN 16
1679/* Board name / adapter model (as null-terminated US-ASCII string) */
1680#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_OFST 220
1681#define MC_CMD_GET_VERSION_V2_OUT_BOARD_NAME_LEN 16
1682/* Board revision number */
1683#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_OFST 236
1684#define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4
1685/* Board serial number (as null-terminated US-ASCII string) */
1686#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_OFST 240
1687#define MC_CMD_GET_VERSION_V2_OUT_BOARD_SERIAL_LEN 64
1688
1689
1690/***********************************/
1691/* MC_CMD_PTP
1692 * Perform PTP operation
1693 */
1694#define MC_CMD_PTP 0xb
1695#undef MC_CMD_0xb_PRIVILEGE_CTG
1696
1697#define MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
1698
1699/* MC_CMD_PTP_IN msgrequest */
1700#define MC_CMD_PTP_IN_LEN 1
1701/* PTP operation code */
1702#define MC_CMD_PTP_IN_OP_OFST 0
1703#define MC_CMD_PTP_IN_OP_LEN 1
1704/* enum: Enable PTP packet timestamping operation. */
1705#define MC_CMD_PTP_OP_ENABLE 0x1
1706/* enum: Disable PTP packet timestamping operation. */
1707#define MC_CMD_PTP_OP_DISABLE 0x2
1708/* enum: Send a PTP packet. This operation is used on Siena and Huntington.
1709 * From Medford onwards it is not supported: on those platforms PTP transmit
1710 * timestamping is done using the fast path.
1711 */
1712#define MC_CMD_PTP_OP_TRANSMIT 0x3
1713/* enum: Read the current NIC time. */
1714#define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
1715/* enum: Get the current PTP status. Note that the clock frequency returned (in
1716 * Hz) is rounded to the nearest MHz (e.g. 666000000 for 666666666).
1717 */
1718#define MC_CMD_PTP_OP_STATUS 0x5
1719/* enum: Adjust the PTP NIC's time. */
1720#define MC_CMD_PTP_OP_ADJUST 0x6
1721/* enum: Synchronize host and NIC time. */
1722#define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
1723/* enum: Basic manufacturing tests. Siena PTP adapters only. */
1724#define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
1725/* enum: Packet based manufacturing tests. Siena PTP adapters only. */
1726#define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
1727/* enum: Reset some of the PTP related statistics */
1728#define MC_CMD_PTP_OP_RESET_STATS 0xa
1729/* enum: Debug operations to MC. */
1730#define MC_CMD_PTP_OP_DEBUG 0xb
1731/* enum: Read an FPGA register. Siena PTP adapters only. */
1732#define MC_CMD_PTP_OP_FPGAREAD 0xc
1733/* enum: Write an FPGA register. Siena PTP adapters only. */
1734#define MC_CMD_PTP_OP_FPGAWRITE 0xd
1735/* enum: Apply an offset to the NIC clock */
1736#define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
1737/* enum: Change the frequency correction applied to the NIC clock */
1738#define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
1739/* enum: Set the MC packet filter VLAN tags for received PTP packets.
1740 * Deprecated for Huntington onwards.
1741 */
1742#define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
1743/* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for
1744 * Huntington onwards.
1745 */
1746#define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
1747/* enum: Set the MC packet filter Domain for received PTP packets. Deprecated
1748 * for Huntington onwards.
1749 */
1750#define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
1751/* enum: Set the clock source. Required for snapper tests on Huntington and
1752 * Medford. Not implemented for Siena or Medford2.
1753 */
1754#define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
1755/* enum: Reset value of Timer Reg. Not implemented. */
1756#define MC_CMD_PTP_OP_RST_CLK 0x14
1757/* enum: Enable the forwarding of PPS events to the host */
1758#define MC_CMD_PTP_OP_PPS_ENABLE 0x15
1759/* enum: Get the time format used by this NIC for PTP operations */
1760#define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
1761/* enum: Get the clock attributes. NOTE- extended version of
1762 * MC_CMD_PTP_OP_GET_TIME_FORMAT
1763 */
1764#define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
1765/* enum: Get corrections that should be applied to the various different
1766 * timestamps
1767 */
1768#define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
1769/* enum: Subscribe to receive periodic time events indicating the current NIC
1770 * time
1771 */
1772#define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
1773/* enum: Unsubscribe to stop receiving time events */
1774#define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
1775/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS
1776 * input on the same NIC. Siena PTP adapters only.
1777 */
1778#define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
1779/* enum: Set the PTP sync status. Status is used by firmware to report to event
1780 * subscribers.
1781 */
1782#define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
1783/* enum: Above this for future use. */
1784#define MC_CMD_PTP_OP_MAX 0x1c
1785
1786/* MC_CMD_PTP_IN_ENABLE msgrequest */
1787#define MC_CMD_PTP_IN_ENABLE_LEN 16
1788#define MC_CMD_PTP_IN_CMD_OFST 0
1789#define MC_CMD_PTP_IN_CMD_LEN 4
1790#define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
1791#define MC_CMD_PTP_IN_PERIPH_ID_LEN 4
1792/* Not used. Events are always sent to function relative queue 0. */
1793#define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
1794#define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
1795/* PTP timestamping mode. Not used from Huntington onwards. */
1796#define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
1797#define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
1798/* enum: PTP, version 1 */
1799#define MC_CMD_PTP_MODE_V1 0x0
1800/* enum: PTP, version 1, with VLAN headers - deprecated */
1801#define MC_CMD_PTP_MODE_V1_VLAN 0x1
1802/* enum: PTP, version 2 */
1803#define MC_CMD_PTP_MODE_V2 0x2
1804/* enum: PTP, version 2, with VLAN headers - deprecated */
1805#define MC_CMD_PTP_MODE_V2_VLAN 0x3
1806/* enum: PTP, version 2, with improved UUID filtering */
1807#define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
1808/* enum: FCoE (seconds and microseconds) */
1809#define MC_CMD_PTP_MODE_FCOE 0x5
1810
1811/* MC_CMD_PTP_IN_DISABLE msgrequest */
1812#define MC_CMD_PTP_IN_DISABLE_LEN 8
1813/* MC_CMD_PTP_IN_CMD_OFST 0 */
1814/* MC_CMD_PTP_IN_CMD_LEN 4 */
1815/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1816/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1817
1818/* MC_CMD_PTP_IN_TRANSMIT msgrequest */
1819#define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
1820#define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
1821#define MC_CMD_PTP_IN_TRANSMIT_LENMAX_MCDI2 1020
1822#define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
1823#define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)
1824/* MC_CMD_PTP_IN_CMD_OFST 0 */
1825/* MC_CMD_PTP_IN_CMD_LEN 4 */
1826/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1827/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1828/* Transmit packet length */
1829#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
1830#define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
1831/* Transmit packet data */
1832#define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
1833#define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
1834#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
1835#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
1836#define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM_MCDI2 1008
1837
1838/* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
1839#define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
1840/* MC_CMD_PTP_IN_CMD_OFST 0 */
1841/* MC_CMD_PTP_IN_CMD_LEN 4 */
1842/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1843/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1844
1845/* MC_CMD_PTP_IN_READ_NIC_TIME_V2 msgrequest */
1846#define MC_CMD_PTP_IN_READ_NIC_TIME_V2_LEN 8
1847/* MC_CMD_PTP_IN_CMD_OFST 0 */
1848/* MC_CMD_PTP_IN_CMD_LEN 4 */
1849/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1850/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1851
1852/* MC_CMD_PTP_IN_STATUS msgrequest */
1853#define MC_CMD_PTP_IN_STATUS_LEN 8
1854/* MC_CMD_PTP_IN_CMD_OFST 0 */
1855/* MC_CMD_PTP_IN_CMD_LEN 4 */
1856/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1857/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1858
1859/* MC_CMD_PTP_IN_ADJUST msgrequest */
1860#define MC_CMD_PTP_IN_ADJUST_LEN 24
1861/* MC_CMD_PTP_IN_CMD_OFST 0 */
1862/* MC_CMD_PTP_IN_CMD_LEN 4 */
1863/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1864/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1865/* Frequency adjustment 40 bit fixed point ns */
1866#define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
1867#define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
1868#define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
1869#define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
1870/* enum: Number of fractional bits in frequency adjustment */
1871#define MC_CMD_PTP_IN_ADJUST_BITS 0x28
1872/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
1873 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
1874 * field.
1875 */
1876#define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
1877/* Time adjustment in seconds */
1878#define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
1879#define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
1880/* Time adjustment major value */
1881#define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16
1882#define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
1883/* Time adjustment in nanoseconds */
1884#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
1885#define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
1886/* Time adjustment minor value */
1887#define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20
1888#define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4
1889
1890/* MC_CMD_PTP_IN_ADJUST_V2 msgrequest */
1891#define MC_CMD_PTP_IN_ADJUST_V2_LEN 28
1892/* MC_CMD_PTP_IN_CMD_OFST 0 */
1893/* MC_CMD_PTP_IN_CMD_LEN 4 */
1894/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1895/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1896/* Frequency adjustment 40 bit fixed point ns */
1897#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_OFST 8
1898#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LEN 8
1899#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_OFST 8
1900#define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_OFST 12
1901/* enum: Number of fractional bits in frequency adjustment */
1902/* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
1903/* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
1904 * is indicated in the MC_CMD_PTP_OUT_GET_ATTRIBUTES command CAPABILITIES
1905 * field.
1906 */
1907/* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
1908/* Time adjustment in seconds */
1909#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_OFST 16
1910#define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
1911/* Time adjustment major value */
1912#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_OFST 16
1913#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
1914/* Time adjustment in nanoseconds */
1915#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_OFST 20
1916#define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
1917/* Time adjustment minor value */
1918#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_OFST 20
1919#define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
1920/* Upper 32bits of major time offset adjustment */
1921#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_OFST 24
1922#define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4
1923
1924/* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
1925#define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
1926/* MC_CMD_PTP_IN_CMD_OFST 0 */
1927/* MC_CMD_PTP_IN_CMD_LEN 4 */
1928/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1929/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1930/* Number of time readings to capture */
1931#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
1932#define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
1933/* Host address in which to write "synchronization started" indication (64
1934 * bits)
1935 */
1936#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
1937#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
1938#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
1939#define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
1940
1941/* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
1942#define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
1943/* MC_CMD_PTP_IN_CMD_OFST 0 */
1944/* MC_CMD_PTP_IN_CMD_LEN 4 */
1945/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1946/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1947
1948/* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
1949#define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
1950/* MC_CMD_PTP_IN_CMD_OFST 0 */
1951/* MC_CMD_PTP_IN_CMD_LEN 4 */
1952/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1953/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1954/* Enable or disable packet testing */
1955#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
1956#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
1957
1958/* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */
1959#define MC_CMD_PTP_IN_RESET_STATS_LEN 8
1960/* MC_CMD_PTP_IN_CMD_OFST 0 */
1961/* MC_CMD_PTP_IN_CMD_LEN 4 */
1962/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1963/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1964
1965/* MC_CMD_PTP_IN_DEBUG msgrequest */
1966#define MC_CMD_PTP_IN_DEBUG_LEN 12
1967/* MC_CMD_PTP_IN_CMD_OFST 0 */
1968/* MC_CMD_PTP_IN_CMD_LEN 4 */
1969/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1970/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1971/* Debug operations */
1972#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
1973#define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4
1974
1975/* MC_CMD_PTP_IN_FPGAREAD msgrequest */
1976#define MC_CMD_PTP_IN_FPGAREAD_LEN 16
1977/* MC_CMD_PTP_IN_CMD_OFST 0 */
1978/* MC_CMD_PTP_IN_CMD_LEN 4 */
1979/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1980/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1981#define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8
1982#define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
1983#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12
1984#define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4
1985
1986/* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
1987#define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
1988#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
1989#define MC_CMD_PTP_IN_FPGAWRITE_LENMAX_MCDI2 1020
1990#define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
1991#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)
1992/* MC_CMD_PTP_IN_CMD_OFST 0 */
1993/* MC_CMD_PTP_IN_CMD_LEN 4 */
1994/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1995/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
1996#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8
1997#define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
1998#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12
1999#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
2000#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
2001#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
2002#define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM_MCDI2 1008
2003
2004/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
2005#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
2006/* MC_CMD_PTP_IN_CMD_OFST 0 */
2007/* MC_CMD_PTP_IN_CMD_LEN 4 */
2008/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2009/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2010/* Time adjustment in seconds */
2011#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
2012#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
2013/* Time adjustment major value */
2014#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8
2015#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
2016/* Time adjustment in nanoseconds */
2017#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
2018#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
2019/* Time adjustment minor value */
2020#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12
2021#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4
2022
2023/* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2 msgrequest */
2024#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_LEN 20
2025/* MC_CMD_PTP_IN_CMD_OFST 0 */
2026/* MC_CMD_PTP_IN_CMD_LEN 4 */
2027/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2028/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2029/* Time adjustment in seconds */
2030#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_OFST 8
2031#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
2032/* Time adjustment major value */
2033#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_OFST 8
2034#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
2035/* Time adjustment in nanoseconds */
2036#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_OFST 12
2037#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
2038/* Time adjustment minor value */
2039#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_OFST 12
2040#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
2041/* Upper 32bits of major time offset adjustment */
2042#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_OFST 16
2043#define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4
2044
2045/* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
2046#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
2047/* MC_CMD_PTP_IN_CMD_OFST 0 */
2048/* MC_CMD_PTP_IN_CMD_LEN 4 */
2049/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2050/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2051/* Frequency adjustment 40 bit fixed point ns */
2052#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
2053#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
2054#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
2055#define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
2056/* Enum values, see field(s): */
2057/* MC_CMD_PTP/MC_CMD_PTP_IN_ADJUST/FREQ */
2058
2059/* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
2060#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
2061/* MC_CMD_PTP_IN_CMD_OFST 0 */
2062/* MC_CMD_PTP_IN_CMD_LEN 4 */
2063/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2064/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2065/* Number of VLAN tags, 0 if not VLAN */
2066#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
2067#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
2068/* Set of VLAN tags to filter against */
2069#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
2070#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
2071#define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3
2072
2073/* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */
2074#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
2075/* MC_CMD_PTP_IN_CMD_OFST 0 */
2076/* MC_CMD_PTP_IN_CMD_LEN 4 */
2077/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2078/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2079/* 1 to enable UUID filtering, 0 to disable */
2080#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
2081#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
2082/* UUID to filter against */
2083#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
2084#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
2085#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
2086#define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
2087
2088/* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
2089#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
2090/* MC_CMD_PTP_IN_CMD_OFST 0 */
2091/* MC_CMD_PTP_IN_CMD_LEN 4 */
2092/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2093/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2094/* 1 to enable Domain filtering, 0 to disable */
2095#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
2096#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
2097/* Domain number to filter against */
2098#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
2099#define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4
2100
2101/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */
2102#define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12
2103/* MC_CMD_PTP_IN_CMD_OFST 0 */
2104/* MC_CMD_PTP_IN_CMD_LEN 4 */
2105/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2106/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2107/* Set the clock source. */
2108#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8
2109#define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
2110/* enum: Internal. */
2111#define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
2112/* enum: External. */
2113#define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
2114
2115/* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */
2116#define MC_CMD_PTP_IN_RST_CLK_LEN 8
2117/* MC_CMD_PTP_IN_CMD_OFST 0 */
2118/* MC_CMD_PTP_IN_CMD_LEN 4 */
2119/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2120/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2121
2122/* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
2123#define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
2124/* MC_CMD_PTP_IN_CMD_OFST 0 */
2125/* MC_CMD_PTP_IN_CMD_LEN 4 */
2126/* Enable or disable */
2127#define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
2128#define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
2129/* enum: Enable */
2130#define MC_CMD_PTP_ENABLE_PPS 0x0
2131/* enum: Disable */
2132#define MC_CMD_PTP_DISABLE_PPS 0x1
2133/* Not used. Events are always sent to function relative queue 0. */
2134#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
2135#define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4
2136
2137/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */
2138#define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8
2139/* MC_CMD_PTP_IN_CMD_OFST 0 */
2140/* MC_CMD_PTP_IN_CMD_LEN 4 */
2141/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2142/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2143
2144/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */
2145#define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8
2146/* MC_CMD_PTP_IN_CMD_OFST 0 */
2147/* MC_CMD_PTP_IN_CMD_LEN 4 */
2148/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2149/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2150
2151/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */
2152#define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8
2153/* MC_CMD_PTP_IN_CMD_OFST 0 */
2154/* MC_CMD_PTP_IN_CMD_LEN 4 */
2155/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2156/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2157
2158/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */
2159#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12
2160/* MC_CMD_PTP_IN_CMD_OFST 0 */
2161/* MC_CMD_PTP_IN_CMD_LEN 4 */
2162/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2163/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2164/* Original field containing queue ID. Now extended to include flags. */
2165#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8
2166#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
2167#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_OFST 8
2168#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
2169#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16
2170#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_OFST 8
2171#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31
2172#define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1
2173
2174/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */
2175#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16
2176/* MC_CMD_PTP_IN_CMD_OFST 0 */
2177/* MC_CMD_PTP_IN_CMD_LEN 4 */
2178/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2179/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2180/* Unsubscribe options */
2181#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8
2182#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
2183/* enum: Unsubscribe a single queue */
2184#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
2185/* enum: Unsubscribe all queues */
2186#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
2187/* Event queue ID */
2188#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
2189#define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
2190
2191/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
2192#define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
2193/* MC_CMD_PTP_IN_CMD_OFST 0 */
2194/* MC_CMD_PTP_IN_CMD_LEN 4 */
2195/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2196/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2197/* 1 to enable PPS test mode, 0 to disable and return result. */
2198#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8
2199#define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4
2200
2201/* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */
2202#define MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24
2203/* MC_CMD_PTP_IN_CMD_OFST 0 */
2204/* MC_CMD_PTP_IN_CMD_LEN 4 */
2205/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2206/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2207/* NIC - Host System Clock Synchronization status */
2208#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8
2209#define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
2210/* enum: Host System clock and NIC clock are not in sync */
2211#define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
2212/* enum: Host System clock and NIC clock are synchronized */
2213#define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
2214/* If synchronized, number of seconds until clocks should be considered to be
2215 * no longer in sync.
2216 */
2217#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12
2218#define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
2219#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16
2220#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
2221#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20
2222#define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
2223
2224/* MC_CMD_PTP_OUT msgresponse */
2225#define MC_CMD_PTP_OUT_LEN 0
2226
2227/* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
2228#define MC_CMD_PTP_OUT_TRANSMIT_LEN 8
2229/* Value of seconds timestamp */
2230#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
2231#define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
2232/* Timestamp major value */
2233#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
2234#define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
2235/* Value of nanoseconds timestamp */
2236#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
2237#define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
2238/* Timestamp minor value */
2239#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
2240#define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4
2241
2242/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */
2243#define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
2244
2245/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */
2246#define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
2247
2248/* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
2249#define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
2250/* Value of seconds timestamp */
2251#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
2252#define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
2253/* Timestamp major value */
2254#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
2255#define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
2256/* Value of nanoseconds timestamp */
2257#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
2258#define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
2259/* Timestamp minor value */
2260#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
2261#define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
2262
2263/* MC_CMD_PTP_OUT_READ_NIC_TIME_V2 msgresponse */
2264#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_LEN 12
2265/* Value of seconds timestamp */
2266#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
2267#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
2268/* Timestamp major value */
2269#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
2270#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
2271/* Value of nanoseconds timestamp */
2272#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
2273#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
2274/* Timestamp minor value */
2275#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
2276#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
2277/* Upper 32bits of major timestamp value */
2278#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_OFST 8
2279#define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
2280
2281/* MC_CMD_PTP_OUT_STATUS msgresponse */
2282#define MC_CMD_PTP_OUT_STATUS_LEN 64
2283/* Frequency of NIC's hardware clock */
2284#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
2285#define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
2286/* Number of packets transmitted and timestamped */
2287#define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
2288#define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
2289/* Number of packets received and timestamped */
2290#define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
2291#define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
2292/* Number of packets timestamped by the FPGA */
2293#define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
2294#define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
2295/* Number of packets filter matched */
2296#define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
2297#define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
2298/* Number of packets not filter matched */
2299#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
2300#define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
2301/* Number of PPS overflows (noise on input?) */
2302#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
2303#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
2304/* Number of PPS bad periods */
2305#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
2306#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
2307/* Minimum period of PPS pulse in nanoseconds */
2308#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
2309#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
2310/* Maximum period of PPS pulse in nanoseconds */
2311#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
2312#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
2313/* Last period of PPS pulse in nanoseconds */
2314#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
2315#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
2316/* Mean period of PPS pulse in nanoseconds */
2317#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
2318#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
2319/* Minimum offset of PPS pulse in nanoseconds (signed) */
2320#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
2321#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
2322/* Maximum offset of PPS pulse in nanoseconds (signed) */
2323#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
2324#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
2325/* Last offset of PPS pulse in nanoseconds (signed) */
2326#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
2327#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
2328/* Mean offset of PPS pulse in nanoseconds (signed) */
2329#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
2330#define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
2331
2332/* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
2333#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
2334#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
2335#define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX_MCDI2 1020
2336#define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
2337#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
2338/* A set of host and NIC times */
2339#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
2340#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
2341#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
2342#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
2343#define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM_MCDI2 51
2344/* Host time immediately before NIC's hardware clock read */
2345#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
2346#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
2347/* Value of seconds timestamp */
2348#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
2349#define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
2350/* Timestamp major value */
2351#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
2352#define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
2353/* Value of nanoseconds timestamp */
2354#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
2355#define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
2356/* Timestamp minor value */
2357#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8
2358#define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
2359/* Host time immediately after NIC's hardware clock read */
2360#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
2361#define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
2362/* Number of nanoseconds waited after reading NIC's hardware clock */
2363#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
2364#define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
2365
2366/* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
2367#define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
2368/* Results of testing */
2369#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
2370#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
2371/* enum: Successful test */
2372#define MC_CMD_PTP_MANF_SUCCESS 0x0
2373/* enum: FPGA load failed */
2374#define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
2375/* enum: FPGA version invalid */
2376#define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
2377/* enum: FPGA registers incorrect */
2378#define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
2379/* enum: Oscillator possibly not working? */
2380#define MC_CMD_PTP_MANF_OSCILLATOR 0x4
2381/* enum: Timestamps not increasing */
2382#define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
2383/* enum: Mismatched packet count */
2384#define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
2385/* enum: Mismatched packet count (Siena filter and FPGA) */
2386#define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
2387/* enum: Not enough packets to perform timestamp check */
2388#define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
2389/* enum: Timestamp trigger GPIO not working */
2390#define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
2391/* enum: Insufficient PPS events to perform checks */
2392#define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
2393/* enum: PPS time event period not sufficiently close to 1s. */
2394#define MC_CMD_PTP_MANF_PPS_PERIOD 0xb
2395/* enum: PPS time event nS reading not sufficiently close to zero. */
2396#define MC_CMD_PTP_MANF_PPS_NS 0xc
2397/* enum: PTP peripheral registers incorrect */
2398#define MC_CMD_PTP_MANF_REGISTERS 0xd
2399/* enum: Failed to read time from PTP peripheral */
2400#define MC_CMD_PTP_MANF_CLOCK_READ 0xe
2401/* Presence of external oscillator */
2402#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
2403#define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
2404
2405/* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
2406#define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
2407/* Results of testing */
2408#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
2409#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
2410/* Number of packets received by FPGA */
2411#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
2412#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
2413/* Number of packets received by Siena filters */
2414#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
2415#define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
2416
2417/* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
2418#define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
2419#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
2420#define MC_CMD_PTP_OUT_FPGAREAD_LENMAX_MCDI2 1020
2421#define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
2422#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
2423#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
2424#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
2425#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
2426#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
2427#define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM_MCDI2 1020
2428
2429/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */
2430#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
2431/* Time format required/used by for this NIC. Applies to all PTP MCDI
2432 * operations that pass times between the host and firmware. If this operation
2433 * is not supported (older firmware) a format of seconds and nanoseconds should
2434 * be assumed. Note this enum is deprecated. Do not add to it- use the
2435 * TIME_FORMAT field in MC_CMD_PTP_OUT_GET_ATTRIBUTES instead.
2436 */
2437#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
2438#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
2439/* enum: Times are in seconds and nanoseconds */
2440#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
2441/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
2442#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
2443/* enum: Major register has units of seconds, minor 2^-27s per tick */
2444#define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
2445
2446/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */
2447#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24
2448/* Time format required/used by for this NIC. Applies to all PTP MCDI
2449 * operations that pass times between the host and firmware. If this operation
2450 * is not supported (older firmware) a format of seconds and nanoseconds should
2451 * be assumed.
2452 */
2453#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
2454#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
2455/* enum: Times are in seconds and nanoseconds */
2456#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
2457/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
2458#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
2459/* enum: Major register has units of seconds, minor 2^-27s per tick */
2460#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
2461/* enum: Major register units are seconds, minor units are quarter nanoseconds
2462 */
2463#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
2464/* Minimum acceptable value for a corrected synchronization timeset. When
2465 * comparing host and NIC clock times, the MC returns a set of samples that
2466 * contain the host start and end time, the MC time when the host start was
2467 * detected and the time the MC waited between reading the time and detecting
2468 * the host end. The corrected sync window is the difference between the host
2469 * end and start times minus the time that the MC waited for host end.
2470 */
2471#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
2472#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
2473/* Various PTP capabilities */
2474#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8
2475#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
2476#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_OFST 8
2477#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
2478#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
2479#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_OFST 8
2480#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_LBN 1
2481#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RX_TSTAMP_OOB_WIDTH 1
2482#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_OFST 8
2483#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_LBN 2
2484#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_64BIT_SECONDS_WIDTH 1
2485#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_OFST 8
2486#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_LBN 3
2487#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_FP44_FREQ_ADJ_WIDTH 1
2488#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12
2489#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
2490#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16
2491#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
2492#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20
2493#define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
2494
2495/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */
2496#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16
2497/* Uncorrected error on PTP transmit timestamps in NIC clock format */
2498#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
2499#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
2500/* Uncorrected error on PTP receive timestamps in NIC clock format */
2501#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
2502#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
2503/* Uncorrected error on PPS output in NIC clock format */
2504#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8
2505#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
2506/* Uncorrected error on PPS input in NIC clock format */
2507#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12
2508#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
2509
2510/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */
2511#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24
2512/* Uncorrected error on PTP transmit timestamps in NIC clock format */
2513#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
2514#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
2515/* Uncorrected error on PTP receive timestamps in NIC clock format */
2516#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
2517#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
2518/* Uncorrected error on PPS output in NIC clock format */
2519#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8
2520#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
2521/* Uncorrected error on PPS input in NIC clock format */
2522#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12
2523#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
2524/* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
2525#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16
2526#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
2527/* Uncorrected error on non-PTP receive timestamps in NIC clock format */
2528#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20
2529#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
2530
2531/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */
2532#define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
2533/* Results of testing */
2534#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
2535#define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
2536/* Enum values, see field(s): */
2537/* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */
2538
2539/* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */
2540#define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
2541
2542
2543/***********************************/
2544/* MC_CMD_CSR_READ32
2545 * Read 32bit words from the indirect memory map.
2546 */
2547#define MC_CMD_CSR_READ32 0xc
2548#undef MC_CMD_0xc_PRIVILEGE_CTG
2549
2550#define MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2551
2552/* MC_CMD_CSR_READ32_IN msgrequest */
2553#define MC_CMD_CSR_READ32_IN_LEN 12
2554/* Address */
2555#define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
2556#define MC_CMD_CSR_READ32_IN_ADDR_LEN 4
2557#define MC_CMD_CSR_READ32_IN_STEP_OFST 4
2558#define MC_CMD_CSR_READ32_IN_STEP_LEN 4
2559#define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
2560#define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4
2561
2562/* MC_CMD_CSR_READ32_OUT msgresponse */
2563#define MC_CMD_CSR_READ32_OUT_LENMIN 4
2564#define MC_CMD_CSR_READ32_OUT_LENMAX 252
2565#define MC_CMD_CSR_READ32_OUT_LENMAX_MCDI2 1020
2566#define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
2567#define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
2568/* The last dword is the status, not a value read */
2569#define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
2570#define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
2571#define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
2572#define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
2573#define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM_MCDI2 255
2574
2575
2576/***********************************/
2577/* MC_CMD_CSR_WRITE32
2578 * Write 32bit dwords to the indirect memory map.
2579 */
2580#define MC_CMD_CSR_WRITE32 0xd
2581#undef MC_CMD_0xd_PRIVILEGE_CTG
2582
2583#define MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2584
2585/* MC_CMD_CSR_WRITE32_IN msgrequest */
2586#define MC_CMD_CSR_WRITE32_IN_LENMIN 12
2587#define MC_CMD_CSR_WRITE32_IN_LENMAX 252
2588#define MC_CMD_CSR_WRITE32_IN_LENMAX_MCDI2 1020
2589#define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
2590#define MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4)
2591/* Address */
2592#define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
2593#define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
2594#define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
2595#define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4
2596#define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
2597#define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
2598#define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
2599#define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
2600#define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM_MCDI2 253
2601
2602/* MC_CMD_CSR_WRITE32_OUT msgresponse */
2603#define MC_CMD_CSR_WRITE32_OUT_LEN 4
2604#define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
2605#define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4
2606
2607
2608/***********************************/
2609/* MC_CMD_HP
2610 * These commands are used for HP related features. They are grouped under one
2611 * MCDI command to avoid creating too many MCDI commands.
2612 */
2613#define MC_CMD_HP 0x54
2614#undef MC_CMD_0x54_PRIVILEGE_CTG
2615
2616#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2617
2618/* MC_CMD_HP_IN msgrequest */
2619#define MC_CMD_HP_IN_LEN 16
2620/* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
2621 * the specified address with the specified interval.When address is NULL,
2622 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
2623 * state / 2: (debug) Show temperature reported by one of the supported
2624 * sensors.
2625 */
2626#define MC_CMD_HP_IN_SUBCMD_OFST 0
2627#define MC_CMD_HP_IN_SUBCMD_LEN 4
2628/* enum: OCSD (Option Card Sensor Data) sub-command. */
2629#define MC_CMD_HP_IN_OCSD_SUBCMD 0x0
2630/* enum: Last known valid HP sub-command. */
2631#define MC_CMD_HP_IN_LAST_SUBCMD 0x0
2632/* The address to the array of sensor fields. (Or NULL to use a sub-command.)
2633 */
2634#define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
2635#define MC_CMD_HP_IN_OCSD_ADDR_LEN 8
2636#define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
2637#define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
2638/* The requested update interval, in seconds. (Or the sub-command if ADDR is
2639 * NULL.)
2640 */
2641#define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12
2642#define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4
2643
2644/* MC_CMD_HP_OUT msgresponse */
2645#define MC_CMD_HP_OUT_LEN 4
2646#define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
2647#define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4
2648/* enum: OCSD stopped for this card. */
2649#define MC_CMD_HP_OUT_OCSD_STOPPED 0x1
2650/* enum: OCSD was successfully started with the address provided. */
2651#define MC_CMD_HP_OUT_OCSD_STARTED 0x2
2652/* enum: OCSD was already started for this card. */
2653#define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
2654
2655
2656/***********************************/
2657/* MC_CMD_STACKINFO
2658 * Get stack information.
2659 */
2660#define MC_CMD_STACKINFO 0xf
2661#undef MC_CMD_0xf_PRIVILEGE_CTG
2662
2663#define MC_CMD_0xf_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2664
2665/* MC_CMD_STACKINFO_IN msgrequest */
2666#define MC_CMD_STACKINFO_IN_LEN 0
2667
2668/* MC_CMD_STACKINFO_OUT msgresponse */
2669#define MC_CMD_STACKINFO_OUT_LENMIN 12
2670#define MC_CMD_STACKINFO_OUT_LENMAX 252
2671#define MC_CMD_STACKINFO_OUT_LENMAX_MCDI2 1020
2672#define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
2673#define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)
2674/* (thread ptr, stack size, free space) for each thread in system */
2675#define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
2676#define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
2677#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
2678#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
2679#define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM_MCDI2 85
2680
2681
2682/***********************************/
2683/* MC_CMD_MDIO_READ
2684 * MDIO register read.
2685 */
2686#define MC_CMD_MDIO_READ 0x10
2687#undef MC_CMD_0x10_PRIVILEGE_CTG
2688
2689#define MC_CMD_0x10_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2690
2691/* MC_CMD_MDIO_READ_IN msgrequest */
2692#define MC_CMD_MDIO_READ_IN_LEN 16
2693/* Bus number; there are two MDIO buses: one for the internal PHY, and one for
2694 * external devices.
2695 */
2696#define MC_CMD_MDIO_READ_IN_BUS_OFST 0
2697#define MC_CMD_MDIO_READ_IN_BUS_LEN 4
2698/* enum: Internal. */
2699#define MC_CMD_MDIO_BUS_INTERNAL 0x0
2700/* enum: External. */
2701#define MC_CMD_MDIO_BUS_EXTERNAL 0x1
2702/* Port address */
2703#define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
2704#define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4
2705/* Device Address or clause 22. */
2706#define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
2707#define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4
2708/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
2709 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
2710 */
2711#define MC_CMD_MDIO_CLAUSE22 0x20
2712/* Address */
2713#define MC_CMD_MDIO_READ_IN_ADDR_OFST 12
2714#define MC_CMD_MDIO_READ_IN_ADDR_LEN 4
2715
2716/* MC_CMD_MDIO_READ_OUT msgresponse */
2717#define MC_CMD_MDIO_READ_OUT_LEN 8
2718/* Value */
2719#define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
2720#define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4
2721/* Status the MDIO commands return the raw status bits from the MDIO block. A
2722 * "good" transaction should have the DONE bit set and all other bits clear.
2723 */
2724#define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
2725#define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4
2726/* enum: Good. */
2727#define MC_CMD_MDIO_STATUS_GOOD 0x8
2728
2729
2730/***********************************/
2731/* MC_CMD_MDIO_WRITE
2732 * MDIO register write.
2733 */
2734#define MC_CMD_MDIO_WRITE 0x11
2735#undef MC_CMD_0x11_PRIVILEGE_CTG
2736
2737#define MC_CMD_0x11_PRIVILEGE_CTG SRIOV_CTG_ADMIN
2738
2739/* MC_CMD_MDIO_WRITE_IN msgrequest */
2740#define MC_CMD_MDIO_WRITE_IN_LEN 20
2741/* Bus number; there are two MDIO buses: one for the internal PHY, and one for
2742 * external devices.
2743 */
2744#define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
2745#define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4
2746/* enum: Internal. */
2747/* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
2748/* enum: External. */
2749/* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
2750/* Port address */
2751#define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
2752#define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4
2753/* Device Address or clause 22. */
2754#define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
2755#define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4
2756/* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
2757 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
2758 */
2759/* MC_CMD_MDIO_CLAUSE22 0x20 */
2760/* Address */
2761#define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
2762#define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4
2763/* Value */
2764#define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
2765#define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4
2766
2767/* MC_CMD_MDIO_WRITE_OUT msgresponse */
2768#define MC_CMD_MDIO_WRITE_OUT_LEN 4
2769/* Status; the MDIO commands return the raw status bits from the MDIO block. A
2770 * "good" transaction should have the DONE bit set and all other bits clear.
2771 */
2772#define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
2773#define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4
2774/* enum: Good. */
2775/* MC_CMD_MDIO_STATUS_GOOD 0x8 */
2776
2777
2778/***********************************/
2779/* MC_CMD_DBI_WRITE
2780 * Write DBI register(s).
2781 */
2782#define MC_CMD_DBI_WRITE 0x12
2783#undef MC_CMD_0x12_PRIVILEGE_CTG
2784
2785#define MC_CMD_0x12_PRIVILEGE_CTG SRIOV_CTG_INSECURE
2786
2787/* MC_CMD_DBI_WRITE_IN msgrequest */
2788#define MC_CMD_DBI_WRITE_IN_LENMIN 12
2789#define MC_CMD_DBI_WRITE_IN_LENMAX 252
2790#define MC_CMD_DBI_WRITE_IN_LENMAX_MCDI2 1020
2791#define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
2792#define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)
2793/* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
2794 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.
2795 */
2796#define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
2797#define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
2798#define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
2799#define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
2800#define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM_MCDI2 85
2801
2802/* MC_CMD_DBI_WRITE_OUT msgresponse */
2803#define MC_CMD_DBI_WRITE_OUT_LEN 0
2804
2805/* MC_CMD_DBIWROP_TYPEDEF structuredef */
2806#define MC_CMD_DBIWROP_TYPEDEF_LEN 12
2807#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
2808#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4
2809#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
2810#define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
2811#define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
2812#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4
2813#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 4
2814#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16
2815#define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16
2816#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 4
2817#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15
2818#define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
2819#define MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 4
2820#define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14
2821#define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
2822#define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32
2823#define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32
2824#define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
2825#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4
2826#define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
2827#define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32
2828
2829
2830/***********************************/
2831/* MC_CMD_PORT_READ32
2832 * Read a 32-bit register from the indirect port register map. The port to
2833 * access is implied by the Shared memory channel used.
2834 */
2835#define MC_CMD_PORT_READ32 0x14
2836
2837/* MC_CMD_PORT_READ32_IN msgrequest */
2838#define MC_CMD_PORT_READ32_IN_LEN 4
2839/* Address */
2840#define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
2841#define MC_CMD_PORT_READ32_IN_ADDR_LEN 4
2842
2843/* MC_CMD_PORT_READ32_OUT msgresponse */
2844#define MC_CMD_PORT_READ32_OUT_LEN 8
2845/* Value */
2846#define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
2847#define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4
2848/* Status */
2849#define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
2850#define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4
2851
2852
2853/***********************************/
2854/* MC_CMD_PORT_WRITE32
2855 * Write a 32-bit register to the indirect port register map. The port to
2856 * access is implied by the Shared memory channel used.
2857 */
2858#define MC_CMD_PORT_WRITE32 0x15
2859
2860/* MC_CMD_PORT_WRITE32_IN msgrequest */
2861#define MC_CMD_PORT_WRITE32_IN_LEN 8
2862/* Address */
2863#define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
2864#define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4
2865/* Value */
2866#define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
2867#define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4
2868
2869/* MC_CMD_PORT_WRITE32_OUT msgresponse */
2870#define MC_CMD_PORT_WRITE32_OUT_LEN 4
2871/* Status */
2872#define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
2873#define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4
2874
2875
2876/***********************************/
2877/* MC_CMD_PORT_READ128
2878 * Read a 128-bit register from the indirect port register map. The port to
2879 * access is implied by the Shared memory channel used.
2880 */
2881#define MC_CMD_PORT_READ128 0x16
2882
2883/* MC_CMD_PORT_READ128_IN msgrequest */
2884#define MC_CMD_PORT_READ128_IN_LEN 4
2885/* Address */
2886#define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
2887#define MC_CMD_PORT_READ128_IN_ADDR_LEN 4
2888
2889/* MC_CMD_PORT_READ128_OUT msgresponse */
2890#define MC_CMD_PORT_READ128_OUT_LEN 20
2891/* Value */
2892#define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
2893#define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
2894/* Status */
2895#define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
2896#define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4
2897
2898
2899/***********************************/
2900/* MC_CMD_PORT_WRITE128
2901 * Write a 128-bit register to the indirect port register map. The port to
2902 * access is implied by the Shared memory channel used.
2903 */
2904#define MC_CMD_PORT_WRITE128 0x17
2905
2906/* MC_CMD_PORT_WRITE128_IN msgrequest */
2907#define MC_CMD_PORT_WRITE128_IN_LEN 20
2908/* Address */
2909#define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
2910#define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4
2911/* Value */
2912#define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
2913#define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16
2914
2915/* MC_CMD_PORT_WRITE128_OUT msgresponse */
2916#define MC_CMD_PORT_WRITE128_OUT_LEN 4
2917/* Status */
2918#define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
2919#define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4
2920
2921/* MC_CMD_CAPABILITIES structuredef */
2922#define MC_CMD_CAPABILITIES_LEN 4
2923/* Small buf table. */
2924#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
2925#define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1
2926/* Turbo mode (for Maranello). */
2927#define MC_CMD_CAPABILITIES_TURBO_LBN 1
2928#define MC_CMD_CAPABILITIES_TURBO_WIDTH 1
2929/* Turbo mode active (for Maranello). */
2930#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2
2931#define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1
2932/* PTP offload. */
2933#define MC_CMD_CAPABILITIES_PTP_LBN 3
2934#define MC_CMD_CAPABILITIES_PTP_WIDTH 1
2935/* AOE mode. */
2936#define MC_CMD_CAPABILITIES_AOE_LBN 4
2937#define MC_CMD_CAPABILITIES_AOE_WIDTH 1
2938/* AOE mode active. */
2939#define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5
2940#define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1
2941/* AOE mode active. */
2942#define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6
2943#define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1
2944#define MC_CMD_CAPABILITIES_RESERVED_LBN 7
2945#define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25
2946
2947
2948/***********************************/
2949/* MC_CMD_GET_BOARD_CFG
2950 * Returns the MC firmware configuration structure.
2951 */
2952#define MC_CMD_GET_BOARD_CFG 0x18
2953#undef MC_CMD_0x18_PRIVILEGE_CTG
2954
2955#define MC_CMD_0x18_PRIVILEGE_CTG SRIOV_CTG_GENERAL
2956
2957/* MC_CMD_GET_BOARD_CFG_IN msgrequest */
2958#define MC_CMD_GET_BOARD_CFG_IN_LEN 0
2959
2960/* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
2961#define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
2962#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
2963#define MC_CMD_GET_BOARD_CFG_OUT_LENMAX_MCDI2 136
2964#define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
2965#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)
2966#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
2967#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
2968#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
2969#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
2970/* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on
2971 * EF10 and later (use MC_CMD_GET_CAPABILITIES).
2972 */
2973#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
2974#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
2975/* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on
2976 * EF10 and later (use MC_CMD_GET_CAPABILITIES).
2977 */
2978#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
2979#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
2980/* Base MAC address for Siena Port0. Unused on EF10 and later (use
2981 * MC_CMD_GET_MAC_ADDRESSES).
2982 */
2983#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
2984#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
2985/* Base MAC address for Siena Port1. Unused on EF10 and later (use
2986 * MC_CMD_GET_MAC_ADDRESSES).
2987 */
2988#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
2989#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
2990/* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use
2991 * MC_CMD_GET_MAC_ADDRESSES).
2992 */
2993#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
2994#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
2995/* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use
2996 * MC_CMD_GET_MAC_ADDRESSES).
2997 */
2998#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
2999#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
3000/* Increment between addresses in MAC address pool for Siena Port0. Unused on
3001 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
3002 */
3003#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
3004#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
3005/* Increment between addresses in MAC address pool for Siena Port1. Unused on
3006 * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
3007 */
3008#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
3009#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
3010/* Siena only. This field contains a 16-bit value for each of the types of
3011 * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a
3012 * specific board type, but otherwise have no meaning to the MC; they are used
3013 * by the driver to manage selection of appropriate firmware updates. Unused on
3014 * EF10 and later (use MC_CMD_NVRAM_METADATA).
3015 */
3016#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
3017#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
3018#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
3019#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
3020#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM_MCDI2 32
3021
3022
3023/***********************************/
3024/* MC_CMD_DBI_READX
3025 * Read DBI register(s) -- extended functionality
3026 */
3027#define MC_CMD_DBI_READX 0x19
3028#undef MC_CMD_0x19_PRIVILEGE_CTG
3029
3030#define MC_CMD_0x19_PRIVILEGE_CTG SRIOV_CTG_INSECURE
3031
3032/* MC_CMD_DBI_READX_IN msgrequest */
3033#define MC_CMD_DBI_READX_IN_LENMIN 8
3034#define MC_CMD_DBI_READX_IN_LENMAX 248
3035#define MC_CMD_DBI_READX_IN_LENMAX_MCDI2 1016
3036#define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
3037#define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)
3038/* Each Read op consists of an address (offset 0), VF/CS2) */
3039#define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
3040#define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
3041#define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
3042#define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
3043#define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
3044#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
3045#define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM_MCDI2 127
3046
3047/* MC_CMD_DBI_READX_OUT msgresponse */
3048#define MC_CMD_DBI_READX_OUT_LENMIN 4
3049#define MC_CMD_DBI_READX_OUT_LENMAX 252
3050#define MC_CMD_DBI_READX_OUT_LENMAX_MCDI2 1020
3051#define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
3052#define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)
3053/* Value */
3054#define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
3055#define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
3056#define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
3057#define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
3058#define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM_MCDI2 255
3059
3060/* MC_CMD_DBIRDOP_TYPEDEF structuredef */
3061#define MC_CMD_DBIRDOP_TYPEDEF_LEN 8
3062#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
3063#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4
3064#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
3065#define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32
3066#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
3067#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4
3068#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 4
3069#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16
3070#define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16
3071#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 4
3072#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15
3073#define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
3074#define MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 4
3075#define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14
3076#define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
3077#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32
3078#define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32
3079
3080
3081/***********************************/
3082/* MC_CMD_SET_RAND_SEED
3083 * Set the 16byte seed for the MC pseudo-random generator.
3084 */
3085#define MC_CMD_SET_RAND_SEED 0x1a
3086#undef MC_CMD_0x1a_PRIVILEGE_CTG
3087
3088#define MC_CMD_0x1a_PRIVILEGE_CTG SRIOV_CTG_INSECURE
3089
3090/* MC_CMD_SET_RAND_SEED_IN msgrequest */
3091#define MC_CMD_SET_RAND_SEED_IN_LEN 16
3092/* Seed value. */
3093#define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
3094#define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16
3095
3096/* MC_CMD_SET_RAND_SEED_OUT msgresponse */
3097#define MC_CMD_SET_RAND_SEED_OUT_LEN 0
3098
3099
3100/***********************************/
3101/* MC_CMD_LTSSM_HIST
3102 * Retrieve the history of the LTSSM, if the build supports it.
3103 */
3104#define MC_CMD_LTSSM_HIST 0x1b
3105
3106/* MC_CMD_LTSSM_HIST_IN msgrequest */
3107#define MC_CMD_LTSSM_HIST_IN_LEN 0
3108
3109/* MC_CMD_LTSSM_HIST_OUT msgresponse */
3110#define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
3111#define MC_CMD_LTSSM_HIST_OUT_LENMAX 252
3112#define MC_CMD_LTSSM_HIST_OUT_LENMAX_MCDI2 1020
3113#define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
3114#define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)
3115/* variable number of LTSSM values, as bytes. The history is read-to-clear. */
3116#define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
3117#define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
3118#define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
3119#define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
3120#define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM_MCDI2 255
3121
3122
3123/***********************************/
3124/* MC_CMD_DRV_ATTACH
3125 * Inform MCPU that this port is managed on the host (i.e. driver active). For
3126 * Huntington, also request the preferred datapath firmware to use if possible
3127 * (it may not be possible for this request to be fulfilled; the driver must
3128 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which
3129 * features are actually available). The FIRMWARE_ID field is ignored by older
3130 * platforms.
3131 */
3132#define MC_CMD_DRV_ATTACH 0x1c
3133#undef MC_CMD_0x1c_PRIVILEGE_CTG
3134
3135#define MC_CMD_0x1c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3136
3137/* MC_CMD_DRV_ATTACH_IN msgrequest */
3138#define MC_CMD_DRV_ATTACH_IN_LEN 12
3139/* new state to set if UPDATE=1 */
3140#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
3141#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
3142#define MC_CMD_DRV_ATTACH_OFST 0
3143#define MC_CMD_DRV_ATTACH_LBN 0
3144#define MC_CMD_DRV_ATTACH_WIDTH 1
3145#define MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0
3146#define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
3147#define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
3148#define MC_CMD_DRV_PREBOOT_OFST 0
3149#define MC_CMD_DRV_PREBOOT_LBN 1
3150#define MC_CMD_DRV_PREBOOT_WIDTH 1
3151#define MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0
3152#define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
3153#define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
3154#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0
3155#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2
3156#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
3157#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0
3158#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_LBN 3
3159#define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_WIDTH 1
3160#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0
3161#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4
3162#define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_WIDTH 1
3163#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
3164#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
3165#define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
3166#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0
3167#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_LBN 5
3168#define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_WIDTH 1
3169/* 1 to set new state, or 0 to just report the existing state */
3170#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
3171#define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
3172/* preferred datapath firmware (for Huntington; ignored for Siena) */
3173#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8
3174#define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
3175/* enum: Prefer to use full featured firmware */
3176#define MC_CMD_FW_FULL_FEATURED 0x0
3177/* enum: Prefer to use firmware with fewer features but lower latency */
3178#define MC_CMD_FW_LOW_LATENCY 0x1
3179/* enum: Prefer to use firmware for SolarCapture packed stream mode */
3180#define MC_CMD_FW_PACKED_STREAM 0x2
3181/* enum: Prefer to use firmware with fewer features and simpler TX event
3182 * batching but higher TX packet rate
3183 */
3184#define MC_CMD_FW_HIGH_TX_RATE 0x3
3185/* enum: Reserved value */
3186#define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
3187/* enum: Prefer to use firmware with additional "rules engine" filtering
3188 * support
3189 */
3190#define MC_CMD_FW_RULES_ENGINE 0x5
3191/* enum: Prefer to use firmware with additional DPDK support */
3192#define MC_CMD_FW_DPDK 0x6
3193/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
3194 * bug69716)
3195 */
3196#define MC_CMD_FW_L3XUDP 0x7
3197/* enum: Requests that the MC keep whatever datapath firmware is currently
3198 * running. It's used for test purposes, where we want to be able to shmboot
3199 * special test firmware variants. This option is only recognised in eftest
3200 * (i.e. non-production) builds.
3201 */
3202#define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe
3203/* enum: Only this option is allowed for non-admin functions */
3204#define MC_CMD_FW_DONT_CARE 0xffffffff
3205
3206/* MC_CMD_DRV_ATTACH_IN_V2 msgrequest: Updated DRV_ATTACH to include driver
3207 * version
3208 */
3209#define MC_CMD_DRV_ATTACH_IN_V2_LEN 32
3210/* new state to set if UPDATE=1 */
3211#define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0
3212#define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4
3213/* MC_CMD_DRV_ATTACH_OFST 0 */
3214/* MC_CMD_DRV_ATTACH_LBN 0 */
3215/* MC_CMD_DRV_ATTACH_WIDTH 1 */
3216#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0
3217#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0
3218#define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_WIDTH 1
3219/* MC_CMD_DRV_PREBOOT_OFST 0 */
3220/* MC_CMD_DRV_PREBOOT_LBN 1 */
3221/* MC_CMD_DRV_PREBOOT_WIDTH 1 */
3222#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0
3223#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_LBN 1
3224#define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_WIDTH 1
3225#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0
3226#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_LBN 2
3227#define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_WIDTH 1
3228#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0
3229#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_LBN 3
3230#define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_WIDTH 1
3231#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0
3232#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4
3233#define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_WIDTH 1
3234#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
3235#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_LBN 5
3236#define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_WIDTH 1
3237#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0
3238#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_LBN 5
3239#define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_WIDTH 1
3240/* 1 to set new state, or 0 to just report the existing state */
3241#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4
3242#define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4
3243/* preferred datapath firmware (for Huntington; ignored for Siena) */
3244#define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_OFST 8
3245#define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4
3246/* enum: Prefer to use full featured firmware */
3247/* MC_CMD_FW_FULL_FEATURED 0x0 */
3248/* enum: Prefer to use firmware with fewer features but lower latency */
3249/* MC_CMD_FW_LOW_LATENCY 0x1 */
3250/* enum: Prefer to use firmware for SolarCapture packed stream mode */
3251/* MC_CMD_FW_PACKED_STREAM 0x2 */
3252/* enum: Prefer to use firmware with fewer features and simpler TX event
3253 * batching but higher TX packet rate
3254 */
3255/* MC_CMD_FW_HIGH_TX_RATE 0x3 */
3256/* enum: Reserved value */
3257/* MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */
3258/* enum: Prefer to use firmware with additional "rules engine" filtering
3259 * support
3260 */
3261/* MC_CMD_FW_RULES_ENGINE 0x5 */
3262/* enum: Prefer to use firmware with additional DPDK support */
3263/* MC_CMD_FW_DPDK 0x6 */
3264/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
3265 * bug69716)
3266 */
3267/* MC_CMD_FW_L3XUDP 0x7 */
3268/* enum: Requests that the MC keep whatever datapath firmware is currently
3269 * running. It's used for test purposes, where we want to be able to shmboot
3270 * special test firmware variants. This option is only recognised in eftest
3271 * (i.e. non-production) builds.
3272 */
3273/* MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */
3274/* enum: Only this option is allowed for non-admin functions */
3275/* MC_CMD_FW_DONT_CARE 0xffffffff */
3276/* Version of the driver to be reported by management protocols (e.g. NC-SI)
3277 * handled by the NIC. This is a zero-terminated ASCII string.
3278 */
3279#define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_OFST 12
3280#define MC_CMD_DRV_ATTACH_IN_V2_DRIVER_VERSION_LEN 20
3281
3282/* MC_CMD_DRV_ATTACH_OUT msgresponse */
3283#define MC_CMD_DRV_ATTACH_OUT_LEN 4
3284/* previous or existing state, see the bitmask at NEW_STATE */
3285#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
3286#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
3287
3288/* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */
3289#define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8
3290/* previous or existing state, see the bitmask at NEW_STATE */
3291#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
3292#define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
3293/* Flags associated with this function */
3294#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
3295#define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
3296/* enum: Labels the lowest-numbered function visible to the OS */
3297#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
3298/* enum: The function can control the link state of the physical port it is
3299 * bound to.
3300 */
3301#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
3302/* enum: The function can perform privileged operations */
3303#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
3304/* enum: The function does not have an active port associated with it. The port
3305 * refers to the Sorrento external FPGA port.
3306 */
3307#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
3308/* enum: If set, indicates that VI spreading is currently enabled. Will always
3309 * indicate the current state, regardless of the value in the WANT_VI_SPREADING
3310 * input.
3311 */
3312#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
3313/* enum: Used during development only. Should no longer be used. */
3314#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5
3315/* enum: If set, indicates that TX only spreading is enabled. Even-numbered
3316 * TXQs will use one engine, and odd-numbered TXQs will use the other. This
3317 * also has the effect that only even-numbered RXQs will receive traffic.
3318 */
3319#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5
3320
3321
3322/***********************************/
3323/* MC_CMD_SHMUART
3324 * Route UART output to circular buffer in shared memory instead.
3325 */
3326#define MC_CMD_SHMUART 0x1f
3327
3328/* MC_CMD_SHMUART_IN msgrequest */
3329#define MC_CMD_SHMUART_IN_LEN 4
3330/* ??? */
3331#define MC_CMD_SHMUART_IN_FLAG_OFST 0
3332#define MC_CMD_SHMUART_IN_FLAG_LEN 4
3333
3334/* MC_CMD_SHMUART_OUT msgresponse */
3335#define MC_CMD_SHMUART_OUT_LEN 0
3336
3337
3338/***********************************/
3339/* MC_CMD_PORT_RESET
3340 * Generic per-port reset. There is no equivalent for per-board reset. Locks
3341 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
3342 * use MC_CMD_ENTITY_RESET instead.
3343 */
3344#define MC_CMD_PORT_RESET 0x20
3345#undef MC_CMD_0x20_PRIVILEGE_CTG
3346
3347#define MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3348
3349/* MC_CMD_PORT_RESET_IN msgrequest */
3350#define MC_CMD_PORT_RESET_IN_LEN 0
3351
3352/* MC_CMD_PORT_RESET_OUT msgresponse */
3353#define MC_CMD_PORT_RESET_OUT_LEN 0
3354
3355
3356/***********************************/
3357/* MC_CMD_ENTITY_RESET
3358 * Generic per-resource reset. There is no equivalent for per-board reset.
3359 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
3360 * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
3361 */
3362#define MC_CMD_ENTITY_RESET 0x20
3363/* MC_CMD_0x20_PRIVILEGE_CTG SRIOV_CTG_GENERAL */
3364
3365/* MC_CMD_ENTITY_RESET_IN msgrequest */
3366#define MC_CMD_ENTITY_RESET_IN_LEN 4
3367/* Optional flags field. Omitting this will perform a "legacy" reset action
3368 * (TBD).
3369 */
3370#define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
3371#define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
3372#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 0
3373#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
3374#define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
3375
3376/* MC_CMD_ENTITY_RESET_OUT msgresponse */
3377#define MC_CMD_ENTITY_RESET_OUT_LEN 0
3378
3379
3380/***********************************/
3381/* MC_CMD_PCIE_CREDITS
3382 * Read instantaneous and minimum flow control thresholds.
3383 */
3384#define MC_CMD_PCIE_CREDITS 0x21
3385
3386/* MC_CMD_PCIE_CREDITS_IN msgrequest */
3387#define MC_CMD_PCIE_CREDITS_IN_LEN 8
3388/* poll period. 0 is disabled */
3389#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
3390#define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4
3391/* wipe statistics */
3392#define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
3393#define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4
3394
3395/* MC_CMD_PCIE_CREDITS_OUT msgresponse */
3396#define MC_CMD_PCIE_CREDITS_OUT_LEN 16
3397#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
3398#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
3399#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
3400#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
3401#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
3402#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
3403#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
3404#define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
3405#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
3406#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
3407#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
3408#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
3409#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
3410#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
3411#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
3412#define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2
3413
3414
3415/***********************************/
3416/* MC_CMD_RXD_MONITOR
3417 * Get histogram of RX queue fill level.
3418 */
3419#define MC_CMD_RXD_MONITOR 0x22
3420
3421/* MC_CMD_RXD_MONITOR_IN msgrequest */
3422#define MC_CMD_RXD_MONITOR_IN_LEN 12
3423#define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
3424#define MC_CMD_RXD_MONITOR_IN_QID_LEN 4
3425#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
3426#define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4
3427#define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
3428#define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4
3429
3430/* MC_CMD_RXD_MONITOR_OUT msgresponse */
3431#define MC_CMD_RXD_MONITOR_OUT_LEN 80
3432#define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
3433#define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4
3434#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
3435#define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4
3436#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
3437#define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4
3438#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
3439#define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4
3440#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
3441#define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4
3442#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
3443#define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4
3444#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
3445#define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4
3446#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
3447#define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4
3448#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
3449#define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4
3450#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
3451#define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4
3452#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
3453#define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4
3454#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
3455#define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4
3456#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
3457#define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4
3458#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
3459#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4
3460#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
3461#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4
3462#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
3463#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4
3464#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
3465#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4
3466#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
3467#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4
3468#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
3469#define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4
3470#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
3471#define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4
3472
3473
3474/***********************************/
3475/* MC_CMD_PUTS
3476 * Copy the given ASCII string out onto UART and/or out of the network port.
3477 */
3478#define MC_CMD_PUTS 0x23
3479#undef MC_CMD_0x23_PRIVILEGE_CTG
3480
3481#define MC_CMD_0x23_PRIVILEGE_CTG SRIOV_CTG_INSECURE
3482
3483/* MC_CMD_PUTS_IN msgrequest */
3484#define MC_CMD_PUTS_IN_LENMIN 13
3485#define MC_CMD_PUTS_IN_LENMAX 252
3486#define MC_CMD_PUTS_IN_LENMAX_MCDI2 1020
3487#define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
3488#define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)
3489#define MC_CMD_PUTS_IN_DEST_OFST 0
3490#define MC_CMD_PUTS_IN_DEST_LEN 4
3491#define MC_CMD_PUTS_IN_UART_OFST 0
3492#define MC_CMD_PUTS_IN_UART_LBN 0
3493#define MC_CMD_PUTS_IN_UART_WIDTH 1
3494#define MC_CMD_PUTS_IN_PORT_OFST 0
3495#define MC_CMD_PUTS_IN_PORT_LBN 1
3496#define MC_CMD_PUTS_IN_PORT_WIDTH 1
3497#define MC_CMD_PUTS_IN_DHOST_OFST 4
3498#define MC_CMD_PUTS_IN_DHOST_LEN 6
3499#define MC_CMD_PUTS_IN_STRING_OFST 12
3500#define MC_CMD_PUTS_IN_STRING_LEN 1
3501#define MC_CMD_PUTS_IN_STRING_MINNUM 1
3502#define MC_CMD_PUTS_IN_STRING_MAXNUM 240
3503#define MC_CMD_PUTS_IN_STRING_MAXNUM_MCDI2 1008
3504
3505/* MC_CMD_PUTS_OUT msgresponse */
3506#define MC_CMD_PUTS_OUT_LEN 0
3507
3508
3509/***********************************/
3510/* MC_CMD_GET_PHY_CFG
3511 * Report PHY configuration. This guarantees to succeed even if the PHY is in a
3512 * 'zombie' state. Locks required: None
3513 */
3514#define MC_CMD_GET_PHY_CFG 0x24
3515#undef MC_CMD_0x24_PRIVILEGE_CTG
3516
3517#define MC_CMD_0x24_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3518
3519/* MC_CMD_GET_PHY_CFG_IN msgrequest */
3520#define MC_CMD_GET_PHY_CFG_IN_LEN 0
3521
3522/* MC_CMD_GET_PHY_CFG_OUT msgresponse */
3523#define MC_CMD_GET_PHY_CFG_OUT_LEN 72
3524/* flags */
3525#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
3526#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
3527#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 0
3528#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
3529#define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
3530#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 0
3531#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
3532#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
3533#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 0
3534#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
3535#define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
3536#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 0
3537#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
3538#define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
3539#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 0
3540#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
3541#define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
3542#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 0
3543#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
3544#define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
3545#define MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 0
3546#define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
3547#define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
3548/* ?? */
3549#define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
3550#define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
3551/* Bitmask of supported capabilities */
3552#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
3553#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
3554#define MC_CMD_PHY_CAP_10HDX_OFST 8
3555#define MC_CMD_PHY_CAP_10HDX_LBN 1
3556#define MC_CMD_PHY_CAP_10HDX_WIDTH 1
3557#define MC_CMD_PHY_CAP_10FDX_OFST 8
3558#define MC_CMD_PHY_CAP_10FDX_LBN 2
3559#define MC_CMD_PHY_CAP_10FDX_WIDTH 1
3560#define MC_CMD_PHY_CAP_100HDX_OFST 8
3561#define MC_CMD_PHY_CAP_100HDX_LBN 3
3562#define MC_CMD_PHY_CAP_100HDX_WIDTH 1
3563#define MC_CMD_PHY_CAP_100FDX_OFST 8
3564#define MC_CMD_PHY_CAP_100FDX_LBN 4
3565#define MC_CMD_PHY_CAP_100FDX_WIDTH 1
3566#define MC_CMD_PHY_CAP_1000HDX_OFST 8
3567#define MC_CMD_PHY_CAP_1000HDX_LBN 5
3568#define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
3569#define MC_CMD_PHY_CAP_1000FDX_OFST 8
3570#define MC_CMD_PHY_CAP_1000FDX_LBN 6
3571#define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
3572#define MC_CMD_PHY_CAP_10000FDX_OFST 8
3573#define MC_CMD_PHY_CAP_10000FDX_LBN 7
3574#define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
3575#define MC_CMD_PHY_CAP_PAUSE_OFST 8
3576#define MC_CMD_PHY_CAP_PAUSE_LBN 8
3577#define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
3578#define MC_CMD_PHY_CAP_ASYM_OFST 8
3579#define MC_CMD_PHY_CAP_ASYM_LBN 9
3580#define MC_CMD_PHY_CAP_ASYM_WIDTH 1
3581#define MC_CMD_PHY_CAP_AN_OFST 8
3582#define MC_CMD_PHY_CAP_AN_LBN 10
3583#define MC_CMD_PHY_CAP_AN_WIDTH 1
3584#define MC_CMD_PHY_CAP_40000FDX_OFST 8
3585#define MC_CMD_PHY_CAP_40000FDX_LBN 11
3586#define MC_CMD_PHY_CAP_40000FDX_WIDTH 1
3587#define MC_CMD_PHY_CAP_DDM_OFST 8
3588#define MC_CMD_PHY_CAP_DDM_LBN 12
3589#define MC_CMD_PHY_CAP_DDM_WIDTH 1
3590#define MC_CMD_PHY_CAP_100000FDX_OFST 8
3591#define MC_CMD_PHY_CAP_100000FDX_LBN 13
3592#define MC_CMD_PHY_CAP_100000FDX_WIDTH 1
3593#define MC_CMD_PHY_CAP_25000FDX_OFST 8
3594#define MC_CMD_PHY_CAP_25000FDX_LBN 14
3595#define MC_CMD_PHY_CAP_25000FDX_WIDTH 1
3596#define MC_CMD_PHY_CAP_50000FDX_OFST 8
3597#define MC_CMD_PHY_CAP_50000FDX_LBN 15
3598#define MC_CMD_PHY_CAP_50000FDX_WIDTH 1
3599#define MC_CMD_PHY_CAP_BASER_FEC_OFST 8
3600#define MC_CMD_PHY_CAP_BASER_FEC_LBN 16
3601#define MC_CMD_PHY_CAP_BASER_FEC_WIDTH 1
3602#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_OFST 8
3603#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN 17
3604#define MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_WIDTH 1
3605#define MC_CMD_PHY_CAP_RS_FEC_OFST 8
3606#define MC_CMD_PHY_CAP_RS_FEC_LBN 18
3607#define MC_CMD_PHY_CAP_RS_FEC_WIDTH 1
3608#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_OFST 8
3609#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN 19
3610#define MC_CMD_PHY_CAP_RS_FEC_REQUESTED_WIDTH 1
3611#define MC_CMD_PHY_CAP_25G_BASER_FEC_OFST 8
3612#define MC_CMD_PHY_CAP_25G_BASER_FEC_LBN 20
3613#define MC_CMD_PHY_CAP_25G_BASER_FEC_WIDTH 1
3614#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_OFST 8
3615#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN 21
3616#define MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_WIDTH 1
3617/* ?? */
3618#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
3619#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
3620/* ?? */
3621#define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
3622#define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
3623/* ?? */
3624#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
3625#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
3626/* ?? */
3627#define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
3628#define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
3629/* ?? */
3630#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
3631#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
3632/* enum: Xaui. */
3633#define MC_CMD_MEDIA_XAUI 0x1
3634/* enum: CX4. */
3635#define MC_CMD_MEDIA_CX4 0x2
3636/* enum: KX4. */
3637#define MC_CMD_MEDIA_KX4 0x3
3638/* enum: XFP Far. */
3639#define MC_CMD_MEDIA_XFP 0x4
3640/* enum: SFP+. */
3641#define MC_CMD_MEDIA_SFP_PLUS 0x5
3642/* enum: 10GBaseT. */
3643#define MC_CMD_MEDIA_BASE_T 0x6
3644/* enum: QSFP+. */
3645#define MC_CMD_MEDIA_QSFP_PLUS 0x7
3646#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
3647#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
3648/* enum: Native clause 22 */
3649#define MC_CMD_MMD_CLAUSE22 0x0
3650#define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
3651#define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
3652#define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
3653#define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
3654#define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
3655#define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
3656#define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
3657/* enum: Clause22 proxied over clause45 by PHY. */
3658#define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
3659#define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
3660#define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
3661#define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
3662#define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
3663
3664
3665/***********************************/
3666/* MC_CMD_START_BIST
3667 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST
3668 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
3669 */
3670#define MC_CMD_START_BIST 0x25
3671#undef MC_CMD_0x25_PRIVILEGE_CTG
3672
3673#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3674
3675/* MC_CMD_START_BIST_IN msgrequest */
3676#define MC_CMD_START_BIST_IN_LEN 4
3677/* Type of test. */
3678#define MC_CMD_START_BIST_IN_TYPE_OFST 0
3679#define MC_CMD_START_BIST_IN_TYPE_LEN 4
3680/* enum: Run the PHY's short cable BIST. */
3681#define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
3682/* enum: Run the PHY's long cable BIST. */
3683#define MC_CMD_PHY_BIST_CABLE_LONG 0x2
3684/* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */
3685#define MC_CMD_BPX_SERDES_BIST 0x3
3686/* enum: Run the MC loopback tests. */
3687#define MC_CMD_MC_LOOPBACK_BIST 0x4
3688/* enum: Run the PHY's standard BIST. */
3689#define MC_CMD_PHY_BIST 0x5
3690/* enum: Run MC RAM test. */
3691#define MC_CMD_MC_MEM_BIST 0x6
3692/* enum: Run Port RAM test. */
3693#define MC_CMD_PORT_MEM_BIST 0x7
3694/* enum: Run register test. */
3695#define MC_CMD_REG_BIST 0x8
3696
3697/* MC_CMD_START_BIST_OUT msgresponse */
3698#define MC_CMD_START_BIST_OUT_LEN 0
3699
3700
3701/***********************************/
3702/* MC_CMD_POLL_BIST
3703 * Poll for BIST completion. Returns a single status code, and optionally some
3704 * PHY specific bist output. The driver should only consume the BIST output
3705 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't
3706 * successfully parse the BIST output, it should still respect the pass/Fail in
3707 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
3708 * EACCES (if PHY_LOCK is not held).
3709 */
3710#define MC_CMD_POLL_BIST 0x26
3711#undef MC_CMD_0x26_PRIVILEGE_CTG
3712
3713#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN
3714
3715/* MC_CMD_POLL_BIST_IN msgrequest */
3716#define MC_CMD_POLL_BIST_IN_LEN 0
3717
3718/* MC_CMD_POLL_BIST_OUT msgresponse */
3719#define MC_CMD_POLL_BIST_OUT_LEN 8
3720/* result */
3721#define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
3722#define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
3723/* enum: Running. */
3724#define MC_CMD_POLL_BIST_RUNNING 0x1
3725/* enum: Passed. */
3726#define MC_CMD_POLL_BIST_PASSED 0x2
3727/* enum: Failed. */
3728#define MC_CMD_POLL_BIST_FAILED 0x3
3729/* enum: Timed-out. */
3730#define MC_CMD_POLL_BIST_TIMEOUT 0x4
3731#define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
3732#define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4
3733
3734/* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
3735#define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
3736/* result */
3737/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3738/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3739/* Enum values, see field(s): */
3740/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3741#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
3742#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
3743#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
3744#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
3745#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
3746#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
3747#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
3748#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
3749/* Status of each channel A */
3750#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
3751#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
3752/* enum: Ok. */
3753#define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
3754/* enum: Open. */
3755#define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
3756/* enum: Intra-pair short. */
3757#define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
3758/* enum: Inter-pair short. */
3759#define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
3760/* enum: Busy. */
3761#define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
3762/* Status of each channel B */
3763#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
3764#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
3765/* Enum values, see field(s): */
3766/* CABLE_STATUS_A */
3767/* Status of each channel C */
3768#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
3769#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
3770/* Enum values, see field(s): */
3771/* CABLE_STATUS_A */
3772/* Status of each channel D */
3773#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
3774#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
3775/* Enum values, see field(s): */
3776/* CABLE_STATUS_A */
3777
3778/* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
3779#define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
3780/* result */
3781/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3782/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3783/* Enum values, see field(s): */
3784/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3785#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
3786#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
3787/* enum: Complete. */
3788#define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
3789/* enum: Bus switch off I2C write. */
3790#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
3791/* enum: Bus switch off I2C no access IO exp. */
3792#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
3793/* enum: Bus switch off I2C no access module. */
3794#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
3795/* enum: IO exp I2C configure. */
3796#define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
3797/* enum: Bus switch I2C no cross talk. */
3798#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
3799/* enum: Module presence. */
3800#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
3801/* enum: Module ID I2C access. */
3802#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
3803/* enum: Module ID sane value. */
3804#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
3805
3806/* MC_CMD_POLL_BIST_OUT_MEM msgresponse */
3807#define MC_CMD_POLL_BIST_OUT_MEM_LEN 36
3808/* result */
3809/* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
3810/* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
3811/* Enum values, see field(s): */
3812/* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
3813#define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
3814#define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
3815/* enum: Test has completed. */
3816#define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
3817/* enum: RAM test - walk ones. */
3818#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
3819/* enum: RAM test - walk zeros. */
3820#define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
3821/* enum: RAM test - walking inversions zeros/ones. */
3822#define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
3823/* enum: RAM test - walking inversions checkerboard. */
3824#define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
3825/* enum: Register test - set / clear individual bits. */
3826#define MC_CMD_POLL_BIST_MEM_REG 0x5
3827/* enum: ECC error detected. */
3828#define MC_CMD_POLL_BIST_MEM_ECC 0x6
3829/* Failure address, only valid if result is POLL_BIST_FAILED */
3830#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8
3831#define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
3832/* Bus or address space to which the failure address corresponds */
3833#define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12
3834#define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
3835/* enum: MC MIPS bus. */
3836#define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
3837/* enum: CSR IREG bus. */
3838#define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
3839/* enum: RX0 DPCPU bus. */
3840#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
3841/* enum: TX0 DPCPU bus. */
3842#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
3843/* enum: TX1 DPCPU bus. */
3844#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
3845/* enum: RX0 DICPU bus. */
3846#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
3847/* enum: TX DICPU bus. */
3848#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
3849/* enum: RX1 DPCPU bus. */
3850#define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
3851/* enum: RX1 DICPU bus. */
3852#define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
3853/* Pattern written to RAM / register */
3854#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16
3855#define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
3856/* Actual value read from RAM / register */
3857#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20
3858#define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
3859/* ECC error mask */
3860#define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24
3861#define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
3862/* ECC parity error mask */
3863#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28
3864#define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
3865/* ECC fatal error mask */
3866#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32
3867#define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4
3868
3869
3870/***********************************/
3871/* MC_CMD_FLUSH_RX_QUEUES
3872 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ
3873 * flushes should be initiated via this MCDI operation, rather than via
3874 * directly writing FLUSH_CMD.
3875 *
3876 * The flush is completed (either done/fail) asynchronously (after this command
3877 * returns). The driver must still wait for flush done/failure events as usual.
3878 */
3879#define MC_CMD_FLUSH_RX_QUEUES 0x27
3880
3881/* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
3882#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
3883#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
3884#define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX_MCDI2 1020
3885#define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
3886#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)
3887#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
3888#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
3889#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
3890#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
3891#define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM_MCDI2 255
3892
3893/* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
3894#define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
3895
3896
3897/***********************************/
3898/* MC_CMD_GET_LOOPBACK_MODES
3899 * Returns a bitmask of loopback modes available at each speed.
3900 */
3901#define MC_CMD_GET_LOOPBACK_MODES 0x28
3902#undef MC_CMD_0x28_PRIVILEGE_CTG
3903
3904#define MC_CMD_0x28_PRIVILEGE_CTG SRIOV_CTG_GENERAL
3905
3906/* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
3907#define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
3908
3909/* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
3910#define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40
3911/* Supported loopbacks. */
3912#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
3913#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
3914#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
3915#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
3916/* enum: None. */
3917#define MC_CMD_LOOPBACK_NONE 0x0
3918/* enum: Data. */
3919#define MC_CMD_LOOPBACK_DATA 0x1
3920/* enum: GMAC. */
3921#define MC_CMD_LOOPBACK_GMAC 0x2
3922/* enum: XGMII. */
3923#define MC_CMD_LOOPBACK_XGMII 0x3
3924/* enum: XGXS. */
3925#define MC_CMD_LOOPBACK_XGXS 0x4
3926/* enum: XAUI. */
3927#define MC_CMD_LOOPBACK_XAUI 0x5
3928/* enum: GMII. */
3929#define MC_CMD_LOOPBACK_GMII 0x6
3930/* enum: SGMII. */
3931#define MC_CMD_LOOPBACK_SGMII 0x7
3932/* enum: XGBR. */
3933#define MC_CMD_LOOPBACK_XGBR 0x8
3934/* enum: XFI. */
3935#define MC_CMD_LOOPBACK_XFI 0x9
3936/* enum: XAUI Far. */
3937#define MC_CMD_LOOPBACK_XAUI_FAR 0xa
3938/* enum: GMII Far. */
3939#define MC_CMD_LOOPBACK_GMII_FAR 0xb
3940/* enum: SGMII Far. */
3941#define MC_CMD_LOOPBACK_SGMII_FAR 0xc
3942/* enum: XFI Far. */
3943#define MC_CMD_LOOPBACK_XFI_FAR 0xd
3944/* enum: GPhy. */
3945#define MC_CMD_LOOPBACK_GPHY 0xe
3946/* enum: PhyXS. */
3947#define MC_CMD_LOOPBACK_PHYXS 0xf
3948/* enum: PCS. */
3949#define MC_CMD_LOOPBACK_PCS 0x10
3950/* enum: PMA-PMD. */
3951#define MC_CMD_LOOPBACK_PMAPMD 0x11
3952/* enum: Cross-Port. */
3953#define MC_CMD_LOOPBACK_XPORT 0x12
3954/* enum: XGMII-Wireside. */
3955#define MC_CMD_LOOPBACK_XGMII_WS 0x13
3956/* enum: XAUI Wireside. */
3957#define MC_CMD_LOOPBACK_XAUI_WS 0x14
3958/* enum: XAUI Wireside Far. */
3959#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
3960/* enum: XAUI Wireside near. */
3961#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
3962/* enum: GMII Wireside. */
3963#define MC_CMD_LOOPBACK_GMII_WS 0x17
3964/* enum: XFI Wireside. */
3965#define MC_CMD_LOOPBACK_XFI_WS 0x18
3966/* enum: XFI Wireside Far. */
3967#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
3968/* enum: PhyXS Wireside. */
3969#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
3970/* enum: PMA lanes MAC-Serdes. */
3971#define MC_CMD_LOOPBACK_PMA_INT 0x1b
3972/* enum: KR Serdes Parallel (Encoder). */
3973#define MC_CMD_LOOPBACK_SD_NEAR 0x1c
3974/* enum: KR Serdes Serial. */
3975#define MC_CMD_LOOPBACK_SD_FAR 0x1d
3976/* enum: PMA lanes MAC-Serdes Wireside. */
3977#define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
3978/* enum: KR Serdes Parallel Wireside (Full PCS). */
3979#define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
3980/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
3981#define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
3982/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
3983#define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
3984/* enum: KR Serdes Serial Wireside. */
3985#define MC_CMD_LOOPBACK_SD_FES_WS 0x22
3986/* enum: Near side of AOE Siena side port */
3987#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
3988/* enum: Medford Wireside datapath loopback */
3989#define MC_CMD_LOOPBACK_DATA_WS 0x24
3990/* enum: Force link up without setting up any physical loopback (snapper use
3991 * only)
3992 */
3993#define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
3994/* Supported loopbacks. */
3995#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
3996#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
3997#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
3998#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
3999/* Enum values, see field(s): */
4000/* 100M */
4001/* Supported loopbacks. */
4002#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
4003#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
4004#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
4005#define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
4006/* Enum values, see field(s): */
4007/* 100M */
4008/* Supported loopbacks. */
4009#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
4010#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
4011#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
4012#define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
4013/* Enum values, see field(s): */
4014/* 100M */
4015/* Supported loopbacks. */
4016#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
4017#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
4018#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
4019#define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
4020/* Enum values, see field(s): */
4021/* 100M */
4022
4023/* MC_CMD_GET_LOOPBACK_MODES_OUT_V2 msgresponse: Supported loopback modes for
4024 * newer NICs with 25G/50G/100G support
4025 */
4026#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN 64
4027/* Supported loopbacks. */
4028#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
4029#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LEN 8
4030#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
4031#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
4032/* enum: None. */
4033/* MC_CMD_LOOPBACK_NONE 0x0 */
4034/* enum: Data. */
4035/* MC_CMD_LOOPBACK_DATA 0x1 */
4036/* enum: GMAC. */
4037/* MC_CMD_LOOPBACK_GMAC 0x2 */
4038/* enum: XGMII. */
4039/* MC_CMD_LOOPBACK_XGMII 0x3 */
4040/* enum: XGXS. */
4041/* MC_CMD_LOOPBACK_XGXS 0x4 */
4042/* enum: XAUI. */
4043/* MC_CMD_LOOPBACK_XAUI 0x5 */
4044/* enum: GMII. */
4045/* MC_CMD_LOOPBACK_GMII 0x6 */
4046/* enum: SGMII. */
4047/* MC_CMD_LOOPBACK_SGMII 0x7 */
4048/* enum: XGBR. */
4049/* MC_CMD_LOOPBACK_XGBR 0x8 */
4050/* enum: XFI. */
4051/* MC_CMD_LOOPBACK_XFI 0x9 */
4052/* enum: XAUI Far. */
4053/* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
4054/* enum: GMII Far. */
4055/* MC_CMD_LOOPBACK_GMII_FAR 0xb */
4056/* enum: SGMII Far. */
4057/* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
4058/* enum: XFI Far. */
4059/* MC_CMD_LOOPBACK_XFI_FAR 0xd */
4060/* enum: GPhy. */
4061/* MC_CMD_LOOPBACK_GPHY 0xe */
4062/* enum: PhyXS. */
4063/* MC_CMD_LOOPBACK_PHYXS 0xf */
4064/* enum: PCS. */
4065/* MC_CMD_LOOPBACK_PCS 0x10 */
4066/* enum: PMA-PMD. */
4067/* MC_CMD_LOOPBACK_PMAPMD 0x11 */
4068/* enum: Cross-Port. */
4069/* MC_CMD_LOOPBACK_XPORT 0x12 */
4070/* enum: XGMII-Wireside. */
4071/* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
4072/* enum: XAUI Wireside. */
4073/* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
4074/* enum: XAUI Wireside Far. */
4075/* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
4076/* enum: XAUI Wireside near. */
4077/* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
4078/* enum: GMII Wireside. */
4079/* MC_CMD_LOOPBACK_GMII_WS 0x17 */
4080/* enum: XFI Wireside. */
4081/* MC_CMD_LOOPBACK_XFI_WS 0x18 */
4082/* enum: XFI Wireside Far. */
4083/* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
4084/* enum: PhyXS Wireside. */
4085/* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
4086/* enum: PMA lanes MAC-Serdes. */
4087/* MC_CMD_LOOPBACK_PMA_INT 0x1b */
4088/* enum: KR Serdes Parallel (Encoder). */
4089/* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
4090/* enum: KR Serdes Serial. */
4091/* MC_CMD_LOOPBACK_SD_FAR 0x1d */
4092/* enum: PMA lanes MAC-Serdes Wireside. */
4093/* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
4094/* enum: KR Serdes Parallel Wireside (Full PCS). */
4095/* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
4096/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
4097/* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
4098/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
4099/* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
4100/* enum: KR Serdes Serial Wireside. */
4101/* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
4102/* enum: Near side of AOE Siena side port */
4103/* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
4104/* enum: Medford Wireside datapath loopback */
4105/* MC_CMD_LOOPBACK_DATA_WS 0x24 */
4106/* enum: Force link up without setting up any physical loopback (snapper use
4107 * only)
4108 */
4109/* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
4110/* Supported loopbacks. */
4111#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
4112#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
4113#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_OFST 8
4114#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_OFST 12
4115/* Enum values, see field(s): */
4116/* 100M */
4117/* Supported loopbacks. */
4118#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_OFST 16
4119#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LEN 8
4120#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_OFST 16
4121#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_OFST 20
4122/* Enum values, see field(s): */
4123/* 100M */
4124/* Supported loopbacks. */
4125#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_OFST 24
4126#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LEN 8
4127#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_OFST 24
4128#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_OFST 28
4129/* Enum values, see field(s): */
4130/* 100M */
4131/* Supported loopbacks. */
4132#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_OFST 32
4133#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LEN 8
4134#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_OFST 32
4135#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_OFST 36
4136/* Enum values, see field(s): */
4137/* 100M */
4138/* Supported 25G loopbacks. */
4139#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST 40
4140#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN 8
4141#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_OFST 40
4142#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_OFST 44
4143/* Enum values, see field(s): */
4144/* 100M */
4145/* Supported 50 loopbacks. */
4146#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST 48
4147#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN 8
4148#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_OFST 48
4149#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_OFST 52
4150/* Enum values, see field(s): */
4151/* 100M */
4152/* Supported 100G loopbacks. */
4153#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST 56
4154#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN 8
4155#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_OFST 56
4156#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_OFST 60
4157/* Enum values, see field(s): */
4158/* 100M */
4159
4160/* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
4161#define AN_TYPE_LEN 4
4162#define AN_TYPE_TYPE_OFST 0
4163#define AN_TYPE_TYPE_LEN 4
4164/* enum: None, AN disabled or not supported */
4165#define MC_CMD_AN_NONE 0x0
4166/* enum: Clause 28 - BASE-T */
4167#define MC_CMD_AN_CLAUSE28 0x1
4168/* enum: Clause 37 - BASE-X */
4169#define MC_CMD_AN_CLAUSE37 0x2
4170/* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
4171 * assemblies. Includes Clause 72/Clause 92 link-training.
4172 */
4173#define MC_CMD_AN_CLAUSE73 0x3
4174#define AN_TYPE_TYPE_LBN 0
4175#define AN_TYPE_TYPE_WIDTH 32
4176
4177/* FEC_TYPE structuredef: Forward error correction types defined in IEEE802.3
4178 */
4179#define FEC_TYPE_LEN 4
4180#define FEC_TYPE_TYPE_OFST 0
4181#define FEC_TYPE_TYPE_LEN 4
4182/* enum: No FEC */
4183#define MC_CMD_FEC_NONE 0x0
4184/* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
4185#define MC_CMD_FEC_BASER 0x1
4186/* enum: Clause 91/Clause 108 Reed-Solomon FEC */
4187#define MC_CMD_FEC_RS 0x2
4188#define FEC_TYPE_TYPE_LBN 0
4189#define FEC_TYPE_TYPE_WIDTH 32
4190
4191
4192/***********************************/
4193/* MC_CMD_GET_LINK
4194 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
4195 * ETIME.
4196 */
4197#define MC_CMD_GET_LINK 0x29
4198#undef MC_CMD_0x29_PRIVILEGE_CTG
4199
4200#define MC_CMD_0x29_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4201
4202/* MC_CMD_GET_LINK_IN msgrequest */
4203#define MC_CMD_GET_LINK_IN_LEN 0
4204
4205/* MC_CMD_GET_LINK_OUT msgresponse */
4206#define MC_CMD_GET_LINK_OUT_LEN 28
4207/* Near-side advertised capabilities. Refer to
4208 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
4209 */
4210#define MC_CMD_GET_LINK_OUT_CAP_OFST 0
4211#define MC_CMD_GET_LINK_OUT_CAP_LEN 4
4212/* Link-partner advertised capabilities. Refer to
4213 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
4214 */
4215#define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
4216#define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
4217/* Autonegotiated speed in mbit/s. The link may still be down even if this
4218 * reads non-zero.
4219 */
4220#define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
4221#define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
4222/* Current loopback setting. */
4223#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
4224#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
4225/* Enum values, see field(s): */
4226/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
4227#define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
4228#define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
4229#define MC_CMD_GET_LINK_OUT_LINK_UP_OFST 16
4230#define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
4231#define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
4232#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_OFST 16
4233#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
4234#define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
4235#define MC_CMD_GET_LINK_OUT_BPX_LINK_OFST 16
4236#define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
4237#define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
4238#define MC_CMD_GET_LINK_OUT_PHY_LINK_OFST 16
4239#define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
4240#define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
4241#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_OFST 16
4242#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6
4243#define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1
4244#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_OFST 16
4245#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7
4246#define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1
4247#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_OFST 16
4248#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_LBN 8
4249#define MC_CMD_GET_LINK_OUT_MODULE_UP_VALID_WIDTH 1
4250#define MC_CMD_GET_LINK_OUT_MODULE_UP_OFST 16
4251#define MC_CMD_GET_LINK_OUT_MODULE_UP_LBN 9
4252#define MC_CMD_GET_LINK_OUT_MODULE_UP_WIDTH 1
4253/* This returns the negotiated flow control value. */
4254#define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
4255#define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
4256/* Enum values, see field(s): */
4257/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
4258#define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
4259#define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
4260#define MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24
4261#define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
4262#define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
4263#define MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24
4264#define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
4265#define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
4266#define MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24
4267#define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
4268#define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
4269#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24
4270#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
4271#define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
4272
4273/* MC_CMD_GET_LINK_OUT_V2 msgresponse: Extended link state information */
4274#define MC_CMD_GET_LINK_OUT_V2_LEN 44
4275/* Near-side advertised capabilities. Refer to
4276 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
4277 */
4278#define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
4279#define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
4280/* Link-partner advertised capabilities. Refer to
4281 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
4282 */
4283#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
4284#define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
4285/* Autonegotiated speed in mbit/s. The link may still be down even if this
4286 * reads non-zero.
4287 */
4288#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_OFST 8
4289#define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
4290/* Current loopback setting. */
4291#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_OFST 12
4292#define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
4293/* Enum values, see field(s): */
4294/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
4295#define MC_CMD_GET_LINK_OUT_V2_FLAGS_OFST 16
4296#define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
4297#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_OFST 16
4298#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
4299#define MC_CMD_GET_LINK_OUT_V2_LINK_UP_WIDTH 1
4300#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_OFST 16
4301#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_LBN 1
4302#define MC_CMD_GET_LINK_OUT_V2_FULL_DUPLEX_WIDTH 1
4303#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_OFST 16
4304#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_LBN 2
4305#define MC_CMD_GET_LINK_OUT_V2_BPX_LINK_WIDTH 1
4306#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_OFST 16
4307#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_LBN 3
4308#define MC_CMD_GET_LINK_OUT_V2_PHY_LINK_WIDTH 1
4309#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_OFST 16
4310#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_LBN 6
4311#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_RX_WIDTH 1
4312#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_OFST 16
4313#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_LBN 7
4314#define MC_CMD_GET_LINK_OUT_V2_LINK_FAULT_TX_WIDTH 1
4315#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_OFST 16
4316#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_LBN 8
4317#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_VALID_WIDTH 1
4318#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_OFST 16
4319#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_LBN 9
4320#define MC_CMD_GET_LINK_OUT_V2_MODULE_UP_WIDTH 1
4321/* This returns the negotiated flow control value. */
4322#define MC_CMD_GET_LINK_OUT_V2_FCNTL_OFST 20
4323#define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
4324/* Enum values, see field(s): */
4325/* MC_CMD_SET_MAC/MC_CMD_SET_MAC_IN/FCNTL */
4326#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_OFST 24
4327#define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
4328/* MC_CMD_MAC_FAULT_XGMII_LOCAL_OFST 24 */
4329/* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
4330/* MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 */
4331/* MC_CMD_MAC_FAULT_XGMII_REMOTE_OFST 24 */
4332/* MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 */
4333/* MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 */
4334/* MC_CMD_MAC_FAULT_SGMII_REMOTE_OFST 24 */
4335/* MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 */
4336/* MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 */
4337/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_OFST 24 */
4338/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 */
4339/* MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 */
4340/* True local device capabilities (taking into account currently used PMD/MDI,
4341 * e.g. plugged-in module). In general, subset of
4342 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP, but may include extra _FEC_REQUEST
4343 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
4344 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to
4345 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
4346 */
4347#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_OFST 28
4348#define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
4349/* Auto-negotiation type used on the link */
4350#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_OFST 32
4351#define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
4352/* Enum values, see field(s): */
4353/* AN_TYPE/TYPE */
4354/* Forward error correction used on the link */
4355#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_OFST 36
4356#define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
4357/* Enum values, see field(s): */
4358/* FEC_TYPE/TYPE */
4359#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_OFST 40
4360#define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
4361#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_OFST 40
4362#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
4363#define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_WIDTH 1
4364#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_OFST 40
4365#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_LBN 1
4366#define MC_CMD_GET_LINK_OUT_V2_PMD_READY_WIDTH 1
4367#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_OFST 40
4368#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_LBN 2
4369#define MC_CMD_GET_LINK_OUT_V2_PMD_LINK_UP_WIDTH 1
4370#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_OFST 40
4371#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_LBN 3
4372#define MC_CMD_GET_LINK_OUT_V2_PMA_LINK_UP_WIDTH 1
4373#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_OFST 40
4374#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
4375#define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_WIDTH 1
4376#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_OFST 40
4377#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_LBN 5
4378#define MC_CMD_GET_LINK_OUT_V2_ALIGN_LOCK_WIDTH 1
4379#define MC_CMD_GET_LINK_OUT_V2_HI_BER_OFST 40
4380#define MC_CMD_GET_LINK_OUT_V2_HI_BER_LBN 6
4381#define MC_CMD_GET_LINK_OUT_V2_HI_BER_WIDTH 1
4382#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_OFST 40
4383#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_LBN 7
4384#define MC_CMD_GET_LINK_OUT_V2_FEC_LOCK_WIDTH 1
4385#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_OFST 40
4386#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8
4387#define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1
4388#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_OFST 40
4389#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_LBN 9
4390#define MC_CMD_GET_LINK_OUT_V2_PORT_SHUTDOWN_WIDTH 1
4391
4392
4393/***********************************/
4394/* MC_CMD_SET_LINK
4395 * Write the unified MAC/PHY link configuration. Locks required: None. Return
4396 * code: 0, EINVAL, ETIME, EAGAIN
4397 */
4398#define MC_CMD_SET_LINK 0x2a
4399#undef MC_CMD_0x2a_PRIVILEGE_CTG
4400
4401#define MC_CMD_0x2a_PRIVILEGE_CTG SRIOV_CTG_LINK
4402
4403/* MC_CMD_SET_LINK_IN msgrequest */
4404#define MC_CMD_SET_LINK_IN_LEN 16
4405/* Near-side advertised capabilities. Refer to
4406 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
4407 */
4408#define MC_CMD_SET_LINK_IN_CAP_OFST 0
4409#define MC_CMD_SET_LINK_IN_CAP_LEN 4
4410/* Flags */
4411#define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
4412#define MC_CMD_SET_LINK_IN_FLAGS_LEN 4
4413#define MC_CMD_SET_LINK_IN_LOWPOWER_OFST 4
4414#define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
4415#define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
4416#define MC_CMD_SET_LINK_IN_POWEROFF_OFST 4
4417#define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
4418#define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
4419#define MC_CMD_SET_LINK_IN_TXDIS_OFST 4
4420#define MC_CMD_SET_LINK_IN_TXDIS_LBN 2
4421#define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
4422#define MC_CMD_SET_LINK_IN_LINKDOWN_OFST 4
4423#define MC_CMD_SET_LINK_IN_LINKDOWN_LBN 3
4424#define MC_CMD_SET_LINK_IN_LINKDOWN_WIDTH 1
4425/* Loopback mode. */
4426#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
4427#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
4428/* Enum values, see field(s): */
4429/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
4430/* A loopback speed of "0" is supported, and means (choose any available
4431 * speed).
4432 */
4433#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
4434#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
4435
4436/* MC_CMD_SET_LINK_IN_V2 msgrequest: Updated SET_LINK to include sequence
4437 * number to ensure this SET_LINK command corresponds to the latest
4438 * MODULECHANGE event.
4439 */
4440#define MC_CMD_SET_LINK_IN_V2_LEN 17
4441/* Near-side advertised capabilities. Refer to
4442 * MC_CMD_GET_PHY_CFG_OUT/SUPPORTED_CAP for bit definitions.
4443 */
4444#define MC_CMD_SET_LINK_IN_V2_CAP_OFST 0
4445#define MC_CMD_SET_LINK_IN_V2_CAP_LEN 4
4446/* Flags */
4447#define MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4
4448#define MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4
4449#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4
4450#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 0
4451#define MC_CMD_SET_LINK_IN_V2_LOWPOWER_WIDTH 1
4452#define MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4
4453#define MC_CMD_SET_LINK_IN_V2_POWEROFF_LBN 1
4454#define MC_CMD_SET_LINK_IN_V2_POWEROFF_WIDTH 1
4455#define MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4
4456#define MC_CMD_SET_LINK_IN_V2_TXDIS_LBN 2
4457#define MC_CMD_SET_LINK_IN_V2_TXDIS_WIDTH 1
4458#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4
4459#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_LBN 3
4460#define MC_CMD_SET_LINK_IN_V2_LINKDOWN_WIDTH 1
4461/* Loopback mode. */
4462#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_OFST 8
4463#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4
4464/* Enum values, see field(s): */
4465/* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
4466/* A loopback speed of "0" is supported, and means (choose any available
4467 * speed).
4468 */
4469#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_OFST 12
4470#define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4
4471#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_OFST 16
4472#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_LEN 1
4473#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_OFST 16
4474#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 0
4475#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_WIDTH 7
4476#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_OFST 16
4477#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_LBN 7
4478#define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_IGNORE_WIDTH 1
4479
4480/* MC_CMD_SET_LINK_OUT msgresponse */
4481#define MC_CMD_SET_LINK_OUT_LEN 0
4482
4483
4484/***********************************/
4485/* MC_CMD_SET_ID_LED
4486 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
4487 */
4488#define MC_CMD_SET_ID_LED 0x2b
4489#undef MC_CMD_0x2b_PRIVILEGE_CTG
4490
4491#define MC_CMD_0x2b_PRIVILEGE_CTG SRIOV_CTG_LINK
4492
4493/* MC_CMD_SET_ID_LED_IN msgrequest */
4494#define MC_CMD_SET_ID_LED_IN_LEN 4
4495/* Set LED state. */
4496#define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
4497#define MC_CMD_SET_ID_LED_IN_STATE_LEN 4
4498#define MC_CMD_LED_OFF 0x0 /* enum */
4499#define MC_CMD_LED_ON 0x1 /* enum */
4500#define MC_CMD_LED_DEFAULT 0x2 /* enum */
4501
4502/* MC_CMD_SET_ID_LED_OUT msgresponse */
4503#define MC_CMD_SET_ID_LED_OUT_LEN 0
4504
4505
4506/***********************************/
4507/* MC_CMD_SET_MAC
4508 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
4509 */
4510#define MC_CMD_SET_MAC 0x2c
4511#undef MC_CMD_0x2c_PRIVILEGE_CTG
4512
4513#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4514
4515/* MC_CMD_SET_MAC_IN msgrequest */
4516#define MC_CMD_SET_MAC_IN_LEN 28
4517/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
4518 * EtherII, VLAN, bug16011 padding).
4519 */
4520#define MC_CMD_SET_MAC_IN_MTU_OFST 0
4521#define MC_CMD_SET_MAC_IN_MTU_LEN 4
4522#define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
4523#define MC_CMD_SET_MAC_IN_DRAIN_LEN 4
4524#define MC_CMD_SET_MAC_IN_ADDR_OFST 8
4525#define MC_CMD_SET_MAC_IN_ADDR_LEN 8
4526#define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
4527#define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
4528#define MC_CMD_SET_MAC_IN_REJECT_OFST 16
4529#define MC_CMD_SET_MAC_IN_REJECT_LEN 4
4530#define MC_CMD_SET_MAC_IN_REJECT_UNCST_OFST 16
4531#define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
4532#define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
4533#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_OFST 16
4534#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
4535#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
4536#define MC_CMD_SET_MAC_IN_FCNTL_OFST 20
4537#define MC_CMD_SET_MAC_IN_FCNTL_LEN 4
4538/* enum: Flow control is off. */
4539#define MC_CMD_FCNTL_OFF 0x0
4540/* enum: Respond to flow control. */
4541#define MC_CMD_FCNTL_RESPOND 0x1
4542/* enum: Respond to and Issue flow control. */
4543#define MC_CMD_FCNTL_BIDIR 0x2
4544/* enum: Auto neg flow control. */
4545#define MC_CMD_FCNTL_AUTO 0x3
4546/* enum: Priority flow control (eftest builds only). */
4547#define MC_CMD_FCNTL_QBB 0x4
4548/* enum: Issue flow control. */
4549#define MC_CMD_FCNTL_GENERATE 0x5
4550#define MC_CMD_SET_MAC_IN_FLAGS_OFST 24
4551#define MC_CMD_SET_MAC_IN_FLAGS_LEN 4
4552#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_OFST 24
4553#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
4554#define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1
4555
4556/* MC_CMD_SET_MAC_EXT_IN msgrequest */
4557#define MC_CMD_SET_MAC_EXT_IN_LEN 32
4558/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
4559 * EtherII, VLAN, bug16011 padding).
4560 */
4561#define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
4562#define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
4563#define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
4564#define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
4565#define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8
4566#define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8
4567#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8
4568#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12
4569#define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16
4570#define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
4571#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_OFST 16
4572#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
4573#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1
4574#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_OFST 16
4575#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1
4576#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1
4577#define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20
4578#define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
4579/* enum: Flow control is off. */
4580/* MC_CMD_FCNTL_OFF 0x0 */
4581/* enum: Respond to flow control. */
4582/* MC_CMD_FCNTL_RESPOND 0x1 */
4583/* enum: Respond to and Issue flow control. */
4584/* MC_CMD_FCNTL_BIDIR 0x2 */
4585/* enum: Auto neg flow control. */
4586/* MC_CMD_FCNTL_AUTO 0x3 */
4587/* enum: Priority flow control (eftest builds only). */
4588/* MC_CMD_FCNTL_QBB 0x4 */
4589/* enum: Issue flow control. */
4590/* MC_CMD_FCNTL_GENERATE 0x5 */
4591#define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24
4592#define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
4593#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_OFST 24
4594#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
4595#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1
4596/* Select which parameters to configure. A parameter will only be modified if
4597 * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in
4598 * capabilities then this field is ignored (and all flags are assumed to be
4599 * set).
4600 */
4601#define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28
4602#define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
4603#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_OFST 28
4604#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
4605#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1
4606#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_OFST 28
4607#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1
4608#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1
4609#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_OFST 28
4610#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2
4611#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1
4612#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_OFST 28
4613#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3
4614#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1
4615#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_OFST 28
4616#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
4617#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1
4618
4619/* MC_CMD_SET_MAC_OUT msgresponse */
4620#define MC_CMD_SET_MAC_OUT_LEN 0
4621
4622/* MC_CMD_SET_MAC_V2_OUT msgresponse */
4623#define MC_CMD_SET_MAC_V2_OUT_LEN 4
4624/* MTU as configured after processing the request. See comment at
4625 * MC_CMD_SET_MAC_IN/MTU. To query MTU without doing any changes, set CONTROL
4626 * to 0.
4627 */
4628#define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
4629#define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
4630
4631
4632/***********************************/
4633/* MC_CMD_PHY_STATS
4634 * Get generic PHY statistics. This call returns the statistics for a generic
4635 * PHY in a sparse array (indexed by the enumerate). Each value is represented
4636 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
4637 * statistics may be read from the message response. If DMA_ADDR != 0, then the
4638 * statistics are dmad to that (page-aligned location). Locks required: None.
4639 * Returns: 0, ETIME
4640 */
4641#define MC_CMD_PHY_STATS 0x2d
4642#undef MC_CMD_0x2d_PRIVILEGE_CTG
4643
4644#define MC_CMD_0x2d_PRIVILEGE_CTG SRIOV_CTG_LINK
4645
4646/* MC_CMD_PHY_STATS_IN msgrequest */
4647#define MC_CMD_PHY_STATS_IN_LEN 8
4648/* ??? */
4649#define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
4650#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
4651#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
4652#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
4653
4654/* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
4655#define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
4656
4657/* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
4658#define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
4659#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
4660#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
4661#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
4662/* enum: OUI. */
4663#define MC_CMD_OUI 0x0
4664/* enum: PMA-PMD Link Up. */
4665#define MC_CMD_PMA_PMD_LINK_UP 0x1
4666/* enum: PMA-PMD RX Fault. */
4667#define MC_CMD_PMA_PMD_RX_FAULT 0x2
4668/* enum: PMA-PMD TX Fault. */
4669#define MC_CMD_PMA_PMD_TX_FAULT 0x3
4670/* enum: PMA-PMD Signal */
4671#define MC_CMD_PMA_PMD_SIGNAL 0x4
4672/* enum: PMA-PMD SNR A. */
4673#define MC_CMD_PMA_PMD_SNR_A 0x5
4674/* enum: PMA-PMD SNR B. */
4675#define MC_CMD_PMA_PMD_SNR_B 0x6
4676/* enum: PMA-PMD SNR C. */
4677#define MC_CMD_PMA_PMD_SNR_C 0x7
4678/* enum: PMA-PMD SNR D. */
4679#define MC_CMD_PMA_PMD_SNR_D 0x8
4680/* enum: PCS Link Up. */
4681#define MC_CMD_PCS_LINK_UP 0x9
4682/* enum: PCS RX Fault. */
4683#define MC_CMD_PCS_RX_FAULT 0xa
4684/* enum: PCS TX Fault. */
4685#define MC_CMD_PCS_TX_FAULT 0xb
4686/* enum: PCS BER. */
4687#define MC_CMD_PCS_BER 0xc
4688/* enum: PCS Block Errors. */
4689#define MC_CMD_PCS_BLOCK_ERRORS 0xd
4690/* enum: PhyXS Link Up. */
4691#define MC_CMD_PHYXS_LINK_UP 0xe
4692/* enum: PhyXS RX Fault. */
4693#define MC_CMD_PHYXS_RX_FAULT 0xf
4694/* enum: PhyXS TX Fault. */
4695#define MC_CMD_PHYXS_TX_FAULT 0x10
4696/* enum: PhyXS Align. */
4697#define MC_CMD_PHYXS_ALIGN 0x11
4698/* enum: PhyXS Sync. */
4699#define MC_CMD_PHYXS_SYNC 0x12
4700/* enum: AN link-up. */
4701#define MC_CMD_AN_LINK_UP 0x13
4702/* enum: AN Complete. */
4703#define MC_CMD_AN_COMPLETE 0x14
4704/* enum: AN 10GBaseT Status. */
4705#define MC_CMD_AN_10GBT_STATUS 0x15
4706/* enum: Clause 22 Link-Up. */
4707#define MC_CMD_CL22_LINK_UP 0x16
4708/* enum: (Last entry) */
4709#define MC_CMD_PHY_NSTATS 0x17
4710
4711
4712/***********************************/
4713/* MC_CMD_MAC_STATS
4714 * Get generic MAC statistics. This call returns unified statistics maintained
4715 * by the MC as it switches between the GMAC and XMAC. The MC will write out
4716 * all supported stats. The driver should zero initialise the buffer to
4717 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
4718 * performed, and the statistics may be read from the message response. If
4719 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
4720 * Locks required: None. The PERIODIC_CLEAR option is not used and now has no
4721 * effect. Returns: 0, ETIME
4722 */
4723#define MC_CMD_MAC_STATS 0x2e
4724#undef MC_CMD_0x2e_PRIVILEGE_CTG
4725
4726#define MC_CMD_0x2e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
4727
4728/* MC_CMD_MAC_STATS_IN msgrequest */
4729#define MC_CMD_MAC_STATS_IN_LEN 20
4730/* ??? */
4731#define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
4732#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
4733#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
4734#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
4735#define MC_CMD_MAC_STATS_IN_CMD_OFST 8
4736#define MC_CMD_MAC_STATS_IN_CMD_LEN 4
4737#define MC_CMD_MAC_STATS_IN_DMA_OFST 8
4738#define MC_CMD_MAC_STATS_IN_DMA_LBN 0
4739#define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
4740#define MC_CMD_MAC_STATS_IN_CLEAR_OFST 8
4741#define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
4742#define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
4743#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_OFST 8
4744#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
4745#define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
4746#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_OFST 8
4747#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
4748#define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
4749#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_OFST 8
4750#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
4751#define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
4752#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_OFST 8
4753#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
4754#define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
4755#define MC_CMD_MAC_STATS_IN_PERIOD_MS_OFST 8
4756#define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
4757#define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
4758/* DMA length. Should be set to MAC_STATS_NUM_STATS * sizeof(uint64_t), as
4759 * returned by MC_CMD_GET_CAPABILITIES_V4_OUT. For legacy firmware not
4760 * supporting MC_CMD_GET_CAPABILITIES_V4_OUT, DMA_LEN should be set to
4761 * MC_CMD_MAC_NSTATS * sizeof(uint64_t)
4762 */
4763#define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
4764#define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
4765/* port id so vadapter stats can be provided */
4766#define MC_CMD_MAC_STATS_IN_PORT_ID_OFST 16
4767#define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4
4768
4769/* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
4770#define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
4771
4772/* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
4773#define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
4774#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
4775#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
4776#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
4777#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
4778#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
4779#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
4780#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
4781#define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
4782#define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
4783#define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
4784#define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
4785#define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
4786#define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
4787#define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
4788#define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
4789#define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
4790#define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
4791#define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
4792#define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
4793#define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
4794#define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
4795#define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
4796#define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
4797#define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
4798#define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
4799#define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
4800#define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
4801#define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
4802#define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
4803#define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
4804#define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
4805#define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
4806#define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
4807#define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
4808#define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
4809#define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
4810#define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
4811#define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
4812#define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
4813#define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
4814#define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
4815#define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
4816#define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
4817#define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
4818#define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
4819#define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
4820#define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
4821#define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
4822#define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
4823#define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
4824#define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
4825#define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
4826#define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
4827#define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
4828#define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
4829#define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
4830#define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
4831#define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
4832#define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
4833#define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
4834#define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
4835#define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
4836#define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
4837#define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
4838#define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
4839#define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
4840/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4841 * capability only.
4842 */
4843#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
4844/* enum: PM discard_bb_overflow counter. Valid for EF10 with
4845 * PM_AND_RXDP_COUNTERS capability only.
4846 */
4847#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
4848/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4849 * capability only.
4850 */
4851#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
4852/* enum: PM discard_vfifo_full counter. Valid for EF10 with
4853 * PM_AND_RXDP_COUNTERS capability only.
4854 */
4855#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
4856/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4857 * capability only.
4858 */
4859#define MC_CMD_MAC_PM_TRUNC_QBB 0x40
4860/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4861 * capability only.
4862 */
4863#define MC_CMD_MAC_PM_DISCARD_QBB 0x41
4864/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4865 * capability only.
4866 */
4867#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
4868/* enum: RXDP counter: Number of packets dropped due to the queue being
4869 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4870 */
4871#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
4872/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
4873 * with PM_AND_RXDP_COUNTERS capability only.
4874 */
4875#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
4876/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
4877 * PM_AND_RXDP_COUNTERS capability only.
4878 */
4879#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
4880/* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.
4881 * Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4882 */
4883#define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
4884/* enum: RXDP counter: Number of times the DPCPU waited for an existing
4885 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
4886 */
4887#define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
4888#define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
4889#define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
4890#define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
4891#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
4892#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
4893#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
4894#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
4895#define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
4896#define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
4897#define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
4898#define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
4899#define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
4900#define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
4901#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
4902#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
4903#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
4904#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
4905#define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
4906#define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
4907#define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
4908/* enum: Start of GMAC stats buffer space, for Siena only. */
4909#define MC_CMD_GMAC_DMABUF_START 0x40
4910/* enum: End of GMAC stats buffer space, for Siena only. */
4911#define MC_CMD_GMAC_DMABUF_END 0x5f
4912/* enum: GENERATION_END value, used together with GENERATION_START to verify
4913 * consistency of DMAd data. For legacy firmware / drivers without extended
4914 * stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *
4915 * sizeof(uint64_t)), this entry holds the GENERATION_END value. Otherwise,
4916 * this value is invalid/ reserved and GENERATION_END is written as the last
4917 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
4918 * this is consistent with the legacy behaviour, in the sense that entry 96 is
4919 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
4920 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
4921 */
4922#define MC_CMD_MAC_GENERATION_END 0x60
4923#define MC_CMD_MAC_NSTATS 0x61 /* enum */
4924
4925/* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */
4926#define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
4927
4928/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA msgresponse */
4929#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V2*64))>>3)
4930#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
4931#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LEN 8
4932#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
4933#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
4934#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
4935/* enum: Start of FEC stats buffer space, Medford2 and up */
4936#define MC_CMD_MAC_FEC_DMABUF_START 0x61
4937/* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
4938 */
4939#define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
4940/* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
4941 */
4942#define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
4943/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
4944#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
4945/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
4946#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
4947/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
4948#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
4949/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
4950#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
4951/* enum: This includes the space at offset 103 which is the final
4952 * GENERATION_END in a MAC_STATS_V2 response and otherwise unused.
4953 */
4954#define MC_CMD_MAC_NSTATS_V2 0x68
4955/* Other enum values, see field(s): */
4956/* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */
4957
4958/* MC_CMD_MAC_STATS_V3_OUT_DMA msgresponse */
4959#define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0
4960
4961/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA msgresponse */
4962#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V3*64))>>3)
4963#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
4964#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LEN 8
4965#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
4966#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
4967#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3
4968/* enum: Start of CTPIO stats buffer space, Medford2 and up */
4969#define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
4970/* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the
4971 * target VI
4972 */
4973#define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
4974/* enum: Number of times a CTPIO send wrote beyond frame end (informational
4975 * only)
4976 */
4977#define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
4978/* enum: Number of CTPIO failures because the TX doorbell was written before
4979 * the end of the frame data
4980 */
4981#define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
4982/* enum: Number of CTPIO failures because the internal FIFO overflowed */
4983#define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
4984/* enum: Number of CTPIO failures because the host did not deliver data fast
4985 * enough to avoid MAC underflow
4986 */
4987#define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
4988/* enum: Number of CTPIO failures because the host did not deliver all the
4989 * frame data within the timeout
4990 */
4991#define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
4992/* enum: Number of CTPIO failures because the frame data arrived out of order
4993 * or with gaps
4994 */
4995#define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
4996/* enum: Number of CTPIO failures because the host started a new frame before
4997 * completing the previous one
4998 */
4999#define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
5000/* enum: Number of CTPIO failures because a write was not a multiple of 32 bits
5001 * or not 32-bit aligned
5002 */
5003#define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
5004/* enum: Number of CTPIO fallbacks because another VI on the same port was
5005 * sending a CTPIO frame
5006 */
5007#define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
5008/* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled
5009 */
5010#define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
5011/* enum: Number of CTPIO fallbacks because length in header was less than 29
5012 * bytes
5013 */
5014#define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
5015/* enum: Total number of successful CTPIO sends on this port */
5016#define MC_CMD_MAC_CTPIO_SUCCESS 0x74
5017/* enum: Total number of CTPIO fallbacks on this port */
5018#define MC_CMD_MAC_CTPIO_FALLBACK 0x75
5019/* enum: Total number of CTPIO poisoned frames on this port, whether erased or
5020 * not
5021 */
5022#define MC_CMD_MAC_CTPIO_POISON 0x76
5023/* enum: Total number of CTPIO erased frames on this port */
5024#define MC_CMD_MAC_CTPIO_ERASE 0x77
5025/* enum: This includes the space at offset 120 which is the final
5026 * GENERATION_END in a MAC_STATS_V3 response and otherwise unused.
5027 */
5028#define MC_CMD_MAC_NSTATS_V3 0x79
5029/* Other enum values, see field(s): */
5030/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */
5031
5032/* MC_CMD_MAC_STATS_V4_OUT_DMA msgresponse */
5033#define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0
5034
5035/* MC_CMD_MAC_STATS_V4_OUT_NO_DMA msgresponse */
5036#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS_V4*64))>>3)
5037#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
5038#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LEN 8
5039#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
5040#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
5041#define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V4
5042/* enum: Start of V4 stats buffer space */
5043#define MC_CMD_MAC_V4_DMABUF_START 0x79
5044/* enum: RXDP counter: Number of packets truncated because scattering was
5045 * disabled.
5046 */
5047#define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79
5048/* enum: RXDP counter: Number of times the RXDP head of line blocked waiting
5049 * for descriptors. Will be zero unless RXDP_HLB_IDLE capability is set.
5050 */
5051#define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a
5052/* enum: RXDP counter: Number of times the RXDP timed out while head of line
5053 * blocking. Will be zero unless RXDP_HLB_IDLE capability is set.
5054 */
5055#define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b
5056/* enum: This includes the space at offset 124 which is the final
5057 * GENERATION_END in a MAC_STATS_V4 response and otherwise unused.
5058 */
5059#define MC_CMD_MAC_NSTATS_V4 0x7d
5060/* Other enum values, see field(s): */
5061/* MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */
5062
5063
5064/***********************************/
5065/* MC_CMD_SRIOV
5066 * to be documented
5067 */
5068#define MC_CMD_SRIOV 0x30
5069
5070/* MC_CMD_SRIOV_IN msgrequest */
5071#define MC_CMD_SRIOV_IN_LEN 12
5072#define MC_CMD_SRIOV_IN_ENABLE_OFST 0
5073#define MC_CMD_SRIOV_IN_ENABLE_LEN 4
5074#define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
5075#define MC_CMD_SRIOV_IN_VI_BASE_LEN 4
5076#define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
5077#define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4
5078
5079/* MC_CMD_SRIOV_OUT msgresponse */
5080#define MC_CMD_SRIOV_OUT_LEN 8
5081#define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
5082#define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4
5083#define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
5084#define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4
5085
5086/* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
5087#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
5088/* this is only used for the first record */
5089#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
5090#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4
5091#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
5092#define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
5093#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
5094#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4
5095#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
5096#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
5097#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
5098#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
5099#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
5100#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
5101#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
5102#define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
5103#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
5104#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4
5105#define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
5106#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
5107#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
5108#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
5109#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
5110#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
5111#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
5112#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
5113#define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
5114#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
5115#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4
5116#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
5117#define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32
5118
5119
5120/***********************************/
5121/* MC_CMD_MEMCPY
5122 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data
5123 * embedded directly in the command.
5124 *
5125 * A common pattern is for a client to use generation counts to signal a dma
5126 * update of a datastructure. To facilitate this, this MCDI operation can
5127 * contain multiple requests which are executed in strict order. Requests take
5128 * the form of duplicating the entire MCDI request continuously (including the
5129 * requests record, which is ignored in all but the first structure)
5130 *
5131 * The source data can either come from a DMA from the host, or it can be
5132 * embedded within the request directly, thereby eliminating a DMA read. To
5133 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
5134 * ADDR_LO=offset, and inserts the data at %offset from the start of the
5135 * payload. It's the callers responsibility to ensure that the embedded data
5136 * doesn't overlap the records.
5137 *
5138 * Returns: 0, EINVAL (invalid RID)
5139 */
5140#define MC_CMD_MEMCPY 0x31
5141
5142/* MC_CMD_MEMCPY_IN msgrequest */
5143#define MC_CMD_MEMCPY_IN_LENMIN 32
5144#define MC_CMD_MEMCPY_IN_LENMAX 224
5145#define MC_CMD_MEMCPY_IN_LENMAX_MCDI2 992
5146#define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
5147#define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)
5148/* see MC_CMD_MEMCPY_RECORD_TYPEDEF */
5149#define MC_CMD_MEMCPY_IN_RECORD_OFST 0
5150#define MC_CMD_MEMCPY_IN_RECORD_LEN 32
5151#define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
5152#define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
5153#define MC_CMD_MEMCPY_IN_RECORD_MAXNUM_MCDI2 31
5154
5155/* MC_CMD_MEMCPY_OUT msgresponse */
5156#define MC_CMD_MEMCPY_OUT_LEN 0
5157
5158
5159/***********************************/
5160/* MC_CMD_WOL_FILTER_SET
5161 * Set a WoL filter.
5162 */
5163#define MC_CMD_WOL_FILTER_SET 0x32
5164#undef MC_CMD_0x32_PRIVILEGE_CTG
5165
5166#define MC_CMD_0x32_PRIVILEGE_CTG SRIOV_CTG_LINK
5167
5168/* MC_CMD_WOL_FILTER_SET_IN msgrequest */
5169#define MC_CMD_WOL_FILTER_SET_IN_LEN 192
5170#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
5171#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
5172#define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
5173#define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
5174/* A type value of 1 is unused. */
5175#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
5176#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
5177/* enum: Magic */
5178#define MC_CMD_WOL_TYPE_MAGIC 0x0
5179/* enum: MS Windows Magic */
5180#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
5181/* enum: IPv4 Syn */
5182#define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
5183/* enum: IPv6 Syn */
5184#define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
5185/* enum: Bitmap */
5186#define MC_CMD_WOL_TYPE_BITMAP 0x5
5187/* enum: Link */
5188#define MC_CMD_WOL_TYPE_LINK 0x6
5189/* enum: (Above this for future use) */
5190#define MC_CMD_WOL_TYPE_MAX 0x7
5191#define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
5192#define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
5193#define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
5194
5195/* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
5196#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
5197/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5198/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5199/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5200/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5201#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
5202#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
5203#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
5204#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
5205
5206/* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
5207#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
5208/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5209/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5210/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5211/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5212#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
5213#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
5214#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
5215#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
5216#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
5217#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
5218#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
5219#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
5220
5221/* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
5222#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
5223/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5224/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5225/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5226/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5227#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
5228#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
5229#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
5230#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
5231#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
5232#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
5233#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
5234#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
5235
5236/* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
5237#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
5238/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5239/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5240/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5241/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5242#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
5243#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
5244#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
5245#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
5246#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
5247#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
5248#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
5249#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
5250#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
5251#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
5252
5253/* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
5254#define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
5255/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
5256/* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
5257/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
5258/* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
5259#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
5260#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
5261#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_OFST 8
5262#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
5263#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
5264#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_OFST 8
5265#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
5266#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
5267
5268/* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
5269#define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
5270#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
5271#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4
5272
5273
5274/***********************************/
5275/* MC_CMD_WOL_FILTER_REMOVE
5276 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
5277 */
5278#define MC_CMD_WOL_FILTER_REMOVE 0x33
5279#undef MC_CMD_0x33_PRIVILEGE_CTG
5280
5281#define MC_CMD_0x33_PRIVILEGE_CTG SRIOV_CTG_LINK
5282
5283/* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
5284#define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
5285#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
5286#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4
5287
5288/* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
5289#define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
5290
5291
5292/***********************************/
5293/* MC_CMD_WOL_FILTER_RESET
5294 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
5295 * ENOSYS
5296 */
5297#define MC_CMD_WOL_FILTER_RESET 0x34
5298#undef MC_CMD_0x34_PRIVILEGE_CTG
5299
5300#define MC_CMD_0x34_PRIVILEGE_CTG SRIOV_CTG_LINK
5301
5302/* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
5303#define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
5304#define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
5305#define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
5306#define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
5307#define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
5308
5309/* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
5310#define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
5311
5312
5313/***********************************/
5314/* MC_CMD_SET_MCAST_HASH
5315 * Set the MCAST hash value without otherwise reconfiguring the MAC
5316 */
5317#define MC_CMD_SET_MCAST_HASH 0x35
5318
5319/* MC_CMD_SET_MCAST_HASH_IN msgrequest */
5320#define MC_CMD_SET_MCAST_HASH_IN_LEN 32
5321#define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
5322#define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
5323#define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
5324#define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16
5325
5326/* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
5327#define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
5328
5329
5330/***********************************/
5331/* MC_CMD_NVRAM_TYPES
5332 * Return bitfield indicating available types of virtual NVRAM partitions.
5333 * Locks required: none. Returns: 0
5334 */
5335#define MC_CMD_NVRAM_TYPES 0x36
5336#undef MC_CMD_0x36_PRIVILEGE_CTG
5337
5338#define MC_CMD_0x36_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5339
5340/* MC_CMD_NVRAM_TYPES_IN msgrequest */
5341#define MC_CMD_NVRAM_TYPES_IN_LEN 0
5342
5343/* MC_CMD_NVRAM_TYPES_OUT msgresponse */
5344#define MC_CMD_NVRAM_TYPES_OUT_LEN 4
5345/* Bit mask of supported types. */
5346#define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
5347#define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
5348/* enum: Disabled callisto. */
5349#define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
5350/* enum: MC firmware. */
5351#define MC_CMD_NVRAM_TYPE_MC_FW 0x1
5352/* enum: MC backup firmware. */
5353#define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
5354/* enum: Static configuration Port0. */
5355#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
5356/* enum: Static configuration Port1. */
5357#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
5358/* enum: Dynamic configuration Port0. */
5359#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
5360/* enum: Dynamic configuration Port1. */
5361#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
5362/* enum: Expansion Rom. */
5363#define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
5364/* enum: Expansion Rom Configuration Port0. */
5365#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
5366/* enum: Expansion Rom Configuration Port1. */
5367#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
5368/* enum: Phy Configuration Port0. */
5369#define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
5370/* enum: Phy Configuration Port1. */
5371#define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
5372/* enum: Log. */
5373#define MC_CMD_NVRAM_TYPE_LOG 0xc
5374/* enum: FPGA image. */
5375#define MC_CMD_NVRAM_TYPE_FPGA 0xd
5376/* enum: FPGA backup image */
5377#define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
5378/* enum: FC firmware. */
5379#define MC_CMD_NVRAM_TYPE_FC_FW 0xf
5380/* enum: FC backup firmware. */
5381#define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
5382/* enum: CPLD image. */
5383#define MC_CMD_NVRAM_TYPE_CPLD 0x11
5384/* enum: Licensing information. */
5385#define MC_CMD_NVRAM_TYPE_LICENSE 0x12
5386/* enum: FC Log. */
5387#define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
5388/* enum: Additional flash on FPGA. */
5389#define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
5390
5391
5392/***********************************/
5393/* MC_CMD_NVRAM_INFO
5394 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
5395 * EINVAL (bad type).
5396 */
5397#define MC_CMD_NVRAM_INFO 0x37
5398#undef MC_CMD_0x37_PRIVILEGE_CTG
5399
5400#define MC_CMD_0x37_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5401
5402/* MC_CMD_NVRAM_INFO_IN msgrequest */
5403#define MC_CMD_NVRAM_INFO_IN_LEN 4
5404#define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
5405#define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
5406/* Enum values, see field(s): */
5407/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5408
5409/* MC_CMD_NVRAM_INFO_OUT msgresponse */
5410#define MC_CMD_NVRAM_INFO_OUT_LEN 24
5411#define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
5412#define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
5413/* Enum values, see field(s): */
5414/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5415#define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
5416#define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
5417#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
5418#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
5419#define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
5420#define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
5421#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_OFST 12
5422#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
5423#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
5424#define MC_CMD_NVRAM_INFO_OUT_TLV_OFST 12
5425#define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
5426#define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
5427#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12
5428#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
5429#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
5430#define MC_CMD_NVRAM_INFO_OUT_CRC_OFST 12
5431#define MC_CMD_NVRAM_INFO_OUT_CRC_LBN 3
5432#define MC_CMD_NVRAM_INFO_OUT_CRC_WIDTH 1
5433#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_OFST 12
5434#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5
5435#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
5436#define MC_CMD_NVRAM_INFO_OUT_CMAC_OFST 12
5437#define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6
5438#define MC_CMD_NVRAM_INFO_OUT_CMAC_WIDTH 1
5439#define MC_CMD_NVRAM_INFO_OUT_A_B_OFST 12
5440#define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7
5441#define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
5442#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
5443#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
5444#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
5445#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4
5446
5447/* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */
5448#define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28
5449#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
5450#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
5451/* Enum values, see field(s): */
5452/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5453#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
5454#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
5455#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8
5456#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
5457#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12
5458#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
5459#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_OFST 12
5460#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
5461#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
5462#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_OFST 12
5463#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
5464#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
5465#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_OFST 12
5466#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
5467#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
5468#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_OFST 12
5469#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5
5470#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
5471#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_OFST 12
5472#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7
5473#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1
5474#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16
5475#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
5476#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20
5477#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
5478/* Writes must be multiples of this size. Added to support the MUM on Sorrento.
5479 */
5480#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24
5481#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4
5482
5483
5484/***********************************/
5485/* MC_CMD_NVRAM_UPDATE_START
5486 * Start a group of update operations on a virtual NVRAM partition. Locks
5487 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
5488 * PHY_LOCK required and not held). In an adapter bound to a TSA controller,
5489 * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types
5490 * i.e. static config, dynamic config and expansion ROM config. Attempting to
5491 * perform this operation on a restricted partition will return the error
5492 * EPERM.
5493 */
5494#define MC_CMD_NVRAM_UPDATE_START 0x38
5495#undef MC_CMD_0x38_PRIVILEGE_CTG
5496
5497#define MC_CMD_0x38_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5498
5499/* MC_CMD_NVRAM_UPDATE_START_IN msgrequest: Legacy NVRAM_UPDATE_START request.
5500 * Use NVRAM_UPDATE_START_V2_IN in new code
5501 */
5502#define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
5503#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
5504#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
5505/* Enum values, see field(s): */
5506/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5507
5508/* MC_CMD_NVRAM_UPDATE_START_V2_IN msgrequest: Extended NVRAM_UPDATE_START
5509 * request with additional flags indicating version of command in use. See
5510 * MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended functionality. Use
5511 * paired up with NVRAM_UPDATE_FINISH_V2_IN.
5512 */
5513#define MC_CMD_NVRAM_UPDATE_START_V2_IN_LEN 8
5514#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
5515#define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
5516/* Enum values, see field(s): */
5517/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5518#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
5519#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
5520#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4
5521#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
5522#define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
5523
5524/* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
5525#define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
5526
5527
5528/***********************************/
5529/* MC_CMD_NVRAM_READ
5530 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if
5531 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
5532 * PHY_LOCK required and not held)
5533 */
5534#define MC_CMD_NVRAM_READ 0x39
5535#undef MC_CMD_0x39_PRIVILEGE_CTG
5536
5537#define MC_CMD_0x39_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5538
5539/* MC_CMD_NVRAM_READ_IN msgrequest */
5540#define MC_CMD_NVRAM_READ_IN_LEN 12
5541#define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
5542#define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
5543/* Enum values, see field(s): */
5544/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5545#define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
5546#define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
5547/* amount to read in bytes */
5548#define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
5549#define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4
5550
5551/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */
5552#define MC_CMD_NVRAM_READ_IN_V2_LEN 16
5553#define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
5554#define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
5555/* Enum values, see field(s): */
5556/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5557#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
5558#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
5559/* amount to read in bytes */
5560#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8
5561#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
5562/* Optional control info. If a partition is stored with an A/B versioning
5563 * scheme (i.e. in more than one physical partition in NVRAM) the host can set
5564 * this to control which underlying physical partition is used to read data
5565 * from. This allows it to perform a read-modify-write-verify with the write
5566 * lock continuously held by calling NVRAM_UPDATE_START, reading the old
5567 * contents using MODE=TARGET_CURRENT, overwriting the old partition and then
5568 * verifying by reading with MODE=TARGET_BACKUP.
5569 */
5570#define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12
5571#define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
5572/* enum: Same as omitting MODE: caller sees data in current partition unless it
5573 * holds the write lock in which case it sees data in the partition it is
5574 * updating.
5575 */
5576#define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
5577/* enum: Read from the current partition of an A/B pair, even if holding the
5578 * write lock.
5579 */
5580#define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
5581/* enum: Read from the non-current (i.e. to be updated) partition of an A/B
5582 * pair
5583 */
5584#define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
5585
5586/* MC_CMD_NVRAM_READ_OUT msgresponse */
5587#define MC_CMD_NVRAM_READ_OUT_LENMIN 1
5588#define MC_CMD_NVRAM_READ_OUT_LENMAX 252
5589#define MC_CMD_NVRAM_READ_OUT_LENMAX_MCDI2 1020
5590#define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
5591#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
5592#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
5593#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
5594#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
5595#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
5596#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM_MCDI2 1020
5597
5598
5599/***********************************/
5600/* MC_CMD_NVRAM_WRITE
5601 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if
5602 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
5603 * PHY_LOCK required and not held)
5604 */
5605#define MC_CMD_NVRAM_WRITE 0x3a
5606#undef MC_CMD_0x3a_PRIVILEGE_CTG
5607
5608#define MC_CMD_0x3a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5609
5610/* MC_CMD_NVRAM_WRITE_IN msgrequest */
5611#define MC_CMD_NVRAM_WRITE_IN_LENMIN 13
5612#define MC_CMD_NVRAM_WRITE_IN_LENMAX 252
5613#define MC_CMD_NVRAM_WRITE_IN_LENMAX_MCDI2 1020
5614#define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
5615#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)
5616#define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
5617#define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
5618/* Enum values, see field(s): */
5619/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5620#define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
5621#define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
5622#define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
5623#define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
5624#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
5625#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
5626#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
5627#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
5628#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM_MCDI2 1008
5629
5630/* MC_CMD_NVRAM_WRITE_OUT msgresponse */
5631#define MC_CMD_NVRAM_WRITE_OUT_LEN 0
5632
5633
5634/***********************************/
5635/* MC_CMD_NVRAM_ERASE
5636 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if
5637 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
5638 * PHY_LOCK required and not held)
5639 */
5640#define MC_CMD_NVRAM_ERASE 0x3b
5641#undef MC_CMD_0x3b_PRIVILEGE_CTG
5642
5643#define MC_CMD_0x3b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5644
5645/* MC_CMD_NVRAM_ERASE_IN msgrequest */
5646#define MC_CMD_NVRAM_ERASE_IN_LEN 12
5647#define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
5648#define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
5649/* Enum values, see field(s): */
5650/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5651#define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
5652#define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
5653#define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
5654#define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4
5655
5656/* MC_CMD_NVRAM_ERASE_OUT msgresponse */
5657#define MC_CMD_NVRAM_ERASE_OUT_LEN 0
5658
5659
5660/***********************************/
5661/* MC_CMD_NVRAM_UPDATE_FINISH
5662 * Finish a group of update operations on a virtual NVRAM partition. Locks
5663 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
5664 * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to
5665 * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of
5666 * partition types i.e. static config, dynamic config and expansion ROM config.
5667 * Attempting to perform this operation on a restricted partition will return
5668 * the error EPERM.
5669 */
5670#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
5671#undef MC_CMD_0x3c_PRIVILEGE_CTG
5672
5673#define MC_CMD_0x3c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5674
5675/* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest: Legacy NVRAM_UPDATE_FINISH
5676 * request. Use NVRAM_UPDATE_FINISH_V2_IN in new code
5677 */
5678#define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
5679#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
5680#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
5681/* Enum values, see field(s): */
5682/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5683#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
5684#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
5685
5686/* MC_CMD_NVRAM_UPDATE_FINISH_V2_IN msgrequest: Extended NVRAM_UPDATE_FINISH
5687 * request with additional flags indicating version of NVRAM_UPDATE commands in
5688 * use. See MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT for details of extended
5689 * functionality. Use paired up with NVRAM_UPDATE_START_V2_IN.
5690 */
5691#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_LEN 12
5692#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
5693#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
5694/* Enum values, see field(s): */
5695/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
5696#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
5697#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
5698#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_OFST 8
5699#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
5700#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 8
5701#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
5702#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_WIDTH 1
5703#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_OFST 8
5704#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_LBN 1
5705#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_RUN_IN_BACKGROUND_WIDTH 1
5706#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_OFST 8
5707#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_LBN 2
5708#define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_POLL_VERIFY_RESULT_WIDTH 1
5709
5710/* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse: Legacy NVRAM_UPDATE_FINISH
5711 * response. Use NVRAM_UPDATE_FINISH_V2_OUT in new code
5712 */
5713#define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
5714
5715/* MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT msgresponse:
5716 *
5717 * Extended NVRAM_UPDATE_FINISH response that communicates the result of secure
5718 * firmware validation where applicable back to the host.
5719 *
5720 * Medford only: For signed firmware images, such as those for medford, the MC
5721 * firmware verifies the signature before marking the firmware image as valid.
5722 * This process takes a few seconds to complete. So is likely to take more than
5723 * the MCDI timeout. Hence signature verification is initiated when
5724 * MC_CMD_NVRAM_UPDATE_FINISH_V2_IN is received by the firmware, however, the
5725 * MCDI command is run in a background MCDI processing thread. This response
5726 * payload includes the results of the signature verification. Note that the
5727 * per-partition nvram lock in firmware is only released after the verification
5728 * has completed.
5729 */
5730#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
5731/* Result of nvram update completion processing. Result codes that indicate an
5732 * internal build failure and therefore not expected to be seen by customers in
5733 * the field are marked with a prefix 'Internal-error'.
5734 */
5735#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
5736#define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
5737/* enum: Invalid return code; only non-zero values are defined. Defined as
5738 * unknown for backwards compatibility with NVRAM_UPDATE_FINISH_OUT.
5739 */
5740#define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
5741/* enum: Verify succeeded without any errors. */
5742#define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
5743/* enum: CMS format verification failed due to an internal error. */
5744#define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
5745/* enum: Invalid CMS format in image metadata. */
5746#define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
5747/* enum: Message digest verification failed due to an internal error. */
5748#define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
5749/* enum: Error in message digest calculated over the reflash-header, payload
5750 * and reflash-trailer.
5751 */
5752#define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
5753/* enum: Signature verification failed due to an internal error. */
5754#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
5755/* enum: There are no valid signatures in the image. */
5756#define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
5757/* enum: Trusted approvers verification failed due to an internal error. */
5758#define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
5759/* enum: The Trusted approver's list is empty. */
5760#define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
5761/* enum: Signature chain verification failed due to an internal error. */
5762#define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
5763/* enum: The signers of the signatures in the image are not listed in the
5764 * Trusted approver's list.
5765 */
5766#define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
5767/* enum: The image contains a test-signed certificate, but the adapter accepts
5768 * only production signed images.
5769 */
5770#define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
5771/* enum: The image has a lower security level than the current firmware. */
5772#define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
5773/* enum: Internal-error. The signed image is missing the 'contents' section,
5774 * where the 'contents' section holds the actual image payload to be applied.
5775 */
5776#define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe
5777/* enum: Internal-error. The bundle header is invalid. */
5778#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf
5779/* enum: Internal-error. The bundle does not have a valid reflash image layout.
5780 */
5781#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10
5782/* enum: Internal-error. The bundle has an inconsistent layout of components or
5783 * incorrect checksum.
5784 */
5785#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11
5786/* enum: Internal-error. The bundle manifest is inconsistent with components in
5787 * the bundle.
5788 */
5789#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12
5790/* enum: Internal-error. The number of components in a bundle do not match the
5791 * number of components advertised by the bundle manifest.
5792 */
5793#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13
5794/* enum: Internal-error. The bundle contains too many components for the MC
5795 * firmware to process
5796 */
5797#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14
5798/* enum: Internal-error. The bundle manifest has an invalid/inconsistent
5799 * component.
5800 */
5801#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15
5802/* enum: Internal-error. The hash of a component does not match the hash stored
5803 * in the bundle manifest.
5804 */
5805#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16
5806/* enum: Internal-error. Component hash calculation failed. */
5807#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17
5808/* enum: Internal-error. The component does not have a valid reflash image
5809 * layout.
5810 */
5811#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18
5812/* enum: The bundle processing code failed to copy a component to its target
5813 * partition.
5814 */
5815#define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19
5816/* enum: The update operation is in-progress. */
5817#define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a
5818
5819
5820/***********************************/
5821/* MC_CMD_REBOOT
5822 * Reboot the MC.
5823 *
5824 * The AFTER_ASSERTION flag is intended to be used when the driver notices an
5825 * assertion failure (at which point it is expected to perform a complete tear
5826 * down and reinitialise), to allow both ports to reset the MC once in an
5827 * atomic fashion.
5828 *
5829 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
5830 * which means that they will automatically reboot out of the assertion
5831 * handler, so this is in practise an optional operation. It is still
5832 * recommended that drivers execute this to support custom firmwares with
5833 * REBOOT_ON_ASSERT=0.
5834 *
5835 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
5836 * DATALEN=0
5837 */
5838#define MC_CMD_REBOOT 0x3d
5839#undef MC_CMD_0x3d_PRIVILEGE_CTG
5840
5841#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5842
5843/* MC_CMD_REBOOT_IN msgrequest */
5844#define MC_CMD_REBOOT_IN_LEN 4
5845#define MC_CMD_REBOOT_IN_FLAGS_OFST 0
5846#define MC_CMD_REBOOT_IN_FLAGS_LEN 4
5847#define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
5848
5849/* MC_CMD_REBOOT_OUT msgresponse */
5850#define MC_CMD_REBOOT_OUT_LEN 0
5851
5852
5853/***********************************/
5854/* MC_CMD_SCHEDINFO
5855 * Request scheduler info. Locks required: NONE. Returns: An array of
5856 * (timeslice,maximum overrun), one for each thread, in ascending order of
5857 * thread address.
5858 */
5859#define MC_CMD_SCHEDINFO 0x3e
5860#undef MC_CMD_0x3e_PRIVILEGE_CTG
5861
5862#define MC_CMD_0x3e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
5863
5864/* MC_CMD_SCHEDINFO_IN msgrequest */
5865#define MC_CMD_SCHEDINFO_IN_LEN 0
5866
5867/* MC_CMD_SCHEDINFO_OUT msgresponse */
5868#define MC_CMD_SCHEDINFO_OUT_LENMIN 4
5869#define MC_CMD_SCHEDINFO_OUT_LENMAX 252
5870#define MC_CMD_SCHEDINFO_OUT_LENMAX_MCDI2 1020
5871#define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
5872#define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)
5873#define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
5874#define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
5875#define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
5876#define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
5877#define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM_MCDI2 255
5878
5879
5880/***********************************/
5881/* MC_CMD_REBOOT_MODE
5882 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot
5883 * mode to the specified value. Returns the old mode.
5884 */
5885#define MC_CMD_REBOOT_MODE 0x3f
5886#undef MC_CMD_0x3f_PRIVILEGE_CTG
5887
5888#define MC_CMD_0x3f_PRIVILEGE_CTG SRIOV_CTG_INSECURE
5889
5890/* MC_CMD_REBOOT_MODE_IN msgrequest */
5891#define MC_CMD_REBOOT_MODE_IN_LEN 4
5892#define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
5893#define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4
5894/* enum: Normal. */
5895#define MC_CMD_REBOOT_MODE_NORMAL 0x0
5896/* enum: Power-on Reset. */
5897#define MC_CMD_REBOOT_MODE_POR 0x2
5898/* enum: Snapper. */
5899#define MC_CMD_REBOOT_MODE_SNAPPER 0x3
5900/* enum: snapper fake POR */
5901#define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
5902#define MC_CMD_REBOOT_MODE_IN_FAKE_OFST 0
5903#define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7
5904#define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
5905
5906/* MC_CMD_REBOOT_MODE_OUT msgresponse */
5907#define MC_CMD_REBOOT_MODE_OUT_LEN 4
5908#define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
5909#define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4
5910
5911
5912/***********************************/
5913/* MC_CMD_SENSOR_INFO
5914 * Returns information about every available sensor.
5915 *
5916 * Each sensor has a single (16bit) value, and a corresponding state. The
5917 * mapping between value and state is nominally determined by the MC, but may
5918 * be implemented using up to 2 ranges per sensor.
5919 *
5920 * This call returns a mask (32bit) of the sensors that are supported by this
5921 * platform, then an array of sensor information structures, in order of sensor
5922 * type (but without gaps for unimplemented sensors). Each structure defines
5923 * the ranges for the corresponding sensor. An unused range is indicated by
5924 * equal limit values. If one range is used, a value outside that range results
5925 * in STATE_FATAL. If two ranges are used, a value outside the second range
5926 * results in STATE_FATAL while a value outside the first and inside the second
5927 * range results in STATE_WARNING.
5928 *
5929 * Sensor masks and sensor information arrays are organised into pages. For
5930 * backward compatibility, older host software can only use sensors in page 0.
5931 * Bit 32 in the sensor mask was previously unused, and is no reserved for use
5932 * as the next page flag.
5933 *
5934 * If the request does not contain a PAGE value then firmware will only return
5935 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
5936 *
5937 * If the request contains a PAGE value then firmware responds with the sensor
5938 * mask and sensor information array for that page of sensors. In this case bit
5939 * 31 in the mask is set if another page exists.
5940 *
5941 * Locks required: None Returns: 0
5942 */
5943#define MC_CMD_SENSOR_INFO 0x41
5944#undef MC_CMD_0x41_PRIVILEGE_CTG
5945
5946#define MC_CMD_0x41_PRIVILEGE_CTG SRIOV_CTG_GENERAL
5947
5948/* MC_CMD_SENSOR_INFO_IN msgrequest */
5949#define MC_CMD_SENSOR_INFO_IN_LEN 0
5950
5951/* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */
5952#define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
5953/* Which page of sensors to report.
5954 *
5955 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
5956 *
5957 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
5958 */
5959#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
5960#define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
5961
5962/* MC_CMD_SENSOR_INFO_EXT_IN_V2 msgrequest */
5963#define MC_CMD_SENSOR_INFO_EXT_IN_V2_LEN 8
5964/* Which page of sensors to report.
5965 *
5966 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
5967 *
5968 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
5969 */
5970#define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 0
5971#define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4
5972/* Flags controlling information retrieved */
5973#define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4
5974#define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4
5975#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4
5976#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0
5977#define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_WIDTH 1
5978
5979/* MC_CMD_SENSOR_INFO_OUT msgresponse */
5980#define MC_CMD_SENSOR_INFO_OUT_LENMIN 4
5981#define MC_CMD_SENSOR_INFO_OUT_LENMAX 252
5982#define MC_CMD_SENSOR_INFO_OUT_LENMAX_MCDI2 1020
5983#define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
5984#define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
5985#define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
5986#define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
5987/* enum: Controller temperature: degC */
5988#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
5989/* enum: Phy common temperature: degC */
5990#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
5991/* enum: Controller cooling: bool */
5992#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
5993/* enum: Phy 0 temperature: degC */
5994#define MC_CMD_SENSOR_PHY0_TEMP 0x3
5995/* enum: Phy 0 cooling: bool */
5996#define MC_CMD_SENSOR_PHY0_COOLING 0x4
5997/* enum: Phy 1 temperature: degC */
5998#define MC_CMD_SENSOR_PHY1_TEMP 0x5
5999/* enum: Phy 1 cooling: bool */
6000#define MC_CMD_SENSOR_PHY1_COOLING 0x6
6001/* enum: 1.0v power: mV */
6002#define MC_CMD_SENSOR_IN_1V0 0x7
6003/* enum: 1.2v power: mV */
6004#define MC_CMD_SENSOR_IN_1V2 0x8
6005/* enum: 1.8v power: mV */
6006#define MC_CMD_SENSOR_IN_1V8 0x9
6007/* enum: 2.5v power: mV */
6008#define MC_CMD_SENSOR_IN_2V5 0xa
6009/* enum: 3.3v power: mV */
6010#define MC_CMD_SENSOR_IN_3V3 0xb
6011/* enum: 12v power: mV */
6012#define MC_CMD_SENSOR_IN_12V0 0xc
6013/* enum: 1.2v analogue power: mV */
6014#define MC_CMD_SENSOR_IN_1V2A 0xd
6015/* enum: reference voltage: mV */
6016#define MC_CMD_SENSOR_IN_VREF 0xe
6017/* enum: AOE FPGA power: mV */
6018#define MC_CMD_SENSOR_OUT_VAOE 0xf
6019/* enum: AOE FPGA temperature: degC */
6020#define MC_CMD_SENSOR_AOE_TEMP 0x10
6021/* enum: AOE FPGA PSU temperature: degC */
6022#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
6023/* enum: AOE PSU temperature: degC */
6024#define MC_CMD_SENSOR_PSU_TEMP 0x12
6025/* enum: Fan 0 speed: RPM */
6026#define MC_CMD_SENSOR_FAN_0 0x13
6027/* enum: Fan 1 speed: RPM */
6028#define MC_CMD_SENSOR_FAN_1 0x14
6029/* enum: Fan 2 speed: RPM */
6030#define MC_CMD_SENSOR_FAN_2 0x15
6031/* enum: Fan 3 speed: RPM */
6032#define MC_CMD_SENSOR_FAN_3 0x16
6033/* enum: Fan 4 speed: RPM */
6034#define MC_CMD_SENSOR_FAN_4 0x17
6035/* enum: AOE FPGA input power: mV */
6036#define MC_CMD_SENSOR_IN_VAOE 0x18
6037/* enum: AOE FPGA current: mA */
6038#define MC_CMD_SENSOR_OUT_IAOE 0x19
6039/* enum: AOE FPGA input current: mA */
6040#define MC_CMD_SENSOR_IN_IAOE 0x1a
6041/* enum: NIC power consumption: W */
6042#define MC_CMD_SENSOR_NIC_POWER 0x1b
6043/* enum: 0.9v power voltage: mV */
6044#define MC_CMD_SENSOR_IN_0V9 0x1c
6045/* enum: 0.9v power current: mA */
6046#define MC_CMD_SENSOR_IN_I0V9 0x1d
6047/* enum: 1.2v power current: mA */
6048#define MC_CMD_SENSOR_IN_I1V2 0x1e
6049/* enum: Not a sensor: reserved for the next page flag */
6050#define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
6051/* enum: 0.9v power voltage (at ADC): mV */
6052#define MC_CMD_SENSOR_IN_0V9_ADC 0x20
6053/* enum: Controller temperature 2: degC */
6054#define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
6055/* enum: Voltage regulator internal temperature: degC */
6056#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
6057/* enum: 0.9V voltage regulator temperature: degC */
6058#define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
6059/* enum: 1.2V voltage regulator temperature: degC */
6060#define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
6061/* enum: controller internal temperature sensor voltage (internal ADC): mV */
6062#define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
6063/* enum: controller internal temperature (internal ADC): degC */
6064#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
6065/* enum: controller internal temperature sensor voltage (external ADC): mV */
6066#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
6067/* enum: controller internal temperature (external ADC): degC */
6068#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
6069/* enum: ambient temperature: degC */
6070#define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
6071/* enum: air flow: bool */
6072#define MC_CMD_SENSOR_AIRFLOW 0x2a
6073/* enum: voltage between VSS08D and VSS08D at CSR: mV */
6074#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
6075/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
6076#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
6077/* enum: Hotpoint temperature: degC */
6078#define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
6079/* enum: Port 0 PHY power switch over-current: bool */
6080#define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
6081/* enum: Port 1 PHY power switch over-current: bool */
6082#define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
6083/* enum: Mop-up microcontroller reference voltage: mV */
6084#define MC_CMD_SENSOR_MUM_VCC 0x30
6085/* enum: 0.9v power phase A voltage: mV */
6086#define MC_CMD_SENSOR_IN_0V9_A 0x31
6087/* enum: 0.9v power phase A current: mA */
6088#define MC_CMD_SENSOR_IN_I0V9_A 0x32
6089/* enum: 0.9V voltage regulator phase A temperature: degC */
6090#define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
6091/* enum: 0.9v power phase B voltage: mV */
6092#define MC_CMD_SENSOR_IN_0V9_B 0x34
6093/* enum: 0.9v power phase B current: mA */
6094#define MC_CMD_SENSOR_IN_I0V9_B 0x35
6095/* enum: 0.9V voltage regulator phase B temperature: degC */
6096#define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
6097/* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
6098#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
6099/* enum: CCOM AVREG 1v2 supply (external ADC): mV */
6100#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
6101/* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
6102#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
6103/* enum: CCOM AVREG 1v8 supply (external ADC): mV */
6104#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
6105/* enum: CCOM RTS temperature: degC */
6106#define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
6107/* enum: Not a sensor: reserved for the next page flag */
6108#define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
6109/* enum: controller internal temperature sensor voltage on master core
6110 * (internal ADC): mV
6111 */
6112#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
6113/* enum: controller internal temperature on master core (internal ADC): degC */
6114#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
6115/* enum: controller internal temperature sensor voltage on master core
6116 * (external ADC): mV
6117 */
6118#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
6119/* enum: controller internal temperature on master core (external ADC): degC */
6120#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
6121/* enum: controller internal temperature on slave core sensor voltage (internal
6122 * ADC): mV
6123 */
6124#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
6125/* enum: controller internal temperature on slave core (internal ADC): degC */
6126#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
6127/* enum: controller internal temperature on slave core sensor voltage (external
6128 * ADC): mV
6129 */
6130#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
6131/* enum: controller internal temperature on slave core (external ADC): degC */
6132#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
6133/* enum: Voltage supplied to the SODIMMs from their power supply: mV */
6134#define MC_CMD_SENSOR_SODIMM_VOUT 0x49
6135/* enum: Temperature of SODIMM 0 (if installed): degC */
6136#define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
6137/* enum: Temperature of SODIMM 1 (if installed): degC */
6138#define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
6139/* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
6140#define MC_CMD_SENSOR_PHY0_VCC 0x4c
6141/* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
6142#define MC_CMD_SENSOR_PHY1_VCC 0x4d
6143/* enum: Controller die temperature (TDIODE): degC */
6144#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
6145/* enum: Board temperature (front): degC */
6146#define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
6147/* enum: Board temperature (back): degC */
6148#define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
6149/* enum: 1.8v power current: mA */
6150#define MC_CMD_SENSOR_IN_I1V8 0x51
6151/* enum: 2.5v power current: mA */
6152#define MC_CMD_SENSOR_IN_I2V5 0x52
6153/* enum: 3.3v power current: mA */
6154#define MC_CMD_SENSOR_IN_I3V3 0x53
6155/* enum: 12v power current: mA */
6156#define MC_CMD_SENSOR_IN_I12V0 0x54
6157/* enum: 1.3v power: mV */
6158#define MC_CMD_SENSOR_IN_1V3 0x55
6159/* enum: 1.3v power current: mA */
6160#define MC_CMD_SENSOR_IN_I1V3 0x56
6161/* enum: Engineering sensor 1 */
6162#define MC_CMD_SENSOR_ENGINEERING_1 0x57
6163/* enum: Engineering sensor 2 */
6164#define MC_CMD_SENSOR_ENGINEERING_2 0x58
6165/* enum: Engineering sensor 3 */
6166#define MC_CMD_SENSOR_ENGINEERING_3 0x59
6167/* enum: Engineering sensor 4 */
6168#define MC_CMD_SENSOR_ENGINEERING_4 0x5a
6169/* enum: Engineering sensor 5 */
6170#define MC_CMD_SENSOR_ENGINEERING_5 0x5b
6171/* enum: Engineering sensor 6 */
6172#define MC_CMD_SENSOR_ENGINEERING_6 0x5c
6173/* enum: Engineering sensor 7 */
6174#define MC_CMD_SENSOR_ENGINEERING_7 0x5d
6175/* enum: Engineering sensor 8 */
6176#define MC_CMD_SENSOR_ENGINEERING_8 0x5e
6177/* enum: Not a sensor: reserved for the next page flag */
6178#define MC_CMD_SENSOR_PAGE2_NEXT 0x5f
6179/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
6180#define MC_CMD_SENSOR_ENTRY_OFST 4
6181#define MC_CMD_SENSOR_ENTRY_LEN 8
6182#define MC_CMD_SENSOR_ENTRY_LO_OFST 4
6183#define MC_CMD_SENSOR_ENTRY_HI_OFST 8
6184#define MC_CMD_SENSOR_ENTRY_MINNUM 0
6185#define MC_CMD_SENSOR_ENTRY_MAXNUM 31
6186#define MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127
6187
6188/* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */
6189#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
6190#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
6191#define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX_MCDI2 1020
6192#define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
6193#define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
6194#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
6195#define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
6196/* Enum values, see field(s): */
6197/* MC_CMD_SENSOR_INFO_OUT */
6198#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 0
6199#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31
6200#define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
6201/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
6202/* MC_CMD_SENSOR_ENTRY_OFST 4 */
6203/* MC_CMD_SENSOR_ENTRY_LEN 8 */
6204/* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
6205/* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
6206/* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
6207/* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
6208/* MC_CMD_SENSOR_ENTRY_MAXNUM_MCDI2 127 */
6209
6210/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
6211#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
6212#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
6213#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
6214#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
6215#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
6216#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
6217#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
6218#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
6219#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
6220#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
6221#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
6222#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
6223#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
6224#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
6225#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
6226#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
6227#define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
6228
6229
6230/***********************************/
6231/* MC_CMD_READ_SENSORS
6232 * Returns the current reading from each sensor. DMAs an array of sensor
6233 * readings, in order of sensor type (but without gaps for unimplemented
6234 * sensors), into host memory. Each array element is a
6235 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.
6236 *
6237 * If the request does not contain the LENGTH field then only sensors 0 to 30
6238 * are reported, to avoid DMA buffer overflow in older host software. If the
6239 * sensor reading require more space than the LENGTH allows, then return
6240 * EINVAL.
6241 *
6242 * The MC will send a SENSOREVT event every time any sensor changes state. The
6243 * driver is responsible for ensuring that it doesn't miss any events. The
6244 * board will function normally if all sensors are in STATE_OK or
6245 * STATE_WARNING. Otherwise the board should not be expected to function.
6246 */
6247#define MC_CMD_READ_SENSORS 0x42
6248#undef MC_CMD_0x42_PRIVILEGE_CTG
6249
6250#define MC_CMD_0x42_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6251
6252/* MC_CMD_READ_SENSORS_IN msgrequest */
6253#define MC_CMD_READ_SENSORS_IN_LEN 8
6254/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6255 *
6256 * If the address is 0xffffffffffffffff send the readings in the response (used
6257 * by cmdclient).
6258 */
6259#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
6260#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
6261#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
6262#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
6263
6264/* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
6265#define MC_CMD_READ_SENSORS_EXT_IN_LEN 12
6266/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6267 *
6268 * If the address is 0xffffffffffffffff send the readings in the response (used
6269 * by cmdclient).
6270 */
6271#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
6272#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
6273#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
6274#define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
6275/* Size in bytes of host buffer. */
6276#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
6277#define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
6278
6279/* MC_CMD_READ_SENSORS_EXT_IN_V2 msgrequest */
6280#define MC_CMD_READ_SENSORS_EXT_IN_V2_LEN 16
6281/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
6282 *
6283 * If the address is 0xffffffffffffffff send the readings in the response (used
6284 * by cmdclient).
6285 */
6286#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
6287#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LEN 8
6288#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
6289#define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
6290/* Size in bytes of host buffer. */
6291#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_OFST 8
6292#define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
6293/* Flags controlling information retrieved */
6294#define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_OFST 12
6295#define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4
6296#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_OFST 12
6297#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0
6298#define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_WIDTH 1
6299
6300/* MC_CMD_READ_SENSORS_OUT msgresponse */
6301#define MC_CMD_READ_SENSORS_OUT_LEN 0
6302
6303/* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */
6304#define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
6305
6306/* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
6307#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
6308#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
6309#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
6310#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
6311#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
6312#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
6313#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
6314/* enum: Ok. */
6315#define MC_CMD_SENSOR_STATE_OK 0x0
6316/* enum: Breached warning threshold. */
6317#define MC_CMD_SENSOR_STATE_WARNING 0x1
6318/* enum: Breached fatal threshold. */
6319#define MC_CMD_SENSOR_STATE_FATAL 0x2
6320/* enum: Fault with sensor. */
6321#define MC_CMD_SENSOR_STATE_BROKEN 0x3
6322/* enum: Sensor is working but does not currently have a reading. */
6323#define MC_CMD_SENSOR_STATE_NO_READING 0x4
6324/* enum: Sensor initialisation failed. */
6325#define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
6326#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
6327#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
6328#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3
6329#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
6330/* Enum values, see field(s): */
6331/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
6332#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24
6333#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8
6334
6335
6336/***********************************/
6337/* MC_CMD_GET_PHY_STATE
6338 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot
6339 * (e.g. due to missing or corrupted firmware). Locks required: None. Return
6340 * code: 0
6341 */
6342#define MC_CMD_GET_PHY_STATE 0x43
6343#undef MC_CMD_0x43_PRIVILEGE_CTG
6344
6345#define MC_CMD_0x43_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6346
6347/* MC_CMD_GET_PHY_STATE_IN msgrequest */
6348#define MC_CMD_GET_PHY_STATE_IN_LEN 0
6349
6350/* MC_CMD_GET_PHY_STATE_OUT msgresponse */
6351#define MC_CMD_GET_PHY_STATE_OUT_LEN 4
6352#define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
6353#define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
6354/* enum: Ok. */
6355#define MC_CMD_PHY_STATE_OK 0x1
6356/* enum: Faulty. */
6357#define MC_CMD_PHY_STATE_ZOMBIE 0x2
6358
6359
6360/***********************************/
6361/* MC_CMD_SETUP_8021QBB
6362 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
6363 * disable 802.Qbb for a given priority.
6364 */
6365#define MC_CMD_SETUP_8021QBB 0x44
6366
6367/* MC_CMD_SETUP_8021QBB_IN msgrequest */
6368#define MC_CMD_SETUP_8021QBB_IN_LEN 32
6369#define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
6370#define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32
6371
6372/* MC_CMD_SETUP_8021QBB_OUT msgresponse */
6373#define MC_CMD_SETUP_8021QBB_OUT_LEN 0
6374
6375
6376/***********************************/
6377/* MC_CMD_WOL_FILTER_GET
6378 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
6379 */
6380#define MC_CMD_WOL_FILTER_GET 0x45
6381#undef MC_CMD_0x45_PRIVILEGE_CTG
6382
6383#define MC_CMD_0x45_PRIVILEGE_CTG SRIOV_CTG_LINK
6384
6385/* MC_CMD_WOL_FILTER_GET_IN msgrequest */
6386#define MC_CMD_WOL_FILTER_GET_IN_LEN 0
6387
6388/* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
6389#define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
6390#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
6391#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4
6392
6393
6394/***********************************/
6395/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
6396 * Add a protocol offload to NIC for lights-out state. Locks required: None.
6397 * Returns: 0, ENOSYS
6398 */
6399#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
6400#undef MC_CMD_0x46_PRIVILEGE_CTG
6401
6402#define MC_CMD_0x46_PRIVILEGE_CTG SRIOV_CTG_LINK
6403
6404/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
6405#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
6406#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
6407#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX_MCDI2 1020
6408#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
6409#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4)
6410#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
6411#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
6412#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
6413#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
6414#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
6415#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
6416#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
6417#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
6418#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM_MCDI2 254
6419
6420/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
6421#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
6422/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
6423/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
6424#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
6425#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
6426#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
6427#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4
6428
6429/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
6430#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
6431/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
6432/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
6433#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
6434#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
6435#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
6436#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
6437#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
6438#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16
6439
6440/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
6441#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
6442#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
6443#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4
6444
6445
6446/***********************************/
6447/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
6448 * Remove a protocol offload from NIC for lights-out state. Locks required:
6449 * None. Returns: 0, ENOSYS
6450 */
6451#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
6452#undef MC_CMD_0x47_PRIVILEGE_CTG
6453
6454#define MC_CMD_0x47_PRIVILEGE_CTG SRIOV_CTG_LINK
6455
6456/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
6457#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
6458#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
6459#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
6460#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
6461#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4
6462
6463/* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
6464#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
6465
6466
6467/***********************************/
6468/* MC_CMD_MAC_RESET_RESTORE
6469 * Restore MAC after block reset. Locks required: None. Returns: 0.
6470 */
6471#define MC_CMD_MAC_RESET_RESTORE 0x48
6472
6473/* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
6474#define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
6475
6476/* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
6477#define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
6478
6479
6480/***********************************/
6481/* MC_CMD_TESTASSERT
6482 * Deliberately trigger an assert-detonation in the firmware for testing
6483 * purposes (i.e. to allow tests that the driver copes gracefully). Locks
6484 * required: None Returns: 0
6485 */
6486#define MC_CMD_TESTASSERT 0x49
6487#undef MC_CMD_0x49_PRIVILEGE_CTG
6488
6489#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6490
6491/* MC_CMD_TESTASSERT_IN msgrequest */
6492#define MC_CMD_TESTASSERT_IN_LEN 0
6493
6494/* MC_CMD_TESTASSERT_OUT msgresponse */
6495#define MC_CMD_TESTASSERT_OUT_LEN 0
6496
6497/* MC_CMD_TESTASSERT_V2_IN msgrequest */
6498#define MC_CMD_TESTASSERT_V2_IN_LEN 4
6499/* How to provoke the assertion */
6500#define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0
6501#define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4
6502/* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless
6503 * you're testing firmware, this is what you want.
6504 */
6505#define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
6506/* enum: Assert using assert(0); */
6507#define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
6508/* enum: Deliberately trigger a watchdog */
6509#define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
6510/* enum: Deliberately trigger a trap by loading from an invalid address */
6511#define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
6512/* enum: Deliberately trigger a trap by storing to an invalid address */
6513#define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
6514/* enum: Jump to an invalid address */
6515#define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5
6516
6517/* MC_CMD_TESTASSERT_V2_OUT msgresponse */
6518#define MC_CMD_TESTASSERT_V2_OUT_LEN 0
6519
6520
6521/***********************************/
6522/* MC_CMD_WORKAROUND
6523 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't
6524 * understand the given workaround number - which should not be treated as a
6525 * hard error by client code. This op does not imply any semantics about each
6526 * workaround, that's between the driver and the mcfw on a per-workaround
6527 * basis. Locks required: None. Returns: 0, EINVAL .
6528 */
6529#define MC_CMD_WORKAROUND 0x4a
6530#undef MC_CMD_0x4a_PRIVILEGE_CTG
6531
6532#define MC_CMD_0x4a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6533
6534/* MC_CMD_WORKAROUND_IN msgrequest */
6535#define MC_CMD_WORKAROUND_IN_LEN 8
6536/* The enums here must correspond with those in MC_CMD_GET_WORKAROUND. */
6537#define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
6538#define MC_CMD_WORKAROUND_IN_TYPE_LEN 4
6539/* enum: Bug 17230 work around. */
6540#define MC_CMD_WORKAROUND_BUG17230 0x1
6541/* enum: Bug 35388 work around (unsafe EVQ writes). */
6542#define MC_CMD_WORKAROUND_BUG35388 0x2
6543/* enum: Bug35017 workaround (A64 tables must be identity map) */
6544#define MC_CMD_WORKAROUND_BUG35017 0x3
6545/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
6546#define MC_CMD_WORKAROUND_BUG41750 0x4
6547/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
6548 * - before adding code that queries this workaround, remember that there's
6549 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
6550 * and will hence (incorrectly) report that the bug doesn't exist.
6551 */
6552#define MC_CMD_WORKAROUND_BUG42008 0x5
6553/* enum: Bug 26807 features present in firmware (multicast filter chaining)
6554 * This feature cannot be turned on/off while there are any filters already
6555 * present. The behaviour in such case depends on the acting client's privilege
6556 * level. If the client has the admin privilege, then all functions that have
6557 * filters installed will be FLRed and the FLR_DONE flag will be set. Otherwise
6558 * the command will fail with MC_CMD_ERR_FILTERS_PRESENT.
6559 */
6560#define MC_CMD_WORKAROUND_BUG26807 0x6
6561/* enum: Bug 61265 work around (broken EVQ TMR writes). */
6562#define MC_CMD_WORKAROUND_BUG61265 0x7
6563/* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
6564 * the workaround
6565 */
6566#define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
6567#define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
6568
6569/* MC_CMD_WORKAROUND_OUT msgresponse */
6570#define MC_CMD_WORKAROUND_OUT_LEN 0
6571
6572/* MC_CMD_WORKAROUND_EXT_OUT msgresponse: This response format will be used
6573 * when (TYPE == MC_CMD_WORKAROUND_BUG26807)
6574 */
6575#define MC_CMD_WORKAROUND_EXT_OUT_LEN 4
6576#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
6577#define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
6578#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0
6579#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
6580#define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1
6581
6582
6583/***********************************/
6584/* MC_CMD_GET_PHY_MEDIA_INFO
6585 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
6586 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG
6587 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the
6588 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1
6589 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
6590 * Anything else: currently undefined. Locks required: None. Return code: 0.
6591 */
6592#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
6593#undef MC_CMD_0x4b_PRIVILEGE_CTG
6594
6595#define MC_CMD_0x4b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6596
6597/* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
6598#define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
6599#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
6600#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
6601
6602/* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
6603#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
6604#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
6605#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX_MCDI2 1020
6606#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
6607#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)
6608/* in bytes */
6609#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
6610#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
6611#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
6612#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
6613#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
6614#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
6615#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM_MCDI2 1016
6616
6617
6618/***********************************/
6619/* MC_CMD_NVRAM_TEST
6620 * Test a particular NVRAM partition for valid contents (where "valid" depends
6621 * on the type of partition).
6622 */
6623#define MC_CMD_NVRAM_TEST 0x4c
6624#undef MC_CMD_0x4c_PRIVILEGE_CTG
6625
6626#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6627
6628/* MC_CMD_NVRAM_TEST_IN msgrequest */
6629#define MC_CMD_NVRAM_TEST_IN_LEN 4
6630#define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
6631#define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
6632/* Enum values, see field(s): */
6633/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
6634
6635/* MC_CMD_NVRAM_TEST_OUT msgresponse */
6636#define MC_CMD_NVRAM_TEST_OUT_LEN 4
6637#define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
6638#define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
6639/* enum: Passed. */
6640#define MC_CMD_NVRAM_TEST_PASS 0x0
6641/* enum: Failed. */
6642#define MC_CMD_NVRAM_TEST_FAIL 0x1
6643/* enum: Not supported. */
6644#define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
6645
6646
6647/***********************************/
6648/* MC_CMD_MRSFP_TWEAK
6649 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.
6650 * I2C I/O expander bits are always read; if equaliser parameters are supplied,
6651 * they are configured first. Locks required: None. Return code: 0, EINVAL.
6652 */
6653#define MC_CMD_MRSFP_TWEAK 0x4d
6654
6655/* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
6656#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
6657/* 0-6 low->high de-emph. */
6658#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
6659#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4
6660/* 0-8 low->high ref.V */
6661#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
6662#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4
6663/* 0-8 0-8 low->high boost */
6664#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
6665#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4
6666/* 0-8 low->high ref.V */
6667#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
6668#define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4
6669
6670/* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
6671#define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
6672
6673/* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
6674#define MC_CMD_MRSFP_TWEAK_OUT_LEN 12
6675/* input bits */
6676#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
6677#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4
6678/* output bits */
6679#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
6680#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4
6681/* direction */
6682#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
6683#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4
6684/* enum: Out. */
6685#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
6686/* enum: In. */
6687#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
6688
6689
6690/***********************************/
6691/* MC_CMD_SENSOR_SET_LIMS
6692 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
6693 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out
6694 * of range.
6695 */
6696#define MC_CMD_SENSOR_SET_LIMS 0x4e
6697#undef MC_CMD_0x4e_PRIVILEGE_CTG
6698
6699#define MC_CMD_0x4e_PRIVILEGE_CTG SRIOV_CTG_INSECURE
6700
6701/* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
6702#define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
6703#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
6704#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4
6705/* Enum values, see field(s): */
6706/* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
6707/* interpretation is is sensor-specific. */
6708#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
6709#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4
6710/* interpretation is is sensor-specific. */
6711#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
6712#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4
6713/* interpretation is is sensor-specific. */
6714#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
6715#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4
6716/* interpretation is is sensor-specific. */
6717#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
6718#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4
6719
6720/* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
6721#define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
6722
6723
6724/***********************************/
6725/* MC_CMD_GET_RESOURCE_LIMITS
6726 */
6727#define MC_CMD_GET_RESOURCE_LIMITS 0x4f
6728
6729/* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
6730#define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
6731
6732/* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
6733#define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
6734#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
6735#define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4
6736#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
6737#define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4
6738#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
6739#define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4
6740#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
6741#define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4
6742
6743
6744/***********************************/
6745/* MC_CMD_NVRAM_PARTITIONS
6746 * Reads the list of available virtual NVRAM partition types. Locks required:
6747 * none. Returns: 0, EINVAL (bad type).
6748 */
6749#define MC_CMD_NVRAM_PARTITIONS 0x51
6750#undef MC_CMD_0x51_PRIVILEGE_CTG
6751
6752#define MC_CMD_0x51_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6753
6754/* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */
6755#define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
6756
6757/* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */
6758#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
6759#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
6760#define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX_MCDI2 1020
6761#define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
6762#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)
6763/* total number of partitions */
6764#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
6765#define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
6766/* type ID code for each of NUM_PARTITIONS partitions */
6767#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
6768#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
6769#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
6770#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62
6771#define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM_MCDI2 254
6772
6773
6774/***********************************/
6775/* MC_CMD_NVRAM_METADATA
6776 * Reads soft metadata for a virtual NVRAM partition type. Locks required:
6777 * none. Returns: 0, EINVAL (bad type).
6778 */
6779#define MC_CMD_NVRAM_METADATA 0x52
6780#undef MC_CMD_0x52_PRIVILEGE_CTG
6781
6782#define MC_CMD_0x52_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6783
6784/* MC_CMD_NVRAM_METADATA_IN msgrequest */
6785#define MC_CMD_NVRAM_METADATA_IN_LEN 4
6786/* Partition type ID code */
6787#define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
6788#define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
6789
6790/* MC_CMD_NVRAM_METADATA_OUT msgresponse */
6791#define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20
6792#define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
6793#define MC_CMD_NVRAM_METADATA_OUT_LENMAX_MCDI2 1020
6794#define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
6795#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)
6796/* Partition type ID code */
6797#define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
6798#define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
6799#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
6800#define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
6801#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4
6802#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
6803#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
6804#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4
6805#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
6806#define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
6807#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4
6808#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2
6809#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
6810/* Subtype ID code for content of this partition */
6811#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8
6812#define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
6813/* 1st component of W.X.Y.Z version number for content of this partition */
6814#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12
6815#define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2
6816/* 2nd component of W.X.Y.Z version number for content of this partition */
6817#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14
6818#define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2
6819/* 3rd component of W.X.Y.Z version number for content of this partition */
6820#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16
6821#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2
6822/* 4th component of W.X.Y.Z version number for content of this partition */
6823#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18
6824#define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2
6825/* Zero-terminated string describing the content of this partition */
6826#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20
6827#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
6828#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
6829#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232
6830#define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM_MCDI2 1000
6831
6832
6833/***********************************/
6834/* MC_CMD_GET_MAC_ADDRESSES
6835 * Returns the base MAC, count and stride for the requesting function
6836 */
6837#define MC_CMD_GET_MAC_ADDRESSES 0x55
6838#undef MC_CMD_0x55_PRIVILEGE_CTG
6839
6840#define MC_CMD_0x55_PRIVILEGE_CTG SRIOV_CTG_GENERAL
6841
6842/* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */
6843#define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
6844
6845/* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */
6846#define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16
6847/* Base MAC address */
6848#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
6849#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6
6850/* Padding */
6851#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6
6852#define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2
6853/* Number of allocated MAC addresses */
6854#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8
6855#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
6856/* Spacing of allocated MAC addresses */
6857#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12
6858#define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
6859
6860
6861/***********************************/
6862/* MC_CMD_CLP
6863 * Perform a CLP related operation, see SF-110495-PS for details of CLP
6864 * processing. This command has been extended to accomodate the requirements of
6865 * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC,
6866 * SF-120509-TC and SF-117282-PS.
6867 */
6868#define MC_CMD_CLP 0x56
6869#undef MC_CMD_0x56_PRIVILEGE_CTG
6870
6871#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN
6872
6873/* MC_CMD_CLP_IN msgrequest */
6874#define MC_CMD_CLP_IN_LEN 4
6875/* Sub operation */
6876#define MC_CMD_CLP_IN_OP_OFST 0
6877#define MC_CMD_CLP_IN_OP_LEN 4
6878/* enum: Return to factory default settings */
6879#define MC_CMD_CLP_OP_DEFAULT 0x1
6880/* enum: Set MAC address */
6881#define MC_CMD_CLP_OP_SET_MAC 0x2
6882/* enum: Get MAC address */
6883#define MC_CMD_CLP_OP_GET_MAC 0x3
6884/* enum: Set UEFI/GPXE boot mode */
6885#define MC_CMD_CLP_OP_SET_BOOT 0x4
6886/* enum: Get UEFI/GPXE boot mode */
6887#define MC_CMD_CLP_OP_GET_BOOT 0x5
6888
6889/* MC_CMD_CLP_OUT msgresponse */
6890#define MC_CMD_CLP_OUT_LEN 0
6891
6892/* MC_CMD_CLP_IN_DEFAULT msgrequest */
6893#define MC_CMD_CLP_IN_DEFAULT_LEN 4
6894/* MC_CMD_CLP_IN_OP_OFST 0 */
6895/* MC_CMD_CLP_IN_OP_LEN 4 */
6896
6897/* MC_CMD_CLP_OUT_DEFAULT msgresponse */
6898#define MC_CMD_CLP_OUT_DEFAULT_LEN 0
6899
6900/* MC_CMD_CLP_IN_SET_MAC msgrequest */
6901#define MC_CMD_CLP_IN_SET_MAC_LEN 12
6902/* MC_CMD_CLP_IN_OP_OFST 0 */
6903/* MC_CMD_CLP_IN_OP_LEN 4 */
6904/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00
6905 * restores the permanent (factory-programmed) MAC address associated with the
6906 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
6907 */
6908#define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
6909#define MC_CMD_CLP_IN_SET_MAC_ADDR_LEN 6
6910/* Padding */
6911#define MC_CMD_CLP_IN_SET_MAC_RESERVED_OFST 10
6912#define MC_CMD_CLP_IN_SET_MAC_RESERVED_LEN 2
6913
6914/* MC_CMD_CLP_OUT_SET_MAC msgresponse */
6915#define MC_CMD_CLP_OUT_SET_MAC_LEN 0
6916
6917/* MC_CMD_CLP_IN_SET_MAC_V2 msgrequest */
6918#define MC_CMD_CLP_IN_SET_MAC_V2_LEN 16
6919/* MC_CMD_CLP_IN_OP_OFST 0 */
6920/* MC_CMD_CLP_IN_OP_LEN 4 */
6921/* The MAC address assigned to port. A zero MAC address of 00:00:00:00:00:00
6922 * restores the permanent (factory-programmed) MAC address associated with the
6923 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
6924 */
6925#define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 4
6926#define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_LEN 6
6927/* Padding */
6928#define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_OFST 10
6929#define MC_CMD_CLP_IN_SET_MAC_V2_RESERVED_LEN 2
6930#define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_OFST 12
6931#define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4
6932#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_OFST 12
6933#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 0
6934#define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_WIDTH 1
6935
6936/* MC_CMD_CLP_IN_GET_MAC msgrequest */
6937#define MC_CMD_CLP_IN_GET_MAC_LEN 4
6938/* MC_CMD_CLP_IN_OP_OFST 0 */
6939/* MC_CMD_CLP_IN_OP_LEN 4 */
6940
6941/* MC_CMD_CLP_IN_GET_MAC_V2 msgrequest */
6942#define MC_CMD_CLP_IN_GET_MAC_V2_LEN 8
6943/* MC_CMD_CLP_IN_OP_OFST 0 */
6944/* MC_CMD_CLP_IN_OP_LEN 4 */
6945#define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 4
6946#define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 4
6947#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 4
6948#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 0
6949#define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_WIDTH 1
6950
6951/* MC_CMD_CLP_OUT_GET_MAC msgresponse */
6952#define MC_CMD_CLP_OUT_GET_MAC_LEN 8
6953/* MAC address assigned to port */
6954#define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
6955#define MC_CMD_CLP_OUT_GET_MAC_ADDR_LEN 6
6956/* Padding */
6957#define MC_CMD_CLP_OUT_GET_MAC_RESERVED_OFST 6
6958#define MC_CMD_CLP_OUT_GET_MAC_RESERVED_LEN 2
6959
6960/* MC_CMD_CLP_IN_SET_BOOT msgrequest */
6961#define MC_CMD_CLP_IN_SET_BOOT_LEN 5
6962/* MC_CMD_CLP_IN_OP_OFST 0 */
6963/* MC_CMD_CLP_IN_OP_LEN 4 */
6964/* Boot flag */
6965#define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
6966#define MC_CMD_CLP_IN_SET_BOOT_FLAG_LEN 1
6967
6968/* MC_CMD_CLP_OUT_SET_BOOT msgresponse */
6969#define MC_CMD_CLP_OUT_SET_BOOT_LEN 0
6970
6971/* MC_CMD_CLP_IN_GET_BOOT msgrequest */
6972#define MC_CMD_CLP_IN_GET_BOOT_LEN 4
6973/* MC_CMD_CLP_IN_OP_OFST 0 */
6974/* MC_CMD_CLP_IN_OP_LEN 4 */
6975
6976/* MC_CMD_CLP_OUT_GET_BOOT msgresponse */
6977#define MC_CMD_CLP_OUT_GET_BOOT_LEN 4
6978/* Boot flag */
6979#define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
6980#define MC_CMD_CLP_OUT_GET_BOOT_FLAG_LEN 1
6981/* Padding */
6982#define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1
6983#define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3
6984
6985
6986/***********************************/
6987/* MC_CMD_MUM
6988 * Perform a MUM operation
6989 */
6990#define MC_CMD_MUM 0x57
6991#undef MC_CMD_0x57_PRIVILEGE_CTG
6992
6993#define MC_CMD_0x57_PRIVILEGE_CTG SRIOV_CTG_INSECURE
6994
6995/* MC_CMD_MUM_IN msgrequest */
6996#define MC_CMD_MUM_IN_LEN 4
6997#define MC_CMD_MUM_IN_OP_HDR_OFST 0
6998#define MC_CMD_MUM_IN_OP_HDR_LEN 4
6999#define MC_CMD_MUM_IN_OP_OFST 0
7000#define MC_CMD_MUM_IN_OP_LBN 0
7001#define MC_CMD_MUM_IN_OP_WIDTH 8
7002/* enum: NULL MCDI command to MUM */
7003#define MC_CMD_MUM_OP_NULL 0x1
7004/* enum: Get MUM version */
7005#define MC_CMD_MUM_OP_GET_VERSION 0x2
7006/* enum: Issue raw I2C command to MUM */
7007#define MC_CMD_MUM_OP_RAW_CMD 0x3
7008/* enum: Read from registers on devices connected to MUM. */
7009#define MC_CMD_MUM_OP_READ 0x4
7010/* enum: Write to registers on devices connected to MUM. */
7011#define MC_CMD_MUM_OP_WRITE 0x5
7012/* enum: Control UART logging. */
7013#define MC_CMD_MUM_OP_LOG 0x6
7014/* enum: Operations on MUM GPIO lines */
7015#define MC_CMD_MUM_OP_GPIO 0x7
7016/* enum: Get sensor readings from MUM */
7017#define MC_CMD_MUM_OP_READ_SENSORS 0x8
7018/* enum: Initiate clock programming on the MUM */
7019#define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9
7020/* enum: Initiate FPGA load from flash on the MUM */
7021#define MC_CMD_MUM_OP_FPGA_LOAD 0xa
7022/* enum: Request sensor reading from MUM ADC resulting from earlier request via
7023 * MUM ATB
7024 */
7025#define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb
7026/* enum: Send commands relating to the QSFP ports via the MUM for PHY
7027 * operations
7028 */
7029#define MC_CMD_MUM_OP_QSFP 0xc
7030/* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage
7031 * level) from MUM
7032 */
7033#define MC_CMD_MUM_OP_READ_DDR_INFO 0xd
7034
7035/* MC_CMD_MUM_IN_NULL msgrequest */
7036#define MC_CMD_MUM_IN_NULL_LEN 4
7037/* MUM cmd header */
7038#define MC_CMD_MUM_IN_CMD_OFST 0
7039#define MC_CMD_MUM_IN_CMD_LEN 4
7040
7041/* MC_CMD_MUM_IN_GET_VERSION msgrequest */
7042#define MC_CMD_MUM_IN_GET_VERSION_LEN 4
7043/* MUM cmd header */
7044/* MC_CMD_MUM_IN_CMD_OFST 0 */
7045/* MC_CMD_MUM_IN_CMD_LEN 4 */
7046
7047/* MC_CMD_MUM_IN_READ msgrequest */
7048#define MC_CMD_MUM_IN_READ_LEN 16
7049/* MUM cmd header */
7050/* MC_CMD_MUM_IN_CMD_OFST 0 */
7051/* MC_CMD_MUM_IN_CMD_LEN 4 */
7052/* ID of (device connected to MUM) to read from registers of */
7053#define MC_CMD_MUM_IN_READ_DEVICE_OFST 4
7054#define MC_CMD_MUM_IN_READ_DEVICE_LEN 4
7055/* enum: Hittite HMC1035 clock generator on Sorrento board */
7056#define MC_CMD_MUM_DEV_HITTITE 0x1
7057/* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
7058#define MC_CMD_MUM_DEV_HITTITE_NIC 0x2
7059/* 32-bit address to read from */
7060#define MC_CMD_MUM_IN_READ_ADDR_OFST 8
7061#define MC_CMD_MUM_IN_READ_ADDR_LEN 4
7062/* Number of words to read. */
7063#define MC_CMD_MUM_IN_READ_NUMWORDS_OFST 12
7064#define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4
7065
7066/* MC_CMD_MUM_IN_WRITE msgrequest */
7067#define MC_CMD_MUM_IN_WRITE_LENMIN 16
7068#define MC_CMD_MUM_IN_WRITE_LENMAX 252
7069#define MC_CMD_MUM_IN_WRITE_LENMAX_MCDI2 1020
7070#define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
7071#define MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4)
7072/* MUM cmd header */
7073/* MC_CMD_MUM_IN_CMD_OFST 0 */
7074/* MC_CMD_MUM_IN_CMD_LEN 4 */
7075/* ID of (device connected to MUM) to write to registers of */
7076#define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4
7077#define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4
7078/* enum: Hittite HMC1035 clock generator on Sorrento board */
7079/* MC_CMD_MUM_DEV_HITTITE 0x1 */
7080/* 32-bit address to write to */
7081#define MC_CMD_MUM_IN_WRITE_ADDR_OFST 8
7082#define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4
7083/* Words to write */
7084#define MC_CMD_MUM_IN_WRITE_BUFFER_OFST 12
7085#define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
7086#define MC_CMD_MUM_IN_WRITE_BUFFER_MINNUM 1
7087#define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM 60
7088#define MC_CMD_MUM_IN_WRITE_BUFFER_MAXNUM_MCDI2 252
7089
7090/* MC_CMD_MUM_IN_RAW_CMD msgrequest */
7091#define MC_CMD_MUM_IN_RAW_CMD_LENMIN 17
7092#define MC_CMD_MUM_IN_RAW_CMD_LENMAX 252
7093#define MC_CMD_MUM_IN_RAW_CMD_LENMAX_MCDI2 1020
7094#define MC_CMD_MUM_IN_RAW_CMD_LEN(num) (16+1*(num))
7095#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1)
7096/* MUM cmd header */
7097/* MC_CMD_MUM_IN_CMD_OFST 0 */
7098/* MC_CMD_MUM_IN_CMD_LEN 4 */
7099/* MUM I2C cmd code */
7100#define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4
7101#define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4
7102/* Number of bytes to write */
7103#define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_OFST 8
7104#define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4
7105/* Number of bytes to read */
7106#define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_OFST 12
7107#define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4
7108/* Bytes to write */
7109#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_OFST 16
7110#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_LEN 1
7111#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MINNUM 1
7112#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM 236
7113#define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_MAXNUM_MCDI2 1004
7114
7115/* MC_CMD_MUM_IN_LOG msgrequest */
7116#define MC_CMD_MUM_IN_LOG_LEN 8
7117/* MUM cmd header */
7118/* MC_CMD_MUM_IN_CMD_OFST 0 */
7119/* MC_CMD_MUM_IN_CMD_LEN 4 */
7120#define MC_CMD_MUM_IN_LOG_OP_OFST 4
7121#define MC_CMD_MUM_IN_LOG_OP_LEN 4
7122#define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
7123
7124/* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */
7125#define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12
7126/* MC_CMD_MUM_IN_CMD_OFST 0 */
7127/* MC_CMD_MUM_IN_CMD_LEN 4 */
7128/* MC_CMD_MUM_IN_LOG_OP_OFST 4 */
7129/* MC_CMD_MUM_IN_LOG_OP_LEN 4 */
7130/* Enable/disable debug output to UART */
7131#define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_OFST 8
7132#define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4
7133
7134/* MC_CMD_MUM_IN_GPIO msgrequest */
7135#define MC_CMD_MUM_IN_GPIO_LEN 8
7136/* MUM cmd header */
7137/* MC_CMD_MUM_IN_CMD_OFST 0 */
7138/* MC_CMD_MUM_IN_CMD_LEN 4 */
7139#define MC_CMD_MUM_IN_GPIO_HDR_OFST 4
7140#define MC_CMD_MUM_IN_GPIO_HDR_LEN 4
7141#define MC_CMD_MUM_IN_GPIO_OPCODE_OFST 4
7142#define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
7143#define MC_CMD_MUM_IN_GPIO_OPCODE_WIDTH 8
7144#define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
7145#define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
7146#define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
7147#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
7148#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
7149#define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */
7150
7151/* MC_CMD_MUM_IN_GPIO_IN_READ msgrequest */
7152#define MC_CMD_MUM_IN_GPIO_IN_READ_LEN 8
7153/* MC_CMD_MUM_IN_CMD_OFST 0 */
7154/* MC_CMD_MUM_IN_CMD_LEN 4 */
7155#define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4
7156#define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4
7157
7158/* MC_CMD_MUM_IN_GPIO_OUT_WRITE msgrequest */
7159#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_LEN 16
7160/* MC_CMD_MUM_IN_CMD_OFST 0 */
7161/* MC_CMD_MUM_IN_CMD_LEN 4 */
7162#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4
7163#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4
7164/* The first 32-bit word to be written to the GPIO OUT register. */
7165#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_OFST 8
7166#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4
7167/* The second 32-bit word to be written to the GPIO OUT register. */
7168#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_OFST 12
7169#define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4
7170
7171/* MC_CMD_MUM_IN_GPIO_OUT_READ msgrequest */
7172#define MC_CMD_MUM_IN_GPIO_OUT_READ_LEN 8
7173/* MC_CMD_MUM_IN_CMD_OFST 0 */
7174/* MC_CMD_MUM_IN_CMD_LEN 4 */
7175#define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4
7176#define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4
7177
7178/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE msgrequest */
7179#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_LEN 16
7180/* MC_CMD_MUM_IN_CMD_OFST 0 */
7181/* MC_CMD_MUM_IN_CMD_LEN 4 */
7182#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4
7183#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4
7184/* The first 32-bit word to be written to the GPIO OUT ENABLE register. */
7185#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_OFST 8
7186#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4
7187/* The second 32-bit word to be written to the GPIO OUT ENABLE register. */
7188#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_OFST 12
7189#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4
7190
7191/* MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ msgrequest */
7192#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_LEN 8
7193/* MC_CMD_MUM_IN_CMD_OFST 0 */
7194/* MC_CMD_MUM_IN_CMD_LEN 4 */
7195#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4
7196#define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4
7197
7198/* MC_CMD_MUM_IN_GPIO_OP msgrequest */
7199#define MC_CMD_MUM_IN_GPIO_OP_LEN 8
7200/* MC_CMD_MUM_IN_CMD_OFST 0 */
7201/* MC_CMD_MUM_IN_CMD_LEN 4 */
7202#define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
7203#define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4
7204#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 4
7205#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_LBN 8
7206#define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_WIDTH 8
7207#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
7208#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
7209#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
7210#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
7211#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 4
7212#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_LBN 16
7213#define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_WIDTH 8
7214
7215/* MC_CMD_MUM_IN_GPIO_OP_OUT_READ msgrequest */
7216#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_LEN 8
7217/* MC_CMD_MUM_IN_CMD_OFST 0 */
7218/* MC_CMD_MUM_IN_CMD_LEN 4 */
7219#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4
7220#define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4
7221
7222/* MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE msgrequest */
7223#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_LEN 8
7224/* MC_CMD_MUM_IN_CMD_OFST 0 */
7225/* MC_CMD_MUM_IN_CMD_LEN 4 */
7226#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
7227#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4
7228#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 4
7229#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_LBN 24
7230#define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_WIDTH 8
7231
7232/* MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG msgrequest */
7233#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_LEN 8
7234/* MC_CMD_MUM_IN_CMD_OFST 0 */
7235/* MC_CMD_MUM_IN_CMD_LEN 4 */
7236#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
7237#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4
7238#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 4
7239#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_LBN 24
7240#define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_WIDTH 8
7241
7242/* MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE msgrequest */
7243#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_LEN 8
7244/* MC_CMD_MUM_IN_CMD_OFST 0 */
7245/* MC_CMD_MUM_IN_CMD_LEN 4 */
7246#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
7247#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4
7248#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 4
7249#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_LBN 24
7250#define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_WIDTH 8
7251
7252/* MC_CMD_MUM_IN_READ_SENSORS msgrequest */
7253#define MC_CMD_MUM_IN_READ_SENSORS_LEN 8
7254/* MUM cmd header */
7255/* MC_CMD_MUM_IN_CMD_OFST 0 */
7256/* MC_CMD_MUM_IN_CMD_LEN 4 */
7257#define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
7258#define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4
7259#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 4
7260#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
7261#define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_WIDTH 8
7262#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 4
7263#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_LBN 8
7264#define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_WIDTH 8
7265
7266/* MC_CMD_MUM_IN_PROGRAM_CLOCKS msgrequest */
7267#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_LEN 12
7268/* MUM cmd header */
7269/* MC_CMD_MUM_IN_CMD_OFST 0 */
7270/* MC_CMD_MUM_IN_CMD_LEN 4 */
7271/* Bit-mask of clocks to be programmed */
7272#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4
7273#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4
7274#define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
7275#define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
7276#define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
7277/* Control flags for clock programming */
7278#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8
7279#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4
7280#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_OFST 8
7281#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
7282#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1
7283#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_OFST 8
7284#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1
7285#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1
7286#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_OFST 8
7287#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2
7288#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1
7289
7290/* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */
7291#define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8
7292/* MUM cmd header */
7293/* MC_CMD_MUM_IN_CMD_OFST 0 */
7294/* MC_CMD_MUM_IN_CMD_LEN 4 */
7295/* Enable/Disable FPGA config from flash */
7296#define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4
7297#define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4
7298
7299/* MC_CMD_MUM_IN_READ_ATB_SENSOR msgrequest */
7300#define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4
7301/* MUM cmd header */
7302/* MC_CMD_MUM_IN_CMD_OFST 0 */
7303/* MC_CMD_MUM_IN_CMD_LEN 4 */
7304
7305/* MC_CMD_MUM_IN_QSFP msgrequest */
7306#define MC_CMD_MUM_IN_QSFP_LEN 12
7307/* MUM cmd header */
7308/* MC_CMD_MUM_IN_CMD_OFST 0 */
7309/* MC_CMD_MUM_IN_CMD_LEN 4 */
7310#define MC_CMD_MUM_IN_QSFP_HDR_OFST 4
7311#define MC_CMD_MUM_IN_QSFP_HDR_LEN 4
7312#define MC_CMD_MUM_IN_QSFP_OPCODE_OFST 4
7313#define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
7314#define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
7315#define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
7316#define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
7317#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
7318#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
7319#define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
7320#define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
7321#define MC_CMD_MUM_IN_QSFP_IDX_OFST 8
7322#define MC_CMD_MUM_IN_QSFP_IDX_LEN 4
7323
7324/* MC_CMD_MUM_IN_QSFP_INIT msgrequest */
7325#define MC_CMD_MUM_IN_QSFP_INIT_LEN 16
7326/* MC_CMD_MUM_IN_CMD_OFST 0 */
7327/* MC_CMD_MUM_IN_CMD_LEN 4 */
7328#define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4
7329#define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4
7330#define MC_CMD_MUM_IN_QSFP_INIT_IDX_OFST 8
7331#define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4
7332#define MC_CMD_MUM_IN_QSFP_INIT_CAGE_OFST 12
7333#define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4
7334
7335/* MC_CMD_MUM_IN_QSFP_RECONFIGURE msgrequest */
7336#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_LEN 24
7337/* MC_CMD_MUM_IN_CMD_OFST 0 */
7338/* MC_CMD_MUM_IN_CMD_LEN 4 */
7339#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4
7340#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4
7341#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_OFST 8
7342#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4
7343#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_OFST 12
7344#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4
7345#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_OFST 16
7346#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4
7347#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_OFST 20
7348#define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4
7349
7350/* MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP msgrequest */
7351#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_LEN 12
7352/* MC_CMD_MUM_IN_CMD_OFST 0 */
7353/* MC_CMD_MUM_IN_CMD_LEN 4 */
7354#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4
7355#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4
7356#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_OFST 8
7357#define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4
7358
7359/* MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO msgrequest */
7360#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_LEN 16
7361/* MC_CMD_MUM_IN_CMD_OFST 0 */
7362/* MC_CMD_MUM_IN_CMD_LEN 4 */
7363#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4
7364#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4
7365#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_OFST 8
7366#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4
7367#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_OFST 12
7368#define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4
7369
7370/* MC_CMD_MUM_IN_QSFP_FILL_STATS msgrequest */
7371#define MC_CMD_MUM_IN_QSFP_FILL_STATS_LEN 12
7372/* MC_CMD_MUM_IN_CMD_OFST 0 */
7373/* MC_CMD_MUM_IN_CMD_LEN 4 */
7374#define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4
7375#define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4
7376#define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_OFST 8
7377#define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4
7378
7379/* MC_CMD_MUM_IN_QSFP_POLL_BIST msgrequest */
7380#define MC_CMD_MUM_IN_QSFP_POLL_BIST_LEN 12
7381/* MC_CMD_MUM_IN_CMD_OFST 0 */
7382/* MC_CMD_MUM_IN_CMD_LEN 4 */
7383#define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4
7384#define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4
7385#define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8
7386#define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4
7387
7388/* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */
7389#define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4
7390/* MUM cmd header */
7391/* MC_CMD_MUM_IN_CMD_OFST 0 */
7392/* MC_CMD_MUM_IN_CMD_LEN 4 */
7393
7394/* MC_CMD_MUM_OUT msgresponse */
7395#define MC_CMD_MUM_OUT_LEN 0
7396
7397/* MC_CMD_MUM_OUT_NULL msgresponse */
7398#define MC_CMD_MUM_OUT_NULL_LEN 0
7399
7400/* MC_CMD_MUM_OUT_GET_VERSION msgresponse */
7401#define MC_CMD_MUM_OUT_GET_VERSION_LEN 12
7402#define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0
7403#define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4
7404#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
7405#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LEN 8
7406#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
7407#define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_OFST 8
7408
7409/* MC_CMD_MUM_OUT_RAW_CMD msgresponse */
7410#define MC_CMD_MUM_OUT_RAW_CMD_LENMIN 1
7411#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX 252
7412#define MC_CMD_MUM_OUT_RAW_CMD_LENMAX_MCDI2 1020
7413#define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
7414#define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)
7415/* returned data */
7416#define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
7417#define MC_CMD_MUM_OUT_RAW_CMD_DATA_LEN 1
7418#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MINNUM 1
7419#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM 252
7420#define MC_CMD_MUM_OUT_RAW_CMD_DATA_MAXNUM_MCDI2 1020
7421
7422/* MC_CMD_MUM_OUT_READ msgresponse */
7423#define MC_CMD_MUM_OUT_READ_LENMIN 4
7424#define MC_CMD_MUM_OUT_READ_LENMAX 252
7425#define MC_CMD_MUM_OUT_READ_LENMAX_MCDI2 1020
7426#define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
7427#define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)
7428#define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
7429#define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
7430#define MC_CMD_MUM_OUT_READ_BUFFER_MINNUM 1
7431#define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM 63
7432#define MC_CMD_MUM_OUT_READ_BUFFER_MAXNUM_MCDI2 255
7433
7434/* MC_CMD_MUM_OUT_WRITE msgresponse */
7435#define MC_CMD_MUM_OUT_WRITE_LEN 0
7436
7437/* MC_CMD_MUM_OUT_LOG msgresponse */
7438#define MC_CMD_MUM_OUT_LOG_LEN 0
7439
7440/* MC_CMD_MUM_OUT_LOG_OP_UART msgresponse */
7441#define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0
7442
7443/* MC_CMD_MUM_OUT_GPIO_IN_READ msgresponse */
7444#define MC_CMD_MUM_OUT_GPIO_IN_READ_LEN 8
7445/* The first 32-bit word read from the GPIO IN register. */
7446#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0
7447#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4
7448/* The second 32-bit word read from the GPIO IN register. */
7449#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4
7450#define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4
7451
7452/* MC_CMD_MUM_OUT_GPIO_OUT_WRITE msgresponse */
7453#define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0
7454
7455/* MC_CMD_MUM_OUT_GPIO_OUT_READ msgresponse */
7456#define MC_CMD_MUM_OUT_GPIO_OUT_READ_LEN 8
7457/* The first 32-bit word read from the GPIO OUT register. */
7458#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0
7459#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4
7460/* The second 32-bit word read from the GPIO OUT register. */
7461#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4
7462#define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4
7463
7464/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE msgresponse */
7465#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0
7466
7467/* MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ msgresponse */
7468#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_LEN 8
7469#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0
7470#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4
7471#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4
7472#define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4
7473
7474/* MC_CMD_MUM_OUT_GPIO_OP_OUT_READ msgresponse */
7475#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4
7476#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0
7477#define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4
7478
7479/* MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE msgresponse */
7480#define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0
7481
7482/* MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG msgresponse */
7483#define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0
7484
7485/* MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE msgresponse */
7486#define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0
7487
7488/* MC_CMD_MUM_OUT_READ_SENSORS msgresponse */
7489#define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
7490#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX 252
7491#define MC_CMD_MUM_OUT_READ_SENSORS_LENMAX_MCDI2 1020
7492#define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
7493#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)
7494#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
7495#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
7496#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MINNUM 1
7497#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM 63
7498#define MC_CMD_MUM_OUT_READ_SENSORS_DATA_MAXNUM_MCDI2 255
7499#define MC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 0
7500#define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
7501#define MC_CMD_MUM_OUT_READ_SENSORS_READING_WIDTH 16
7502#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 0
7503#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_LBN 16
7504#define MC_CMD_MUM_OUT_READ_SENSORS_STATE_WIDTH 8
7505#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 0
7506#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_LBN 24
7507#define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_WIDTH 8
7508
7509/* MC_CMD_MUM_OUT_PROGRAM_CLOCKS msgresponse */
7510#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4
7511#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0
7512#define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4
7513
7514/* MC_CMD_MUM_OUT_FPGA_LOAD msgresponse */
7515#define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0
7516
7517/* MC_CMD_MUM_OUT_READ_ATB_SENSOR msgresponse */
7518#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4
7519#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0
7520#define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4
7521
7522/* MC_CMD_MUM_OUT_QSFP_INIT msgresponse */
7523#define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0
7524
7525/* MC_CMD_MUM_OUT_QSFP_RECONFIGURE msgresponse */
7526#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_LEN 8
7527#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0
7528#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4
7529#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
7530#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4
7531#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 4
7532#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
7533#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_WIDTH 1
7534#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 4
7535#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_LBN 1
7536#define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_WIDTH 1
7537
7538/* MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP msgresponse */
7539#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4
7540#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0
7541#define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4
7542
7543/* MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO msgresponse */
7544#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMIN 5
7545#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX 252
7546#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LENMAX_MCDI2 1020
7547#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
7548#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)
7549/* in bytes */
7550#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
7551#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
7552#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4
7553#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_LEN 1
7554#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MINNUM 1
7555#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM 248
7556#define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016
7557
7558/* MC_CMD_MUM_OUT_QSFP_FILL_STATS msgresponse */
7559#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_LEN 8
7560#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0
7561#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4
7562#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4
7563#define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4
7564
7565/* MC_CMD_MUM_OUT_QSFP_POLL_BIST msgresponse */
7566#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4
7567#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0
7568#define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4
7569
7570/* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */
7571#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24
7572#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248
7573#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX_MCDI2 1016
7574#define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num))
7575#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8)
7576/* Discrete (soldered) DDR resistor strap info */
7577#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
7578#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
7579#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 0
7580#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
7581#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16
7582#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 0
7583#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16
7584#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16
7585/* Number of SODIMM info records */
7586#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4
7587#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4
7588/* Array of SODIMM info records */
7589#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8
7590#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8
7591#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8
7592#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12
7593#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2
7594#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30
7595#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM_MCDI2 126
7596#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_OFST 8
7597#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
7598#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8
7599/* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */
7600#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0
7601/* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */
7602#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
7603/* enum: Total number of SODIMM banks */
7604#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
7605#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_OFST 8
7606#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8
7607#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8
7608#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_OFST 8
7609#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16
7610#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
7611#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_OFST 8
7612#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20
7613#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
7614#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
7615#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
7616#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
7617#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
7618/* enum: Values 5-15 are reserved for future usage */
7619#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
7620#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_OFST 8
7621#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24
7622#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8
7623#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_OFST 8
7624#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32
7625#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16
7626#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_OFST 8
7627#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48
7628#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
7629/* enum: No module present */
7630#define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0
7631/* enum: Module present supported and powered on */
7632#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1
7633/* enum: Module present but bad type */
7634#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2
7635/* enum: Module present but incompatible voltage */
7636#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3
7637/* enum: Module present but unknown SPD */
7638#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4
7639/* enum: Module present but slot cannot support it */
7640#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5
7641/* enum: Modules may or may not be present, but cannot establish contact by I2C
7642 */
7643#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
7644#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_OFST 8
7645#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52
7646#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12
7647
7648/* MC_CMD_DYNAMIC_SENSORS_LIMITS structuredef: Set of sensor limits. This
7649 * should match the equivalent structure in the sensor_query SPHINX service.
7650 */
7651#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LEN 24
7652/* A value below this will trigger a warning event. */
7653#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0
7654#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4
7655#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0
7656#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_WIDTH 32
7657/* A value below this will trigger a critical event. */
7658#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4
7659#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4
7660#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LBN 32
7661#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_WIDTH 32
7662/* A value below this will shut down the card. */
7663#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_OFST 8
7664#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4
7665#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LBN 64
7666#define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_WIDTH 32
7667/* A value above this will trigger a warning event. */
7668#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_OFST 12
7669#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4
7670#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LBN 96
7671#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_WIDTH 32
7672/* A value above this will trigger a critical event. */
7673#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_OFST 16
7674#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4
7675#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LBN 128
7676#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_WIDTH 32
7677/* A value above this will shut down the card. */
7678#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_OFST 20
7679#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4
7680#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LBN 160
7681#define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_WIDTH 32
7682
7683/* MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structuredef: Description of a sensor.
7684 * This should match the equivalent structure in the sensor_query SPHINX
7685 * service.
7686 */
7687#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LEN 64
7688/* The handle used to identify the sensor in calls to
7689 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES
7690 */
7691#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0
7692#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4
7693#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0
7694#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_WIDTH 32
7695/* A human-readable name for the sensor (zero terminated string, max 32 bytes)
7696 */
7697#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4
7698#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LEN 32
7699#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_LBN 32
7700#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_WIDTH 256
7701/* The type of the sensor device, and by implication the unit of that the
7702 * values will be reported in
7703 */
7704#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_OFST 36
7705#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4
7706/* enum: A voltage sensor. Unit is mV */
7707#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0
7708/* enum: A current sensor. Unit is mA */
7709#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1
7710/* enum: A power sensor. Unit is mW */
7711#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2
7712/* enum: A temperature sensor. Unit is Celsius */
7713#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3
7714/* enum: A cooling fan sensor. Unit is RPM */
7715#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4
7716#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LBN 288
7717#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_WIDTH 32
7718/* A single MC_CMD_DYNAMIC_SENSORS_LIMITS structure */
7719#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_OFST 40
7720#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LEN 24
7721#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_LBN 320
7722#define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_LIMITS_WIDTH 192
7723
7724/* MC_CMD_DYNAMIC_SENSORS_READING structuredef: State and value of a sensor.
7725 * This should match the equivalent structure in the sensor_query SPHINX
7726 * service.
7727 */
7728#define MC_CMD_DYNAMIC_SENSORS_READING_LEN 12
7729/* The handle used to identify the sensor */
7730#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0
7731#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4
7732#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0
7733#define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_WIDTH 32
7734/* The current value of the sensor */
7735#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4
7736#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4
7737#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LBN 32
7738#define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_WIDTH 32
7739/* The sensor's condition, e.g. good, broken or removed */
7740#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_OFST 8
7741#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4
7742/* enum: Sensor working normally within limits */
7743#define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0
7744/* enum: Warning threshold breached */
7745#define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1
7746/* enum: Critical threshold breached */
7747#define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2
7748/* enum: Fatal threshold breached */
7749#define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3
7750/* enum: Sensor not working */
7751#define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4
7752/* enum: Sensor working but no reading available */
7753#define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5
7754/* enum: Sensor initialization failed */
7755#define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6
7756#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LBN 64
7757#define MC_CMD_DYNAMIC_SENSORS_READING_STATE_WIDTH 32
7758
7759
7760/***********************************/
7761/* MC_CMD_DYNAMIC_SENSORS_LIST
7762 * Return a complete list of handles for sensors currently managed by the MC,
7763 * and a generation count for this version of the sensor table. On systems
7764 * advertising the DYNAMIC_SENSORS capability bit, this replaces the
7765 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors
7766 * added by the NMC.
7767 *
7768 * Sensor handles are persistent for the lifetime of the sensor and are used to
7769 * identify sensors in MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS and
7770 * MC_CMD_DYNAMIC_SENSORS_GET_VALUES.
7771 *
7772 * The generation count is maintained by the MC, is persistent across reboots
7773 * and will be incremented each time the sensor table is modified. When the
7774 * table is modified, a CODE_DYNAMIC_SENSORS_CHANGE event will be generated
7775 * containing the new generation count. The driver should compare this against
7776 * the current generation count, and if it is different, call
7777 * MC_CMD_DYNAMIC_SENSORS_LIST again to update it's copy of the sensor table.
7778 *
7779 * The sensor count is provided to allow a future path to supporting more than
7780 * MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 sensors, i.e.
7781 * the maximum number that will fit in a single response. As this is a fairly
7782 * large number (253) it is not anticipated that this will be needed in the
7783 * near future, so can currently be ignored.
7784 *
7785 * On Riverhead this command is implemented as a wrapper for `list` in the
7786 * sensor_query SPHINX service.
7787 */
7788#define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
7789#undef MC_CMD_0x66_PRIVILEGE_CTG
7790
7791#define MC_CMD_0x66_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7792
7793/* MC_CMD_DYNAMIC_SENSORS_LIST_IN msgrequest */
7794#define MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 0
7795
7796/* MC_CMD_DYNAMIC_SENSORS_LIST_OUT msgresponse */
7797#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMIN 8
7798#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX 252
7799#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LENMAX_MCDI2 1020
7800#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))
7801#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)
7802/* Generation count, which will be updated each time a sensor is added to or
7803 * removed from the MC sensor table.
7804 */
7805#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0
7806#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4
7807/* Number of sensors managed by the MC. Note that in principle, this can be
7808 * larger than the size of the HANDLES array.
7809 */
7810#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4
7811#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4
7812/* Array of sensor handles */
7813#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_OFST 8
7814#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4
7815#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0
7816#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM 61
7817#define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MAXNUM_MCDI2 253
7818
7819
7820/***********************************/
7821/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS
7822 * Get descriptions for a set of sensors, specified as an array of sensor
7823 * handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST
7824 *
7825 * Any handles which do not correspond to a sensor currently managed by the MC
7826 * will be dropped from from the response. This may happen when a sensor table
7827 * update is in progress, and effectively means the set of usable sensors is
7828 * the intersection between the sets of sensors known to the driver and the MC.
7829 *
7830 * On Riverhead this command is implemented as a wrapper for
7831 * `get_descriptions` in the sensor_query SPHINX service.
7832 */
7833#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
7834#undef MC_CMD_0x67_PRIVILEGE_CTG
7835
7836#define MC_CMD_0x67_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7837
7838/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN msgrequest */
7839#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 0
7840#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX 252
7841#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMAX_MCDI2 1020
7842#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
7843#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
7844/* Array of sensor handles */
7845#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 0
7846#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4
7847#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 0
7848#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM 63
7849#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MAXNUM_MCDI2 255
7850
7851/* MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT msgresponse */
7852#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 0
7853#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX 192
7854#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMAX_MCDI2 960
7855#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))
7856#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
7857/* Array of MC_CMD_DYNAMIC_SENSORS_DESCRIPTION structures */
7858#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 0
7859#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_LEN 64
7860#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 0
7861#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM 3
7862#define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MAXNUM_MCDI2 15
7863
7864
7865/***********************************/
7866/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS
7867 * Read the state and value for a set of sensors, specified as an array of
7868 * sensor handles as returned by MC_CMD_DYNAMIC_SENSORS_LIST.
7869 *
7870 * In the case of a broken sensor, then the state of the response's
7871 * MC_CMD_DYNAMIC_SENSORS_VALUE entry will be set to BROKEN, and any value
7872 * provided should be treated as erroneous.
7873 *
7874 * Any handles which do not correspond to a sensor currently managed by the MC
7875 * will be dropped from from the response. This may happen when a sensor table
7876 * update is in progress, and effectively means the set of usable sensors is
7877 * the intersection between the sets of sensors known to the driver and the MC.
7878 *
7879 * On Riverhead this command is implemented as a wrapper for `get_readings`
7880 * in the sensor_query SPHINX service.
7881 */
7882#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
7883#undef MC_CMD_0x68_PRIVILEGE_CTG
7884
7885#define MC_CMD_0x68_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7886
7887/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN msgrequest */
7888#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 0
7889#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX 252
7890#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMAX_MCDI2 1020
7891#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
7892#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
7893/* Array of sensor handles */
7894#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 0
7895#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4
7896#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 0
7897#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM 63
7898#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MAXNUM_MCDI2 255
7899
7900/* MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT msgresponse */
7901#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 0
7902#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX 252
7903#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMAX_MCDI2 1020
7904#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))
7905#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
7906/* Array of MC_CMD_DYNAMIC_SENSORS_READING structures */
7907#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 0
7908#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_LEN 12
7909#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 0
7910#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM 21
7911#define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MAXNUM_MCDI2 85
7912
7913
7914/***********************************/
7915/* MC_CMD_EVENT_CTRL
7916 * Configure which categories of unsolicited events the driver expects to
7917 * receive (Riverhead).
7918 */
7919#define MC_CMD_EVENT_CTRL 0x69
7920#undef MC_CMD_0x69_PRIVILEGE_CTG
7921
7922#define MC_CMD_0x69_PRIVILEGE_CTG SRIOV_CTG_GENERAL
7923
7924/* MC_CMD_EVENT_CTRL_IN msgrequest */
7925#define MC_CMD_EVENT_CTRL_IN_LENMIN 0
7926#define MC_CMD_EVENT_CTRL_IN_LENMAX 252
7927#define MC_CMD_EVENT_CTRL_IN_LENMAX_MCDI2 1020
7928#define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))
7929#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)
7930/* Array of event categories for which the driver wishes to receive events. */
7931#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 0
7932#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 4
7933#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 0
7934#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM 63
7935#define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MAXNUM_MCDI2 255
7936/* enum: Driver wishes to receive LINKCHANGE events. */
7937#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x0
7938/* enum: Driver wishes to receive SENSOR_CHANGE and SENSOR_STATE_CHANGE events.
7939 */
7940#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x1
7941/* enum: Driver wishes to receive receive errors. */
7942#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x2
7943/* enum: Driver wishes to receive transmit errors. */
7944#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x3
7945/* enum: Driver wishes to receive firmware alerts. */
7946#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x4
7947/* enum: Driver wishes to receive reboot events. */
7948#define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x5
7949
7950/* MC_CMD_EVENT_CTRL_OUT msgrequest */
7951#define MC_CMD_EVENT_CTRL_OUT_LEN 0
7952
7953/* EVB_PORT_ID structuredef */
7954#define EVB_PORT_ID_LEN 4
7955#define EVB_PORT_ID_PORT_ID_OFST 0
7956#define EVB_PORT_ID_PORT_ID_LEN 4
7957/* enum: An invalid port handle. */
7958#define EVB_PORT_ID_NULL 0x0
7959/* enum: The port assigned to this function.. */
7960#define EVB_PORT_ID_ASSIGNED 0x1000000
7961/* enum: External network port 0 */
7962#define EVB_PORT_ID_MAC0 0x2000000
7963/* enum: External network port 1 */
7964#define EVB_PORT_ID_MAC1 0x2000001
7965/* enum: External network port 2 */
7966#define EVB_PORT_ID_MAC2 0x2000002
7967/* enum: External network port 3 */
7968#define EVB_PORT_ID_MAC3 0x2000003
7969#define EVB_PORT_ID_PORT_ID_LBN 0
7970#define EVB_PORT_ID_PORT_ID_WIDTH 32
7971
7972/* EVB_VLAN_TAG structuredef */
7973#define EVB_VLAN_TAG_LEN 2
7974/* The VLAN tag value */
7975#define EVB_VLAN_TAG_VLAN_ID_LBN 0
7976#define EVB_VLAN_TAG_VLAN_ID_WIDTH 12
7977#define EVB_VLAN_TAG_MODE_LBN 12
7978#define EVB_VLAN_TAG_MODE_WIDTH 4
7979/* enum: Insert the VLAN. */
7980#define EVB_VLAN_TAG_INSERT 0x0
7981/* enum: Replace the VLAN if already present. */
7982#define EVB_VLAN_TAG_REPLACE 0x1
7983
7984/* BUFTBL_ENTRY structuredef */
7985#define BUFTBL_ENTRY_LEN 12
7986/* the owner ID */
7987#define BUFTBL_ENTRY_OID_OFST 0
7988#define BUFTBL_ENTRY_OID_LEN 2
7989#define BUFTBL_ENTRY_OID_LBN 0
7990#define BUFTBL_ENTRY_OID_WIDTH 16
7991/* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */
7992#define BUFTBL_ENTRY_PGSZ_OFST 2
7993#define BUFTBL_ENTRY_PGSZ_LEN 2
7994#define BUFTBL_ENTRY_PGSZ_LBN 16
7995#define BUFTBL_ENTRY_PGSZ_WIDTH 16
7996/* the raw 64-bit address field from the SMC, not adjusted for page size */
7997#define BUFTBL_ENTRY_RAWADDR_OFST 4
7998#define BUFTBL_ENTRY_RAWADDR_LEN 8
7999#define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
8000#define BUFTBL_ENTRY_RAWADDR_HI_OFST 8
8001#define BUFTBL_ENTRY_RAWADDR_LBN 32
8002#define BUFTBL_ENTRY_RAWADDR_WIDTH 64
8003
8004/* NVRAM_PARTITION_TYPE structuredef */
8005#define NVRAM_PARTITION_TYPE_LEN 2
8006#define NVRAM_PARTITION_TYPE_ID_OFST 0
8007#define NVRAM_PARTITION_TYPE_ID_LEN 2
8008/* enum: Primary MC firmware partition */
8009#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
8010/* enum: Secondary MC firmware partition */
8011#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
8012/* enum: Expansion ROM partition */
8013#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
8014/* enum: Static configuration TLV partition */
8015#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
8016/* enum: Dynamic configuration TLV partition */
8017#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
8018/* enum: Expansion ROM configuration data for port 0 */
8019#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
8020/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
8021#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
8022/* enum: Expansion ROM configuration data for port 1 */
8023#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
8024/* enum: Expansion ROM configuration data for port 2 */
8025#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
8026/* enum: Expansion ROM configuration data for port 3 */
8027#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
8028/* enum: Non-volatile log output partition */
8029#define NVRAM_PARTITION_TYPE_LOG 0x700
8030/* enum: Non-volatile log output of second core on dual-core device */
8031#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
8032/* enum: Device state dump output partition */
8033#define NVRAM_PARTITION_TYPE_DUMP 0x800
8034/* enum: Application license key storage partition */
8035#define NVRAM_PARTITION_TYPE_LICENSE 0x900
8036/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
8037#define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
8038/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
8039#define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
8040/* enum: Primary FPGA partition */
8041#define NVRAM_PARTITION_TYPE_FPGA 0xb00
8042/* enum: Secondary FPGA partition */
8043#define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
8044/* enum: FC firmware partition */
8045#define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
8046/* enum: FC License partition */
8047#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
8048/* enum: Non-volatile log output partition for FC */
8049#define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
8050/* enum: MUM firmware partition */
8051#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
8052/* enum: SUC firmware partition (this is intentionally an alias of
8053 * MUM_FIRMWARE)
8054 */
8055#define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
8056/* enum: MUM Non-volatile log output partition. */
8057#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
8058/* enum: MUM Application table partition. */
8059#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
8060/* enum: MUM boot rom partition. */
8061#define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
8062/* enum: MUM production signatures & calibration rom partition. */
8063#define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
8064/* enum: MUM user signatures & calibration rom partition. */
8065#define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
8066/* enum: MUM fuses and lockbits partition. */
8067#define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
8068/* enum: UEFI expansion ROM if separate from PXE */
8069#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
8070/* enum: Used by the expansion ROM for logging */
8071#define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
8072/* enum: Used for XIP code of shmbooted images */
8073#define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
8074/* enum: Spare partition 2 */
8075#define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
8076/* enum: Manufacturing partition. Used during manufacture to pass information
8077 * between XJTAG and Manftest.
8078 */
8079#define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
8080/* enum: Spare partition 4 */
8081#define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
8082/* enum: Spare partition 5 */
8083#define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
8084/* enum: Partition for reporting MC status. See mc_flash_layout.h
8085 * medford_mc_status_hdr_t for layout on Medford.
8086 */
8087#define NVRAM_PARTITION_TYPE_STATUS 0x1600
8088/* enum: Spare partition 13 */
8089#define NVRAM_PARTITION_TYPE_SPARE_13 0x1700
8090/* enum: Spare partition 14 */
8091#define NVRAM_PARTITION_TYPE_SPARE_14 0x1800
8092/* enum: Spare partition 15 */
8093#define NVRAM_PARTITION_TYPE_SPARE_15 0x1900
8094/* enum: Spare partition 16 */
8095#define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
8096/* enum: Factory defaults for dynamic configuration */
8097#define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
8098/* enum: Factory defaults for expansion ROM configuration */
8099#define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
8100/* enum: Field Replaceable Unit inventory information for use on IPMI
8101 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
8102 * subset of the information stored in this partition.
8103 */
8104#define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
8105/* enum: Bundle image partition */
8106#define NVRAM_PARTITION_TYPE_BUNDLE 0x1e00
8107/* enum: Bundle metadata partition that holds additional information related to
8108 * a bundle update in TLV format
8109 */
8110#define NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
8111/* enum: Bundle update non-volatile log output partition */
8112#define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
8113/* enum: Partition for Solarflare gPXE bootrom installed via Bundle update. */
8114#define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
8115/* enum: Start of reserved value range (firmware may use for any purpose) */
8116#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
8117/* enum: End of reserved value range (firmware may use for any purpose) */
8118#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
8119/* enum: Recovery partition map (provided if real map is missing or corrupt) */
8120#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
8121/* enum: Partition map (real map as stored in flash) */
8122#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
8123#define NVRAM_PARTITION_TYPE_ID_LBN 0
8124#define NVRAM_PARTITION_TYPE_ID_WIDTH 16
8125
8126/* LICENSED_APP_ID structuredef */
8127#define LICENSED_APP_ID_LEN 4
8128#define LICENSED_APP_ID_ID_OFST 0
8129#define LICENSED_APP_ID_ID_LEN 4
8130/* enum: OpenOnload */
8131#define LICENSED_APP_ID_ONLOAD 0x1
8132/* enum: PTP timestamping */
8133#define LICENSED_APP_ID_PTP 0x2
8134/* enum: SolarCapture Pro */
8135#define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
8136/* enum: SolarSecure filter engine */
8137#define LICENSED_APP_ID_SOLARSECURE 0x8
8138/* enum: Performance monitor */
8139#define LICENSED_APP_ID_PERF_MONITOR 0x10
8140/* enum: SolarCapture Live */
8141#define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
8142/* enum: Capture SolarSystem */
8143#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
8144/* enum: Network Access Control */
8145#define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
8146/* enum: TCP Direct */
8147#define LICENSED_APP_ID_TCP_DIRECT 0x100
8148/* enum: Low Latency */
8149#define LICENSED_APP_ID_LOW_LATENCY 0x200
8150/* enum: SolarCapture Tap */
8151#define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
8152/* enum: Capture SolarSystem 40G */
8153#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
8154/* enum: Capture SolarSystem 1G */
8155#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
8156/* enum: ScaleOut Onload */
8157#define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
8158/* enum: SCS Network Analytics Dashboard */
8159#define LICENSED_APP_ID_DSHBRD 0x4000
8160/* enum: SolarCapture Trading Analytics */
8161#define LICENSED_APP_ID_SCATRD 0x8000
8162#define LICENSED_APP_ID_ID_LBN 0
8163#define LICENSED_APP_ID_ID_WIDTH 32
8164
8165/* LICENSED_FEATURES structuredef */
8166#define LICENSED_FEATURES_LEN 8
8167/* Bitmask of licensed firmware features */
8168#define LICENSED_FEATURES_MASK_OFST 0
8169#define LICENSED_FEATURES_MASK_LEN 8
8170#define LICENSED_FEATURES_MASK_LO_OFST 0
8171#define LICENSED_FEATURES_MASK_HI_OFST 4
8172#define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0
8173#define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
8174#define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1
8175#define LICENSED_FEATURES_PIO_OFST 0
8176#define LICENSED_FEATURES_PIO_LBN 1
8177#define LICENSED_FEATURES_PIO_WIDTH 1
8178#define LICENSED_FEATURES_EVQ_TIMER_OFST 0
8179#define LICENSED_FEATURES_EVQ_TIMER_LBN 2
8180#define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1
8181#define LICENSED_FEATURES_CLOCK_OFST 0
8182#define LICENSED_FEATURES_CLOCK_LBN 3
8183#define LICENSED_FEATURES_CLOCK_WIDTH 1
8184#define LICENSED_FEATURES_RX_TIMESTAMPS_OFST 0
8185#define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
8186#define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1
8187#define LICENSED_FEATURES_TX_TIMESTAMPS_OFST 0
8188#define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5
8189#define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1
8190#define LICENSED_FEATURES_RX_SNIFF_OFST 0
8191#define LICENSED_FEATURES_RX_SNIFF_LBN 6
8192#define LICENSED_FEATURES_RX_SNIFF_WIDTH 1
8193#define LICENSED_FEATURES_TX_SNIFF_OFST 0
8194#define LICENSED_FEATURES_TX_SNIFF_LBN 7
8195#define LICENSED_FEATURES_TX_SNIFF_WIDTH 1
8196#define LICENSED_FEATURES_PROXY_FILTER_OPS_OFST 0
8197#define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8
8198#define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1
8199#define LICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 0
8200#define LICENSED_FEATURES_EVENT_CUT_THROUGH_LBN 9
8201#define LICENSED_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
8202#define LICENSED_FEATURES_MASK_LBN 0
8203#define LICENSED_FEATURES_MASK_WIDTH 64
8204
8205/* LICENSED_V3_APPS structuredef */
8206#define LICENSED_V3_APPS_LEN 8
8207/* Bitmask of licensed applications */
8208#define LICENSED_V3_APPS_MASK_OFST 0
8209#define LICENSED_V3_APPS_MASK_LEN 8
8210#define LICENSED_V3_APPS_MASK_LO_OFST 0
8211#define LICENSED_V3_APPS_MASK_HI_OFST 4
8212#define LICENSED_V3_APPS_ONLOAD_OFST 0
8213#define LICENSED_V3_APPS_ONLOAD_LBN 0
8214#define LICENSED_V3_APPS_ONLOAD_WIDTH 1
8215#define LICENSED_V3_APPS_PTP_OFST 0
8216#define LICENSED_V3_APPS_PTP_LBN 1
8217#define LICENSED_V3_APPS_PTP_WIDTH 1
8218#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 0
8219#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2
8220#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1
8221#define LICENSED_V3_APPS_SOLARSECURE_OFST 0
8222#define LICENSED_V3_APPS_SOLARSECURE_LBN 3
8223#define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1
8224#define LICENSED_V3_APPS_PERF_MONITOR_OFST 0
8225#define LICENSED_V3_APPS_PERF_MONITOR_LBN 4
8226#define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1
8227#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 0
8228#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5
8229#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1
8230#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 0
8231#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6
8232#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1
8233#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 0
8234#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7
8235#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1
8236#define LICENSED_V3_APPS_TCP_DIRECT_OFST 0
8237#define LICENSED_V3_APPS_TCP_DIRECT_LBN 8
8238#define LICENSED_V3_APPS_TCP_DIRECT_WIDTH 1
8239#define LICENSED_V3_APPS_LOW_LATENCY_OFST 0
8240#define LICENSED_V3_APPS_LOW_LATENCY_LBN 9
8241#define LICENSED_V3_APPS_LOW_LATENCY_WIDTH 1
8242#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 0
8243#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_LBN 10
8244#define LICENSED_V3_APPS_SOLARCAPTURE_TAP_WIDTH 1
8245#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 0
8246#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_LBN 11
8247#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_WIDTH 1
8248#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 0
8249#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_LBN 12
8250#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_WIDTH 1
8251#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 0
8252#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_LBN 13
8253#define LICENSED_V3_APPS_SCALEOUT_ONLOAD_WIDTH 1
8254#define LICENSED_V3_APPS_DSHBRD_OFST 0
8255#define LICENSED_V3_APPS_DSHBRD_LBN 14
8256#define LICENSED_V3_APPS_DSHBRD_WIDTH 1
8257#define LICENSED_V3_APPS_SCATRD_OFST 0
8258#define LICENSED_V3_APPS_SCATRD_LBN 15
8259#define LICENSED_V3_APPS_SCATRD_WIDTH 1
8260#define LICENSED_V3_APPS_MASK_LBN 0
8261#define LICENSED_V3_APPS_MASK_WIDTH 64
8262
8263/* LICENSED_V3_FEATURES structuredef */
8264#define LICENSED_V3_FEATURES_LEN 8
8265/* Bitmask of licensed firmware features */
8266#define LICENSED_V3_FEATURES_MASK_OFST 0
8267#define LICENSED_V3_FEATURES_MASK_LEN 8
8268#define LICENSED_V3_FEATURES_MASK_LO_OFST 0
8269#define LICENSED_V3_FEATURES_MASK_HI_OFST 4
8270#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
8271#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
8272#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1
8273#define LICENSED_V3_FEATURES_PIO_OFST 0
8274#define LICENSED_V3_FEATURES_PIO_LBN 1
8275#define LICENSED_V3_FEATURES_PIO_WIDTH 1
8276#define LICENSED_V3_FEATURES_EVQ_TIMER_OFST 0
8277#define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2
8278#define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1
8279#define LICENSED_V3_FEATURES_CLOCK_OFST 0
8280#define LICENSED_V3_FEATURES_CLOCK_LBN 3
8281#define LICENSED_V3_FEATURES_CLOCK_WIDTH 1
8282#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 0
8283#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
8284#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1
8285#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 0
8286#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5
8287#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1
8288#define LICENSED_V3_FEATURES_RX_SNIFF_OFST 0
8289#define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6
8290#define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1
8291#define LICENSED_V3_FEATURES_TX_SNIFF_OFST 0
8292#define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7
8293#define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1
8294#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 0
8295#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8
8296#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1
8297#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 0
8298#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_LBN 9
8299#define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_WIDTH 1
8300#define LICENSED_V3_FEATURES_MASK_LBN 0
8301#define LICENSED_V3_FEATURES_MASK_WIDTH 64
8302
8303/* TX_TIMESTAMP_EVENT structuredef */
8304#define TX_TIMESTAMP_EVENT_LEN 6
8305/* lower 16 bits of timestamp data */
8306#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
8307#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN 2
8308#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
8309#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH 16
8310/* Type of TX event, ordinary TX completion, low or high part of TX timestamp
8311 */
8312#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3
8313#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1
8314/* enum: This is a TX completion event, not a timestamp */
8315#define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
8316/* enum: This is a TX completion event for a CTPIO transmit. The event format
8317 * is the same as for TX_EV_COMPLETION.
8318 */
8319#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
8320/* enum: This is the low part of a TX timestamp for a CTPIO transmission. The
8321 * event format is the same as for TX_EV_TSTAMP_LO
8322 */
8323#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
8324/* enum: This is the high part of a TX timestamp for a CTPIO transmission. The
8325 * event format is the same as for TX_EV_TSTAMP_HI
8326 */
8327#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
8328/* enum: This is the low part of a TX timestamp event */
8329#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
8330/* enum: This is the high part of a TX timestamp event */
8331#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
8332#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24
8333#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8
8334/* upper 16 bits of timestamp data */
8335#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
8336#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN 2
8337#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN 32
8338#define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH 16
8339
8340/* RSS_MODE structuredef */
8341#define RSS_MODE_LEN 1
8342/* The RSS mode for a particular packet type is a value from 0 - 15 which can
8343 * be considered as 4 bits selecting which fields are included in the hash. (A
8344 * value 0 effectively disables RSS spreading for the packet type.) The YAML
8345 * generation tools require this structure to be a whole number of bytes wide,
8346 * but only 4 bits are relevant.
8347 */
8348#define RSS_MODE_HASH_SELECTOR_OFST 0
8349#define RSS_MODE_HASH_SELECTOR_LEN 1
8350#define RSS_MODE_HASH_SRC_ADDR_OFST 0
8351#define RSS_MODE_HASH_SRC_ADDR_LBN 0
8352#define RSS_MODE_HASH_SRC_ADDR_WIDTH 1
8353#define RSS_MODE_HASH_DST_ADDR_OFST 0
8354#define RSS_MODE_HASH_DST_ADDR_LBN 1
8355#define RSS_MODE_HASH_DST_ADDR_WIDTH 1
8356#define RSS_MODE_HASH_SRC_PORT_OFST 0
8357#define RSS_MODE_HASH_SRC_PORT_LBN 2
8358#define RSS_MODE_HASH_SRC_PORT_WIDTH 1
8359#define RSS_MODE_HASH_DST_PORT_OFST 0
8360#define RSS_MODE_HASH_DST_PORT_LBN 3
8361#define RSS_MODE_HASH_DST_PORT_WIDTH 1
8362#define RSS_MODE_HASH_SELECTOR_LBN 0
8363#define RSS_MODE_HASH_SELECTOR_WIDTH 8
8364
8365/* CTPIO_STATS_MAP structuredef */
8366#define CTPIO_STATS_MAP_LEN 4
8367/* The (function relative) VI number */
8368#define CTPIO_STATS_MAP_VI_OFST 0
8369#define CTPIO_STATS_MAP_VI_LEN 2
8370#define CTPIO_STATS_MAP_VI_LBN 0
8371#define CTPIO_STATS_MAP_VI_WIDTH 16
8372/* The target bucket for the VI */
8373#define CTPIO_STATS_MAP_BUCKET_OFST 2
8374#define CTPIO_STATS_MAP_BUCKET_LEN 2
8375#define CTPIO_STATS_MAP_BUCKET_LBN 16
8376#define CTPIO_STATS_MAP_BUCKET_WIDTH 16
8377
8378
8379/***********************************/
8380/* MC_CMD_READ_REGS
8381 * Get a dump of the MCPU registers
8382 */
8383#define MC_CMD_READ_REGS 0x50
8384#undef MC_CMD_0x50_PRIVILEGE_CTG
8385
8386#define MC_CMD_0x50_PRIVILEGE_CTG SRIOV_CTG_INSECURE
8387
8388/* MC_CMD_READ_REGS_IN msgrequest */
8389#define MC_CMD_READ_REGS_IN_LEN 0
8390
8391/* MC_CMD_READ_REGS_OUT msgresponse */
8392#define MC_CMD_READ_REGS_OUT_LEN 308
8393/* Whether the corresponding register entry contains a valid value */
8394#define MC_CMD_READ_REGS_OUT_MASK_OFST 0
8395#define MC_CMD_READ_REGS_OUT_MASK_LEN 16
8396/* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
8397 * fir, fp)
8398 */
8399#define MC_CMD_READ_REGS_OUT_REGS_OFST 16
8400#define MC_CMD_READ_REGS_OUT_REGS_LEN 4
8401#define MC_CMD_READ_REGS_OUT_REGS_NUM 73
8402
8403
8404/***********************************/
8405/* MC_CMD_INIT_EVQ
8406 * Set up an event queue according to the supplied parameters. The IN arguments
8407 * end with an address for each 4k of host memory required to back the EVQ.
8408 */
8409#define MC_CMD_INIT_EVQ 0x80
8410#undef MC_CMD_0x80_PRIVILEGE_CTG
8411
8412#define MC_CMD_0x80_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8413
8414/* MC_CMD_INIT_EVQ_IN msgrequest */
8415#define MC_CMD_INIT_EVQ_IN_LENMIN 44
8416#define MC_CMD_INIT_EVQ_IN_LENMAX 548
8417#define MC_CMD_INIT_EVQ_IN_LENMAX_MCDI2 548
8418#define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
8419#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
8420/* Size, in entries */
8421#define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
8422#define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
8423/* Desired instance. Must be set to a specific instance, which is a function
8424 * local queue index.
8425 */
8426#define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
8427#define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
8428/* The initial timer value. The load value is ignored if the timer mode is DIS.
8429 */
8430#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
8431#define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4
8432/* The reload value is ignored in one-shot modes */
8433#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
8434#define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4
8435/* tbd */
8436#define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
8437#define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
8438#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_OFST 16
8439#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
8440#define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
8441#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_OFST 16
8442#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
8443#define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
8444#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_OFST 16
8445#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2
8446#define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
8447#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_OFST 16
8448#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3
8449#define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
8450#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_OFST 16
8451#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
8452#define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
8453#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_OFST 16
8454#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5
8455#define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
8456#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_OFST 16
8457#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_LBN 6
8458#define MC_CMD_INIT_EVQ_IN_FLAG_USE_TIMER_WIDTH 1
8459#define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
8460#define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4
8461/* enum: Disabled */
8462#define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
8463/* enum: Immediate */
8464#define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
8465/* enum: Triggered */
8466#define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
8467/* enum: Hold-off */
8468#define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
8469/* Target EVQ for wakeups if in wakeup mode. */
8470#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
8471#define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4
8472/* Target interrupt if in interrupting mode (note union with target EVQ). Use
8473 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
8474 * purposes.
8475 */
8476#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
8477#define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4
8478/* Event Counter Mode. */
8479#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28
8480#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4
8481/* enum: Disabled */
8482#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
8483/* enum: Disabled */
8484#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
8485/* enum: Disabled */
8486#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
8487/* enum: Disabled */
8488#define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
8489/* Event queue packet count threshold. */
8490#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32
8491#define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4
8492/* 64-bit address of 4k of 4k-aligned host memory buffer */
8493#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
8494#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
8495#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
8496#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
8497#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
8498#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
8499#define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM_MCDI2 64
8500
8501/* MC_CMD_INIT_EVQ_OUT msgresponse */
8502#define MC_CMD_INIT_EVQ_OUT_LEN 4
8503/* Only valid if INTRFLAG was true */
8504#define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
8505#define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4
8506
8507/* MC_CMD_INIT_EVQ_V2_IN msgrequest */
8508#define MC_CMD_INIT_EVQ_V2_IN_LENMIN 44
8509#define MC_CMD_INIT_EVQ_V2_IN_LENMAX 548
8510#define MC_CMD_INIT_EVQ_V2_IN_LENMAX_MCDI2 548
8511#define MC_CMD_INIT_EVQ_V2_IN_LEN(num) (36+8*(num))
8512#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
8513/* Size, in entries */
8514#define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
8515#define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
8516/* Desired instance. Must be set to a specific instance, which is a function
8517 * local queue index.
8518 */
8519#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
8520#define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
8521/* The initial timer value. The load value is ignored if the timer mode is DIS.
8522 */
8523#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_OFST 8
8524#define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4
8525/* The reload value is ignored in one-shot modes */
8526#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_OFST 12
8527#define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4
8528/* tbd */
8529#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_OFST 16
8530#define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
8531#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_OFST 16
8532#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
8533#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_WIDTH 1
8534#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_OFST 16
8535#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_LBN 1
8536#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RPTR_DOS_WIDTH 1
8537#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_OFST 16
8538#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_LBN 2
8539#define MC_CMD_INIT_EVQ_V2_IN_FLAG_INT_ARMD_WIDTH 1
8540#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_OFST 16
8541#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_LBN 3
8542#define MC_CMD_INIT_EVQ_V2_IN_FLAG_CUT_THRU_WIDTH 1
8543#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_OFST 16
8544#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
8545#define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_WIDTH 1
8546#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_OFST 16
8547#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_LBN 5
8548#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TX_MERGE_WIDTH 1
8549#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_OFST 16
8550#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_LBN 6
8551#define MC_CMD_INIT_EVQ_V2_IN_FLAG_USE_TIMER_WIDTH 1
8552#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_OFST 16
8553#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LBN 7
8554#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
8555/* enum: All initialisation flags specified by host. */
8556#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
8557/* enum: MEDFORD only. Certain initialisation flags specified by host may be
8558 * over-ridden by firmware based on licenses and firmware variant in order to
8559 * provide the lowest latency achievable. See
8560 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
8561 */
8562#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
8563/* enum: MEDFORD only. Certain initialisation flags specified by host may be
8564 * over-ridden by firmware based on licenses and firmware variant in order to
8565 * provide the best throughput achievable. See
8566 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
8567 */
8568#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
8569/* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
8570 * firmware based on licenses and firmware variant. See
8571 * MC_CMD_INIT_EVQ_V2/MC_CMD_INIT_EVQ_V2_OUT/FLAGS for list of affected flags.
8572 */
8573#define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
8574#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_OFST 16
8575#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_LBN 11
8576#define MC_CMD_INIT_EVQ_V2_IN_FLAG_EXT_WIDTH_WIDTH 1
8577#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_OFST 20
8578#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
8579/* enum: Disabled */
8580#define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
8581/* enum: Immediate */
8582#define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
8583/* enum: Triggered */
8584#define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
8585/* enum: Hold-off */
8586#define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
8587/* Target EVQ for wakeups if in wakeup mode. */
8588#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_OFST 24
8589#define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4
8590/* Target interrupt if in interrupting mode (note union with target EVQ). Use
8591 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
8592 * purposes.
8593 */
8594#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_OFST 24
8595#define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4
8596/* Event Counter Mode. */
8597#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_OFST 28
8598#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4
8599/* enum: Disabled */
8600#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
8601/* enum: Disabled */
8602#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
8603/* enum: Disabled */
8604#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
8605/* enum: Disabled */
8606#define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
8607/* Event queue packet count threshold. */
8608#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_OFST 32
8609#define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4
8610/* 64-bit address of 4k of 4k-aligned host memory buffer */
8611#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_OFST 36
8612#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LEN 8
8613#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_OFST 36
8614#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_OFST 40
8615#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MINNUM 1
8616#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM 64
8617#define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_MAXNUM_MCDI2 64
8618
8619/* MC_CMD_INIT_EVQ_V2_OUT msgresponse */
8620#define MC_CMD_INIT_EVQ_V2_OUT_LEN 8
8621/* Only valid if INTRFLAG was true */
8622#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
8623#define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4
8624/* Actual configuration applied on the card */
8625#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
8626#define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
8627#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 4
8628#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
8629#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_WIDTH 1
8630#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 4
8631#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_LBN 1
8632#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_WIDTH 1
8633#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 4
8634#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_LBN 2
8635#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_WIDTH 1
8636#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
8637#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_LBN 3
8638#define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_WIDTH 1
8639
8640/* QUEUE_CRC_MODE structuredef */
8641#define QUEUE_CRC_MODE_LEN 1
8642#define QUEUE_CRC_MODE_MODE_LBN 0
8643#define QUEUE_CRC_MODE_MODE_WIDTH 4
8644/* enum: No CRC. */
8645#define QUEUE_CRC_MODE_NONE 0x0
8646/* enum: CRC Fiber channel over ethernet. */
8647#define QUEUE_CRC_MODE_FCOE 0x1
8648/* enum: CRC (digest) iSCSI header only. */
8649#define QUEUE_CRC_MODE_ISCSI_HDR 0x2
8650/* enum: CRC (digest) iSCSI header and payload. */
8651#define QUEUE_CRC_MODE_ISCSI 0x3
8652/* enum: CRC Fiber channel over IP over ethernet. */
8653#define QUEUE_CRC_MODE_FCOIPOE 0x4
8654/* enum: CRC MPA. */
8655#define QUEUE_CRC_MODE_MPA 0x5
8656#define QUEUE_CRC_MODE_SPARE_LBN 4
8657#define QUEUE_CRC_MODE_SPARE_WIDTH 4
8658
8659
8660/***********************************/
8661/* MC_CMD_INIT_RXQ
8662 * set up a receive queue according to the supplied parameters. The IN
8663 * arguments end with an address for each 4k of host memory required to back
8664 * the RXQ.
8665 */
8666#define MC_CMD_INIT_RXQ 0x81
8667#undef MC_CMD_0x81_PRIVILEGE_CTG
8668
8669#define MC_CMD_0x81_PRIVILEGE_CTG SRIOV_CTG_GENERAL
8670
8671/* MC_CMD_INIT_RXQ_IN msgrequest: Legacy RXQ_INIT request. Use extended version
8672 * in new code.
8673 */
8674#define MC_CMD_INIT_RXQ_IN_LENMIN 36
8675#define MC_CMD_INIT_RXQ_IN_LENMAX 252
8676#define MC_CMD_INIT_RXQ_IN_LENMAX_MCDI2 1020
8677#define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
8678#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
8679/* Size, in entries */
8680#define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
8681#define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
8682/* The EVQ to send events to. This is an index originally specified to INIT_EVQ
8683 */
8684#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
8685#define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4
8686/* The value to put in the event data. Check hardware spec. for valid range. */
8687#define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
8688#define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
8689/* Desired instance. Must be set to a specific instance, which is a function
8690 * local queue index.
8691 */
8692#define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
8693#define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
8694/* There will be more flags here. */
8695#define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
8696#define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
8697#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_OFST 16
8698#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
8699#define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
8700#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_OFST 16
8701#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
8702#define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
8703#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_OFST 16
8704#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2
8705#define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
8706#define MC_CMD_INIT_RXQ_IN_CRC_MODE_OFST 16
8707#define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
8708#define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
8709#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_OFST 16
8710#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7
8711#define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
8712#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_OFST 16
8713#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8
8714#define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
8715#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_OFST 16
8716#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9
8717#define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1
8718#define MC_CMD_INIT_RXQ_IN_UNUSED_OFST 16
8719#define MC_CMD_INIT_RXQ_IN_UNUSED_LBN 10
8720#define MC_CMD_INIT_RXQ_IN_UNUSED_WIDTH 1
8721/* Owner ID to use if in buffer mode (zero if physical) */
8722#define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
8723#define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4
8724/* The port ID associated with the v-adaptor which should contain this DMAQ. */
8725#define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24
8726#define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4
8727/* 64-bit address of 4k of 4k-aligned host memory buffer */
8728#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
8729#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
8730#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
8731#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
8732#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
8733#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
8734#define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
8735
8736/* MC_CMD_INIT_RXQ_EXT_IN msgrequest: Extended RXQ_INIT with additional mode
8737 * flags
8738 */
8739#define MC_CMD_INIT_RXQ_EXT_IN_LEN 544
8740/* Size, in entries */
8741#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
8742#define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
8743/* The EVQ to send events to. This is an index originally specified to
8744 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
8745 */
8746#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
8747#define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
8748/* The value to put in the event data. Check hardware spec. for valid range.
8749 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
8750 * == PACKED_STREAM.
8751 */
8752#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_OFST 8
8753#define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
8754/* Desired instance. Must be set to a specific instance, which is a function
8755 * local queue index.
8756 */
8757#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_OFST 12
8758#define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
8759/* There will be more flags here. */
8760#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_OFST 16
8761#define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
8762#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16
8763#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
8764#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
8765#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_OFST 16
8766#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_LBN 1
8767#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT_WIDTH 1
8768#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16
8769#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_LBN 2
8770#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
8771#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_OFST 16
8772#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_LBN 3
8773#define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
8774#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_OFST 16
8775#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_LBN 7
8776#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_CHAIN_WIDTH 1
8777#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_OFST 16
8778#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_LBN 8
8779#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_PREFIX_WIDTH 1
8780#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_OFST 16
8781#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_LBN 9
8782#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_DISABLE_SCATTER_WIDTH 1
8783#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_OFST 16
8784#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10
8785#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
8786/* enum: One packet per descriptor (for normal networking) */
8787#define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
8788/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
8789#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
8790/* enum: Pack multiple packets into large descriptors using the format designed
8791 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
8792 * multiple fixed-size packet buffers within each bucket. For a full
8793 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
8794 * firmware.
8795 */
8796#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
8797/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
8798#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
8799#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_OFST 16
8800#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14
8801#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
8802#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
8803#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
8804#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
8805#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
8806#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
8807#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
8808#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
8809#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
8810#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
8811#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
8812#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
8813#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_OFST 16
8814#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19
8815#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
8816#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_OFST 16
8817#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_LBN 20
8818#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV_WIDTH 1
8819/* Owner ID to use if in buffer mode (zero if physical) */
8820#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20
8821#define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
8822/* The port ID associated with the v-adaptor which should contain this DMAQ. */
8823#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_OFST 24
8824#define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4
8825/* 64-bit address of 4k of 4k-aligned host memory buffer */
8826#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_OFST 28
8827#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LEN 8
8828#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_OFST 28
8829#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_OFST 32
8830#define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_NUM 64
8831/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
8832#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_OFST 540
8833#define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
8834
8835/* MC_CMD_INIT_RXQ_V3_IN msgrequest */
8836#define MC_CMD_INIT_RXQ_V3_IN_LEN 560
8837/* Size, in entries */
8838#define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0
8839#define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4
8840/* The EVQ to send events to. This is an index originally specified to
8841 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
8842 */
8843#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
8844#define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
8845/* The value to put in the event data. Check hardware spec. for valid range.
8846 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
8847 * == PACKED_STREAM.
8848 */
8849#define MC_CMD_INIT_RXQ_V3_IN_LABEL_OFST 8
8850#define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
8851/* Desired instance. Must be set to a specific instance, which is a function
8852 * local queue index.
8853 */
8854#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_OFST 12
8855#define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
8856/* There will be more flags here. */
8857#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_OFST 16
8858#define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
8859#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_OFST 16
8860#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
8861#define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_WIDTH 1
8862#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_OFST 16
8863#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_LBN 1
8864#define MC_CMD_INIT_RXQ_V3_IN_FLAG_HDR_SPLIT_WIDTH 1
8865#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_OFST 16
8866#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_LBN 2
8867#define MC_CMD_INIT_RXQ_V3_IN_FLAG_TIMESTAMP_WIDTH 1
8868#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_OFST 16
8869#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_LBN 3
8870#define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
8871#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_OFST 16
8872#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_LBN 7
8873#define MC_CMD_INIT_RXQ_V3_IN_FLAG_CHAIN_WIDTH 1
8874#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_OFST 16
8875#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_LBN 8
8876#define MC_CMD_INIT_RXQ_V3_IN_FLAG_PREFIX_WIDTH 1
8877#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_OFST 16
8878#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_LBN 9
8879#define MC_CMD_INIT_RXQ_V3_IN_FLAG_DISABLE_SCATTER_WIDTH 1
8880#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_OFST 16
8881#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10
8882#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
8883/* enum: One packet per descriptor (for normal networking) */
8884#define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
8885/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
8886#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
8887/* enum: Pack multiple packets into large descriptors using the format designed
8888 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
8889 * multiple fixed-size packet buffers within each bucket. For a full
8890 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
8891 * firmware.
8892 */
8893#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
8894/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
8895#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
8896#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_OFST 16
8897#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14
8898#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
8899#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
8900#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
8901#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
8902#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
8903#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
8904#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
8905#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
8906#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
8907#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
8908#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
8909#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
8910#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_OFST 16
8911#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19
8912#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
8913#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_OFST 16
8914#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_LBN 20
8915#define MC_CMD_INIT_RXQ_V3_IN_FLAG_NO_CONT_EV_WIDTH 1
8916/* Owner ID to use if in buffer mode (zero if physical) */
8917#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_OFST 20
8918#define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
8919/* The port ID associated with the v-adaptor which should contain this DMAQ. */
8920#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_OFST 24
8921#define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4
8922/* 64-bit address of 4k of 4k-aligned host memory buffer */
8923#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_OFST 28
8924#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LEN 8
8925#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_OFST 28
8926#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_OFST 32
8927#define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_NUM 64
8928/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
8929#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_OFST 540
8930#define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
8931/* The number of packet buffers that will be contained within each
8932 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
8933 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
8934 */
8935#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
8936#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
8937/* The length in bytes of the area in each packet buffer that can be written to
8938 * by the adapter. This is used to store the packet prefix and the packet
8939 * payload. This length does not include any end padding added by the driver.
8940 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
8941 */
8942#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_OFST 548
8943#define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
8944/* The length in bytes of a single packet buffer within a
8945 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
8946 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
8947 */
8948#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_OFST 552
8949#define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
8950/* The maximum time in nanoseconds that the datapath will be backpressured if
8951 * there are no RX descriptors available. If the timeout is reached and there
8952 * are still no descriptors then the packet will be dropped. A timeout of 0
8953 * means the datapath will never be blocked. This field is ignored unless
8954 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
8955 */
8956#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
8957#define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
8958
8959/* MC_CMD_INIT_RXQ_V4_IN msgrequest: INIT_RXQ request with new field required
8960 * for systems with a QDMA (currently, Riverhead)
8961 */
8962#define MC_CMD_INIT_RXQ_V4_IN_LEN 564
8963/* Size, in entries */
8964#define MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 0
8965#define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 4
8966/* The EVQ to send events to. This is an index originally specified to
8967 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
8968 */
8969#define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 4
8970#define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 4
8971/* The value to put in the event data. Check hardware spec. for valid range.
8972 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
8973 * == PACKED_STREAM.
8974 */
8975#define MC_CMD_INIT_RXQ_V4_IN_LABEL_OFST 8
8976#define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
8977/* Desired instance. Must be set to a specific instance, which is a function
8978 * local queue index.
8979 */
8980#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_OFST 12
8981#define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
8982/* There will be more flags here. */
8983#define MC_CMD_INIT_RXQ_V4_IN_FLAGS_OFST 16
8984#define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4
8985#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_OFST 16
8986#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 0
8987#define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_WIDTH 1
8988#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_OFST 16
8989#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_LBN 1
8990#define MC_CMD_INIT_RXQ_V4_IN_FLAG_HDR_SPLIT_WIDTH 1
8991#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_OFST 16
8992#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_LBN 2
8993#define MC_CMD_INIT_RXQ_V4_IN_FLAG_TIMESTAMP_WIDTH 1
8994#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_OFST 16
8995#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_LBN 3
8996#define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4
8997#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_OFST 16
8998#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_LBN 7
8999#define MC_CMD_INIT_RXQ_V4_IN_FLAG_CHAIN_WIDTH 1
9000#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_OFST 16
9001#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_LBN 8
9002#define MC_CMD_INIT_RXQ_V4_IN_FLAG_PREFIX_WIDTH 1
9003#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_OFST 16
9004#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_LBN 9
9005#define MC_CMD_INIT_RXQ_V4_IN_FLAG_DISABLE_SCATTER_WIDTH 1
9006#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_OFST 16
9007#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_LBN 10
9008#define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4
9009/* enum: One packet per descriptor (for normal networking) */
9010#define MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x0
9011/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
9012#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x1
9013/* enum: Pack multiple packets into large descriptors using the format designed
9014 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
9015 * multiple fixed-size packet buffers within each bucket. For a full
9016 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
9017 * firmware.
9018 */
9019#define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
9020/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
9021#define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
9022#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_OFST 16
9023#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_LBN 14
9024#define MC_CMD_INIT_RXQ_V4_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
9025#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
9026#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
9027#define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
9028#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */
9029#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */
9030#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */
9031#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */
9032#define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */
9033#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
9034#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
9035#define MC_CMD_INIT_RXQ_V4_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
9036#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_OFST 16
9037#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_LBN 19
9038#define MC_CMD_INIT_RXQ_V4_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
9039#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_OFST 16
9040#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_LBN 20
9041#define MC_CMD_INIT_RXQ_V4_IN_FLAG_NO_CONT_EV_WIDTH 1
9042/* Owner ID to use if in buffer mode (zero if physical) */
9043#define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_OFST 20
9044#define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4
9045/* The port ID associated with the v-adaptor which should contain this DMAQ. */
9046#define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_OFST 24
9047#define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 4
9048/* 64-bit address of 4k of 4k-aligned host memory buffer */
9049#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_OFST 28
9050#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LEN 8
9051#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_OFST 28
9052#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_OFST 32
9053#define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_NUM 64
9054/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
9055#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_OFST 540
9056#define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 4
9057/* The number of packet buffers that will be contained within each
9058 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
9059 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9060 */
9061#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
9062#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
9063/* The length in bytes of the area in each packet buffer that can be written to
9064 * by the adapter. This is used to store the packet prefix and the packet
9065 * payload. This length does not include any end padding added by the driver.
9066 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9067 */
9068#define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_OFST 548
9069#define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 4
9070/* The length in bytes of a single packet buffer within a
9071 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
9072 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9073 */
9074#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_OFST 552
9075#define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 4
9076/* The maximum time in nanoseconds that the datapath will be backpressured if
9077 * there are no RX descriptors available. If the timeout is reached and there
9078 * are still no descriptors then the packet will be dropped. A timeout of 0
9079 * means the datapath will never be blocked. This field is ignored unless
9080 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9081 */
9082#define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
9083#define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
9084/* V4 message data */
9085#define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_OFST 560
9086#define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 4
9087/* Size in bytes of buffers attached to descriptors posted to this queue. Set
9088 * to zero if using this message on non-QDMA based platforms. Currently in
9089 * Riverhead there is a global limit of eight different buffer sizes across all
9090 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
9091 * request for a different buffer size will fail if there are already eight
9092 * other buffer sizes in use. In future Riverhead this limit will go away and
9093 * any size will be accepted.
9094 */
9095#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_OFST 560
9096#define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4
9097
9098/* MC_CMD_INIT_RXQ_V5_IN msgrequest: INIT_RXQ request with ability to request a
9099 * different RX packet prefix
9100 */
9101#define MC_CMD_INIT_RXQ_V5_IN_LEN 568
9102/* Size, in entries */
9103#define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 0
9104#define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4
9105/* The EVQ to send events to. This is an index originally specified to
9106 * INIT_EVQ. If DMA_MODE == PACKED_STREAM this must be equal to INSTANCE.
9107 */
9108#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4
9109#define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4
9110/* The value to put in the event data. Check hardware spec. for valid range.
9111 * This field is ignored if DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER or DMA_MODE
9112 * == PACKED_STREAM.
9113 */
9114#define MC_CMD_INIT_RXQ_V5_IN_LABEL_OFST 8
9115#define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
9116/* Desired instance. Must be set to a specific instance, which is a function
9117 * local queue index.
9118 */
9119#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_OFST 12
9120#define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
9121/* There will be more flags here. */
9122#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_OFST 16
9123#define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4
9124#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_OFST 16
9125#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0
9126#define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_WIDTH 1
9127#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_OFST 16
9128#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_LBN 1
9129#define MC_CMD_INIT_RXQ_V5_IN_FLAG_HDR_SPLIT_WIDTH 1
9130#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_OFST 16
9131#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_LBN 2
9132#define MC_CMD_INIT_RXQ_V5_IN_FLAG_TIMESTAMP_WIDTH 1
9133#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_OFST 16
9134#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_LBN 3
9135#define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4
9136#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_OFST 16
9137#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_LBN 7
9138#define MC_CMD_INIT_RXQ_V5_IN_FLAG_CHAIN_WIDTH 1
9139#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_OFST 16
9140#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_LBN 8
9141#define MC_CMD_INIT_RXQ_V5_IN_FLAG_PREFIX_WIDTH 1
9142#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_OFST 16
9143#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_LBN 9
9144#define MC_CMD_INIT_RXQ_V5_IN_FLAG_DISABLE_SCATTER_WIDTH 1
9145#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_OFST 16
9146#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_LBN 10
9147#define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4
9148/* enum: One packet per descriptor (for normal networking) */
9149#define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x0
9150/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
9151#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x1
9152/* enum: Pack multiple packets into large descriptors using the format designed
9153 * to maximise packet rate. This mode uses 1 "bucket" per descriptor with
9154 * multiple fixed-size packet buffers within each bucket. For a full
9155 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
9156 * firmware.
9157 */
9158#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
9159/* enum: Deprecated name for EQUAL_STRIDE_SUPER_BUFFER. */
9160#define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
9161#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_OFST 16
9162#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_LBN 14
9163#define MC_CMD_INIT_RXQ_V5_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
9164#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_OFST 16
9165#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
9166#define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
9167#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */
9168#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */
9169#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */
9170#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */
9171#define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */
9172#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_OFST 16
9173#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
9174#define MC_CMD_INIT_RXQ_V5_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
9175#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_OFST 16
9176#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_LBN 19
9177#define MC_CMD_INIT_RXQ_V5_IN_FLAG_FORCE_EV_MERGING_WIDTH 1
9178#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_OFST 16
9179#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_LBN 20
9180#define MC_CMD_INIT_RXQ_V5_IN_FLAG_NO_CONT_EV_WIDTH 1
9181/* Owner ID to use if in buffer mode (zero if physical) */
9182#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_OFST 20
9183#define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
9184/* The port ID associated with the v-adaptor which should contain this DMAQ. */
9185#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_OFST 24
9186#define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4
9187/* 64-bit address of 4k of 4k-aligned host memory buffer */
9188#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_OFST 28
9189#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LEN 8
9190#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_OFST 28
9191#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_OFST 32
9192#define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_NUM 64
9193/* Maximum length of packet to receive, if SNAPSHOT_MODE flag is set */
9194#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_OFST 540
9195#define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4
9196/* The number of packet buffers that will be contained within each
9197 * EQUAL_STRIDE_SUPER_BUFFER format bucket supplied by the driver. This field
9198 * is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9199 */
9200#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_OFST 544
9201#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
9202/* The length in bytes of the area in each packet buffer that can be written to
9203 * by the adapter. This is used to store the packet prefix and the packet
9204 * payload. This length does not include any end padding added by the driver.
9205 * This field is ignored unless DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9206 */
9207#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_OFST 548
9208#define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4
9209/* The length in bytes of a single packet buffer within a
9210 * EQUAL_STRIDE_SUPER_BUFFER format bucket. This field is ignored unless
9211 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9212 */
9213#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_OFST 552
9214#define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4
9215/* The maximum time in nanoseconds that the datapath will be backpressured if
9216 * there are no RX descriptors available. If the timeout is reached and there
9217 * are still no descriptors then the packet will be dropped. A timeout of 0
9218 * means the datapath will never be blocked. This field is ignored unless
9219 * DMA_MODE == EQUAL_STRIDE_SUPER_BUFFER.
9220 */
9221#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_OFST 556
9222#define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
9223/* V4 message data */
9224#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_OFST 560
9225#define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4
9226/* Size in bytes of buffers attached to descriptors posted to this queue. Set
9227 * to zero if using this message on non-QDMA based platforms. Currently in
9228 * Riverhead there is a global limit of eight different buffer sizes across all
9229 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
9230 * request for a different buffer size will fail if there are already eight
9231 * other buffer sizes in use. In future Riverhead this limit will go away and
9232 * any size will be accepted.
9233 */
9234#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_OFST 560
9235#define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4
9236/* Prefix id for the RX prefix format to use on packets delivered this queue.
9237 * Zero is always a valid prefix id and means the default prefix format
9238 * documented for the platform. Other prefix ids can be obtained by calling
9239 * MC_CMD_GET_RX_PREFIX_ID with a requested set of prefix fields.
9240 */
9241#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_OFST 564
9242#define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4
9243
9244/* MC_CMD_INIT_RXQ_OUT msgresponse */
9245#define MC_CMD_INIT_RXQ_OUT_LEN 0
9246
9247/* MC_CMD_INIT_RXQ_EXT_OUT msgresponse */
9248#define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
9249
9250/* MC_CMD_INIT_RXQ_V3_OUT msgresponse */
9251#define MC_CMD_INIT_RXQ_V3_OUT_LEN 0
9252
9253/* MC_CMD_INIT_RXQ_V4_OUT msgresponse */
9254#define MC_CMD_INIT_RXQ_V4_OUT_LEN 0
9255
9256/* MC_CMD_INIT_RXQ_V5_OUT msgresponse */
9257#define MC_CMD_INIT_RXQ_V5_OUT_LEN 0
9258
9259
9260/***********************************/
9261/* MC_CMD_INIT_TXQ
9262 */
9263#define MC_CMD_INIT_TXQ 0x82
9264#undef MC_CMD_0x82_PRIVILEGE_CTG
9265
9266#define MC_CMD_0x82_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9267
9268/* MC_CMD_INIT_TXQ_IN msgrequest: Legacy INIT_TXQ request. Use extended version
9269 * in new code.
9270 */
9271#define MC_CMD_INIT_TXQ_IN_LENMIN 36
9272#define MC_CMD_INIT_TXQ_IN_LENMAX 252
9273#define MC_CMD_INIT_TXQ_IN_LENMAX_MCDI2 1020
9274#define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
9275#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
9276/* Size, in entries */
9277#define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
9278#define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
9279/* The EVQ to send events to. This is an index originally specified to
9280 * INIT_EVQ.
9281 */
9282#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
9283#define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4
9284/* The value to put in the event data. Check hardware spec. for valid range. */
9285#define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
9286#define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
9287/* Desired instance. Must be set to a specific instance, which is a function
9288 * local queue index.
9289 */
9290#define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
9291#define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
9292/* There will be more flags here. */
9293#define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
9294#define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
9295#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_OFST 16
9296#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
9297#define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
9298#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_OFST 16
9299#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
9300#define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
9301#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_OFST 16
9302#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
9303#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
9304#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_OFST 16
9305#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
9306#define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
9307#define MC_CMD_INIT_TXQ_IN_CRC_MODE_OFST 16
9308#define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
9309#define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
9310#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_OFST 16
9311#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8
9312#define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
9313#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_OFST 16
9314#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9
9315#define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
9316#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_OFST 16
9317#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
9318#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
9319#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16
9320#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
9321#define MC_CMD_INIT_TXQ_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
9322/* Owner ID to use if in buffer mode (zero if physical) */
9323#define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
9324#define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4
9325/* The port ID associated with the v-adaptor which should contain this DMAQ. */
9326#define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24
9327#define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4
9328/* 64-bit address of 4k of 4k-aligned host memory buffer */
9329#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
9330#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
9331#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
9332#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
9333#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
9334#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
9335#define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM_MCDI2 124
9336
9337/* MC_CMD_INIT_TXQ_EXT_IN msgrequest: Extended INIT_TXQ with additional mode
9338 * flags
9339 */
9340#define MC_CMD_INIT_TXQ_EXT_IN_LEN 544
9341/* Size, in entries */
9342#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
9343#define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4
9344/* The EVQ to send events to. This is an index originally specified to
9345 * INIT_EVQ.
9346 */
9347#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
9348#define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4
9349/* The value to put in the event data. Check hardware spec. for valid range. */
9350#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_OFST 8
9351#define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
9352/* Desired instance. Must be set to a specific instance, which is a function
9353 * local queue index.
9354 */
9355#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_OFST 12
9356#define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
9357/* There will be more flags here. */
9358#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_OFST 16
9359#define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
9360#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_OFST 16
9361#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
9362#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_WIDTH 1
9363#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_OFST 16
9364#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_LBN 1
9365#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_IP_CSUM_DIS_WIDTH 1
9366#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_OFST 16
9367#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_LBN 2
9368#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
9369#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_OFST 16
9370#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_LBN 3
9371#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
9372#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_OFST 16
9373#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
9374#define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
9375#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_OFST 16
9376#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_LBN 8
9377#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TIMESTAMP_WIDTH 1
9378#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_OFST 16
9379#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_LBN 9
9380#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_PACER_BYPASS_WIDTH 1
9381#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_OFST 16
9382#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_LBN 10
9383#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1
9384#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_OFST 16
9385#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11
9386#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1
9387#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_OFST 16
9388#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12
9389#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1
9390#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_OFST 16
9391#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_LBN 13
9392#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_WIDTH 1
9393#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_OFST 16
9394#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_LBN 14
9395#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_CTPIO_UTHRESH_WIDTH 1
9396#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_OFST 16
9397#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_LBN 15
9398#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_M2M_D2C_WIDTH 1
9399#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_OFST 16
9400#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_LBN 16
9401#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_DESC_PROXY_WIDTH 1
9402/* Owner ID to use if in buffer mode (zero if physical) */
9403#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20
9404#define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
9405/* The port ID associated with the v-adaptor which should contain this DMAQ. */
9406#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_OFST 24
9407#define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4
9408/* 64-bit address of 4k of 4k-aligned host memory buffer */
9409#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_OFST 28
9410#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LEN 8
9411#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_OFST 28
9412#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_OFST 32
9413#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 1
9414#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM 64
9415#define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MAXNUM_MCDI2 64
9416/* Flags related to Qbb flow control mode. */
9417#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_OFST 540
9418#define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
9419#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_OFST 540
9420#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
9421#define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_WIDTH 1
9422#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_OFST 540
9423#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_LBN 1
9424#define MC_CMD_INIT_TXQ_EXT_IN_QBB_PRIORITY_WIDTH 3
9425
9426/* MC_CMD_INIT_TXQ_OUT msgresponse */
9427#define MC_CMD_INIT_TXQ_OUT_LEN 0
9428
9429
9430/***********************************/
9431/* MC_CMD_FINI_EVQ
9432 * Teardown an EVQ.
9433 *
9434 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first
9435 * or the operation will fail with EBUSY
9436 */
9437#define MC_CMD_FINI_EVQ 0x83
9438#undef MC_CMD_0x83_PRIVILEGE_CTG
9439
9440#define MC_CMD_0x83_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9441
9442/* MC_CMD_FINI_EVQ_IN msgrequest */
9443#define MC_CMD_FINI_EVQ_IN_LEN 4
9444/* Instance of EVQ to destroy. Should be the same instance as that previously
9445 * passed to INIT_EVQ
9446 */
9447#define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
9448#define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
9449
9450/* MC_CMD_FINI_EVQ_OUT msgresponse */
9451#define MC_CMD_FINI_EVQ_OUT_LEN 0
9452
9453
9454/***********************************/
9455/* MC_CMD_FINI_RXQ
9456 * Teardown a RXQ.
9457 */
9458#define MC_CMD_FINI_RXQ 0x84
9459#undef MC_CMD_0x84_PRIVILEGE_CTG
9460
9461#define MC_CMD_0x84_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9462
9463/* MC_CMD_FINI_RXQ_IN msgrequest */
9464#define MC_CMD_FINI_RXQ_IN_LEN 4
9465/* Instance of RXQ to destroy */
9466#define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
9467#define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4
9468
9469/* MC_CMD_FINI_RXQ_OUT msgresponse */
9470#define MC_CMD_FINI_RXQ_OUT_LEN 0
9471
9472
9473/***********************************/
9474/* MC_CMD_FINI_TXQ
9475 * Teardown a TXQ.
9476 */
9477#define MC_CMD_FINI_TXQ 0x85
9478#undef MC_CMD_0x85_PRIVILEGE_CTG
9479
9480#define MC_CMD_0x85_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9481
9482/* MC_CMD_FINI_TXQ_IN msgrequest */
9483#define MC_CMD_FINI_TXQ_IN_LEN 4
9484/* Instance of TXQ to destroy */
9485#define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
9486#define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4
9487
9488/* MC_CMD_FINI_TXQ_OUT msgresponse */
9489#define MC_CMD_FINI_TXQ_OUT_LEN 0
9490
9491
9492/***********************************/
9493/* MC_CMD_DRIVER_EVENT
9494 * Generate an event on an EVQ belonging to the function issuing the command.
9495 */
9496#define MC_CMD_DRIVER_EVENT 0x86
9497#undef MC_CMD_0x86_PRIVILEGE_CTG
9498
9499#define MC_CMD_0x86_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9500
9501/* MC_CMD_DRIVER_EVENT_IN msgrequest */
9502#define MC_CMD_DRIVER_EVENT_IN_LEN 12
9503/* Handle of target EVQ */
9504#define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
9505#define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4
9506/* Bits 0 - 63 of event */
9507#define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
9508#define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
9509#define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
9510#define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
9511
9512/* MC_CMD_DRIVER_EVENT_OUT msgresponse */
9513#define MC_CMD_DRIVER_EVENT_OUT_LEN 0
9514
9515
9516/***********************************/
9517/* MC_CMD_ALLOC_BUFTBL_CHUNK
9518 * Allocate a set of buffer table entries using the specified owner ID. This
9519 * operation allocates the required buffer table entries (and fails if it
9520 * cannot do so). The buffer table entries will initially be zeroed.
9521 */
9522#define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
9523#undef MC_CMD_0x87_PRIVILEGE_CTG
9524
9525#define MC_CMD_0x87_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
9526
9527/* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */
9528#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8
9529/* Owner ID to use */
9530#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
9531#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4
9532/* Size of buffer table pages to use, in bytes (note that only a few values are
9533 * legal on any specific hardware).
9534 */
9535#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
9536#define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4
9537
9538/* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */
9539#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12
9540#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
9541#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4
9542#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
9543#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4
9544/* Buffer table IDs for use in DMA descriptors. */
9545#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8
9546#define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4
9547
9548
9549/***********************************/
9550/* MC_CMD_PROGRAM_BUFTBL_ENTRIES
9551 * Reprogram a set of buffer table entries in the specified chunk.
9552 */
9553#define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
9554#undef MC_CMD_0x88_PRIVILEGE_CTG
9555
9556#define MC_CMD_0x88_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
9557
9558/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */
9559#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20
9560#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 268
9561#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX_MCDI2 268
9562#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
9563#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8)
9564#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
9565#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4
9566/* ID */
9567#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
9568#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
9569/* Num entries */
9570#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8
9571#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
9572/* Buffer table entry address */
9573#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
9574#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
9575#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
9576#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
9577#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
9578#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 32
9579#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM_MCDI2 32
9580
9581/* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */
9582#define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
9583
9584
9585/***********************************/
9586/* MC_CMD_FREE_BUFTBL_CHUNK
9587 */
9588#define MC_CMD_FREE_BUFTBL_CHUNK 0x89
9589#undef MC_CMD_0x89_PRIVILEGE_CTG
9590
9591#define MC_CMD_0x89_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
9592
9593/* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */
9594#define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
9595#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
9596#define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4
9597
9598/* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */
9599#define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
9600
9601
9602/***********************************/
9603/* MC_CMD_FILTER_OP
9604 * Multiplexed MCDI call for filter operations
9605 */
9606#define MC_CMD_FILTER_OP 0x8a
9607#undef MC_CMD_0x8a_PRIVILEGE_CTG
9608
9609#define MC_CMD_0x8a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
9610
9611/* MC_CMD_FILTER_OP_IN msgrequest */
9612#define MC_CMD_FILTER_OP_IN_LEN 108
9613/* identifies the type of operation requested */
9614#define MC_CMD_FILTER_OP_IN_OP_OFST 0
9615#define MC_CMD_FILTER_OP_IN_OP_LEN 4
9616/* enum: single-recipient filter insert */
9617#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
9618/* enum: single-recipient filter remove */
9619#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
9620/* enum: multi-recipient filter subscribe */
9621#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
9622/* enum: multi-recipient filter unsubscribe */
9623#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
9624/* enum: replace one recipient with another (warning - the filter handle may
9625 * change)
9626 */
9627#define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
9628/* filter handle (for remove / unsubscribe operations) */
9629#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
9630#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
9631#define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
9632#define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
9633/* The port ID associated with the v-adaptor which should contain this filter.
9634 */
9635#define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
9636#define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4
9637/* fields to include in match criteria */
9638#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16
9639#define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
9640#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_OFST 16
9641#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
9642#define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
9643#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_OFST 16
9644#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
9645#define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
9646#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_OFST 16
9647#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
9648#define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
9649#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_OFST 16
9650#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
9651#define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
9652#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_OFST 16
9653#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
9654#define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
9655#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_OFST 16
9656#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
9657#define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
9658#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_OFST 16
9659#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
9660#define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
9661#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_OFST 16
9662#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
9663#define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
9664#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_OFST 16
9665#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
9666#define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
9667#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_OFST 16
9668#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
9669#define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
9670#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_OFST 16
9671#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
9672#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
9673#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_OFST 16
9674#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
9675#define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
9676#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
9677#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
9678#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
9679#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
9680#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
9681#define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
9682/* receive destination */
9683#define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20
9684#define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
9685/* enum: drop packets */
9686#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
9687/* enum: receive to host */
9688#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
9689/* enum: receive to MC */
9690#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
9691/* enum: loop back to TXDP 0 */
9692#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
9693/* enum: loop back to TXDP 1 */
9694#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
9695/* receive queue handle (for multiple queue modes, this is the base queue) */
9696#define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24
9697#define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
9698/* receive mode */
9699#define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28
9700#define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
9701/* enum: receive to just the specified queue */
9702#define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
9703/* enum: receive to multiple queues using RSS context */
9704#define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
9705/* enum: receive to multiple queues using .1p mapping */
9706#define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
9707/* enum: install a filter entry that will never match; for test purposes only
9708 */
9709#define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
9710/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
9711 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
9712 * MC_CMD_DOT1P_MAPPING_ALLOC.
9713 */
9714#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32
9715#define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4
9716/* transmit domain (reserved; set to 0) */
9717#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36
9718#define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4
9719/* transmit destination (either set the MAC and/or PM bits for explicit
9720 * control, or set this field to TX_DEST_DEFAULT for sensible default
9721 * behaviour)
9722 */
9723#define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40
9724#define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
9725/* enum: request default behaviour (based on filter type) */
9726#define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
9727#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_OFST 40
9728#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
9729#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
9730#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_OFST 40
9731#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
9732#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
9733/* source MAC address to match (as bytes in network order) */
9734#define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44
9735#define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
9736/* source port to match (as bytes in network order) */
9737#define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50
9738#define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
9739/* destination MAC address to match (as bytes in network order) */
9740#define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52
9741#define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
9742/* destination port to match (as bytes in network order) */
9743#define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58
9744#define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
9745/* Ethernet type to match (as bytes in network order) */
9746#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60
9747#define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
9748/* Inner VLAN tag to match (as bytes in network order) */
9749#define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62
9750#define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
9751/* Outer VLAN tag to match (as bytes in network order) */
9752#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64
9753#define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
9754/* IP protocol to match (in low byte; set high byte to 0) */
9755#define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66
9756#define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
9757/* Firmware defined register 0 to match (reserved; set to 0) */
9758#define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68
9759#define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4
9760/* Firmware defined register 1 to match (reserved; set to 0) */
9761#define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72
9762#define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4
9763/* source IP address to match (as bytes in network order; set last 12 bytes to
9764 * 0 for IPv4 address)
9765 */
9766#define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76
9767#define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
9768/* destination IP address to match (as bytes in network order; set last 12
9769 * bytes to 0 for IPv4 address)
9770 */
9771#define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92
9772#define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
9773
9774/* MC_CMD_FILTER_OP_EXT_IN msgrequest: Extension to MC_CMD_FILTER_OP_IN to
9775 * include handling of VXLAN/NVGRE encapsulated frame filtering (which is
9776 * supported on Medford only).
9777 */
9778#define MC_CMD_FILTER_OP_EXT_IN_LEN 172
9779/* identifies the type of operation requested */
9780#define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
9781#define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4
9782/* Enum values, see field(s): */
9783/* MC_CMD_FILTER_OP_IN/OP */
9784/* filter handle (for remove / unsubscribe operations) */
9785#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
9786#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LEN 8
9787#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
9788#define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_OFST 8
9789/* The port ID associated with the v-adaptor which should contain this filter.
9790 */
9791#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_OFST 12
9792#define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4
9793/* fields to include in match criteria */
9794#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_OFST 16
9795#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
9796#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_OFST 16
9797#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
9798#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_WIDTH 1
9799#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_OFST 16
9800#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_LBN 1
9801#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_IP_WIDTH 1
9802#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_OFST 16
9803#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_LBN 2
9804#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_MAC_WIDTH 1
9805#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_OFST 16
9806#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_LBN 3
9807#define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_PORT_WIDTH 1
9808#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_OFST 16
9809#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
9810#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_WIDTH 1
9811#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_OFST 16
9812#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_LBN 5
9813#define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_PORT_WIDTH 1
9814#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_OFST 16
9815#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_LBN 6
9816#define MC_CMD_FILTER_OP_EXT_IN_MATCH_ETHER_TYPE_WIDTH 1
9817#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_OFST 16
9818#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_LBN 7
9819#define MC_CMD_FILTER_OP_EXT_IN_MATCH_INNER_VLAN_WIDTH 1
9820#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_OFST 16
9821#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_LBN 8
9822#define MC_CMD_FILTER_OP_EXT_IN_MATCH_OUTER_VLAN_WIDTH 1
9823#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_OFST 16
9824#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_LBN 9
9825#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IP_PROTO_WIDTH 1
9826#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_OFST 16
9827#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_LBN 10
9828#define MC_CMD_FILTER_OP_EXT_IN_MATCH_FWDEF0_WIDTH 1
9829#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_OFST 16
9830#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_LBN 11
9831#define MC_CMD_FILTER_OP_EXT_IN_MATCH_VNI_OR_VSID_WIDTH 1
9832#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_OFST 16
9833#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_LBN 12
9834#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_IP_WIDTH 1
9835#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_OFST 16
9836#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_LBN 13
9837#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_IP_WIDTH 1
9838#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_OFST 16
9839#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_LBN 14
9840#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
9841#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_OFST 16
9842#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_LBN 15
9843#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
9844#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_OFST 16
9845#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_LBN 16
9846#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_MAC_WIDTH 1
9847#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_OFST 16
9848#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_LBN 17
9849#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_DST_PORT_WIDTH 1
9850#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_OFST 16
9851#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
9852#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
9853#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_OFST 16
9854#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_LBN 19
9855#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
9856#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_OFST 16
9857#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
9858#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
9859#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_OFST 16
9860#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_LBN 21
9861#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
9862#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_OFST 16
9863#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_LBN 22
9864#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF0_WIDTH 1
9865#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_OFST 16
9866#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_LBN 23
9867#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_FWDEF1_WIDTH 1
9868#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16
9869#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
9870#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
9871#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16
9872#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
9873#define MC_CMD_FILTER_OP_EXT_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
9874#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
9875#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
9876#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
9877#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
9878#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
9879#define MC_CMD_FILTER_OP_EXT_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
9880/* receive destination */
9881#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20
9882#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
9883/* enum: drop packets */
9884#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
9885/* enum: receive to host */
9886#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
9887/* enum: receive to MC */
9888#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
9889/* enum: loop back to TXDP 0 */
9890#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
9891/* enum: loop back to TXDP 1 */
9892#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
9893/* receive queue handle (for multiple queue modes, this is the base queue) */
9894#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24
9895#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
9896/* receive mode */
9897#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28
9898#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
9899/* enum: receive to just the specified queue */
9900#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
9901/* enum: receive to multiple queues using RSS context */
9902#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
9903/* enum: receive to multiple queues using .1p mapping */
9904#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
9905/* enum: install a filter entry that will never match; for test purposes only
9906 */
9907#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
9908/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
9909 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
9910 * MC_CMD_DOT1P_MAPPING_ALLOC.
9911 */
9912#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_OFST 32
9913#define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4
9914/* transmit domain (reserved; set to 0) */
9915#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_OFST 36
9916#define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4
9917/* transmit destination (either set the MAC and/or PM bits for explicit
9918 * control, or set this field to TX_DEST_DEFAULT for sensible default
9919 * behaviour)
9920 */
9921#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40
9922#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
9923/* enum: request default behaviour (based on filter type) */
9924#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
9925#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_OFST 40
9926#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
9927#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
9928#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_OFST 40
9929#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
9930#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_WIDTH 1
9931/* source MAC address to match (as bytes in network order) */
9932#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_OFST 44
9933#define MC_CMD_FILTER_OP_EXT_IN_SRC_MAC_LEN 6
9934/* source port to match (as bytes in network order) */
9935#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_OFST 50
9936#define MC_CMD_FILTER_OP_EXT_IN_SRC_PORT_LEN 2
9937/* destination MAC address to match (as bytes in network order) */
9938#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_OFST 52
9939#define MC_CMD_FILTER_OP_EXT_IN_DST_MAC_LEN 6
9940/* destination port to match (as bytes in network order) */
9941#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_OFST 58
9942#define MC_CMD_FILTER_OP_EXT_IN_DST_PORT_LEN 2
9943/* Ethernet type to match (as bytes in network order) */
9944#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_OFST 60
9945#define MC_CMD_FILTER_OP_EXT_IN_ETHER_TYPE_LEN 2
9946/* Inner VLAN tag to match (as bytes in network order) */
9947#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_OFST 62
9948#define MC_CMD_FILTER_OP_EXT_IN_INNER_VLAN_LEN 2
9949/* Outer VLAN tag to match (as bytes in network order) */
9950#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_OFST 64
9951#define MC_CMD_FILTER_OP_EXT_IN_OUTER_VLAN_LEN 2
9952/* IP protocol to match (in low byte; set high byte to 0) */
9953#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_OFST 66
9954#define MC_CMD_FILTER_OP_EXT_IN_IP_PROTO_LEN 2
9955/* Firmware defined register 0 to match (reserved; set to 0) */
9956#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_OFST 68
9957#define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4
9958/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
9959 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
9960 * VXLAN/NVGRE, or 1 for Geneve)
9961 */
9962#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_OFST 72
9963#define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
9964#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_OFST 72
9965#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
9966#define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_WIDTH 24
9967#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_OFST 72
9968#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24
9969#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8
9970/* enum: Match VXLAN traffic with this VNI */
9971#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
9972/* enum: Match Geneve traffic with this VNI */
9973#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
9974/* enum: Reserved for experimental development use */
9975#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
9976#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_OFST 72
9977#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
9978#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24
9979#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_OFST 72
9980#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24
9981#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8
9982/* enum: Match NVGRE traffic with this VSID */
9983#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
9984/* source IP address to match (as bytes in network order; set last 12 bytes to
9985 * 0 for IPv4 address)
9986 */
9987#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_OFST 76
9988#define MC_CMD_FILTER_OP_EXT_IN_SRC_IP_LEN 16
9989/* destination IP address to match (as bytes in network order; set last 12
9990 * bytes to 0 for IPv4 address)
9991 */
9992#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_OFST 92
9993#define MC_CMD_FILTER_OP_EXT_IN_DST_IP_LEN 16
9994/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
9995 * order)
9996 */
9997#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_OFST 108
9998#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_MAC_LEN 6
9999/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
10000#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_OFST 114
10001#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_PORT_LEN 2
10002/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
10003 * network order)
10004 */
10005#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_OFST 116
10006#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_MAC_LEN 6
10007/* VXLAN/NVGRE inner frame destination port to match (as bytes in network
10008 * order)
10009 */
10010#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_OFST 122
10011#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_PORT_LEN 2
10012/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
10013 */
10014#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_OFST 124
10015#define MC_CMD_FILTER_OP_EXT_IN_IFRM_ETHER_TYPE_LEN 2
10016/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
10017 */
10018#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_OFST 126
10019#define MC_CMD_FILTER_OP_EXT_IN_IFRM_INNER_VLAN_LEN 2
10020/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
10021 */
10022#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_OFST 128
10023#define MC_CMD_FILTER_OP_EXT_IN_IFRM_OUTER_VLAN_LEN 2
10024/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
10025 * 0)
10026 */
10027#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_OFST 130
10028#define MC_CMD_FILTER_OP_EXT_IN_IFRM_IP_PROTO_LEN 2
10029/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
10030 * to 0)
10031 */
10032#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_OFST 132
10033#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4
10034/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
10035 * to 0)
10036 */
10037#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_OFST 136
10038#define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4
10039/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
10040 * order; set last 12 bytes to 0 for IPv4 address)
10041 */
10042#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_OFST 140
10043#define MC_CMD_FILTER_OP_EXT_IN_IFRM_SRC_IP_LEN 16
10044/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
10045 * order; set last 12 bytes to 0 for IPv4 address)
10046 */
10047#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_OFST 156
10048#define MC_CMD_FILTER_OP_EXT_IN_IFRM_DST_IP_LEN 16
10049
10050/* MC_CMD_FILTER_OP_V3_IN msgrequest: FILTER_OP extension to support additional
10051 * filter actions for Intel's DPDK (Data Plane Development Kit, dpdk.org) via
10052 * its rte_flow API. This extension is only useful with the sfc_efx driver
10053 * included as part of DPDK, used in conjunction with the dpdk datapath
10054 * firmware variant.
10055 */
10056#define MC_CMD_FILTER_OP_V3_IN_LEN 180
10057/* identifies the type of operation requested */
10058#define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0
10059#define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4
10060/* Enum values, see field(s): */
10061/* MC_CMD_FILTER_OP_IN/OP */
10062/* filter handle (for remove / unsubscribe operations) */
10063#define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
10064#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LEN 8
10065#define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
10066#define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_OFST 8
10067/* The port ID associated with the v-adaptor which should contain this filter.
10068 */
10069#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_OFST 12
10070#define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4
10071/* fields to include in match criteria */
10072#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_OFST 16
10073#define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
10074#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_OFST 16
10075#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
10076#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_WIDTH 1
10077#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_OFST 16
10078#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_LBN 1
10079#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_IP_WIDTH 1
10080#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_OFST 16
10081#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_LBN 2
10082#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_MAC_WIDTH 1
10083#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_OFST 16
10084#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_LBN 3
10085#define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_PORT_WIDTH 1
10086#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_OFST 16
10087#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
10088#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_WIDTH 1
10089#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_OFST 16
10090#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_LBN 5
10091#define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_PORT_WIDTH 1
10092#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_OFST 16
10093#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_LBN 6
10094#define MC_CMD_FILTER_OP_V3_IN_MATCH_ETHER_TYPE_WIDTH 1
10095#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_OFST 16
10096#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_LBN 7
10097#define MC_CMD_FILTER_OP_V3_IN_MATCH_INNER_VLAN_WIDTH 1
10098#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_OFST 16
10099#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_LBN 8
10100#define MC_CMD_FILTER_OP_V3_IN_MATCH_OUTER_VLAN_WIDTH 1
10101#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_OFST 16
10102#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_LBN 9
10103#define MC_CMD_FILTER_OP_V3_IN_MATCH_IP_PROTO_WIDTH 1
10104#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_OFST 16
10105#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_LBN 10
10106#define MC_CMD_FILTER_OP_V3_IN_MATCH_FWDEF0_WIDTH 1
10107#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_OFST 16
10108#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_LBN 11
10109#define MC_CMD_FILTER_OP_V3_IN_MATCH_VNI_OR_VSID_WIDTH 1
10110#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_OFST 16
10111#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_LBN 12
10112#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_IP_WIDTH 1
10113#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_OFST 16
10114#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_LBN 13
10115#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_IP_WIDTH 1
10116#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_OFST 16
10117#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_LBN 14
10118#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_MAC_WIDTH 1
10119#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_OFST 16
10120#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_LBN 15
10121#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_SRC_PORT_WIDTH 1
10122#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_OFST 16
10123#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_LBN 16
10124#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_MAC_WIDTH 1
10125#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_OFST 16
10126#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_LBN 17
10127#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_DST_PORT_WIDTH 1
10128#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_OFST 16
10129#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_LBN 18
10130#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_ETHER_TYPE_WIDTH 1
10131#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_OFST 16
10132#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_LBN 19
10133#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_INNER_VLAN_WIDTH 1
10134#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_OFST 16
10135#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_LBN 20
10136#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_OUTER_VLAN_WIDTH 1
10137#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_OFST 16
10138#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_LBN 21
10139#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_IP_PROTO_WIDTH 1
10140#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_OFST 16
10141#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_LBN 22
10142#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF0_WIDTH 1
10143#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_OFST 16
10144#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_LBN 23
10145#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_FWDEF1_WIDTH 1
10146#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_OFST 16
10147#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_LBN 24
10148#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_MCAST_DST_WIDTH 1
10149#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_OFST 16
10150#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_LBN 25
10151#define MC_CMD_FILTER_OP_V3_IN_MATCH_IFRM_UNKNOWN_UCAST_DST_WIDTH 1
10152#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_OFST 16
10153#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
10154#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
10155#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_OFST 16
10156#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
10157#define MC_CMD_FILTER_OP_V3_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
10158/* receive destination */
10159#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20
10160#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
10161/* enum: drop packets */
10162#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
10163/* enum: receive to host */
10164#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
10165/* enum: receive to MC */
10166#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
10167/* enum: loop back to TXDP 0 */
10168#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
10169/* enum: loop back to TXDP 1 */
10170#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
10171/* receive queue handle (for multiple queue modes, this is the base queue) */
10172#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24
10173#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
10174/* receive mode */
10175#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28
10176#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
10177/* enum: receive to just the specified queue */
10178#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
10179/* enum: receive to multiple queues using RSS context */
10180#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
10181/* enum: receive to multiple queues using .1p mapping */
10182#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
10183/* enum: install a filter entry that will never match; for test purposes only
10184 */
10185#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
10186/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
10187 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
10188 * MC_CMD_DOT1P_MAPPING_ALLOC.
10189 */
10190#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_OFST 32
10191#define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4
10192/* transmit domain (reserved; set to 0) */
10193#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_OFST 36
10194#define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4
10195/* transmit destination (either set the MAC and/or PM bits for explicit
10196 * control, or set this field to TX_DEST_DEFAULT for sensible default
10197 * behaviour)
10198 */
10199#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40
10200#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
10201/* enum: request default behaviour (based on filter type) */
10202#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
10203#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_OFST 40
10204#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
10205#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1
10206#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_OFST 40
10207#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1
10208#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_WIDTH 1
10209/* source MAC address to match (as bytes in network order) */
10210#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_OFST 44
10211#define MC_CMD_FILTER_OP_V3_IN_SRC_MAC_LEN 6
10212/* source port to match (as bytes in network order) */
10213#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_OFST 50
10214#define MC_CMD_FILTER_OP_V3_IN_SRC_PORT_LEN 2
10215/* destination MAC address to match (as bytes in network order) */
10216#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_OFST 52
10217#define MC_CMD_FILTER_OP_V3_IN_DST_MAC_LEN 6
10218/* destination port to match (as bytes in network order) */
10219#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_OFST 58
10220#define MC_CMD_FILTER_OP_V3_IN_DST_PORT_LEN 2
10221/* Ethernet type to match (as bytes in network order) */
10222#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_OFST 60
10223#define MC_CMD_FILTER_OP_V3_IN_ETHER_TYPE_LEN 2
10224/* Inner VLAN tag to match (as bytes in network order) */
10225#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_OFST 62
10226#define MC_CMD_FILTER_OP_V3_IN_INNER_VLAN_LEN 2
10227/* Outer VLAN tag to match (as bytes in network order) */
10228#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_OFST 64
10229#define MC_CMD_FILTER_OP_V3_IN_OUTER_VLAN_LEN 2
10230/* IP protocol to match (in low byte; set high byte to 0) */
10231#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_OFST 66
10232#define MC_CMD_FILTER_OP_V3_IN_IP_PROTO_LEN 2
10233/* Firmware defined register 0 to match (reserved; set to 0) */
10234#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_OFST 68
10235#define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4
10236/* VNI (for VXLAN/Geneve, when IP protocol is UDP) or VSID (for NVGRE, when IP
10237 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
10238 * VXLAN/NVGRE, or 1 for Geneve)
10239 */
10240#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_OFST 72
10241#define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
10242#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_OFST 72
10243#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
10244#define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_WIDTH 24
10245#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_OFST 72
10246#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24
10247#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8
10248/* enum: Match VXLAN traffic with this VNI */
10249#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
10250/* enum: Match Geneve traffic with this VNI */
10251#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
10252/* enum: Reserved for experimental development use */
10253#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
10254#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_OFST 72
10255#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
10256#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24
10257#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_OFST 72
10258#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24
10259#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8
10260/* enum: Match NVGRE traffic with this VSID */
10261#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
10262/* source IP address to match (as bytes in network order; set last 12 bytes to
10263 * 0 for IPv4 address)
10264 */
10265#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_OFST 76
10266#define MC_CMD_FILTER_OP_V3_IN_SRC_IP_LEN 16
10267/* destination IP address to match (as bytes in network order; set last 12
10268 * bytes to 0 for IPv4 address)
10269 */
10270#define MC_CMD_FILTER_OP_V3_IN_DST_IP_OFST 92
10271#define MC_CMD_FILTER_OP_V3_IN_DST_IP_LEN 16
10272/* VXLAN/NVGRE inner frame source MAC address to match (as bytes in network
10273 * order)
10274 */
10275#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_OFST 108
10276#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_MAC_LEN 6
10277/* VXLAN/NVGRE inner frame source port to match (as bytes in network order) */
10278#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_OFST 114
10279#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_PORT_LEN 2
10280/* VXLAN/NVGRE inner frame destination MAC address to match (as bytes in
10281 * network order)
10282 */
10283#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_OFST 116
10284#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_MAC_LEN 6
10285/* VXLAN/NVGRE inner frame destination port to match (as bytes in network
10286 * order)
10287 */
10288#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_OFST 122
10289#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_PORT_LEN 2
10290/* VXLAN/NVGRE inner frame Ethernet type to match (as bytes in network order)
10291 */
10292#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_OFST 124
10293#define MC_CMD_FILTER_OP_V3_IN_IFRM_ETHER_TYPE_LEN 2
10294/* VXLAN/NVGRE inner frame Inner VLAN tag to match (as bytes in network order)
10295 */
10296#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_OFST 126
10297#define MC_CMD_FILTER_OP_V3_IN_IFRM_INNER_VLAN_LEN 2
10298/* VXLAN/NVGRE inner frame Outer VLAN tag to match (as bytes in network order)
10299 */
10300#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_OFST 128
10301#define MC_CMD_FILTER_OP_V3_IN_IFRM_OUTER_VLAN_LEN 2
10302/* VXLAN/NVGRE inner frame IP protocol to match (in low byte; set high byte to
10303 * 0)
10304 */
10305#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_OFST 130
10306#define MC_CMD_FILTER_OP_V3_IN_IFRM_IP_PROTO_LEN 2
10307/* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
10308 * to 0)
10309 */
10310#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_OFST 132
10311#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4
10312/* VXLAN/NVGRE inner frame Firmware defined register 1 to match (reserved; set
10313 * to 0)
10314 */
10315#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_OFST 136
10316#define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4
10317/* VXLAN/NVGRE inner frame source IP address to match (as bytes in network
10318 * order; set last 12 bytes to 0 for IPv4 address)
10319 */
10320#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_OFST 140
10321#define MC_CMD_FILTER_OP_V3_IN_IFRM_SRC_IP_LEN 16
10322/* VXLAN/NVGRE inner frame destination IP address to match (as bytes in network
10323 * order; set last 12 bytes to 0 for IPv4 address)
10324 */
10325#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_OFST 156
10326#define MC_CMD_FILTER_OP_V3_IN_IFRM_DST_IP_LEN 16
10327/* Set an action for all packets matching this filter. The DPDK driver and dpdk
10328 * f/w variant use their own specific delivery structures, which are documented
10329 * in the DPDK Firmware Driver Interface (SF-119419-TC). Requesting anything
10330 * other than MATCH_ACTION_NONE when the NIC is running another f/w variant
10331 * will cause the filter insertion to fail with ENOTSUP.
10332 */
10333#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172
10334#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
10335/* enum: do nothing extra */
10336#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
10337/* enum: Set the match flag in the packet prefix for packets matching the
10338 * filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
10339 * support the DPDK rte_flow "FLAG" action.
10340 */
10341#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
10342/* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching
10343 * the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
10344 * support the DPDK rte_flow "MARK" action.
10345 */
10346#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
10347/* the mark value for MATCH_ACTION_MARK. Requesting a value larger than the
10348 * maximum (obtained from MC_CMD_GET_CAPABILITIES_V5/FILTER_ACTION_MARK_MAX)
10349 * will cause the filter insertion to fail with EINVAL.
10350 */
10351#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176
10352#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
10353
10354/* MC_CMD_FILTER_OP_OUT msgresponse */
10355#define MC_CMD_FILTER_OP_OUT_LEN 12
10356/* identifies the type of operation requested */
10357#define MC_CMD_FILTER_OP_OUT_OP_OFST 0
10358#define MC_CMD_FILTER_OP_OUT_OP_LEN 4
10359/* Enum values, see field(s): */
10360/* MC_CMD_FILTER_OP_IN/OP */
10361/* Returned filter handle (for insert / subscribe operations). Note that these
10362 * handles should be considered opaque to the host, although a value of
10363 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
10364 */
10365#define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
10366#define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
10367#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
10368#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
10369/* enum: guaranteed invalid filter handle (low 32 bits) */
10370#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
10371/* enum: guaranteed invalid filter handle (high 32 bits) */
10372#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
10373
10374/* MC_CMD_FILTER_OP_EXT_OUT msgresponse */
10375#define MC_CMD_FILTER_OP_EXT_OUT_LEN 12
10376/* identifies the type of operation requested */
10377#define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
10378#define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4
10379/* Enum values, see field(s): */
10380/* MC_CMD_FILTER_OP_EXT_IN/OP */
10381/* Returned filter handle (for insert / subscribe operations). Note that these
10382 * handles should be considered opaque to the host, although a value of
10383 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
10384 */
10385#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
10386#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LEN 8
10387#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
10388#define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_OFST 8
10389/* Enum values, see field(s): */
10390/* MC_CMD_FILTER_OP_OUT/HANDLE */
10391
10392
10393/***********************************/
10394/* MC_CMD_GET_PARSER_DISP_INFO
10395 * Get information related to the parser-dispatcher subsystem
10396 */
10397#define MC_CMD_GET_PARSER_DISP_INFO 0xe4
10398#undef MC_CMD_0xe4_PRIVILEGE_CTG
10399
10400#define MC_CMD_0xe4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10401
10402/* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */
10403#define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
10404/* identifies the type of operation requested */
10405#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
10406#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
10407/* enum: read the list of supported RX filter matches */
10408#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
10409/* enum: read flags indicating restrictions on filter insertion for the calling
10410 * client
10411 */
10412#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
10413/* enum: read properties relating to security rules (Medford-only; for use by
10414 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
10415 */
10416#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
10417/* enum: read the list of supported RX filter matches for VXLAN/NVGRE
10418 * encapsulated frames, which follow a different match sequence to normal
10419 * frames (Medford only)
10420 */
10421#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
10422/* enum: read the list of supported matches for the encapsulation detection
10423 * rules inserted by MC_CMD_VNIC_ENCAP_RULE_ADD. (ef100 and later)
10424 */
10425#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5
10426
10427/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
10428#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
10429#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252
10430#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX_MCDI2 1020
10431#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
10432#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
10433/* identifies the type of operation requested */
10434#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
10435#define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
10436/* Enum values, see field(s): */
10437/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
10438/* number of supported match types */
10439#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
10440#define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4
10441/* array of supported match types (valid MATCH_FIELDS values for
10442 * MC_CMD_FILTER_OP) sorted in decreasing priority order
10443 */
10444#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8
10445#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
10446#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
10447#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61
10448#define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253
10449
10450/* MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT msgresponse */
10451#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_LEN 8
10452/* identifies the type of operation requested */
10453#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
10454#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4
10455/* Enum values, see field(s): */
10456/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
10457/* bitfield of filter insertion restrictions */
10458#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
10459#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
10460#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4
10461#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
10462#define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_WIDTH 1
10463
10464/* MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT msgresponse: This response is
10465 * returned if a MC_CMD_GET_PARSER_DISP_INFO_IN request is sent with OP value
10466 * OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES. It contains information about the
10467 * supported match types that can be used in the encapsulation detection rules
10468 * inserted by MC_CMD_VNIC_ENCAP_RULE_ADD.
10469 */
10470#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMIN 8
10471#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX 252
10472#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LENMAX_MCDI2 1020
10473#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))
10474#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
10475/* The op code OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES is returned. */
10476#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 0
10477#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4
10478/* Enum values, see field(s): */
10479/* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
10480/* number of supported match types */
10481#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4
10482#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4
10483/* array of supported match types (valid MATCH_FLAGS values for
10484 * MC_CMD_VNIC_ENCAP_RULE_ADD) sorted in decreasing priority order
10485 */
10486#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_OFST 8
10487#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4
10488#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 0
10489#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM 61
10490#define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MAXNUM_MCDI2 253
10491
10492
10493/***********************************/
10494/* MC_CMD_GET_PORT_ASSIGNMENT
10495 * Get port assignment for current PCI function.
10496 */
10497#define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
10498#undef MC_CMD_0xb8_PRIVILEGE_CTG
10499
10500#define MC_CMD_0xb8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10501
10502/* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
10503#define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
10504
10505/* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
10506#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
10507/* Identifies the port assignment for this function. */
10508#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
10509#define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
10510
10511
10512/***********************************/
10513/* MC_CMD_SET_PORT_ASSIGNMENT
10514 * Set port assignment for current PCI function.
10515 */
10516#define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
10517#undef MC_CMD_0xb9_PRIVILEGE_CTG
10518
10519#define MC_CMD_0xb9_PRIVILEGE_CTG SRIOV_CTG_ADMIN
10520
10521/* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */
10522#define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
10523/* Identifies the port assignment for this function. */
10524#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
10525#define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4
10526
10527/* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */
10528#define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
10529
10530
10531/***********************************/
10532/* MC_CMD_ALLOC_VIS
10533 * Allocate VIs for current PCI function.
10534 */
10535#define MC_CMD_ALLOC_VIS 0x8b
10536#undef MC_CMD_0x8b_PRIVILEGE_CTG
10537
10538#define MC_CMD_0x8b_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10539
10540/* MC_CMD_ALLOC_VIS_IN msgrequest */
10541#define MC_CMD_ALLOC_VIS_IN_LEN 8
10542/* The minimum number of VIs that is acceptable */
10543#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
10544#define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4
10545/* The maximum number of VIs that would be useful */
10546#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
10547#define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
10548
10549/* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
10550 * Use extended version in new code.
10551 */
10552#define MC_CMD_ALLOC_VIS_OUT_LEN 8
10553/* The number of VIs allocated on this function */
10554#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
10555#define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4
10556/* The base absolute VI number allocated to this function. Required to
10557 * correctly interpret wakeup events.
10558 */
10559#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
10560#define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
10561
10562/* MC_CMD_ALLOC_VIS_EXT_OUT msgresponse */
10563#define MC_CMD_ALLOC_VIS_EXT_OUT_LEN 12
10564/* The number of VIs allocated on this function */
10565#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
10566#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4
10567/* The base absolute VI number allocated to this function. Required to
10568 * correctly interpret wakeup events.
10569 */
10570#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
10571#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4
10572/* Function's port vi_shift value (always 0 on Huntington) */
10573#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8
10574#define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
10575
10576
10577/***********************************/
10578/* MC_CMD_FREE_VIS
10579 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,
10580 * but not freed.
10581 */
10582#define MC_CMD_FREE_VIS 0x8c
10583#undef MC_CMD_0x8c_PRIVILEGE_CTG
10584
10585#define MC_CMD_0x8c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10586
10587/* MC_CMD_FREE_VIS_IN msgrequest */
10588#define MC_CMD_FREE_VIS_IN_LEN 0
10589
10590/* MC_CMD_FREE_VIS_OUT msgresponse */
10591#define MC_CMD_FREE_VIS_OUT_LEN 0
10592
10593
10594/***********************************/
10595/* MC_CMD_GET_SRIOV_CFG
10596 * Get SRIOV config for this PF.
10597 */
10598#define MC_CMD_GET_SRIOV_CFG 0xba
10599#undef MC_CMD_0xba_PRIVILEGE_CTG
10600
10601#define MC_CMD_0xba_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10602
10603/* MC_CMD_GET_SRIOV_CFG_IN msgrequest */
10604#define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
10605
10606/* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */
10607#define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20
10608/* Number of VFs currently enabled. */
10609#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
10610#define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4
10611/* Max number of VFs before sriov stride and offset may need to be changed. */
10612#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
10613#define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
10614#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
10615#define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
10616#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_OFST 8
10617#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
10618#define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
10619/* RID offset of first VF from PF. */
10620#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12
10621#define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4
10622/* RID offset of each subsequent VF from the previous. */
10623#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16
10624#define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
10625
10626
10627/***********************************/
10628/* MC_CMD_SET_SRIOV_CFG
10629 * Set SRIOV config for this PF.
10630 */
10631#define MC_CMD_SET_SRIOV_CFG 0xbb
10632#undef MC_CMD_0xbb_PRIVILEGE_CTG
10633
10634#define MC_CMD_0xbb_PRIVILEGE_CTG SRIOV_CTG_ADMIN
10635
10636/* MC_CMD_SET_SRIOV_CFG_IN msgrequest */
10637#define MC_CMD_SET_SRIOV_CFG_IN_LEN 20
10638/* Number of VFs currently enabled. */
10639#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
10640#define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4
10641/* Max number of VFs before sriov stride and offset may need to be changed. */
10642#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
10643#define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4
10644#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8
10645#define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4
10646#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_OFST 8
10647#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
10648#define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
10649/* RID offset of first VF from PF, or 0 for no change, or
10650 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.
10651 */
10652#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12
10653#define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4
10654/* RID offset of each subsequent VF from the previous, 0 for no change, or
10655 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.
10656 */
10657#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16
10658#define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4
10659
10660/* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */
10661#define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
10662
10663
10664/***********************************/
10665/* MC_CMD_GET_VI_ALLOC_INFO
10666 * Get information about number of VI's and base VI number allocated to this
10667 * function.
10668 */
10669#define MC_CMD_GET_VI_ALLOC_INFO 0x8d
10670#undef MC_CMD_0x8d_PRIVILEGE_CTG
10671
10672#define MC_CMD_0x8d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10673
10674/* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */
10675#define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
10676
10677/* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */
10678#define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 12
10679/* The number of VIs allocated on this function */
10680#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
10681#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4
10682/* The base absolute VI number allocated to this function. Required to
10683 * correctly interpret wakeup events.
10684 */
10685#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
10686#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4
10687/* Function's port vi_shift value (always 0 on Huntington) */
10688#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8
10689#define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4
10690
10691
10692/***********************************/
10693/* MC_CMD_DUMP_VI_STATE
10694 * For CmdClient use. Dump pertinent information on a specific absolute VI.
10695 */
10696#define MC_CMD_DUMP_VI_STATE 0x8e
10697#undef MC_CMD_0x8e_PRIVILEGE_CTG
10698
10699#define MC_CMD_0x8e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10700
10701/* MC_CMD_DUMP_VI_STATE_IN msgrequest */
10702#define MC_CMD_DUMP_VI_STATE_IN_LEN 4
10703/* The VI number to query. */
10704#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
10705#define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
10706
10707/* MC_CMD_DUMP_VI_STATE_OUT msgresponse */
10708#define MC_CMD_DUMP_VI_STATE_OUT_LEN 96
10709/* The PF part of the function owning this VI. */
10710#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
10711#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2
10712/* The VF part of the function owning this VI. */
10713#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2
10714#define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2
10715/* Base of VIs allocated to this function. */
10716#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
10717#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2
10718/* Count of VIs allocated to the owner function. */
10719#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6
10720#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2
10721/* Base interrupt vector allocated to this function. */
10722#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8
10723#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2
10724/* Number of interrupt vectors allocated to this function. */
10725#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10
10726#define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2
10727/* Raw evq ptr table data. */
10728#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12
10729#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8
10730#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12
10731#define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16
10732/* Raw evq timer table data. */
10733#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20
10734#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8
10735#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20
10736#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24
10737/* Combined metadata field. */
10738#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
10739#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
10740#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_OFST 28
10741#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
10742#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16
10743#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_OFST 28
10744#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16
10745#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8
10746#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_OFST 28
10747#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24
10748#define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8
10749/* TXDPCPU raw table data for queue. */
10750#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32
10751#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8
10752#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32
10753#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36
10754/* TXDPCPU raw table data for queue. */
10755#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40
10756#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8
10757#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40
10758#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44
10759/* TXDPCPU raw table data for queue. */
10760#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48
10761#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8
10762#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48
10763#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52
10764/* Combined metadata field. */
10765#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56
10766#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
10767#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
10768#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
10769#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_OFST 56
10770#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
10771#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
10772#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_OFST 56
10773#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16
10774#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8
10775#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_OFST 56
10776#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24
10777#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8
10778#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_OFST 56
10779#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32
10780#define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8
10781#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_OFST 56
10782#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40
10783#define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24
10784/* RXDPCPU raw table data for queue. */
10785#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64
10786#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8
10787#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64
10788#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68
10789/* RXDPCPU raw table data for queue. */
10790#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72
10791#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8
10792#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72
10793#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76
10794/* Reserved, currently 0. */
10795#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80
10796#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8
10797#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80
10798#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84
10799/* Combined metadata field. */
10800#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88
10801#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
10802#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
10803#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
10804#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_OFST 88
10805#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
10806#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
10807#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_OFST 88
10808#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16
10809#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8
10810#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_OFST 88
10811#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24
10812#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8
10813#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_OFST 88
10814#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
10815#define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
10816
10817
10818/***********************************/
10819/* MC_CMD_ALLOC_PIOBUF
10820 * Allocate a push I/O buffer for later use with a tx queue.
10821 */
10822#define MC_CMD_ALLOC_PIOBUF 0x8f
10823#undef MC_CMD_0x8f_PRIVILEGE_CTG
10824
10825#define MC_CMD_0x8f_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
10826
10827/* MC_CMD_ALLOC_PIOBUF_IN msgrequest */
10828#define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
10829
10830/* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */
10831#define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
10832/* Handle for allocated push I/O buffer. */
10833#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
10834#define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4
10835
10836
10837/***********************************/
10838/* MC_CMD_FREE_PIOBUF
10839 * Free a push I/O buffer.
10840 */
10841#define MC_CMD_FREE_PIOBUF 0x90
10842#undef MC_CMD_0x90_PRIVILEGE_CTG
10843
10844#define MC_CMD_0x90_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
10845
10846/* MC_CMD_FREE_PIOBUF_IN msgrequest */
10847#define MC_CMD_FREE_PIOBUF_IN_LEN 4
10848/* Handle for allocated push I/O buffer. */
10849#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
10850#define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
10851
10852/* MC_CMD_FREE_PIOBUF_OUT msgresponse */
10853#define MC_CMD_FREE_PIOBUF_OUT_LEN 0
10854
10855
10856/***********************************/
10857/* MC_CMD_GET_CAPABILITIES
10858 * Get device capabilities.
10859 *
10860 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to
10861 * reference inherent device capabilities as opposed to current NVRAM config.
10862 */
10863#define MC_CMD_GET_CAPABILITIES 0xbe
10864#undef MC_CMD_0xbe_PRIVILEGE_CTG
10865
10866#define MC_CMD_0xbe_PRIVILEGE_CTG SRIOV_CTG_GENERAL
10867
10868/* MC_CMD_GET_CAPABILITIES_IN msgrequest */
10869#define MC_CMD_GET_CAPABILITIES_IN_LEN 0
10870
10871/* MC_CMD_GET_CAPABILITIES_OUT msgresponse */
10872#define MC_CMD_GET_CAPABILITIES_OUT_LEN 20
10873/* First word of flags. */
10874#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
10875#define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
10876#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 0
10877#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3
10878#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1
10879#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 0
10880#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
10881#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1
10882#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 0
10883#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5
10884#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1
10885#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
10886#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
10887#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
10888#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 0
10889#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7
10890#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
10891#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 0
10892#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8
10893#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
10894#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 0
10895#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9
10896#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1
10897#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
10898#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
10899#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
10900#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
10901#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
10902#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
10903#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
10904#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
10905#define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
10906#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 0
10907#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13
10908#define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
10909#define MC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 0
10910#define MC_CMD_GET_CAPABILITIES_OUT_QBB_LBN 14
10911#define MC_CMD_GET_CAPABILITIES_OUT_QBB_WIDTH 1
10912#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
10913#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
10914#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
10915#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 0
10916#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN 16
10917#define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_WIDTH 1
10918#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 0
10919#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_LBN 17
10920#define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_WIDTH 1
10921#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 0
10922#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN 18
10923#define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_WIDTH 1
10924#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 0
10925#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19
10926#define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
10927#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 0
10928#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20
10929#define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
10930#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 0
10931#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21
10932#define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
10933#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 0
10934#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22
10935#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
10936#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 0
10937#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23
10938#define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
10939#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 0
10940#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24
10941#define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
10942#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 0
10943#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25
10944#define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
10945#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 0
10946#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26
10947#define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
10948#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 0
10949#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27
10950#define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
10951#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 0
10952#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_LBN 28
10953#define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_WIDTH 1
10954#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
10955#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
10956#define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
10957#define MC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 0
10958#define MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN 30
10959#define MC_CMD_GET_CAPABILITIES_OUT_EVB_WIDTH 1
10960#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 0
10961#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN 31
10962#define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_WIDTH 1
10963/* RxDPCPU firmware id. */
10964#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
10965#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2
10966/* enum: Standard RXDP firmware */
10967#define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
10968/* enum: Low latency RXDP firmware */
10969#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
10970/* enum: Packed stream RXDP firmware */
10971#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
10972/* enum: Rules engine RXDP firmware */
10973#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
10974/* enum: DPDK RXDP firmware */
10975#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
10976/* enum: BIST RXDP firmware */
10977#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
10978/* enum: RXDP Test firmware image 1 */
10979#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
10980/* enum: RXDP Test firmware image 2 */
10981#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
10982/* enum: RXDP Test firmware image 3 */
10983#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
10984/* enum: RXDP Test firmware image 4 */
10985#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
10986/* enum: RXDP Test firmware image 5 */
10987#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
10988/* enum: RXDP Test firmware image 6 */
10989#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
10990/* enum: RXDP Test firmware image 7 */
10991#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
10992/* enum: RXDP Test firmware image 8 */
10993#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
10994/* enum: RXDP Test firmware image 9 */
10995#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
10996/* enum: RXDP Test firmware image 10 */
10997#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
10998/* TxDPCPU firmware id. */
10999#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6
11000#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2
11001/* enum: Standard TXDP firmware */
11002#define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
11003/* enum: Low latency TXDP firmware */
11004#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
11005/* enum: High packet rate TXDP firmware */
11006#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
11007/* enum: Rules engine TXDP firmware */
11008#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
11009/* enum: DPDK TXDP firmware */
11010#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
11011/* enum: BIST TXDP firmware */
11012#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
11013/* enum: TXDP Test firmware image 1 */
11014#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
11015/* enum: TXDP Test firmware image 2 */
11016#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
11017/* enum: TXDP CSR bus test firmware */
11018#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
11019#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8
11020#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2
11021#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_OFST 8
11022#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
11023#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12
11024#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_OFST 8
11025#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12
11026#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
11027/* enum: reserved value - do not use (may indicate alternative interpretation
11028 * of REV field in future)
11029 */
11030#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
11031/* enum: Trivial RX PD firmware for early Huntington development (Huntington
11032 * development only)
11033 */
11034#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
11035/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
11036 */
11037#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11038/* enum: RX PD firmware with approximately Siena-compatible behaviour
11039 * (Huntington development only)
11040 */
11041#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
11042/* enum: Full featured RX PD production firmware */
11043#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
11044/* enum: (deprecated original name for the FULL_FEATURED variant) */
11045#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
11046/* enum: siena_compat variant RX PD firmware using PM rather than MAC
11047 * (Huntington development only)
11048 */
11049#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11050/* enum: Low latency RX PD production firmware */
11051#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
11052/* enum: Packed stream RX PD production firmware */
11053#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
11054/* enum: RX PD firmware handling layer 2 only for high packet rate performance
11055 * tests (Medford development only)
11056 */
11057#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
11058/* enum: Rules engine RX PD production firmware */
11059#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
11060/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11061#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
11062/* enum: DPDK RX PD production firmware */
11063#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
11064/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
11065#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11066/* enum: RX PD firmware parsing but not filtering network overlay tunnel
11067 * encapsulations (Medford development only)
11068 */
11069#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
11070#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10
11071#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2
11072#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_OFST 10
11073#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
11074#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12
11075#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_OFST 10
11076#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12
11077#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
11078/* enum: reserved value - do not use (may indicate alternative interpretation
11079 * of REV field in future)
11080 */
11081#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
11082/* enum: Trivial TX PD firmware for early Huntington development (Huntington
11083 * development only)
11084 */
11085#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
11086/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
11087 */
11088#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11089/* enum: TX PD firmware with approximately Siena-compatible behaviour
11090 * (Huntington development only)
11091 */
11092#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
11093/* enum: Full featured TX PD production firmware */
11094#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
11095/* enum: (deprecated original name for the FULL_FEATURED variant) */
11096#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
11097/* enum: siena_compat variant TX PD firmware using PM rather than MAC
11098 * (Huntington development only)
11099 */
11100#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11101#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
11102/* enum: TX PD firmware handling layer 2 only for high packet rate performance
11103 * tests (Medford development only)
11104 */
11105#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
11106/* enum: Rules engine TX PD production firmware */
11107#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
11108/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11109#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
11110/* enum: DPDK TX PD production firmware */
11111#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
11112/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
11113#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11114/* Hardware capabilities of NIC */
11115#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12
11116#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
11117/* Licensed capabilities */
11118#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16
11119#define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4
11120
11121/* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */
11122#define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
11123
11124/* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */
11125#define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 72
11126/* First word of flags. */
11127#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
11128#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
11129#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 0
11130#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3
11131#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1
11132#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 0
11133#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
11134#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1
11135#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 0
11136#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5
11137#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1
11138#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
11139#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
11140#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
11141#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 0
11142#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7
11143#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
11144#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 0
11145#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8
11146#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
11147#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 0
11148#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9
11149#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1
11150#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
11151#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
11152#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
11153#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
11154#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
11155#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
11156#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
11157#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
11158#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
11159#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 0
11160#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13
11161#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
11162#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 0
11163#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14
11164#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1
11165#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
11166#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
11167#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
11168#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 0
11169#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16
11170#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1
11171#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 0
11172#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17
11173#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1
11174#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 0
11175#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18
11176#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1
11177#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 0
11178#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19
11179#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1
11180#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 0
11181#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20
11182#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1
11183#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 0
11184#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21
11185#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1
11186#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 0
11187#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22
11188#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1
11189#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 0
11190#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23
11191#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1
11192#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 0
11193#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24
11194#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1
11195#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 0
11196#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25
11197#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1
11198#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 0
11199#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26
11200#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1
11201#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 0
11202#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27
11203#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
11204#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 0
11205#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28
11206#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1
11207#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
11208#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
11209#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
11210#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 0
11211#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30
11212#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1
11213#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 0
11214#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31
11215#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1
11216/* RxDPCPU firmware id. */
11217#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
11218#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2
11219/* enum: Standard RXDP firmware */
11220#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
11221/* enum: Low latency RXDP firmware */
11222#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
11223/* enum: Packed stream RXDP firmware */
11224#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
11225/* enum: Rules engine RXDP firmware */
11226#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
11227/* enum: DPDK RXDP firmware */
11228#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
11229/* enum: BIST RXDP firmware */
11230#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
11231/* enum: RXDP Test firmware image 1 */
11232#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
11233/* enum: RXDP Test firmware image 2 */
11234#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
11235/* enum: RXDP Test firmware image 3 */
11236#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
11237/* enum: RXDP Test firmware image 4 */
11238#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
11239/* enum: RXDP Test firmware image 5 */
11240#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
11241/* enum: RXDP Test firmware image 6 */
11242#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
11243/* enum: RXDP Test firmware image 7 */
11244#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
11245/* enum: RXDP Test firmware image 8 */
11246#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
11247/* enum: RXDP Test firmware image 9 */
11248#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
11249/* enum: RXDP Test firmware image 10 */
11250#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
11251/* TxDPCPU firmware id. */
11252#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6
11253#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2
11254/* enum: Standard TXDP firmware */
11255#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
11256/* enum: Low latency TXDP firmware */
11257#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
11258/* enum: High packet rate TXDP firmware */
11259#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
11260/* enum: Rules engine TXDP firmware */
11261#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
11262/* enum: DPDK TXDP firmware */
11263#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
11264/* enum: BIST TXDP firmware */
11265#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
11266/* enum: TXDP Test firmware image 1 */
11267#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
11268/* enum: TXDP Test firmware image 2 */
11269#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
11270/* enum: TXDP CSR bus test firmware */
11271#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
11272#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8
11273#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2
11274#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_OFST 8
11275#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
11276#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12
11277#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_OFST 8
11278#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12
11279#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
11280/* enum: reserved value - do not use (may indicate alternative interpretation
11281 * of REV field in future)
11282 */
11283#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
11284/* enum: Trivial RX PD firmware for early Huntington development (Huntington
11285 * development only)
11286 */
11287#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
11288/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
11289 */
11290#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11291/* enum: RX PD firmware with approximately Siena-compatible behaviour
11292 * (Huntington development only)
11293 */
11294#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
11295/* enum: Full featured RX PD production firmware */
11296#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
11297/* enum: (deprecated original name for the FULL_FEATURED variant) */
11298#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
11299/* enum: siena_compat variant RX PD firmware using PM rather than MAC
11300 * (Huntington development only)
11301 */
11302#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11303/* enum: Low latency RX PD production firmware */
11304#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
11305/* enum: Packed stream RX PD production firmware */
11306#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
11307/* enum: RX PD firmware handling layer 2 only for high packet rate performance
11308 * tests (Medford development only)
11309 */
11310#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
11311/* enum: Rules engine RX PD production firmware */
11312#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
11313/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11314#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
11315/* enum: DPDK RX PD production firmware */
11316#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
11317/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
11318#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11319/* enum: RX PD firmware parsing but not filtering network overlay tunnel
11320 * encapsulations (Medford development only)
11321 */
11322#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
11323#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10
11324#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2
11325#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_OFST 10
11326#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
11327#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12
11328#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_OFST 10
11329#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12
11330#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
11331/* enum: reserved value - do not use (may indicate alternative interpretation
11332 * of REV field in future)
11333 */
11334#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
11335/* enum: Trivial TX PD firmware for early Huntington development (Huntington
11336 * development only)
11337 */
11338#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
11339/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
11340 */
11341#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11342/* enum: TX PD firmware with approximately Siena-compatible behaviour
11343 * (Huntington development only)
11344 */
11345#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
11346/* enum: Full featured TX PD production firmware */
11347#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
11348/* enum: (deprecated original name for the FULL_FEATURED variant) */
11349#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
11350/* enum: siena_compat variant TX PD firmware using PM rather than MAC
11351 * (Huntington development only)
11352 */
11353#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11354#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
11355/* enum: TX PD firmware handling layer 2 only for high packet rate performance
11356 * tests (Medford development only)
11357 */
11358#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
11359/* enum: Rules engine TX PD production firmware */
11360#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
11361/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11362#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
11363/* enum: DPDK TX PD production firmware */
11364#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
11365/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
11366#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11367/* Hardware capabilities of NIC */
11368#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12
11369#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
11370/* Licensed capabilities */
11371#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16
11372#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4
11373/* Second word of flags. Not present on older firmware (check the length). */
11374#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20
11375#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
11376#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_OFST 20
11377#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
11378#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1
11379#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_OFST 20
11380#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1
11381#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1
11382#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_OFST 20
11383#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_LBN 2
11384#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVQ_TIMER_CTRL_WIDTH 1
11385#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_OFST 20
11386#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_LBN 3
11387#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVENT_CUT_THROUGH_WIDTH 1
11388#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_OFST 20
11389#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
11390#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_WIDTH 1
11391#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_OFST 20
11392#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_LBN 5
11393#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
11394#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
11395#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
11396#define MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
11397#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
11398#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
11399#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
11400#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_OFST 20
11401#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN 7
11402#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_WIDTH 1
11403#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_OFST 20
11404#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_LBN 8
11405#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
11406#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_OFST 20
11407#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_LBN 9
11408#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TIMESTAMP_WIDTH 1
11409#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_OFST 20
11410#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_LBN 10
11411#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_SNIFF_WIDTH 1
11412#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_OFST 20
11413#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_LBN 11
11414#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_SNIFF_WIDTH 1
11415#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
11416#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
11417#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
11418#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_OFST 20
11419#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_LBN 13
11420#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_BACKGROUND_WIDTH 1
11421#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_OFST 20
11422#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_LBN 14
11423#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCDI_DB_RETURN_WIDTH 1
11424#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_OFST 20
11425#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_LBN 15
11426#define MC_CMD_GET_CAPABILITIES_V2_OUT_CTPIO_WIDTH 1
11427#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_OFST 20
11428#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_LBN 16
11429#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_SUPPORT_WIDTH 1
11430#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_OFST 20
11431#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_LBN 17
11432#define MC_CMD_GET_CAPABILITIES_V2_OUT_TSA_BOUND_WIDTH 1
11433#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
11434#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
11435#define MC_CMD_GET_CAPABILITIES_V2_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
11436#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_OFST 20
11437#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_LBN 19
11438#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_FLAG_WIDTH 1
11439#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_OFST 20
11440#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_LBN 20
11441#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1
11442#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
11443#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
11444#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
11445#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
11446#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
11447#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
11448#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_OFST 20
11449#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22
11450#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1
11451#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
11452#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
11453#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
11454#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_OFST 20
11455#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_LBN 24
11456#define MC_CMD_GET_CAPABILITIES_V2_OUT_VI_SPREADING_WIDTH 1
11457#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_OFST 20
11458#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_LBN 25
11459#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_HLB_IDLE_WIDTH 1
11460#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
11461#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
11462#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
11463#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
11464#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
11465#define MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
11466#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_OFST 20
11467#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_LBN 28
11468#define MC_CMD_GET_CAPABILITIES_V2_OUT_BUNDLE_UPDATE_WIDTH 1
11469#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_OFST 20
11470#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_LBN 29
11471#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V3_WIDTH 1
11472#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_OFST 20
11473#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_LBN 30
11474#define MC_CMD_GET_CAPABILITIES_V2_OUT_DYNAMIC_SENSORS_WIDTH 1
11475#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
11476#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
11477#define MC_CMD_GET_CAPABILITIES_V2_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
11478/* Number of FATSOv2 contexts per datapath supported by this NIC (when
11479 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
11480 */
11481#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
11482#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
11483/* One byte per PF containing the number of the external port assigned to this
11484 * PF, indexed by PF number. Special values indicate that a PF is either not
11485 * present or not assigned.
11486 */
11487#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
11488#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
11489#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
11490/* enum: The caller is not permitted to access information on this PF. */
11491#define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
11492/* enum: PF does not exist. */
11493#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
11494/* enum: PF does exist but is not assigned to any external port. */
11495#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
11496/* enum: This value indicates that PF is assigned, but it cannot be expressed
11497 * in this field. It is intended for a possible future situation where a more
11498 * complex scheme of PFs to ports mapping is being used. The future driver
11499 * should look for a new field supporting the new scheme. The current/old
11500 * driver should treat this value as PF_NOT_ASSIGNED.
11501 */
11502#define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
11503/* One byte per PF containing the number of its VFs, indexed by PF number. A
11504 * special value indicates that a PF is not present.
11505 */
11506#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_OFST 42
11507#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1
11508#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16
11509/* enum: The caller is not permitted to access information on this PF. */
11510/* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
11511/* enum: PF does not exist. */
11512/* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
11513/* Number of VIs available for each external port */
11514#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58
11515#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2
11516#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
11517/* Size of RX descriptor cache expressed as binary logarithm The actual size
11518 * equals (2 ^ RX_DESC_CACHE_SIZE)
11519 */
11520#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_OFST 66
11521#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DESC_CACHE_SIZE_LEN 1
11522/* Size of TX descriptor cache expressed as binary logarithm The actual size
11523 * equals (2 ^ TX_DESC_CACHE_SIZE)
11524 */
11525#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_OFST 67
11526#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DESC_CACHE_SIZE_LEN 1
11527/* Total number of available PIO buffers */
11528#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_OFST 68
11529#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_PIO_BUFFS_LEN 2
11530/* Size of a single PIO buffer */
11531#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_OFST 70
11532#define MC_CMD_GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF_LEN 2
11533
11534/* MC_CMD_GET_CAPABILITIES_V3_OUT msgresponse */
11535#define MC_CMD_GET_CAPABILITIES_V3_OUT_LEN 76
11536/* First word of flags. */
11537#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
11538#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
11539#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 0
11540#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_LBN 3
11541#define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_WIDTH 1
11542#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 0
11543#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
11544#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_WIDTH 1
11545#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 0
11546#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_LBN 5
11547#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_WIDTH 1
11548#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
11549#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
11550#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
11551#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 0
11552#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_LBN 7
11553#define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
11554#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 0
11555#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_LBN 8
11556#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
11557#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 0
11558#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_LBN 9
11559#define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_WIDTH 1
11560#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
11561#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
11562#define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
11563#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
11564#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
11565#define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
11566#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
11567#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
11568#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
11569#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 0
11570#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_LBN 13
11571#define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
11572#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 0
11573#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_LBN 14
11574#define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_WIDTH 1
11575#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
11576#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
11577#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
11578#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 0
11579#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_LBN 16
11580#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_WIDTH 1
11581#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 0
11582#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_LBN 17
11583#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_WIDTH 1
11584#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 0
11585#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_LBN 18
11586#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_WIDTH 1
11587#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 0
11588#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_LBN 19
11589#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_WIDTH 1
11590#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 0
11591#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_LBN 20
11592#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_WIDTH 1
11593#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 0
11594#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_LBN 21
11595#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_WIDTH 1
11596#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 0
11597#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_LBN 22
11598#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_WIDTH 1
11599#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 0
11600#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_LBN 23
11601#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_WIDTH 1
11602#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 0
11603#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_LBN 24
11604#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_WIDTH 1
11605#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 0
11606#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_LBN 25
11607#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_WIDTH 1
11608#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 0
11609#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_LBN 26
11610#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_WIDTH 1
11611#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 0
11612#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_LBN 27
11613#define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
11614#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 0
11615#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_LBN 28
11616#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_WIDTH 1
11617#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
11618#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
11619#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
11620#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 0
11621#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_LBN 30
11622#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_WIDTH 1
11623#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 0
11624#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_LBN 31
11625#define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_WIDTH 1
11626/* RxDPCPU firmware id. */
11627#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
11628#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2
11629/* enum: Standard RXDP firmware */
11630#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
11631/* enum: Low latency RXDP firmware */
11632#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
11633/* enum: Packed stream RXDP firmware */
11634#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
11635/* enum: Rules engine RXDP firmware */
11636#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
11637/* enum: DPDK RXDP firmware */
11638#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
11639/* enum: BIST RXDP firmware */
11640#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
11641/* enum: RXDP Test firmware image 1 */
11642#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
11643/* enum: RXDP Test firmware image 2 */
11644#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
11645/* enum: RXDP Test firmware image 3 */
11646#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
11647/* enum: RXDP Test firmware image 4 */
11648#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
11649/* enum: RXDP Test firmware image 5 */
11650#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
11651/* enum: RXDP Test firmware image 6 */
11652#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
11653/* enum: RXDP Test firmware image 7 */
11654#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
11655/* enum: RXDP Test firmware image 8 */
11656#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
11657/* enum: RXDP Test firmware image 9 */
11658#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
11659/* enum: RXDP Test firmware image 10 */
11660#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
11661/* TxDPCPU firmware id. */
11662#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6
11663#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2
11664/* enum: Standard TXDP firmware */
11665#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
11666/* enum: Low latency TXDP firmware */
11667#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
11668/* enum: High packet rate TXDP firmware */
11669#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
11670/* enum: Rules engine TXDP firmware */
11671#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
11672/* enum: DPDK TXDP firmware */
11673#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
11674/* enum: BIST TXDP firmware */
11675#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
11676/* enum: TXDP Test firmware image 1 */
11677#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
11678/* enum: TXDP Test firmware image 2 */
11679#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
11680/* enum: TXDP CSR bus test firmware */
11681#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
11682#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8
11683#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2
11684#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_OFST 8
11685#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
11686#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_WIDTH 12
11687#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_OFST 8
11688#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_LBN 12
11689#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
11690/* enum: reserved value - do not use (may indicate alternative interpretation
11691 * of REV field in future)
11692 */
11693#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
11694/* enum: Trivial RX PD firmware for early Huntington development (Huntington
11695 * development only)
11696 */
11697#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
11698/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
11699 */
11700#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11701/* enum: RX PD firmware with approximately Siena-compatible behaviour
11702 * (Huntington development only)
11703 */
11704#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
11705/* enum: Full featured RX PD production firmware */
11706#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
11707/* enum: (deprecated original name for the FULL_FEATURED variant) */
11708#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
11709/* enum: siena_compat variant RX PD firmware using PM rather than MAC
11710 * (Huntington development only)
11711 */
11712#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11713/* enum: Low latency RX PD production firmware */
11714#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
11715/* enum: Packed stream RX PD production firmware */
11716#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
11717/* enum: RX PD firmware handling layer 2 only for high packet rate performance
11718 * tests (Medford development only)
11719 */
11720#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
11721/* enum: Rules engine RX PD production firmware */
11722#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
11723/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11724#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
11725/* enum: DPDK RX PD production firmware */
11726#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
11727/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
11728#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11729/* enum: RX PD firmware parsing but not filtering network overlay tunnel
11730 * encapsulations (Medford development only)
11731 */
11732#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
11733#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10
11734#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2
11735#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_OFST 10
11736#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
11737#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_WIDTH 12
11738#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_OFST 10
11739#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_LBN 12
11740#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
11741/* enum: reserved value - do not use (may indicate alternative interpretation
11742 * of REV field in future)
11743 */
11744#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
11745/* enum: Trivial TX PD firmware for early Huntington development (Huntington
11746 * development only)
11747 */
11748#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
11749/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
11750 */
11751#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
11752/* enum: TX PD firmware with approximately Siena-compatible behaviour
11753 * (Huntington development only)
11754 */
11755#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
11756/* enum: Full featured TX PD production firmware */
11757#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
11758/* enum: (deprecated original name for the FULL_FEATURED variant) */
11759#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
11760/* enum: siena_compat variant TX PD firmware using PM rather than MAC
11761 * (Huntington development only)
11762 */
11763#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
11764#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
11765/* enum: TX PD firmware handling layer 2 only for high packet rate performance
11766 * tests (Medford development only)
11767 */
11768#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
11769/* enum: Rules engine TX PD production firmware */
11770#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
11771/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
11772#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
11773/* enum: DPDK TX PD production firmware */
11774#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
11775/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
11776#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
11777/* Hardware capabilities of NIC */
11778#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12
11779#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
11780/* Licensed capabilities */
11781#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_OFST 16
11782#define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4
11783/* Second word of flags. Not present on older firmware (check the length). */
11784#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_OFST 20
11785#define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
11786#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_OFST 20
11787#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
11788#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_WIDTH 1
11789#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_OFST 20
11790#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_LBN 1
11791#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_ENCAP_WIDTH 1
11792#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_OFST 20
11793#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_LBN 2
11794#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVQ_TIMER_CTRL_WIDTH 1
11795#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_OFST 20
11796#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_LBN 3
11797#define MC_CMD_GET_CAPABILITIES_V3_OUT_EVENT_CUT_THROUGH_WIDTH 1
11798#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_OFST 20
11799#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
11800#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_WIDTH 1
11801#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_OFST 20
11802#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_LBN 5
11803#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
11804#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
11805#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
11806#define MC_CMD_GET_CAPABILITIES_V3_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
11807#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
11808#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
11809#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
11810#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_OFST 20
11811#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_LBN 7
11812#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_EVQ_V2_WIDTH 1
11813#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_OFST 20
11814#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_LBN 8
11815#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
11816#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_OFST 20
11817#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_LBN 9
11818#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TIMESTAMP_WIDTH 1
11819#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_OFST 20
11820#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_LBN 10
11821#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_SNIFF_WIDTH 1
11822#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_OFST 20
11823#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_LBN 11
11824#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_SNIFF_WIDTH 1
11825#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
11826#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
11827#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
11828#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_OFST 20
11829#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_LBN 13
11830#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_BACKGROUND_WIDTH 1
11831#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_OFST 20
11832#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_LBN 14
11833#define MC_CMD_GET_CAPABILITIES_V3_OUT_MCDI_DB_RETURN_WIDTH 1
11834#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_OFST 20
11835#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_LBN 15
11836#define MC_CMD_GET_CAPABILITIES_V3_OUT_CTPIO_WIDTH 1
11837#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_OFST 20
11838#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_LBN 16
11839#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_SUPPORT_WIDTH 1
11840#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_OFST 20
11841#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_LBN 17
11842#define MC_CMD_GET_CAPABILITIES_V3_OUT_TSA_BOUND_WIDTH 1
11843#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
11844#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
11845#define MC_CMD_GET_CAPABILITIES_V3_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
11846#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_OFST 20
11847#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_LBN 19
11848#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_FLAG_WIDTH 1
11849#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_OFST 20
11850#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_LBN 20
11851#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1
11852#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
11853#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
11854#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
11855#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
11856#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
11857#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
11858#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_OFST 20
11859#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22
11860#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1
11861#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
11862#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
11863#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
11864#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_OFST 20
11865#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_LBN 24
11866#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_SPREADING_WIDTH 1
11867#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_OFST 20
11868#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_LBN 25
11869#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_HLB_IDLE_WIDTH 1
11870#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
11871#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
11872#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
11873#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
11874#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
11875#define MC_CMD_GET_CAPABILITIES_V3_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
11876#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_OFST 20
11877#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_LBN 28
11878#define MC_CMD_GET_CAPABILITIES_V3_OUT_BUNDLE_UPDATE_WIDTH 1
11879#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_OFST 20
11880#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_LBN 29
11881#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V3_WIDTH 1
11882#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_OFST 20
11883#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_LBN 30
11884#define MC_CMD_GET_CAPABILITIES_V3_OUT_DYNAMIC_SENSORS_WIDTH 1
11885#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
11886#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
11887#define MC_CMD_GET_CAPABILITIES_V3_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
11888/* Number of FATSOv2 contexts per datapath supported by this NIC (when
11889 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
11890 */
11891#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
11892#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
11893/* One byte per PF containing the number of the external port assigned to this
11894 * PF, indexed by PF number. Special values indicate that a PF is either not
11895 * present or not assigned.
11896 */
11897#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
11898#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
11899#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
11900/* enum: The caller is not permitted to access information on this PF. */
11901#define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
11902/* enum: PF does not exist. */
11903#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
11904/* enum: PF does exist but is not assigned to any external port. */
11905#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
11906/* enum: This value indicates that PF is assigned, but it cannot be expressed
11907 * in this field. It is intended for a possible future situation where a more
11908 * complex scheme of PFs to ports mapping is being used. The future driver
11909 * should look for a new field supporting the new scheme. The current/old
11910 * driver should treat this value as PF_NOT_ASSIGNED.
11911 */
11912#define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
11913/* One byte per PF containing the number of its VFs, indexed by PF number. A
11914 * special value indicates that a PF is not present.
11915 */
11916#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_OFST 42
11917#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1
11918#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16
11919/* enum: The caller is not permitted to access information on this PF. */
11920/* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
11921/* enum: PF does not exist. */
11922/* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
11923/* Number of VIs available for each external port */
11924#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58
11925#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2
11926#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
11927/* Size of RX descriptor cache expressed as binary logarithm The actual size
11928 * equals (2 ^ RX_DESC_CACHE_SIZE)
11929 */
11930#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_OFST 66
11931#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DESC_CACHE_SIZE_LEN 1
11932/* Size of TX descriptor cache expressed as binary logarithm The actual size
11933 * equals (2 ^ TX_DESC_CACHE_SIZE)
11934 */
11935#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_OFST 67
11936#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DESC_CACHE_SIZE_LEN 1
11937/* Total number of available PIO buffers */
11938#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_OFST 68
11939#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_PIO_BUFFS_LEN 2
11940/* Size of a single PIO buffer */
11941#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_OFST 70
11942#define MC_CMD_GET_CAPABILITIES_V3_OUT_SIZE_PIO_BUFF_LEN 2
11943/* On chips later than Medford the amount of address space assigned to each VI
11944 * is configurable. This is a global setting that the driver must query to
11945 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
11946 * with 8k VI windows.
11947 */
11948#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_OFST 72
11949#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_LEN 1
11950/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
11951 * CTPIO is not mapped.
11952 */
11953#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
11954/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
11955#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
11956/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
11957#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
11958/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
11959 * (SF-115995-SW) in the present configuration of firmware and port mode.
11960 */
11961#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
11962#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
11963/* Number of buffers per adapter that can be used for VFIFO Stuffing
11964 * (SF-115995-SW) in the present configuration of firmware and port mode.
11965 */
11966#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
11967#define MC_CMD_GET_CAPABILITIES_V3_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
11968
11969/* MC_CMD_GET_CAPABILITIES_V4_OUT msgresponse */
11970#define MC_CMD_GET_CAPABILITIES_V4_OUT_LEN 78
11971/* First word of flags. */
11972#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
11973#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
11974#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 0
11975#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_LBN 3
11976#define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_WIDTH 1
11977#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 0
11978#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
11979#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_WIDTH 1
11980#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 0
11981#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_LBN 5
11982#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_WIDTH 1
11983#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
11984#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
11985#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
11986#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 0
11987#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_LBN 7
11988#define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
11989#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 0
11990#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_LBN 8
11991#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
11992#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 0
11993#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_LBN 9
11994#define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_WIDTH 1
11995#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
11996#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
11997#define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
11998#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
11999#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
12000#define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
12001#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
12002#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
12003#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
12004#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 0
12005#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_LBN 13
12006#define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
12007#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 0
12008#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_LBN 14
12009#define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_WIDTH 1
12010#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
12011#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
12012#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
12013#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 0
12014#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_LBN 16
12015#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_WIDTH 1
12016#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 0
12017#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_LBN 17
12018#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_WIDTH 1
12019#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 0
12020#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_LBN 18
12021#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_WIDTH 1
12022#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 0
12023#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_LBN 19
12024#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_WIDTH 1
12025#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 0
12026#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_LBN 20
12027#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_WIDTH 1
12028#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 0
12029#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_LBN 21
12030#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_WIDTH 1
12031#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 0
12032#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_LBN 22
12033#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_WIDTH 1
12034#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 0
12035#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_LBN 23
12036#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_WIDTH 1
12037#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 0
12038#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_LBN 24
12039#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_WIDTH 1
12040#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 0
12041#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_LBN 25
12042#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_WIDTH 1
12043#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 0
12044#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_LBN 26
12045#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_WIDTH 1
12046#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 0
12047#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_LBN 27
12048#define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
12049#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 0
12050#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_LBN 28
12051#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_WIDTH 1
12052#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
12053#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
12054#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
12055#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 0
12056#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_LBN 30
12057#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_WIDTH 1
12058#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 0
12059#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_LBN 31
12060#define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_WIDTH 1
12061/* RxDPCPU firmware id. */
12062#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
12063#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2
12064/* enum: Standard RXDP firmware */
12065#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
12066/* enum: Low latency RXDP firmware */
12067#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
12068/* enum: Packed stream RXDP firmware */
12069#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
12070/* enum: Rules engine RXDP firmware */
12071#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
12072/* enum: DPDK RXDP firmware */
12073#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
12074/* enum: BIST RXDP firmware */
12075#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
12076/* enum: RXDP Test firmware image 1 */
12077#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
12078/* enum: RXDP Test firmware image 2 */
12079#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
12080/* enum: RXDP Test firmware image 3 */
12081#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
12082/* enum: RXDP Test firmware image 4 */
12083#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
12084/* enum: RXDP Test firmware image 5 */
12085#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
12086/* enum: RXDP Test firmware image 6 */
12087#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
12088/* enum: RXDP Test firmware image 7 */
12089#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
12090/* enum: RXDP Test firmware image 8 */
12091#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
12092/* enum: RXDP Test firmware image 9 */
12093#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
12094/* enum: RXDP Test firmware image 10 */
12095#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
12096/* TxDPCPU firmware id. */
12097#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6
12098#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2
12099/* enum: Standard TXDP firmware */
12100#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
12101/* enum: Low latency TXDP firmware */
12102#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
12103/* enum: High packet rate TXDP firmware */
12104#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
12105/* enum: Rules engine TXDP firmware */
12106#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
12107/* enum: DPDK TXDP firmware */
12108#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
12109/* enum: BIST TXDP firmware */
12110#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
12111/* enum: TXDP Test firmware image 1 */
12112#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
12113/* enum: TXDP Test firmware image 2 */
12114#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
12115/* enum: TXDP CSR bus test firmware */
12116#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
12117#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8
12118#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2
12119#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_OFST 8
12120#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
12121#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_WIDTH 12
12122#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_OFST 8
12123#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_LBN 12
12124#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
12125/* enum: reserved value - do not use (may indicate alternative interpretation
12126 * of REV field in future)
12127 */
12128#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
12129/* enum: Trivial RX PD firmware for early Huntington development (Huntington
12130 * development only)
12131 */
12132#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
12133/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
12134 */
12135#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
12136/* enum: RX PD firmware with approximately Siena-compatible behaviour
12137 * (Huntington development only)
12138 */
12139#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
12140/* enum: Full featured RX PD production firmware */
12141#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
12142/* enum: (deprecated original name for the FULL_FEATURED variant) */
12143#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
12144/* enum: siena_compat variant RX PD firmware using PM rather than MAC
12145 * (Huntington development only)
12146 */
12147#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
12148/* enum: Low latency RX PD production firmware */
12149#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
12150/* enum: Packed stream RX PD production firmware */
12151#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
12152/* enum: RX PD firmware handling layer 2 only for high packet rate performance
12153 * tests (Medford development only)
12154 */
12155#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
12156/* enum: Rules engine RX PD production firmware */
12157#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
12158/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12159#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
12160/* enum: DPDK RX PD production firmware */
12161#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
12162/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
12163#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
12164/* enum: RX PD firmware parsing but not filtering network overlay tunnel
12165 * encapsulations (Medford development only)
12166 */
12167#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
12168#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10
12169#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2
12170#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_OFST 10
12171#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
12172#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_WIDTH 12
12173#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_OFST 10
12174#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_LBN 12
12175#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
12176/* enum: reserved value - do not use (may indicate alternative interpretation
12177 * of REV field in future)
12178 */
12179#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
12180/* enum: Trivial TX PD firmware for early Huntington development (Huntington
12181 * development only)
12182 */
12183#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
12184/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
12185 */
12186#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
12187/* enum: TX PD firmware with approximately Siena-compatible behaviour
12188 * (Huntington development only)
12189 */
12190#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
12191/* enum: Full featured TX PD production firmware */
12192#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
12193/* enum: (deprecated original name for the FULL_FEATURED variant) */
12194#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
12195/* enum: siena_compat variant TX PD firmware using PM rather than MAC
12196 * (Huntington development only)
12197 */
12198#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
12199#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
12200/* enum: TX PD firmware handling layer 2 only for high packet rate performance
12201 * tests (Medford development only)
12202 */
12203#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
12204/* enum: Rules engine TX PD production firmware */
12205#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
12206/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12207#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
12208/* enum: DPDK TX PD production firmware */
12209#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
12210/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
12211#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
12212/* Hardware capabilities of NIC */
12213#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12
12214#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
12215/* Licensed capabilities */
12216#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_OFST 16
12217#define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4
12218/* Second word of flags. Not present on older firmware (check the length). */
12219#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST 20
12220#define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
12221#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_OFST 20
12222#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
12223#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_WIDTH 1
12224#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_OFST 20
12225#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_LBN 1
12226#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_ENCAP_WIDTH 1
12227#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_OFST 20
12228#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_LBN 2
12229#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVQ_TIMER_CTRL_WIDTH 1
12230#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_OFST 20
12231#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_LBN 3
12232#define MC_CMD_GET_CAPABILITIES_V4_OUT_EVENT_CUT_THROUGH_WIDTH 1
12233#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_OFST 20
12234#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
12235#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_WIDTH 1
12236#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_OFST 20
12237#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_LBN 5
12238#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
12239#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
12240#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
12241#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
12242#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
12243#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
12244#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
12245#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_OFST 20
12246#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_LBN 7
12247#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_EVQ_V2_WIDTH 1
12248#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_OFST 20
12249#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_LBN 8
12250#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
12251#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_OFST 20
12252#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_LBN 9
12253#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TIMESTAMP_WIDTH 1
12254#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_OFST 20
12255#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_LBN 10
12256#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_SNIFF_WIDTH 1
12257#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_OFST 20
12258#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_LBN 11
12259#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_SNIFF_WIDTH 1
12260#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
12261#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
12262#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
12263#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_OFST 20
12264#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_LBN 13
12265#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_BACKGROUND_WIDTH 1
12266#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_OFST 20
12267#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_LBN 14
12268#define MC_CMD_GET_CAPABILITIES_V4_OUT_MCDI_DB_RETURN_WIDTH 1
12269#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_OFST 20
12270#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN 15
12271#define MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_WIDTH 1
12272#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_OFST 20
12273#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_LBN 16
12274#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_SUPPORT_WIDTH 1
12275#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_OFST 20
12276#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_LBN 17
12277#define MC_CMD_GET_CAPABILITIES_V4_OUT_TSA_BOUND_WIDTH 1
12278#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
12279#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
12280#define MC_CMD_GET_CAPABILITIES_V4_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
12281#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_OFST 20
12282#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_LBN 19
12283#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_FLAG_WIDTH 1
12284#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_OFST 20
12285#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_LBN 20
12286#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1
12287#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
12288#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
12289#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
12290#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
12291#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
12292#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
12293#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_OFST 20
12294#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22
12295#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1
12296#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
12297#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
12298#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
12299#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_OFST 20
12300#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_LBN 24
12301#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_SPREADING_WIDTH 1
12302#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_OFST 20
12303#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_LBN 25
12304#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_HLB_IDLE_WIDTH 1
12305#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
12306#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
12307#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
12308#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
12309#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
12310#define MC_CMD_GET_CAPABILITIES_V4_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
12311#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_OFST 20
12312#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_LBN 28
12313#define MC_CMD_GET_CAPABILITIES_V4_OUT_BUNDLE_UPDATE_WIDTH 1
12314#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_OFST 20
12315#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_LBN 29
12316#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V3_WIDTH 1
12317#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_OFST 20
12318#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_LBN 30
12319#define MC_CMD_GET_CAPABILITIES_V4_OUT_DYNAMIC_SENSORS_WIDTH 1
12320#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
12321#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
12322#define MC_CMD_GET_CAPABILITIES_V4_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
12323/* Number of FATSOv2 contexts per datapath supported by this NIC (when
12324 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
12325 */
12326#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
12327#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
12328/* One byte per PF containing the number of the external port assigned to this
12329 * PF, indexed by PF number. Special values indicate that a PF is either not
12330 * present or not assigned.
12331 */
12332#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
12333#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
12334#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
12335/* enum: The caller is not permitted to access information on this PF. */
12336#define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
12337/* enum: PF does not exist. */
12338#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
12339/* enum: PF does exist but is not assigned to any external port. */
12340#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
12341/* enum: This value indicates that PF is assigned, but it cannot be expressed
12342 * in this field. It is intended for a possible future situation where a more
12343 * complex scheme of PFs to ports mapping is being used. The future driver
12344 * should look for a new field supporting the new scheme. The current/old
12345 * driver should treat this value as PF_NOT_ASSIGNED.
12346 */
12347#define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
12348/* One byte per PF containing the number of its VFs, indexed by PF number. A
12349 * special value indicates that a PF is not present.
12350 */
12351#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_OFST 42
12352#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1
12353#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16
12354/* enum: The caller is not permitted to access information on this PF. */
12355/* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
12356/* enum: PF does not exist. */
12357/* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
12358/* Number of VIs available for each external port */
12359#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58
12360#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2
12361#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
12362/* Size of RX descriptor cache expressed as binary logarithm The actual size
12363 * equals (2 ^ RX_DESC_CACHE_SIZE)
12364 */
12365#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_OFST 66
12366#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DESC_CACHE_SIZE_LEN 1
12367/* Size of TX descriptor cache expressed as binary logarithm The actual size
12368 * equals (2 ^ TX_DESC_CACHE_SIZE)
12369 */
12370#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_OFST 67
12371#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DESC_CACHE_SIZE_LEN 1
12372/* Total number of available PIO buffers */
12373#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_OFST 68
12374#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_PIO_BUFFS_LEN 2
12375/* Size of a single PIO buffer */
12376#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_OFST 70
12377#define MC_CMD_GET_CAPABILITIES_V4_OUT_SIZE_PIO_BUFF_LEN 2
12378/* On chips later than Medford the amount of address space assigned to each VI
12379 * is configurable. This is a global setting that the driver must query to
12380 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
12381 * with 8k VI windows.
12382 */
12383#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_OFST 72
12384#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_LEN 1
12385/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
12386 * CTPIO is not mapped.
12387 */
12388#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
12389/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
12390#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
12391/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
12392#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
12393/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
12394 * (SF-115995-SW) in the present configuration of firmware and port mode.
12395 */
12396#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
12397#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
12398/* Number of buffers per adapter that can be used for VFIFO Stuffing
12399 * (SF-115995-SW) in the present configuration of firmware and port mode.
12400 */
12401#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
12402#define MC_CMD_GET_CAPABILITIES_V4_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
12403/* Entry count in the MAC stats array, including the final GENERATION_END
12404 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
12405 * hold at least this many 64-bit stats values, if they wish to receive all
12406 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
12407 * stats array returned will be truncated.
12408 */
12409#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_OFST 76
12410#define MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS_LEN 2
12411
12412/* MC_CMD_GET_CAPABILITIES_V5_OUT msgresponse */
12413#define MC_CMD_GET_CAPABILITIES_V5_OUT_LEN 84
12414/* First word of flags. */
12415#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0
12416#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4
12417#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 0
12418#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_LBN 3
12419#define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_WIDTH 1
12420#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 0
12421#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4
12422#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_WIDTH 1
12423#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 0
12424#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_LBN 5
12425#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_WIDTH 1
12426#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
12427#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
12428#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
12429#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 0
12430#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_LBN 7
12431#define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
12432#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 0
12433#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_LBN 8
12434#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
12435#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 0
12436#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_LBN 9
12437#define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_WIDTH 1
12438#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
12439#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
12440#define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
12441#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
12442#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
12443#define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
12444#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
12445#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
12446#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
12447#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 0
12448#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_LBN 13
12449#define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
12450#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 0
12451#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_LBN 14
12452#define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_WIDTH 1
12453#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
12454#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
12455#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
12456#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 0
12457#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_LBN 16
12458#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_WIDTH 1
12459#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 0
12460#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_LBN 17
12461#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_WIDTH 1
12462#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 0
12463#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_LBN 18
12464#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_WIDTH 1
12465#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 0
12466#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_LBN 19
12467#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_WIDTH 1
12468#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 0
12469#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_LBN 20
12470#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_WIDTH 1
12471#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 0
12472#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_LBN 21
12473#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_WIDTH 1
12474#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 0
12475#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_LBN 22
12476#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_WIDTH 1
12477#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 0
12478#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_LBN 23
12479#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_WIDTH 1
12480#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 0
12481#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_LBN 24
12482#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_WIDTH 1
12483#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 0
12484#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_LBN 25
12485#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_WIDTH 1
12486#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 0
12487#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_LBN 26
12488#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_WIDTH 1
12489#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 0
12490#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_LBN 27
12491#define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
12492#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 0
12493#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_LBN 28
12494#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_WIDTH 1
12495#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
12496#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
12497#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
12498#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 0
12499#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_LBN 30
12500#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_WIDTH 1
12501#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 0
12502#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_LBN 31
12503#define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_WIDTH 1
12504/* RxDPCPU firmware id. */
12505#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4
12506#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_LEN 2
12507/* enum: Standard RXDP firmware */
12508#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0
12509/* enum: Low latency RXDP firmware */
12510#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1
12511/* enum: Packed stream RXDP firmware */
12512#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2
12513/* enum: Rules engine RXDP firmware */
12514#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5
12515/* enum: DPDK RXDP firmware */
12516#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6
12517/* enum: BIST RXDP firmware */
12518#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a
12519/* enum: RXDP Test firmware image 1 */
12520#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
12521/* enum: RXDP Test firmware image 2 */
12522#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
12523/* enum: RXDP Test firmware image 3 */
12524#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
12525/* enum: RXDP Test firmware image 4 */
12526#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
12527/* enum: RXDP Test firmware image 5 */
12528#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105
12529/* enum: RXDP Test firmware image 6 */
12530#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
12531/* enum: RXDP Test firmware image 7 */
12532#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
12533/* enum: RXDP Test firmware image 8 */
12534#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
12535/* enum: RXDP Test firmware image 9 */
12536#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
12537/* enum: RXDP Test firmware image 10 */
12538#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c
12539/* TxDPCPU firmware id. */
12540#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_OFST 6
12541#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DPCPU_FW_ID_LEN 2
12542/* enum: Standard TXDP firmware */
12543#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0
12544/* enum: Low latency TXDP firmware */
12545#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1
12546/* enum: High packet rate TXDP firmware */
12547#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3
12548/* enum: Rules engine TXDP firmware */
12549#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5
12550/* enum: DPDK TXDP firmware */
12551#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6
12552/* enum: BIST TXDP firmware */
12553#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d
12554/* enum: TXDP Test firmware image 1 */
12555#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
12556/* enum: TXDP Test firmware image 2 */
12557#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
12558/* enum: TXDP CSR bus test firmware */
12559#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103
12560#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_OFST 8
12561#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_LEN 2
12562#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_OFST 8
12563#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0
12564#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_WIDTH 12
12565#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_OFST 8
12566#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_LBN 12
12567#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
12568/* enum: reserved value - do not use (may indicate alternative interpretation
12569 * of REV field in future)
12570 */
12571#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0
12572/* enum: Trivial RX PD firmware for early Huntington development (Huntington
12573 * development only)
12574 */
12575#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
12576/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
12577 */
12578#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
12579/* enum: RX PD firmware with approximately Siena-compatible behaviour
12580 * (Huntington development only)
12581 */
12582#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
12583/* enum: Full featured RX PD production firmware */
12584#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
12585/* enum: (deprecated original name for the FULL_FEATURED variant) */
12586#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3
12587/* enum: siena_compat variant RX PD firmware using PM rather than MAC
12588 * (Huntington development only)
12589 */
12590#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
12591/* enum: Low latency RX PD production firmware */
12592#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
12593/* enum: Packed stream RX PD production firmware */
12594#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
12595/* enum: RX PD firmware handling layer 2 only for high packet rate performance
12596 * tests (Medford development only)
12597 */
12598#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
12599/* enum: Rules engine RX PD production firmware */
12600#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
12601/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12602#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9
12603/* enum: DPDK RX PD production firmware */
12604#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa
12605/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
12606#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
12607/* enum: RX PD firmware parsing but not filtering network overlay tunnel
12608 * encapsulations (Medford development only)
12609 */
12610#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
12611#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_OFST 10
12612#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_LEN 2
12613#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_OFST 10
12614#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0
12615#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_WIDTH 12
12616#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_OFST 10
12617#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_LBN 12
12618#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
12619/* enum: reserved value - do not use (may indicate alternative interpretation
12620 * of REV field in future)
12621 */
12622#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0
12623/* enum: Trivial TX PD firmware for early Huntington development (Huntington
12624 * development only)
12625 */
12626#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
12627/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
12628 */
12629#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
12630/* enum: TX PD firmware with approximately Siena-compatible behaviour
12631 * (Huntington development only)
12632 */
12633#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
12634/* enum: Full featured TX PD production firmware */
12635#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
12636/* enum: (deprecated original name for the FULL_FEATURED variant) */
12637#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3
12638/* enum: siena_compat variant TX PD firmware using PM rather than MAC
12639 * (Huntington development only)
12640 */
12641#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
12642#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
12643/* enum: TX PD firmware handling layer 2 only for high packet rate performance
12644 * tests (Medford development only)
12645 */
12646#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
12647/* enum: Rules engine TX PD production firmware */
12648#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
12649/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
12650#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9
12651/* enum: DPDK TX PD production firmware */
12652#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa
12653/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
12654#define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
12655/* Hardware capabilities of NIC */
12656#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_OFST 12
12657#define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4
12658/* Licensed capabilities */
12659#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_OFST 16
12660#define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4
12661/* Second word of flags. Not present on older firmware (check the length). */
12662#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_OFST 20
12663#define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4
12664#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_OFST 20
12665#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0
12666#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_WIDTH 1
12667#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_OFST 20
12668#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_LBN 1
12669#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_ENCAP_WIDTH 1
12670#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_OFST 20
12671#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_LBN 2
12672#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVQ_TIMER_CTRL_WIDTH 1
12673#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_OFST 20
12674#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_LBN 3
12675#define MC_CMD_GET_CAPABILITIES_V5_OUT_EVENT_CUT_THROUGH_WIDTH 1
12676#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_OFST 20
12677#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4
12678#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_WIDTH 1
12679#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_OFST 20
12680#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_LBN 5
12681#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
12682#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
12683#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
12684#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
12685#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
12686#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
12687#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
12688#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_OFST 20
12689#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_LBN 7
12690#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_EVQ_V2_WIDTH 1
12691#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_OFST 20
12692#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_LBN 8
12693#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
12694#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_OFST 20
12695#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_LBN 9
12696#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TIMESTAMP_WIDTH 1
12697#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_OFST 20
12698#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_LBN 10
12699#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_SNIFF_WIDTH 1
12700#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_OFST 20
12701#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_LBN 11
12702#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_SNIFF_WIDTH 1
12703#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
12704#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
12705#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
12706#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_OFST 20
12707#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_LBN 13
12708#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_BACKGROUND_WIDTH 1
12709#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_OFST 20
12710#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_LBN 14
12711#define MC_CMD_GET_CAPABILITIES_V5_OUT_MCDI_DB_RETURN_WIDTH 1
12712#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_OFST 20
12713#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_LBN 15
12714#define MC_CMD_GET_CAPABILITIES_V5_OUT_CTPIO_WIDTH 1
12715#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_OFST 20
12716#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_LBN 16
12717#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_SUPPORT_WIDTH 1
12718#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_OFST 20
12719#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_LBN 17
12720#define MC_CMD_GET_CAPABILITIES_V5_OUT_TSA_BOUND_WIDTH 1
12721#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
12722#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
12723#define MC_CMD_GET_CAPABILITIES_V5_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
12724#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_OFST 20
12725#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_LBN 19
12726#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_FLAG_WIDTH 1
12727#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_OFST 20
12728#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_LBN 20
12729#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_WIDTH 1
12730#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
12731#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
12732#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
12733#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
12734#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
12735#define MC_CMD_GET_CAPABILITIES_V5_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
12736#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_OFST 20
12737#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_LBN 22
12738#define MC_CMD_GET_CAPABILITIES_V5_OUT_L3XUDP_SUPPORT_WIDTH 1
12739#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
12740#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
12741#define MC_CMD_GET_CAPABILITIES_V5_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
12742#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_OFST 20
12743#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_LBN 24
12744#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_SPREADING_WIDTH 1
12745#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_OFST 20
12746#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_LBN 25
12747#define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_HLB_IDLE_WIDTH 1
12748#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
12749#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
12750#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
12751#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
12752#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
12753#define MC_CMD_GET_CAPABILITIES_V5_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
12754#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_OFST 20
12755#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_LBN 28
12756#define MC_CMD_GET_CAPABILITIES_V5_OUT_BUNDLE_UPDATE_WIDTH 1
12757#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_OFST 20
12758#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_LBN 29
12759#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V3_WIDTH 1
12760#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_OFST 20
12761#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_LBN 30
12762#define MC_CMD_GET_CAPABILITIES_V5_OUT_DYNAMIC_SENSORS_WIDTH 1
12763#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
12764#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
12765#define MC_CMD_GET_CAPABILITIES_V5_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
12766/* Number of FATSOv2 contexts per datapath supported by this NIC (when
12767 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
12768 */
12769#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
12770#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
12771/* One byte per PF containing the number of the external port assigned to this
12772 * PF, indexed by PF number. Special values indicate that a PF is either not
12773 * present or not assigned.
12774 */
12775#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
12776#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
12777#define MC_CMD_GET_CAPABILITIES_V5_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
12778/* enum: The caller is not permitted to access information on this PF. */
12779#define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff
12780/* enum: PF does not exist. */
12781#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe
12782/* enum: PF does exist but is not assigned to any external port. */
12783#define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd
12784/* enum: This value indicates that PF is assigned, but it cannot be expressed
12785 * in this field. It is intended for a possible future situation where a more
12786 * complex scheme of PFs to ports mapping is being used. The future driver
12787 * should look for a new field supporting the new scheme. The current/old
12788 * driver should treat this value as PF_NOT_ASSIGNED.
12789 */
12790#define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
12791/* One byte per PF containing the number of its VFs, indexed by PF number. A
12792 * special value indicates that a PF is not present.
12793 */
12794#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_OFST 42
12795#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_LEN 1
12796#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VFS_PER_PF_NUM 16
12797/* enum: The caller is not permitted to access information on this PF. */
12798/* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */
12799/* enum: PF does not exist. */
12800/* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */
12801/* Number of VIs available for each external port */
12802#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_OFST 58
12803#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_LEN 2
12804#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4
12805/* Size of RX descriptor cache expressed as binary logarithm The actual size
12806 * equals (2 ^ RX_DESC_CACHE_SIZE)
12807 */
12808#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_OFST 66
12809#define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DESC_CACHE_SIZE_LEN 1
12810/* Size of TX descriptor cache expressed as binary logarithm The actual size
12811 * equals (2 ^ TX_DESC_CACHE_SIZE)
12812 */
12813#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_OFST 67
12814#define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_DESC_CACHE_SIZE_LEN 1
12815/* Total number of available PIO buffers */
12816#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_OFST 68
12817#define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_PIO_BUFFS_LEN 2
12818/* Size of a single PIO buffer */
12819#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_OFST 70
12820#define MC_CMD_GET_CAPABILITIES_V5_OUT_SIZE_PIO_BUFF_LEN 2
12821/* On chips later than Medford the amount of address space assigned to each VI
12822 * is configurable. This is a global setting that the driver must query to
12823 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
12824 * with 8k VI windows.
12825 */
12826#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_OFST 72
12827#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_LEN 1
12828/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
12829 * CTPIO is not mapped.
12830 */
12831#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0
12832/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
12833#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1
12834/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
12835#define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2
12836/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
12837 * (SF-115995-SW) in the present configuration of firmware and port mode.
12838 */
12839#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
12840#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
12841/* Number of buffers per adapter that can be used for VFIFO Stuffing
12842 * (SF-115995-SW) in the present configuration of firmware and port mode.
12843 */
12844#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
12845#define MC_CMD_GET_CAPABILITIES_V5_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
12846/* Entry count in the MAC stats array, including the final GENERATION_END
12847 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
12848 * hold at least this many 64-bit stats values, if they wish to receive all
12849 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
12850 * stats array returned will be truncated.
12851 */
12852#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_OFST 76
12853#define MC_CMD_GET_CAPABILITIES_V5_OUT_MAC_STATS_NUM_STATS_LEN 2
12854/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
12855 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
12856 */
12857#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_OFST 80
12858#define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4
12859
12860/* MC_CMD_GET_CAPABILITIES_V6_OUT msgresponse */
12861#define MC_CMD_GET_CAPABILITIES_V6_OUT_LEN 148
12862/* First word of flags. */
12863#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 0
12864#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4
12865#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 0
12866#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_LBN 3
12867#define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_WIDTH 1
12868#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 0
12869#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4
12870#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_WIDTH 1
12871#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 0
12872#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_LBN 5
12873#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_WIDTH 1
12874#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
12875#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
12876#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
12877#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 0
12878#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_LBN 7
12879#define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
12880#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 0
12881#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_LBN 8
12882#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
12883#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 0
12884#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_LBN 9
12885#define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_WIDTH 1
12886#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
12887#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
12888#define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
12889#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
12890#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
12891#define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
12892#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
12893#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
12894#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
12895#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 0
12896#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_LBN 13
12897#define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
12898#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 0
12899#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_LBN 14
12900#define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_WIDTH 1
12901#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
12902#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
12903#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
12904#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 0
12905#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_LBN 16
12906#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_WIDTH 1
12907#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 0
12908#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_LBN 17
12909#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_WIDTH 1
12910#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 0
12911#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_LBN 18
12912#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_WIDTH 1
12913#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 0
12914#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_LBN 19
12915#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_WIDTH 1
12916#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 0
12917#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_LBN 20
12918#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_WIDTH 1
12919#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 0
12920#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_LBN 21
12921#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_WIDTH 1
12922#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 0
12923#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_LBN 22
12924#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_WIDTH 1
12925#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 0
12926#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_LBN 23
12927#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_WIDTH 1
12928#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 0
12929#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_LBN 24
12930#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_WIDTH 1
12931#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 0
12932#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_LBN 25
12933#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_WIDTH 1
12934#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 0
12935#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_LBN 26
12936#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_WIDTH 1
12937#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 0
12938#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_LBN 27
12939#define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
12940#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 0
12941#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_LBN 28
12942#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_WIDTH 1
12943#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
12944#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
12945#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
12946#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 0
12947#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_LBN 30
12948#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_WIDTH 1
12949#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 0
12950#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_LBN 31
12951#define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_WIDTH 1
12952/* RxDPCPU firmware id. */
12953#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 4
12954#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_LEN 2
12955/* enum: Standard RXDP firmware */
12956#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x0
12957/* enum: Low latency RXDP firmware */
12958#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x1
12959/* enum: Packed stream RXDP firmware */
12960#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x2
12961/* enum: Rules engine RXDP firmware */
12962#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x5
12963/* enum: DPDK RXDP firmware */
12964#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x6
12965/* enum: BIST RXDP firmware */
12966#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a
12967/* enum: RXDP Test firmware image 1 */
12968#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
12969/* enum: RXDP Test firmware image 2 */
12970#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
12971/* enum: RXDP Test firmware image 3 */
12972#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
12973/* enum: RXDP Test firmware image 4 */
12974#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
12975/* enum: RXDP Test firmware image 5 */
12976#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x105
12977/* enum: RXDP Test firmware image 6 */
12978#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
12979/* enum: RXDP Test firmware image 7 */
12980#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
12981/* enum: RXDP Test firmware image 8 */
12982#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
12983/* enum: RXDP Test firmware image 9 */
12984#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
12985/* enum: RXDP Test firmware image 10 */
12986#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c
12987/* TxDPCPU firmware id. */
12988#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_OFST 6
12989#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DPCPU_FW_ID_LEN 2
12990/* enum: Standard TXDP firmware */
12991#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x0
12992/* enum: Low latency TXDP firmware */
12993#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x1
12994/* enum: High packet rate TXDP firmware */
12995#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x3
12996/* enum: Rules engine TXDP firmware */
12997#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x5
12998/* enum: DPDK TXDP firmware */
12999#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x6
13000/* enum: BIST TXDP firmware */
13001#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d
13002/* enum: TXDP Test firmware image 1 */
13003#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13004/* enum: TXDP Test firmware image 2 */
13005#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13006/* enum: TXDP CSR bus test firmware */
13007#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x103
13008#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_OFST 8
13009#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_LEN 2
13010#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_OFST 8
13011#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 0
13012#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_WIDTH 12
13013#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_OFST 8
13014#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_LBN 12
13015#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13016/* enum: reserved value - do not use (may indicate alternative interpretation
13017 * of REV field in future)
13018 */
13019#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x0
13020/* enum: Trivial RX PD firmware for early Huntington development (Huntington
13021 * development only)
13022 */
13023#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
13024/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
13025 */
13026#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13027/* enum: RX PD firmware with approximately Siena-compatible behaviour
13028 * (Huntington development only)
13029 */
13030#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
13031/* enum: Full featured RX PD production firmware */
13032#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
13033/* enum: (deprecated original name for the FULL_FEATURED variant) */
13034#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x3
13035/* enum: siena_compat variant RX PD firmware using PM rather than MAC
13036 * (Huntington development only)
13037 */
13038#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13039/* enum: Low latency RX PD production firmware */
13040#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
13041/* enum: Packed stream RX PD production firmware */
13042#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
13043/* enum: RX PD firmware handling layer 2 only for high packet rate performance
13044 * tests (Medford development only)
13045 */
13046#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
13047/* enum: Rules engine RX PD production firmware */
13048#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
13049/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13050#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x9
13051/* enum: DPDK RX PD production firmware */
13052#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa
13053/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
13054#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13055/* enum: RX PD firmware parsing but not filtering network overlay tunnel
13056 * encapsulations (Medford development only)
13057 */
13058#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
13059#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_OFST 10
13060#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_LEN 2
13061#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_OFST 10
13062#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 0
13063#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_WIDTH 12
13064#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_OFST 10
13065#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_LBN 12
13066#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
13067/* enum: reserved value - do not use (may indicate alternative interpretation
13068 * of REV field in future)
13069 */
13070#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x0
13071/* enum: Trivial TX PD firmware for early Huntington development (Huntington
13072 * development only)
13073 */
13074#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
13075/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
13076 */
13077#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13078/* enum: TX PD firmware with approximately Siena-compatible behaviour
13079 * (Huntington development only)
13080 */
13081#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
13082/* enum: Full featured TX PD production firmware */
13083#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
13084/* enum: (deprecated original name for the FULL_FEATURED variant) */
13085#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x3
13086/* enum: siena_compat variant TX PD firmware using PM rather than MAC
13087 * (Huntington development only)
13088 */
13089#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13090#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
13091/* enum: TX PD firmware handling layer 2 only for high packet rate performance
13092 * tests (Medford development only)
13093 */
13094#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
13095/* enum: Rules engine TX PD production firmware */
13096#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
13097/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13098#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x9
13099/* enum: DPDK TX PD production firmware */
13100#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa
13101/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
13102#define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13103/* Hardware capabilities of NIC */
13104#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_OFST 12
13105#define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 4
13106/* Licensed capabilities */
13107#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_OFST 16
13108#define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 4
13109/* Second word of flags. Not present on older firmware (check the length). */
13110#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_OFST 20
13111#define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4
13112#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_OFST 20
13113#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 0
13114#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_WIDTH 1
13115#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_OFST 20
13116#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_LBN 1
13117#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_ENCAP_WIDTH 1
13118#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_OFST 20
13119#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_LBN 2
13120#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVQ_TIMER_CTRL_WIDTH 1
13121#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_OFST 20
13122#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_LBN 3
13123#define MC_CMD_GET_CAPABILITIES_V6_OUT_EVENT_CUT_THROUGH_WIDTH 1
13124#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_OFST 20
13125#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4
13126#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_WIDTH 1
13127#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_OFST 20
13128#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_LBN 5
13129#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
13130#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
13131#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
13132#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
13133#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
13134#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
13135#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
13136#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_OFST 20
13137#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_LBN 7
13138#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_EVQ_V2_WIDTH 1
13139#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_OFST 20
13140#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_LBN 8
13141#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
13142#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_OFST 20
13143#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_LBN 9
13144#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TIMESTAMP_WIDTH 1
13145#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_OFST 20
13146#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_LBN 10
13147#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_SNIFF_WIDTH 1
13148#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_OFST 20
13149#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_LBN 11
13150#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_SNIFF_WIDTH 1
13151#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
13152#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
13153#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
13154#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_OFST 20
13155#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_LBN 13
13156#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_BACKGROUND_WIDTH 1
13157#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_OFST 20
13158#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_LBN 14
13159#define MC_CMD_GET_CAPABILITIES_V6_OUT_MCDI_DB_RETURN_WIDTH 1
13160#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_OFST 20
13161#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_LBN 15
13162#define MC_CMD_GET_CAPABILITIES_V6_OUT_CTPIO_WIDTH 1
13163#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_OFST 20
13164#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_LBN 16
13165#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_SUPPORT_WIDTH 1
13166#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_OFST 20
13167#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_LBN 17
13168#define MC_CMD_GET_CAPABILITIES_V6_OUT_TSA_BOUND_WIDTH 1
13169#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
13170#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
13171#define MC_CMD_GET_CAPABILITIES_V6_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
13172#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_OFST 20
13173#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_LBN 19
13174#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_FLAG_WIDTH 1
13175#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_OFST 20
13176#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_LBN 20
13177#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_WIDTH 1
13178#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
13179#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
13180#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
13181#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
13182#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
13183#define MC_CMD_GET_CAPABILITIES_V6_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
13184#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_OFST 20
13185#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_LBN 22
13186#define MC_CMD_GET_CAPABILITIES_V6_OUT_L3XUDP_SUPPORT_WIDTH 1
13187#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
13188#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
13189#define MC_CMD_GET_CAPABILITIES_V6_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
13190#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_OFST 20
13191#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_LBN 24
13192#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_SPREADING_WIDTH 1
13193#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_OFST 20
13194#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_LBN 25
13195#define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_HLB_IDLE_WIDTH 1
13196#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
13197#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
13198#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
13199#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
13200#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
13201#define MC_CMD_GET_CAPABILITIES_V6_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
13202#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_OFST 20
13203#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_LBN 28
13204#define MC_CMD_GET_CAPABILITIES_V6_OUT_BUNDLE_UPDATE_WIDTH 1
13205#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_OFST 20
13206#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_LBN 29
13207#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V3_WIDTH 1
13208#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_OFST 20
13209#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_LBN 30
13210#define MC_CMD_GET_CAPABILITIES_V6_OUT_DYNAMIC_SENSORS_WIDTH 1
13211#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
13212#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
13213#define MC_CMD_GET_CAPABILITIES_V6_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
13214/* Number of FATSOv2 contexts per datapath supported by this NIC (when
13215 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
13216 */
13217#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
13218#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
13219/* One byte per PF containing the number of the external port assigned to this
13220 * PF, indexed by PF number. Special values indicate that a PF is either not
13221 * present or not assigned.
13222 */
13223#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
13224#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
13225#define MC_CMD_GET_CAPABILITIES_V6_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
13226/* enum: The caller is not permitted to access information on this PF. */
13227#define MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff
13228/* enum: PF does not exist. */
13229#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe
13230/* enum: PF does exist but is not assigned to any external port. */
13231#define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd
13232/* enum: This value indicates that PF is assigned, but it cannot be expressed
13233 * in this field. It is intended for a possible future situation where a more
13234 * complex scheme of PFs to ports mapping is being used. The future driver
13235 * should look for a new field supporting the new scheme. The current/old
13236 * driver should treat this value as PF_NOT_ASSIGNED.
13237 */
13238#define MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
13239/* One byte per PF containing the number of its VFs, indexed by PF number. A
13240 * special value indicates that a PF is not present.
13241 */
13242#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_OFST 42
13243#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_LEN 1
13244#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VFS_PER_PF_NUM 16
13245/* enum: The caller is not permitted to access information on this PF. */
13246/* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */
13247/* enum: PF does not exist. */
13248/* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */
13249/* Number of VIs available for each external port */
13250#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_OFST 58
13251#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_LEN 2
13252#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
13253/* Size of RX descriptor cache expressed as binary logarithm The actual size
13254 * equals (2 ^ RX_DESC_CACHE_SIZE)
13255 */
13256#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_OFST 66
13257#define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DESC_CACHE_SIZE_LEN 1
13258/* Size of TX descriptor cache expressed as binary logarithm The actual size
13259 * equals (2 ^ TX_DESC_CACHE_SIZE)
13260 */
13261#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_OFST 67
13262#define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_DESC_CACHE_SIZE_LEN 1
13263/* Total number of available PIO buffers */
13264#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_OFST 68
13265#define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_PIO_BUFFS_LEN 2
13266/* Size of a single PIO buffer */
13267#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_OFST 70
13268#define MC_CMD_GET_CAPABILITIES_V6_OUT_SIZE_PIO_BUFF_LEN 2
13269/* On chips later than Medford the amount of address space assigned to each VI
13270 * is configurable. This is a global setting that the driver must query to
13271 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
13272 * with 8k VI windows.
13273 */
13274#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_OFST 72
13275#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_LEN 1
13276/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
13277 * CTPIO is not mapped.
13278 */
13279#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x0
13280/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
13281#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x1
13282/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
13283#define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x2
13284/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
13285 * (SF-115995-SW) in the present configuration of firmware and port mode.
13286 */
13287#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
13288#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
13289/* Number of buffers per adapter that can be used for VFIFO Stuffing
13290 * (SF-115995-SW) in the present configuration of firmware and port mode.
13291 */
13292#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
13293#define MC_CMD_GET_CAPABILITIES_V6_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
13294/* Entry count in the MAC stats array, including the final GENERATION_END
13295 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
13296 * hold at least this many 64-bit stats values, if they wish to receive all
13297 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
13298 * stats array returned will be truncated.
13299 */
13300#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_OFST 76
13301#define MC_CMD_GET_CAPABILITIES_V6_OUT_MAC_STATS_NUM_STATS_LEN 2
13302/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
13303 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
13304 */
13305#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_OFST 80
13306#define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 4
13307/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
13308 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
13309 * they create an RX queue. Due to hardware limitations, only a small number of
13310 * different buffer sizes may be available concurrently. Nonzero entries in
13311 * this array are the sizes of buffers which the system guarantees will be
13312 * available for use. If the list is empty, there are no limitations on
13313 * concurrent buffer sizes.
13314 */
13315#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
13316#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
13317#define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
13318
13319/* MC_CMD_GET_CAPABILITIES_V7_OUT msgresponse */
13320#define MC_CMD_GET_CAPABILITIES_V7_OUT_LEN 152
13321/* First word of flags. */
13322#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 0
13323#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 4
13324#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 0
13325#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_LBN 3
13326#define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_WIDTH 1
13327#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 0
13328#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 4
13329#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_WIDTH 1
13330#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 0
13331#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_LBN 5
13332#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_WIDTH 1
13333#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13334#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
13335#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
13336#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 0
13337#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_LBN 7
13338#define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
13339#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13340#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_LBN 8
13341#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
13342#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 0
13343#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_LBN 9
13344#define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_WIDTH 1
13345#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13346#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
13347#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
13348#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13349#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
13350#define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
13351#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13352#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
13353#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
13354#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 0
13355#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_LBN 13
13356#define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
13357#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 0
13358#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_LBN 14
13359#define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_WIDTH 1
13360#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13361#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
13362#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
13363#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 0
13364#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_LBN 16
13365#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_WIDTH 1
13366#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 0
13367#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_LBN 17
13368#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_WIDTH 1
13369#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 0
13370#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_LBN 18
13371#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_WIDTH 1
13372#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 0
13373#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_LBN 19
13374#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_WIDTH 1
13375#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 0
13376#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_LBN 20
13377#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_WIDTH 1
13378#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 0
13379#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_LBN 21
13380#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_WIDTH 1
13381#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 0
13382#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_LBN 22
13383#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_WIDTH 1
13384#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 0
13385#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_LBN 23
13386#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_WIDTH 1
13387#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 0
13388#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_LBN 24
13389#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_WIDTH 1
13390#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 0
13391#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_LBN 25
13392#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_WIDTH 1
13393#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 0
13394#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_LBN 26
13395#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_WIDTH 1
13396#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13397#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_LBN 27
13398#define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
13399#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 0
13400#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_LBN 28
13401#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_WIDTH 1
13402#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13403#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
13404#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
13405#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 0
13406#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_LBN 30
13407#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_WIDTH 1
13408#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 0
13409#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_LBN 31
13410#define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_WIDTH 1
13411/* RxDPCPU firmware id. */
13412#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 4
13413#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_LEN 2
13414/* enum: Standard RXDP firmware */
13415#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x0
13416/* enum: Low latency RXDP firmware */
13417#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x1
13418/* enum: Packed stream RXDP firmware */
13419#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x2
13420/* enum: Rules engine RXDP firmware */
13421#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x5
13422/* enum: DPDK RXDP firmware */
13423#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x6
13424/* enum: BIST RXDP firmware */
13425#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a
13426/* enum: RXDP Test firmware image 1 */
13427#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13428/* enum: RXDP Test firmware image 2 */
13429#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13430/* enum: RXDP Test firmware image 3 */
13431#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13432/* enum: RXDP Test firmware image 4 */
13433#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13434/* enum: RXDP Test firmware image 5 */
13435#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x105
13436/* enum: RXDP Test firmware image 6 */
13437#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13438/* enum: RXDP Test firmware image 7 */
13439#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13440/* enum: RXDP Test firmware image 8 */
13441#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13442/* enum: RXDP Test firmware image 9 */
13443#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13444/* enum: RXDP Test firmware image 10 */
13445#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c
13446/* TxDPCPU firmware id. */
13447#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_OFST 6
13448#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DPCPU_FW_ID_LEN 2
13449/* enum: Standard TXDP firmware */
13450#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x0
13451/* enum: Low latency TXDP firmware */
13452#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x1
13453/* enum: High packet rate TXDP firmware */
13454#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x3
13455/* enum: Rules engine TXDP firmware */
13456#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x5
13457/* enum: DPDK TXDP firmware */
13458#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x6
13459/* enum: BIST TXDP firmware */
13460#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d
13461/* enum: TXDP Test firmware image 1 */
13462#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13463/* enum: TXDP Test firmware image 2 */
13464#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13465/* enum: TXDP CSR bus test firmware */
13466#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x103
13467#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_OFST 8
13468#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_LEN 2
13469#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_OFST 8
13470#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 0
13471#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_WIDTH 12
13472#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_OFST 8
13473#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_LBN 12
13474#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13475/* enum: reserved value - do not use (may indicate alternative interpretation
13476 * of REV field in future)
13477 */
13478#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x0
13479/* enum: Trivial RX PD firmware for early Huntington development (Huntington
13480 * development only)
13481 */
13482#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
13483/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
13484 */
13485#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13486/* enum: RX PD firmware with approximately Siena-compatible behaviour
13487 * (Huntington development only)
13488 */
13489#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
13490/* enum: Full featured RX PD production firmware */
13491#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
13492/* enum: (deprecated original name for the FULL_FEATURED variant) */
13493#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x3
13494/* enum: siena_compat variant RX PD firmware using PM rather than MAC
13495 * (Huntington development only)
13496 */
13497#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13498/* enum: Low latency RX PD production firmware */
13499#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
13500/* enum: Packed stream RX PD production firmware */
13501#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
13502/* enum: RX PD firmware handling layer 2 only for high packet rate performance
13503 * tests (Medford development only)
13504 */
13505#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
13506/* enum: Rules engine RX PD production firmware */
13507#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
13508/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13509#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x9
13510/* enum: DPDK RX PD production firmware */
13511#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa
13512/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
13513#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13514/* enum: RX PD firmware parsing but not filtering network overlay tunnel
13515 * encapsulations (Medford development only)
13516 */
13517#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
13518#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_OFST 10
13519#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_LEN 2
13520#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_OFST 10
13521#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 0
13522#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_WIDTH 12
13523#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_OFST 10
13524#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_LBN 12
13525#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
13526/* enum: reserved value - do not use (may indicate alternative interpretation
13527 * of REV field in future)
13528 */
13529#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x0
13530/* enum: Trivial TX PD firmware for early Huntington development (Huntington
13531 * development only)
13532 */
13533#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
13534/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
13535 */
13536#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13537/* enum: TX PD firmware with approximately Siena-compatible behaviour
13538 * (Huntington development only)
13539 */
13540#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
13541/* enum: Full featured TX PD production firmware */
13542#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
13543/* enum: (deprecated original name for the FULL_FEATURED variant) */
13544#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x3
13545/* enum: siena_compat variant TX PD firmware using PM rather than MAC
13546 * (Huntington development only)
13547 */
13548#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13549#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
13550/* enum: TX PD firmware handling layer 2 only for high packet rate performance
13551 * tests (Medford development only)
13552 */
13553#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
13554/* enum: Rules engine TX PD production firmware */
13555#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
13556/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13557#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x9
13558/* enum: DPDK TX PD production firmware */
13559#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa
13560/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
13561#define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13562/* Hardware capabilities of NIC */
13563#define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_OFST 12
13564#define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 4
13565/* Licensed capabilities */
13566#define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_OFST 16
13567#define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 4
13568/* Second word of flags. Not present on older firmware (check the length). */
13569#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_OFST 20
13570#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 4
13571#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_OFST 20
13572#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 0
13573#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_WIDTH 1
13574#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_OFST 20
13575#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_LBN 1
13576#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_ENCAP_WIDTH 1
13577#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_OFST 20
13578#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_LBN 2
13579#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVQ_TIMER_CTRL_WIDTH 1
13580#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_OFST 20
13581#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_LBN 3
13582#define MC_CMD_GET_CAPABILITIES_V7_OUT_EVENT_CUT_THROUGH_WIDTH 1
13583#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_OFST 20
13584#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 4
13585#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_WIDTH 1
13586#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_OFST 20
13587#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_LBN 5
13588#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
13589#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
13590#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
13591#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
13592#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
13593#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
13594#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
13595#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_OFST 20
13596#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_LBN 7
13597#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_EVQ_V2_WIDTH 1
13598#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_OFST 20
13599#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_LBN 8
13600#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
13601#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_OFST 20
13602#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_LBN 9
13603#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TIMESTAMP_WIDTH 1
13604#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_OFST 20
13605#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_LBN 10
13606#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_SNIFF_WIDTH 1
13607#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_OFST 20
13608#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_LBN 11
13609#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_SNIFF_WIDTH 1
13610#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
13611#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
13612#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
13613#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_OFST 20
13614#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_LBN 13
13615#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_BACKGROUND_WIDTH 1
13616#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_OFST 20
13617#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_LBN 14
13618#define MC_CMD_GET_CAPABILITIES_V7_OUT_MCDI_DB_RETURN_WIDTH 1
13619#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_OFST 20
13620#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_LBN 15
13621#define MC_CMD_GET_CAPABILITIES_V7_OUT_CTPIO_WIDTH 1
13622#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_OFST 20
13623#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_LBN 16
13624#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_SUPPORT_WIDTH 1
13625#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_OFST 20
13626#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_LBN 17
13627#define MC_CMD_GET_CAPABILITIES_V7_OUT_TSA_BOUND_WIDTH 1
13628#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
13629#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
13630#define MC_CMD_GET_CAPABILITIES_V7_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
13631#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_OFST 20
13632#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_LBN 19
13633#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_FLAG_WIDTH 1
13634#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_OFST 20
13635#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_LBN 20
13636#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_WIDTH 1
13637#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
13638#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
13639#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
13640#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
13641#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
13642#define MC_CMD_GET_CAPABILITIES_V7_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
13643#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_OFST 20
13644#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_LBN 22
13645#define MC_CMD_GET_CAPABILITIES_V7_OUT_L3XUDP_SUPPORT_WIDTH 1
13646#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
13647#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
13648#define MC_CMD_GET_CAPABILITIES_V7_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
13649#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_OFST 20
13650#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_LBN 24
13651#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_SPREADING_WIDTH 1
13652#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_OFST 20
13653#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_LBN 25
13654#define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_HLB_IDLE_WIDTH 1
13655#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
13656#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
13657#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
13658#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
13659#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
13660#define MC_CMD_GET_CAPABILITIES_V7_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
13661#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_OFST 20
13662#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_LBN 28
13663#define MC_CMD_GET_CAPABILITIES_V7_OUT_BUNDLE_UPDATE_WIDTH 1
13664#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_OFST 20
13665#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_LBN 29
13666#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V3_WIDTH 1
13667#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_OFST 20
13668#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_LBN 30
13669#define MC_CMD_GET_CAPABILITIES_V7_OUT_DYNAMIC_SENSORS_WIDTH 1
13670#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
13671#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
13672#define MC_CMD_GET_CAPABILITIES_V7_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
13673/* Number of FATSOv2 contexts per datapath supported by this NIC (when
13674 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
13675 */
13676#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
13677#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
13678/* One byte per PF containing the number of the external port assigned to this
13679 * PF, indexed by PF number. Special values indicate that a PF is either not
13680 * present or not assigned.
13681 */
13682#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
13683#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
13684#define MC_CMD_GET_CAPABILITIES_V7_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
13685/* enum: The caller is not permitted to access information on this PF. */
13686#define MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff
13687/* enum: PF does not exist. */
13688#define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe
13689/* enum: PF does exist but is not assigned to any external port. */
13690#define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd
13691/* enum: This value indicates that PF is assigned, but it cannot be expressed
13692 * in this field. It is intended for a possible future situation where a more
13693 * complex scheme of PFs to ports mapping is being used. The future driver
13694 * should look for a new field supporting the new scheme. The current/old
13695 * driver should treat this value as PF_NOT_ASSIGNED.
13696 */
13697#define MC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
13698/* One byte per PF containing the number of its VFs, indexed by PF number. A
13699 * special value indicates that a PF is not present.
13700 */
13701#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_OFST 42
13702#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_LEN 1
13703#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VFS_PER_PF_NUM 16
13704/* enum: The caller is not permitted to access information on this PF. */
13705/* MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */
13706/* enum: PF does not exist. */
13707/* MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */
13708/* Number of VIs available for each external port */
13709#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_OFST 58
13710#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_LEN 2
13711#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4
13712/* Size of RX descriptor cache expressed as binary logarithm The actual size
13713 * equals (2 ^ RX_DESC_CACHE_SIZE)
13714 */
13715#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_OFST 66
13716#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DESC_CACHE_SIZE_LEN 1
13717/* Size of TX descriptor cache expressed as binary logarithm The actual size
13718 * equals (2 ^ TX_DESC_CACHE_SIZE)
13719 */
13720#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_OFST 67
13721#define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_DESC_CACHE_SIZE_LEN 1
13722/* Total number of available PIO buffers */
13723#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_OFST 68
13724#define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_PIO_BUFFS_LEN 2
13725/* Size of a single PIO buffer */
13726#define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_OFST 70
13727#define MC_CMD_GET_CAPABILITIES_V7_OUT_SIZE_PIO_BUFF_LEN 2
13728/* On chips later than Medford the amount of address space assigned to each VI
13729 * is configurable. This is a global setting that the driver must query to
13730 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
13731 * with 8k VI windows.
13732 */
13733#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_OFST 72
13734#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_LEN 1
13735/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
13736 * CTPIO is not mapped.
13737 */
13738#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x0
13739/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
13740#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x1
13741/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
13742#define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x2
13743/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
13744 * (SF-115995-SW) in the present configuration of firmware and port mode.
13745 */
13746#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
13747#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
13748/* Number of buffers per adapter that can be used for VFIFO Stuffing
13749 * (SF-115995-SW) in the present configuration of firmware and port mode.
13750 */
13751#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
13752#define MC_CMD_GET_CAPABILITIES_V7_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
13753/* Entry count in the MAC stats array, including the final GENERATION_END
13754 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
13755 * hold at least this many 64-bit stats values, if they wish to receive all
13756 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
13757 * stats array returned will be truncated.
13758 */
13759#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_OFST 76
13760#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAC_STATS_NUM_STATS_LEN 2
13761/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
13762 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
13763 */
13764#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_OFST 80
13765#define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 4
13766/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
13767 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
13768 * they create an RX queue. Due to hardware limitations, only a small number of
13769 * different buffer sizes may be available concurrently. Nonzero entries in
13770 * this array are the sizes of buffers which the system guarantees will be
13771 * available for use. If the list is empty, there are no limitations on
13772 * concurrent buffer sizes.
13773 */
13774#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
13775#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
13776#define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
13777/* Third word of flags. Not present on older firmware (check the length). */
13778#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_OFST 148
13779#define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 4
13780#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_OFST 148
13781#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 0
13782#define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_WIDTH 1
13783#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_OFST 148
13784#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_LBN 1
13785#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_EVEN_SPREADING_WIDTH 1
13786#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
13787#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
13788#define MC_CMD_GET_CAPABILITIES_V7_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
13789#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_OFST 148
13790#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_LBN 3
13791#define MC_CMD_GET_CAPABILITIES_V7_OUT_MAE_SUPPORTED_WIDTH 1
13792#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_OFST 148
13793#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 4
13794#define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_WIDTH 1
13795#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
13796#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
13797#define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
13798#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
13799#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
13800#define MC_CMD_GET_CAPABILITIES_V7_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
13801#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
13802#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
13803#define MC_CMD_GET_CAPABILITIES_V7_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
13804
13805/* MC_CMD_GET_CAPABILITIES_V8_OUT msgresponse */
13806#define MC_CMD_GET_CAPABILITIES_V8_OUT_LEN 160
13807/* First word of flags. */
13808#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 0
13809#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 4
13810#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 0
13811#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_LBN 3
13812#define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_WIDTH 1
13813#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 0
13814#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 4
13815#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_WIDTH 1
13816#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 0
13817#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_LBN 5
13818#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_WIDTH 1
13819#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13820#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
13821#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
13822#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 0
13823#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_LBN 7
13824#define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
13825#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13826#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_LBN 8
13827#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
13828#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 0
13829#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_LBN 9
13830#define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_WIDTH 1
13831#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13832#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
13833#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
13834#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13835#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
13836#define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
13837#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13838#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
13839#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
13840#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 0
13841#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_LBN 13
13842#define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
13843#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 0
13844#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_LBN 14
13845#define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_WIDTH 1
13846#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13847#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
13848#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
13849#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 0
13850#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_LBN 16
13851#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_WIDTH 1
13852#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 0
13853#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_LBN 17
13854#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_WIDTH 1
13855#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 0
13856#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_LBN 18
13857#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_WIDTH 1
13858#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 0
13859#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_LBN 19
13860#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_WIDTH 1
13861#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 0
13862#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_LBN 20
13863#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_WIDTH 1
13864#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 0
13865#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_LBN 21
13866#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_WIDTH 1
13867#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 0
13868#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_LBN 22
13869#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_WIDTH 1
13870#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 0
13871#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_LBN 23
13872#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_WIDTH 1
13873#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 0
13874#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_LBN 24
13875#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_WIDTH 1
13876#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 0
13877#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_LBN 25
13878#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_WIDTH 1
13879#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 0
13880#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_LBN 26
13881#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_WIDTH 1
13882#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13883#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_LBN 27
13884#define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
13885#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 0
13886#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_LBN 28
13887#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_WIDTH 1
13888#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13889#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
13890#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
13891#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 0
13892#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_LBN 30
13893#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_WIDTH 1
13894#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 0
13895#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_LBN 31
13896#define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_WIDTH 1
13897/* RxDPCPU firmware id. */
13898#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 4
13899#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_LEN 2
13900/* enum: Standard RXDP firmware */
13901#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x0
13902/* enum: Low latency RXDP firmware */
13903#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x1
13904/* enum: Packed stream RXDP firmware */
13905#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x2
13906/* enum: Rules engine RXDP firmware */
13907#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x5
13908/* enum: DPDK RXDP firmware */
13909#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x6
13910/* enum: BIST RXDP firmware */
13911#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a
13912/* enum: RXDP Test firmware image 1 */
13913#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13914/* enum: RXDP Test firmware image 2 */
13915#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13916/* enum: RXDP Test firmware image 3 */
13917#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13918/* enum: RXDP Test firmware image 4 */
13919#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13920/* enum: RXDP Test firmware image 5 */
13921#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x105
13922/* enum: RXDP Test firmware image 6 */
13923#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13924/* enum: RXDP Test firmware image 7 */
13925#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13926/* enum: RXDP Test firmware image 8 */
13927#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13928/* enum: RXDP Test firmware image 9 */
13929#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13930/* enum: RXDP Test firmware image 10 */
13931#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c
13932/* TxDPCPU firmware id. */
13933#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_OFST 6
13934#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DPCPU_FW_ID_LEN 2
13935/* enum: Standard TXDP firmware */
13936#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x0
13937/* enum: Low latency TXDP firmware */
13938#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x1
13939/* enum: High packet rate TXDP firmware */
13940#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x3
13941/* enum: Rules engine TXDP firmware */
13942#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x5
13943/* enum: DPDK TXDP firmware */
13944#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x6
13945/* enum: BIST TXDP firmware */
13946#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d
13947/* enum: TXDP Test firmware image 1 */
13948#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13949/* enum: TXDP Test firmware image 2 */
13950#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13951/* enum: TXDP CSR bus test firmware */
13952#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x103
13953#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_OFST 8
13954#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_LEN 2
13955#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_OFST 8
13956#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 0
13957#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_WIDTH 12
13958#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_OFST 8
13959#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_LBN 12
13960#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13961/* enum: reserved value - do not use (may indicate alternative interpretation
13962 * of REV field in future)
13963 */
13964#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x0
13965/* enum: Trivial RX PD firmware for early Huntington development (Huntington
13966 * development only)
13967 */
13968#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
13969/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
13970 */
13971#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13972/* enum: RX PD firmware with approximately Siena-compatible behaviour
13973 * (Huntington development only)
13974 */
13975#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
13976/* enum: Full featured RX PD production firmware */
13977#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
13978/* enum: (deprecated original name for the FULL_FEATURED variant) */
13979#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x3
13980/* enum: siena_compat variant RX PD firmware using PM rather than MAC
13981 * (Huntington development only)
13982 */
13983#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13984/* enum: Low latency RX PD production firmware */
13985#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
13986/* enum: Packed stream RX PD production firmware */
13987#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
13988/* enum: RX PD firmware handling layer 2 only for high packet rate performance
13989 * tests (Medford development only)
13990 */
13991#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
13992/* enum: Rules engine RX PD production firmware */
13993#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
13994/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13995#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x9
13996/* enum: DPDK RX PD production firmware */
13997#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa
13998/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
13999#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14000/* enum: RX PD firmware parsing but not filtering network overlay tunnel
14001 * encapsulations (Medford development only)
14002 */
14003#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14004#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_OFST 10
14005#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_LEN 2
14006#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_OFST 10
14007#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 0
14008#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_WIDTH 12
14009#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_OFST 10
14010#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_LBN 12
14011#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14012/* enum: reserved value - do not use (may indicate alternative interpretation
14013 * of REV field in future)
14014 */
14015#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x0
14016/* enum: Trivial TX PD firmware for early Huntington development (Huntington
14017 * development only)
14018 */
14019#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14020/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
14021 */
14022#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14023/* enum: TX PD firmware with approximately Siena-compatible behaviour
14024 * (Huntington development only)
14025 */
14026#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14027/* enum: Full featured TX PD production firmware */
14028#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14029/* enum: (deprecated original name for the FULL_FEATURED variant) */
14030#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14031/* enum: siena_compat variant TX PD firmware using PM rather than MAC
14032 * (Huntington development only)
14033 */
14034#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14035#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14036/* enum: TX PD firmware handling layer 2 only for high packet rate performance
14037 * tests (Medford development only)
14038 */
14039#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14040/* enum: Rules engine TX PD production firmware */
14041#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14042/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14043#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14044/* enum: DPDK TX PD production firmware */
14045#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa
14046/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14047#define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14048/* Hardware capabilities of NIC */
14049#define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_OFST 12
14050#define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 4
14051/* Licensed capabilities */
14052#define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_OFST 16
14053#define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 4
14054/* Second word of flags. Not present on older firmware (check the length). */
14055#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST 20
14056#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 4
14057#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_OFST 20
14058#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 0
14059#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_WIDTH 1
14060#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_OFST 20
14061#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_LBN 1
14062#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14063#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_OFST 20
14064#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_LBN 2
14065#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVQ_TIMER_CTRL_WIDTH 1
14066#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_OFST 20
14067#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_LBN 3
14068#define MC_CMD_GET_CAPABILITIES_V8_OUT_EVENT_CUT_THROUGH_WIDTH 1
14069#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_OFST 20
14070#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 4
14071#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_WIDTH 1
14072#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_OFST 20
14073#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_LBN 5
14074#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14075#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
14076#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
14077#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14078#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
14079#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
14080#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14081#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_OFST 20
14082#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_LBN 7
14083#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_EVQ_V2_WIDTH 1
14084#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_OFST 20
14085#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_LBN 8
14086#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14087#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_OFST 20
14088#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_LBN 9
14089#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TIMESTAMP_WIDTH 1
14090#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_OFST 20
14091#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_LBN 10
14092#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_SNIFF_WIDTH 1
14093#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_OFST 20
14094#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_LBN 11
14095#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_SNIFF_WIDTH 1
14096#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
14097#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
14098#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14099#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_OFST 20
14100#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_LBN 13
14101#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_BACKGROUND_WIDTH 1
14102#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_OFST 20
14103#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_LBN 14
14104#define MC_CMD_GET_CAPABILITIES_V8_OUT_MCDI_DB_RETURN_WIDTH 1
14105#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_OFST 20
14106#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_LBN 15
14107#define MC_CMD_GET_CAPABILITIES_V8_OUT_CTPIO_WIDTH 1
14108#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_OFST 20
14109#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_LBN 16
14110#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_SUPPORT_WIDTH 1
14111#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_OFST 20
14112#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_LBN 17
14113#define MC_CMD_GET_CAPABILITIES_V8_OUT_TSA_BOUND_WIDTH 1
14114#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
14115#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
14116#define MC_CMD_GET_CAPABILITIES_V8_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14117#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_OFST 20
14118#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_LBN 19
14119#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_FLAG_WIDTH 1
14120#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_OFST 20
14121#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_LBN 20
14122#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_WIDTH 1
14123#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
14124#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
14125#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14126#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
14127#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
14128#define MC_CMD_GET_CAPABILITIES_V8_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14129#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_OFST 20
14130#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_LBN 22
14131#define MC_CMD_GET_CAPABILITIES_V8_OUT_L3XUDP_SUPPORT_WIDTH 1
14132#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
14133#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
14134#define MC_CMD_GET_CAPABILITIES_V8_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14135#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_OFST 20
14136#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_LBN 24
14137#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_SPREADING_WIDTH 1
14138#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_OFST 20
14139#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_LBN 25
14140#define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_HLB_IDLE_WIDTH 1
14141#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
14142#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
14143#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14144#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
14145#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
14146#define MC_CMD_GET_CAPABILITIES_V8_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14147#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_OFST 20
14148#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_LBN 28
14149#define MC_CMD_GET_CAPABILITIES_V8_OUT_BUNDLE_UPDATE_WIDTH 1
14150#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_OFST 20
14151#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_LBN 29
14152#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V3_WIDTH 1
14153#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_OFST 20
14154#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_LBN 30
14155#define MC_CMD_GET_CAPABILITIES_V8_OUT_DYNAMIC_SENSORS_WIDTH 1
14156#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
14157#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
14158#define MC_CMD_GET_CAPABILITIES_V8_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14159/* Number of FATSOv2 contexts per datapath supported by this NIC (when
14160 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14161 */
14162#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
14163#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
14164/* One byte per PF containing the number of the external port assigned to this
14165 * PF, indexed by PF number. Special values indicate that a PF is either not
14166 * present or not assigned.
14167 */
14168#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
14169#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14170#define MC_CMD_GET_CAPABILITIES_V8_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
14171/* enum: The caller is not permitted to access information on this PF. */
14172#define MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff
14173/* enum: PF does not exist. */
14174#define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe
14175/* enum: PF does exist but is not assigned to any external port. */
14176#define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd
14177/* enum: This value indicates that PF is assigned, but it cannot be expressed
14178 * in this field. It is intended for a possible future situation where a more
14179 * complex scheme of PFs to ports mapping is being used. The future driver
14180 * should look for a new field supporting the new scheme. The current/old
14181 * driver should treat this value as PF_NOT_ASSIGNED.
14182 */
14183#define MC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14184/* One byte per PF containing the number of its VFs, indexed by PF number. A
14185 * special value indicates that a PF is not present.
14186 */
14187#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_OFST 42
14188#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_LEN 1
14189#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VFS_PER_PF_NUM 16
14190/* enum: The caller is not permitted to access information on this PF. */
14191/* MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */
14192/* enum: PF does not exist. */
14193/* MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */
14194/* Number of VIs available for each external port */
14195#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_OFST 58
14196#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_LEN 2
14197#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4
14198/* Size of RX descriptor cache expressed as binary logarithm The actual size
14199 * equals (2 ^ RX_DESC_CACHE_SIZE)
14200 */
14201#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_OFST 66
14202#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DESC_CACHE_SIZE_LEN 1
14203/* Size of TX descriptor cache expressed as binary logarithm The actual size
14204 * equals (2 ^ TX_DESC_CACHE_SIZE)
14205 */
14206#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_OFST 67
14207#define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_DESC_CACHE_SIZE_LEN 1
14208/* Total number of available PIO buffers */
14209#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_OFST 68
14210#define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_PIO_BUFFS_LEN 2
14211/* Size of a single PIO buffer */
14212#define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_OFST 70
14213#define MC_CMD_GET_CAPABILITIES_V8_OUT_SIZE_PIO_BUFF_LEN 2
14214/* On chips later than Medford the amount of address space assigned to each VI
14215 * is configurable. This is a global setting that the driver must query to
14216 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14217 * with 8k VI windows.
14218 */
14219#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_OFST 72
14220#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_LEN 1
14221/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14222 * CTPIO is not mapped.
14223 */
14224#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x0
14225/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14226#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x1
14227/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14228#define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x2
14229/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
14230 * (SF-115995-SW) in the present configuration of firmware and port mode.
14231 */
14232#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
14233#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
14234/* Number of buffers per adapter that can be used for VFIFO Stuffing
14235 * (SF-115995-SW) in the present configuration of firmware and port mode.
14236 */
14237#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
14238#define MC_CMD_GET_CAPABILITIES_V8_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
14239/* Entry count in the MAC stats array, including the final GENERATION_END
14240 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
14241 * hold at least this many 64-bit stats values, if they wish to receive all
14242 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
14243 * stats array returned will be truncated.
14244 */
14245#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_OFST 76
14246#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAC_STATS_NUM_STATS_LEN 2
14247/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
14248 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
14249 */
14250#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_OFST 80
14251#define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 4
14252/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
14253 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
14254 * they create an RX queue. Due to hardware limitations, only a small number of
14255 * different buffer sizes may be available concurrently. Nonzero entries in
14256 * this array are the sizes of buffers which the system guarantees will be
14257 * available for use. If the list is empty, there are no limitations on
14258 * concurrent buffer sizes.
14259 */
14260#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
14261#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
14262#define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
14263/* Third word of flags. Not present on older firmware (check the length). */
14264#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST 148
14265#define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 4
14266#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_OFST 148
14267#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 0
14268#define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_WIDTH 1
14269#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_OFST 148
14270#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_LBN 1
14271#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_EVEN_SPREADING_WIDTH 1
14272#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
14273#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
14274#define MC_CMD_GET_CAPABILITIES_V8_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
14275#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_OFST 148
14276#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_LBN 3
14277#define MC_CMD_GET_CAPABILITIES_V8_OUT_MAE_SUPPORTED_WIDTH 1
14278#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_OFST 148
14279#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 4
14280#define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_WIDTH 1
14281#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
14282#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
14283#define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
14284#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
14285#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
14286#define MC_CMD_GET_CAPABILITIES_V8_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
14287#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
14288#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
14289#define MC_CMD_GET_CAPABILITIES_V8_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
14290/* These bits are reserved for communicating test-specific capabilities to
14291 * host-side test software. All production drivers should treat this field as
14292 * opaque.
14293 */
14294#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_OFST 152
14295#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LEN 8
14296#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_OFST 152
14297#define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_OFST 156
14298
14299/* MC_CMD_GET_CAPABILITIES_V9_OUT msgresponse */
14300#define MC_CMD_GET_CAPABILITIES_V9_OUT_LEN 184
14301/* First word of flags. */
14302#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 0
14303#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 4
14304#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 0
14305#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_LBN 3
14306#define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_WIDTH 1
14307#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 0
14308#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 4
14309#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_WIDTH 1
14310#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 0
14311#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_LBN 5
14312#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_WIDTH 1
14313#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14314#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6
14315#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1
14316#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 0
14317#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_LBN 7
14318#define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_WIDTH 1
14319#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14320#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_LBN 8
14321#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1
14322#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 0
14323#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_LBN 9
14324#define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_WIDTH 1
14325#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14326#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10
14327#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1
14328#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14329#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11
14330#define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
14331#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14332#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_LBN 12
14333#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1
14334#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 0
14335#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_LBN 13
14336#define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_WIDTH 1
14337#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 0
14338#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_LBN 14
14339#define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_WIDTH 1
14340#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14341#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15
14342#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1
14343#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 0
14344#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_LBN 16
14345#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_WIDTH 1
14346#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 0
14347#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_LBN 17
14348#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_WIDTH 1
14349#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 0
14350#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_LBN 18
14351#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_WIDTH 1
14352#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 0
14353#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_LBN 19
14354#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_WIDTH 1
14355#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 0
14356#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_LBN 20
14357#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_WIDTH 1
14358#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 0
14359#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_LBN 21
14360#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_WIDTH 1
14361#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 0
14362#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_LBN 22
14363#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_WIDTH 1
14364#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 0
14365#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_LBN 23
14366#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_WIDTH 1
14367#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 0
14368#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_LBN 24
14369#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_WIDTH 1
14370#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 0
14371#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_LBN 25
14372#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_WIDTH 1
14373#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 0
14374#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_LBN 26
14375#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_WIDTH 1
14376#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14377#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_LBN 27
14378#define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
14379#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 0
14380#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_LBN 28
14381#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_WIDTH 1
14382#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14383#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29
14384#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1
14385#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 0
14386#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_LBN 30
14387#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_WIDTH 1
14388#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 0
14389#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_LBN 31
14390#define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_WIDTH 1
14391/* RxDPCPU firmware id. */
14392#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 4
14393#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_LEN 2
14394/* enum: Standard RXDP firmware */
14395#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x0
14396/* enum: Low latency RXDP firmware */
14397#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x1
14398/* enum: Packed stream RXDP firmware */
14399#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x2
14400/* enum: Rules engine RXDP firmware */
14401#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x5
14402/* enum: DPDK RXDP firmware */
14403#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x6
14404/* enum: BIST RXDP firmware */
14405#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a
14406/* enum: RXDP Test firmware image 1 */
14407#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14408/* enum: RXDP Test firmware image 2 */
14409#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14410/* enum: RXDP Test firmware image 3 */
14411#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14412/* enum: RXDP Test firmware image 4 */
14413#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14414/* enum: RXDP Test firmware image 5 */
14415#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x105
14416/* enum: RXDP Test firmware image 6 */
14417#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14418/* enum: RXDP Test firmware image 7 */
14419#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14420/* enum: RXDP Test firmware image 8 */
14421#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14422/* enum: RXDP Test firmware image 9 */
14423#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14424/* enum: RXDP Test firmware image 10 */
14425#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c
14426/* TxDPCPU firmware id. */
14427#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_OFST 6
14428#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DPCPU_FW_ID_LEN 2
14429/* enum: Standard TXDP firmware */
14430#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x0
14431/* enum: Low latency TXDP firmware */
14432#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x1
14433/* enum: High packet rate TXDP firmware */
14434#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x3
14435/* enum: Rules engine TXDP firmware */
14436#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x5
14437/* enum: DPDK TXDP firmware */
14438#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x6
14439/* enum: BIST TXDP firmware */
14440#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d
14441/* enum: TXDP Test firmware image 1 */
14442#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14443/* enum: TXDP Test firmware image 2 */
14444#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14445/* enum: TXDP CSR bus test firmware */
14446#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x103
14447#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_OFST 8
14448#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_LEN 2
14449#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_OFST 8
14450#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 0
14451#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_WIDTH 12
14452#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_OFST 8
14453#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_LBN 12
14454#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14455/* enum: reserved value - do not use (may indicate alternative interpretation
14456 * of REV field in future)
14457 */
14458#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x0
14459/* enum: Trivial RX PD firmware for early Huntington development (Huntington
14460 * development only)
14461 */
14462#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14463/* enum: RX PD firmware for telemetry prototyping (Medford2 development only)
14464 */
14465#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14466/* enum: RX PD firmware with approximately Siena-compatible behaviour
14467 * (Huntington development only)
14468 */
14469#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14470/* enum: Full featured RX PD production firmware */
14471#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14472/* enum: (deprecated original name for the FULL_FEATURED variant) */
14473#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14474/* enum: siena_compat variant RX PD firmware using PM rather than MAC
14475 * (Huntington development only)
14476 */
14477#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14478/* enum: Low latency RX PD production firmware */
14479#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14480/* enum: Packed stream RX PD production firmware */
14481#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14482/* enum: RX PD firmware handling layer 2 only for high packet rate performance
14483 * tests (Medford development only)
14484 */
14485#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14486/* enum: Rules engine RX PD production firmware */
14487#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14488/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14489#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14490/* enum: DPDK RX PD production firmware */
14491#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa
14492/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14493#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14494/* enum: RX PD firmware parsing but not filtering network overlay tunnel
14495 * encapsulations (Medford development only)
14496 */
14497#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14498#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_OFST 10
14499#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_LEN 2
14500#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_OFST 10
14501#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 0
14502#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_WIDTH 12
14503#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_OFST 10
14504#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_LBN 12
14505#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14506/* enum: reserved value - do not use (may indicate alternative interpretation
14507 * of REV field in future)
14508 */
14509#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x0
14510/* enum: Trivial TX PD firmware for early Huntington development (Huntington
14511 * development only)
14512 */
14513#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14514/* enum: TX PD firmware for telemetry prototyping (Medford2 development only)
14515 */
14516#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14517/* enum: TX PD firmware with approximately Siena-compatible behaviour
14518 * (Huntington development only)
14519 */
14520#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14521/* enum: Full featured TX PD production firmware */
14522#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14523/* enum: (deprecated original name for the FULL_FEATURED variant) */
14524#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14525/* enum: siena_compat variant TX PD firmware using PM rather than MAC
14526 * (Huntington development only)
14527 */
14528#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14529#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14530/* enum: TX PD firmware handling layer 2 only for high packet rate performance
14531 * tests (Medford development only)
14532 */
14533#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14534/* enum: Rules engine TX PD production firmware */
14535#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14536/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14537#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14538/* enum: DPDK TX PD production firmware */
14539#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa
14540/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
14541#define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14542/* Hardware capabilities of NIC */
14543#define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_OFST 12
14544#define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 4
14545/* Licensed capabilities */
14546#define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_OFST 16
14547#define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 4
14548/* Second word of flags. Not present on older firmware (check the length). */
14549#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_OFST 20
14550#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 4
14551#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_OFST 20
14552#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 0
14553#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_WIDTH 1
14554#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_OFST 20
14555#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_LBN 1
14556#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_ENCAP_WIDTH 1
14557#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_OFST 20
14558#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_LBN 2
14559#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVQ_TIMER_CTRL_WIDTH 1
14560#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_OFST 20
14561#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_LBN 3
14562#define MC_CMD_GET_CAPABILITIES_V9_OUT_EVENT_CUT_THROUGH_WIDTH 1
14563#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_OFST 20
14564#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 4
14565#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_WIDTH 1
14566#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_OFST 20
14567#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_LBN 5
14568#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VFIFO_ULL_MODE_WIDTH 1
14569#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_OFST 20
14570#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN 6
14571#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_40G_TX_SIZE_BINS_WIDTH 1
14572#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_OFST 20
14573#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_LBN 7
14574#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_TYPE_SUPPORTED_WIDTH 1
14575#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_OFST 20
14576#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_LBN 7
14577#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_EVQ_V2_WIDTH 1
14578#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_OFST 20
14579#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_LBN 8
14580#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_TIMESTAMPING_WIDTH 1
14581#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_OFST 20
14582#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_LBN 9
14583#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TIMESTAMP_WIDTH 1
14584#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_OFST 20
14585#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_LBN 10
14586#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_SNIFF_WIDTH 1
14587#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_OFST 20
14588#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_LBN 11
14589#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_SNIFF_WIDTH 1
14590#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_OFST 20
14591#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_LBN 12
14592#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_REPORT_VERIFY_RESULT_WIDTH 1
14593#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_OFST 20
14594#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_LBN 13
14595#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_BACKGROUND_WIDTH 1
14596#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_OFST 20
14597#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_LBN 14
14598#define MC_CMD_GET_CAPABILITIES_V9_OUT_MCDI_DB_RETURN_WIDTH 1
14599#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_OFST 20
14600#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_LBN 15
14601#define MC_CMD_GET_CAPABILITIES_V9_OUT_CTPIO_WIDTH 1
14602#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_OFST 20
14603#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_LBN 16
14604#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_SUPPORT_WIDTH 1
14605#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_OFST 20
14606#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_LBN 17
14607#define MC_CMD_GET_CAPABILITIES_V9_OUT_TSA_BOUND_WIDTH 1
14608#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_OFST 20
14609#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_LBN 18
14610#define MC_CMD_GET_CAPABILITIES_V9_OUT_SF_ADAPTER_AUTHENTICATION_WIDTH 1
14611#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_OFST 20
14612#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_LBN 19
14613#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_FLAG_WIDTH 1
14614#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_OFST 20
14615#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_LBN 20
14616#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_WIDTH 1
14617#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_OFST 20
14618#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_LBN 21
14619#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_SUPER_BUFFER_WIDTH 1
14620#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_OFST 20
14621#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
14622#define MC_CMD_GET_CAPABILITIES_V9_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
14623#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_OFST 20
14624#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_LBN 22
14625#define MC_CMD_GET_CAPABILITIES_V9_OUT_L3XUDP_SUPPORT_WIDTH 1
14626#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_OFST 20
14627#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
14628#define MC_CMD_GET_CAPABILITIES_V9_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
14629#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_OFST 20
14630#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_LBN 24
14631#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_SPREADING_WIDTH 1
14632#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_OFST 20
14633#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_LBN 25
14634#define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_HLB_IDLE_WIDTH 1
14635#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_OFST 20
14636#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_LBN 26
14637#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_NO_CONT_EV_WIDTH 1
14638#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_OFST 20
14639#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_LBN 27
14640#define MC_CMD_GET_CAPABILITIES_V9_OUT_INIT_RXQ_WITH_BUFFER_SIZE_WIDTH 1
14641#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_OFST 20
14642#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_LBN 28
14643#define MC_CMD_GET_CAPABILITIES_V9_OUT_BUNDLE_UPDATE_WIDTH 1
14644#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_OFST 20
14645#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_LBN 29
14646#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V3_WIDTH 1
14647#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_OFST 20
14648#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_LBN 30
14649#define MC_CMD_GET_CAPABILITIES_V9_OUT_DYNAMIC_SENSORS_WIDTH 1
14650#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_OFST 20
14651#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_LBN 31
14652#define MC_CMD_GET_CAPABILITIES_V9_OUT_NVRAM_UPDATE_POLL_VERIFY_RESULT_WIDTH 1
14653/* Number of FATSOv2 contexts per datapath supported by this NIC (when
14654 * TX_TSO_V2 == 1). Not present on older firmware (check the length).
14655 */
14656#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24
14657#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2
14658/* One byte per PF containing the number of the external port assigned to this
14659 * PF, indexed by PF number. Special values indicate that a PF is either not
14660 * present or not assigned.
14661 */
14662#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_OFST 26
14663#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
14664#define MC_CMD_GET_CAPABILITIES_V9_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
14665/* enum: The caller is not permitted to access information on this PF. */
14666#define MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff
14667/* enum: PF does not exist. */
14668#define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe
14669/* enum: PF does exist but is not assigned to any external port. */
14670#define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd
14671/* enum: This value indicates that PF is assigned, but it cannot be expressed
14672 * in this field. It is intended for a possible future situation where a more
14673 * complex scheme of PFs to ports mapping is being used. The future driver
14674 * should look for a new field supporting the new scheme. The current/old
14675 * driver should treat this value as PF_NOT_ASSIGNED.
14676 */
14677#define MC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14678/* One byte per PF containing the number of its VFs, indexed by PF number. A
14679 * special value indicates that a PF is not present.
14680 */
14681#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_OFST 42
14682#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_LEN 1
14683#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VFS_PER_PF_NUM 16
14684/* enum: The caller is not permitted to access information on this PF. */
14685/* MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */
14686/* enum: PF does not exist. */
14687/* MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */
14688/* Number of VIs available for each external port */
14689#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_OFST 58
14690#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_LEN 2
14691#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4
14692/* Size of RX descriptor cache expressed as binary logarithm The actual size
14693 * equals (2 ^ RX_DESC_CACHE_SIZE)
14694 */
14695#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_OFST 66
14696#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DESC_CACHE_SIZE_LEN 1
14697/* Size of TX descriptor cache expressed as binary logarithm The actual size
14698 * equals (2 ^ TX_DESC_CACHE_SIZE)
14699 */
14700#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_OFST 67
14701#define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_DESC_CACHE_SIZE_LEN 1
14702/* Total number of available PIO buffers */
14703#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_OFST 68
14704#define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_PIO_BUFFS_LEN 2
14705/* Size of a single PIO buffer */
14706#define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_OFST 70
14707#define MC_CMD_GET_CAPABILITIES_V9_OUT_SIZE_PIO_BUFF_LEN 2
14708/* On chips later than Medford the amount of address space assigned to each VI
14709 * is configurable. This is a global setting that the driver must query to
14710 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14711 * with 8k VI windows.
14712 */
14713#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_OFST 72
14714#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_LEN 1
14715/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14716 * CTPIO is not mapped.
14717 */
14718#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x0
14719/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14720#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x1
14721/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14722#define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x2
14723/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
14724 * (SF-115995-SW) in the present configuration of firmware and port mode.
14725 */
14726#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_OFST 73
14727#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_VFIFOS_LEN 1
14728/* Number of buffers per adapter that can be used for VFIFO Stuffing
14729 * (SF-115995-SW) in the present configuration of firmware and port mode.
14730 */
14731#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_OFST 74
14732#define MC_CMD_GET_CAPABILITIES_V9_OUT_VFIFO_STUFFING_NUM_CP_BUFFERS_LEN 2
14733/* Entry count in the MAC stats array, including the final GENERATION_END
14734 * entry. For MAC stats DMA, drivers should allocate a buffer large enough to
14735 * hold at least this many 64-bit stats values, if they wish to receive all
14736 * available stats. If the buffer is shorter than MAC_STATS_NUM_STATS * 8, the
14737 * stats array returned will be truncated.
14738 */
14739#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_OFST 76
14740#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAC_STATS_NUM_STATS_LEN 2
14741/* Maximum supported value for MC_CMD_FILTER_OP_V3/MATCH_MARK_VALUE. This field
14742 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
14743 */
14744#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_OFST 80
14745#define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 4
14746/* On devices where the INIT_RXQ_WITH_BUFFER_SIZE flag (in
14747 * GET_CAPABILITIES_OUT_V2) is set, drivers have to specify a buffer size when
14748 * they create an RX queue. Due to hardware limitations, only a small number of
14749 * different buffer sizes may be available concurrently. Nonzero entries in
14750 * this array are the sizes of buffers which the system guarantees will be
14751 * available for use. If the list is empty, there are no limitations on
14752 * concurrent buffer sizes.
14753 */
14754#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_OFST 84
14755#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
14756#define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_NUM 16
14757/* Third word of flags. Not present on older firmware (check the length). */
14758#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_OFST 148
14759#define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 4
14760#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_OFST 148
14761#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 0
14762#define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_WIDTH 1
14763#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_OFST 148
14764#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_LBN 1
14765#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_EVEN_SPREADING_WIDTH 1
14766#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_OFST 148
14767#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_LBN 2
14768#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_SELECTABLE_TABLE_SIZE_WIDTH 1
14769#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_OFST 148
14770#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_LBN 3
14771#define MC_CMD_GET_CAPABILITIES_V9_OUT_MAE_SUPPORTED_WIDTH 1
14772#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_OFST 148
14773#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 4
14774#define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_WIDTH 1
14775#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_OFST 148
14776#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_LBN 5
14777#define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_PER_ENCAP_RULE_WIDTH 1
14778#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_OFST 148
14779#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_LBN 6
14780#define MC_CMD_GET_CAPABILITIES_V9_OUT_EXTENDED_WIDTH_EVQS_SUPPORTED_WIDTH 1
14781#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_OFST 148
14782#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_LBN 7
14783#define MC_CMD_GET_CAPABILITIES_V9_OUT_UNSOL_EV_CREDIT_SUPPORTED_WIDTH 1
14784/* These bits are reserved for communicating test-specific capabilities to
14785 * host-side test software. All production drivers should treat this field as
14786 * opaque.
14787 */
14788#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_OFST 152
14789#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LEN 8
14790#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_OFST 152
14791#define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_OFST 156
14792/* The minimum size (in table entries) of indirection table to be allocated
14793 * from the pool for an RSS context. Note that the table size used must be a
14794 * power of 2.
14795 */
14796#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_OFST 160
14797#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
14798/* The maximum size (in table entries) of indirection table to be allocated
14799 * from the pool for an RSS context. Note that the table size used must be a
14800 * power of 2.
14801 */
14802#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_OFST 164
14803#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
14804/* The maximum number of queues that can be used by an RSS context in exclusive
14805 * mode. In exclusive mode the context has a configurable indirection table and
14806 * a configurable RSS key.
14807 */
14808#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_OFST 168
14809#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
14810/* The maximum number of queues that can be used by an RSS context in even-
14811 * spreading mode. In even-spreading mode the context has no indirection table
14812 * but it does have a configurable RSS key.
14813 */
14814#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_OFST 172
14815#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
14816/* The total number of RSS contexts supported. Note that the number of
14817 * available contexts using indirection tables is also limited by the
14818 * availability of indirection table space allocated from a common pool.
14819 */
14820#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_OFST 176
14821#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 4
14822/* The total amount of indirection table space that can be shared between RSS
14823 * contexts.
14824 */
14825#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_OFST 180
14826#define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 4
14827
14828
14829/***********************************/
14830/* MC_CMD_V2_EXTN
14831 * Encapsulation for a v2 extended command
14832 */
14833#define MC_CMD_V2_EXTN 0x7f
14834
14835/* MC_CMD_V2_EXTN_IN msgrequest */
14836#define MC_CMD_V2_EXTN_IN_LEN 4
14837/* the extended command number */
14838#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
14839#define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
14840#define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
14841#define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
14842/* the actual length of the encapsulated command (which is not in the v1
14843 * header)
14844 */
14845#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
14846#define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
14847#define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
14848#define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2
14849/* Type of command/response */
14850#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28
14851#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
14852/* enum: MCDI command directed to or response originating from the MC. */
14853#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
14854/* enum: MCDI command directed to a TSA controller. MCDI responses of this type
14855 * are not defined.
14856 */
14857#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
14858
14859
14860/***********************************/
14861/* MC_CMD_LINK_PIOBUF
14862 * Link a push I/O buffer to a TxQ
14863 */
14864#define MC_CMD_LINK_PIOBUF 0x92
14865#undef MC_CMD_0x92_PRIVILEGE_CTG
14866
14867#define MC_CMD_0x92_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
14868
14869/* MC_CMD_LINK_PIOBUF_IN msgrequest */
14870#define MC_CMD_LINK_PIOBUF_IN_LEN 8
14871/* Handle for allocated push I/O buffer. */
14872#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
14873#define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
14874/* Function Local Instance (VI) number. */
14875#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
14876#define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
14877
14878/* MC_CMD_LINK_PIOBUF_OUT msgresponse */
14879#define MC_CMD_LINK_PIOBUF_OUT_LEN 0
14880
14881
14882/***********************************/
14883/* MC_CMD_UNLINK_PIOBUF
14884 * Unlink a push I/O buffer from a TxQ
14885 */
14886#define MC_CMD_UNLINK_PIOBUF 0x93
14887#undef MC_CMD_0x93_PRIVILEGE_CTG
14888
14889#define MC_CMD_0x93_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
14890
14891/* MC_CMD_UNLINK_PIOBUF_IN msgrequest */
14892#define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
14893/* Function Local Instance (VI) number. */
14894#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
14895#define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
14896
14897/* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */
14898#define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
14899
14900
14901/***********************************/
14902/* MC_CMD_VSWITCH_ALLOC
14903 * allocate and initialise a v-switch.
14904 */
14905#define MC_CMD_VSWITCH_ALLOC 0x94
14906#undef MC_CMD_0x94_PRIVILEGE_CTG
14907
14908#define MC_CMD_0x94_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14909
14910/* MC_CMD_VSWITCH_ALLOC_IN msgrequest */
14911#define MC_CMD_VSWITCH_ALLOC_IN_LEN 16
14912/* The port to connect to the v-switch's upstream port. */
14913#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
14914#define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
14915/* The type of v-switch to create. */
14916#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
14917#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
14918/* enum: VLAN */
14919#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
14920/* enum: VEB */
14921#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
14922/* enum: VEPA (obsolete) */
14923#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
14924/* enum: MUX */
14925#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
14926/* enum: Snapper specific; semantics TBD */
14927#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
14928/* Flags controlling v-port creation */
14929#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8
14930#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
14931#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_OFST 8
14932#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
14933#define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
14934/* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
14935 * this must be one or greated, and the attached v-ports must have exactly this
14936 * number of tags. For other v-switch types, this must be zero of greater, and
14937 * is an upper limit on the number of VLAN tags for attached v-ports. An error
14938 * will be returned if existing configuration means we can't support attached
14939 * v-ports with this number of tags.
14940 */
14941#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
14942#define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
14943
14944/* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */
14945#define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
14946
14947
14948/***********************************/
14949/* MC_CMD_VSWITCH_FREE
14950 * de-allocate a v-switch.
14951 */
14952#define MC_CMD_VSWITCH_FREE 0x95
14953#undef MC_CMD_0x95_PRIVILEGE_CTG
14954
14955#define MC_CMD_0x95_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14956
14957/* MC_CMD_VSWITCH_FREE_IN msgrequest */
14958#define MC_CMD_VSWITCH_FREE_IN_LEN 4
14959/* The port to which the v-switch is connected. */
14960#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
14961#define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4
14962
14963/* MC_CMD_VSWITCH_FREE_OUT msgresponse */
14964#define MC_CMD_VSWITCH_FREE_OUT_LEN 0
14965
14966
14967/***********************************/
14968/* MC_CMD_VSWITCH_QUERY
14969 * read some config of v-switch. For now this command is an empty placeholder.
14970 * It may be used to check if a v-switch is connected to a given EVB port (if
14971 * not, then the command returns ENOENT).
14972 */
14973#define MC_CMD_VSWITCH_QUERY 0x63
14974#undef MC_CMD_0x63_PRIVILEGE_CTG
14975
14976#define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14977
14978/* MC_CMD_VSWITCH_QUERY_IN msgrequest */
14979#define MC_CMD_VSWITCH_QUERY_IN_LEN 4
14980/* The port to which the v-switch is connected. */
14981#define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
14982#define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
14983
14984/* MC_CMD_VSWITCH_QUERY_OUT msgresponse */
14985#define MC_CMD_VSWITCH_QUERY_OUT_LEN 0
14986
14987
14988/***********************************/
14989/* MC_CMD_VPORT_ALLOC
14990 * allocate a v-port.
14991 */
14992#define MC_CMD_VPORT_ALLOC 0x96
14993#undef MC_CMD_0x96_PRIVILEGE_CTG
14994
14995#define MC_CMD_0x96_PRIVILEGE_CTG SRIOV_CTG_GENERAL
14996
14997/* MC_CMD_VPORT_ALLOC_IN msgrequest */
14998#define MC_CMD_VPORT_ALLOC_IN_LEN 20
14999/* The port to which the v-switch is connected. */
15000#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
15001#define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
15002/* The type of the new v-port. */
15003#define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
15004#define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
15005/* enum: VLAN (obsolete) */
15006#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
15007/* enum: VEB (obsolete) */
15008#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
15009/* enum: VEPA (obsolete) */
15010#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
15011/* enum: A normal v-port receives packets which match a specified MAC and/or
15012 * VLAN.
15013 */
15014#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
15015/* enum: An expansion v-port packets traffic which don't match any other
15016 * v-port.
15017 */
15018#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
15019/* enum: An test v-port receives packets which match any filters installed by
15020 * its downstream components.
15021 */
15022#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
15023/* Flags controlling v-port creation */
15024#define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8
15025#define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
15026#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_OFST 8
15027#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
15028#define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
15029#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_OFST 8
15030#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1
15031#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1
15032/* The number of VLAN tags to insert/remove. An error will be returned if
15033 * incompatible with the number of VLAN tags specified for the upstream
15034 * v-switch.
15035 */
15036#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
15037#define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
15038/* The actual VLAN tags to insert/remove */
15039#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16
15040#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
15041#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_OFST 16
15042#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
15043#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16
15044#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_OFST 16
15045#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16
15046#define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16
15047
15048/* MC_CMD_VPORT_ALLOC_OUT msgresponse */
15049#define MC_CMD_VPORT_ALLOC_OUT_LEN 4
15050/* The handle of the new v-port */
15051#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
15052#define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4
15053
15054
15055/***********************************/
15056/* MC_CMD_VPORT_FREE
15057 * de-allocate a v-port.
15058 */
15059#define MC_CMD_VPORT_FREE 0x97
15060#undef MC_CMD_0x97_PRIVILEGE_CTG
15061
15062#define MC_CMD_0x97_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15063
15064/* MC_CMD_VPORT_FREE_IN msgrequest */
15065#define MC_CMD_VPORT_FREE_IN_LEN 4
15066/* The handle of the v-port */
15067#define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
15068#define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4
15069
15070/* MC_CMD_VPORT_FREE_OUT msgresponse */
15071#define MC_CMD_VPORT_FREE_OUT_LEN 0
15072
15073
15074/***********************************/
15075/* MC_CMD_VADAPTOR_ALLOC
15076 * allocate a v-adaptor.
15077 */
15078#define MC_CMD_VADAPTOR_ALLOC 0x98
15079#undef MC_CMD_0x98_PRIVILEGE_CTG
15080
15081#define MC_CMD_0x98_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15082
15083/* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */
15084#define MC_CMD_VADAPTOR_ALLOC_IN_LEN 30
15085/* The port to connect to the v-adaptor's port. */
15086#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
15087#define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
15088/* Flags controlling v-adaptor creation */
15089#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8
15090#define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
15091#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_OFST 8
15092#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
15093#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
15094#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 8
15095#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1
15096#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1
15097/* The number of VLAN tags to strip on receive */
15098#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12
15099#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4
15100/* The number of VLAN tags to transparently insert/remove. */
15101#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_OFST 16
15102#define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
15103/* The actual VLAN tags to insert/remove */
15104#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_OFST 20
15105#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
15106#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_OFST 20
15107#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
15108#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_WIDTH 16
15109#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_OFST 20
15110#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_LBN 16
15111#define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_1_WIDTH 16
15112/* The MAC address to assign to this v-adaptor */
15113#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24
15114#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6
15115/* enum: Derive the MAC address from the upstream port */
15116#define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
15117
15118/* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */
15119#define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
15120
15121
15122/***********************************/
15123/* MC_CMD_VADAPTOR_FREE
15124 * de-allocate a v-adaptor.
15125 */
15126#define MC_CMD_VADAPTOR_FREE 0x99
15127#undef MC_CMD_0x99_PRIVILEGE_CTG
15128
15129#define MC_CMD_0x99_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15130
15131/* MC_CMD_VADAPTOR_FREE_IN msgrequest */
15132#define MC_CMD_VADAPTOR_FREE_IN_LEN 4
15133/* The port to which the v-adaptor is connected. */
15134#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
15135#define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4
15136
15137/* MC_CMD_VADAPTOR_FREE_OUT msgresponse */
15138#define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
15139
15140
15141/***********************************/
15142/* MC_CMD_VADAPTOR_SET_MAC
15143 * assign a new MAC address to a v-adaptor.
15144 */
15145#define MC_CMD_VADAPTOR_SET_MAC 0x5d
15146#undef MC_CMD_0x5d_PRIVILEGE_CTG
15147
15148#define MC_CMD_0x5d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15149
15150/* MC_CMD_VADAPTOR_SET_MAC_IN msgrequest */
15151#define MC_CMD_VADAPTOR_SET_MAC_IN_LEN 10
15152/* The port to which the v-adaptor is connected. */
15153#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
15154#define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
15155/* The new MAC address to assign to this v-adaptor */
15156#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
15157#define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_LEN 6
15158
15159/* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */
15160#define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
15161
15162
15163/***********************************/
15164/* MC_CMD_VADAPTOR_GET_MAC
15165 * read the MAC address assigned to a v-adaptor.
15166 */
15167#define MC_CMD_VADAPTOR_GET_MAC 0x5e
15168#undef MC_CMD_0x5e_PRIVILEGE_CTG
15169
15170#define MC_CMD_0x5e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15171
15172/* MC_CMD_VADAPTOR_GET_MAC_IN msgrequest */
15173#define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4
15174/* The port to which the v-adaptor is connected. */
15175#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
15176#define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
15177
15178/* MC_CMD_VADAPTOR_GET_MAC_OUT msgresponse */
15179#define MC_CMD_VADAPTOR_GET_MAC_OUT_LEN 6
15180/* The MAC address assigned to this v-adaptor */
15181#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0
15182#define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6
15183
15184
15185/***********************************/
15186/* MC_CMD_VADAPTOR_QUERY
15187 * read some config of v-adaptor.
15188 */
15189#define MC_CMD_VADAPTOR_QUERY 0x61
15190#undef MC_CMD_0x61_PRIVILEGE_CTG
15191
15192#define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15193
15194/* MC_CMD_VADAPTOR_QUERY_IN msgrequest */
15195#define MC_CMD_VADAPTOR_QUERY_IN_LEN 4
15196/* The port to which the v-adaptor is connected. */
15197#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
15198#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
15199
15200/* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */
15201#define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12
15202/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
15203#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
15204#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4
15205/* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
15206#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
15207#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4
15208/* The number of VLAN tags that may still be added */
15209#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8
15210#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
15211
15212
15213/***********************************/
15214/* MC_CMD_EVB_PORT_ASSIGN
15215 * assign a port to a PCI function.
15216 */
15217#define MC_CMD_EVB_PORT_ASSIGN 0x9a
15218#undef MC_CMD_0x9a_PRIVILEGE_CTG
15219
15220#define MC_CMD_0x9a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15221
15222/* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */
15223#define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8
15224/* The port to assign. */
15225#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
15226#define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4
15227/* The target function to modify. */
15228#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
15229#define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
15230#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 4
15231#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
15232#define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16
15233#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 4
15234#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16
15235#define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16
15236
15237/* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */
15238#define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
15239
15240
15241/***********************************/
15242/* MC_CMD_RDWR_A64_REGIONS
15243 * Assign the 64 bit region addresses.
15244 */
15245#define MC_CMD_RDWR_A64_REGIONS 0x9b
15246#undef MC_CMD_0x9b_PRIVILEGE_CTG
15247
15248#define MC_CMD_0x9b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15249
15250/* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */
15251#define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17
15252#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
15253#define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4
15254#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
15255#define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4
15256#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8
15257#define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4
15258#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12
15259#define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4
15260/* Write enable bits 0-3, set to write, clear to read. */
15261#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128
15262#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
15263#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16
15264#define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1
15265
15266/* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included
15267 * regardless of state of write bits in the request.
15268 */
15269#define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16
15270#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
15271#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4
15272#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
15273#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4
15274#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8
15275#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4
15276#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12
15277#define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4
15278
15279
15280/***********************************/
15281/* MC_CMD_ONLOAD_STACK_ALLOC
15282 * Allocate an Onload stack ID.
15283 */
15284#define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
15285#undef MC_CMD_0x9c_PRIVILEGE_CTG
15286
15287#define MC_CMD_0x9c_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
15288
15289/* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */
15290#define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
15291/* The handle of the owning upstream port */
15292#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
15293#define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
15294
15295/* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */
15296#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
15297/* The handle of the new Onload stack */
15298#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
15299#define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4
15300
15301
15302/***********************************/
15303/* MC_CMD_ONLOAD_STACK_FREE
15304 * Free an Onload stack ID.
15305 */
15306#define MC_CMD_ONLOAD_STACK_FREE 0x9d
15307#undef MC_CMD_0x9d_PRIVILEGE_CTG
15308
15309#define MC_CMD_0x9d_PRIVILEGE_CTG SRIOV_CTG_ONLOAD
15310
15311/* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */
15312#define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
15313/* The handle of the Onload stack */
15314#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
15315#define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4
15316
15317/* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */
15318#define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
15319
15320
15321/***********************************/
15322/* MC_CMD_RSS_CONTEXT_ALLOC
15323 * Allocate an RSS context.
15324 */
15325#define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
15326#undef MC_CMD_0x9e_PRIVILEGE_CTG
15327
15328#define MC_CMD_0x9e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15329
15330/* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */
15331#define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12
15332/* The handle of the owning upstream port */
15333#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
15334#define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
15335/* The type of context to allocate */
15336#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
15337#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4
15338/* enum: Allocate a context for exclusive use. The key and indirection table
15339 * must be explicitly configured.
15340 */
15341#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
15342/* enum: Allocate a context for shared use; this will spread across a range of
15343 * queues, but the key and indirection table are pre-configured and may not be
15344 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
15345 */
15346#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
15347/* enum: Allocate a context to spread evenly across an arbitrary number of
15348 * queues. No indirection table space is allocated for this context. (EF100 and
15349 * later)
15350 */
15351#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x2
15352/* Number of queues spanned by this context. For exclusive contexts this must
15353 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
15354 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if
15355 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in
15356 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
15357 * spreading contexts this must be in the range 1 to
15358 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note
15359 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
15360 * be useful as a way of obtaining the Toeplitz hash.
15361 */
15362#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8
15363#define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
15364
15365/* MC_CMD_RSS_CONTEXT_ALLOC_V2_IN msgrequest */
15366#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_LEN 16
15367/* The handle of the owning upstream port */
15368#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 0
15369#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 4
15370/* The type of context to allocate */
15371#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 4
15372#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 4
15373/* enum: Allocate a context for exclusive use. The key and indirection table
15374 * must be explicitly configured.
15375 */
15376#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x0
15377/* enum: Allocate a context for shared use; this will spread across a range of
15378 * queues, but the key and indirection table are pre-configured and may not be
15379 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
15380 */
15381#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x1
15382/* enum: Allocate a context to spread evenly across an arbitrary number of
15383 * queues. No indirection table space is allocated for this context. (EF100 and
15384 * later)
15385 */
15386#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x2
15387/* Number of queues spanned by this context. For exclusive contexts this must
15388 * be in the range 1 to RSS_MAX_INDIRECTION_QUEUES, where
15389 * RSS_MAX_INDIRECTION_QUEUES is queried from MC_CMD_GET_CAPABILITIES_V9 or if
15390 * V9 is not supported then RSS_MAX_INDIRECTION_QUEUES is 64. Valid entries in
15391 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
15392 * spreading contexts this must be in the range 1 to
15393 * RSS_MAX_EVEN_SPREADING_QUEUES as queried from MC_CMD_GET_CAPABILITIES. Note
15394 * that specifying NUM_QUEUES = 1 will not perform any spreading but may still
15395 * be useful as a way of obtaining the Toeplitz hash.
15396 */
15397#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_OFST 8
15398#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 4
15399/* Size of indirection table to be allocated to this context from the pool.
15400 * Must be a power of 2. The minimum and maximum table size can be queried
15401 * using MC_CMD_GET_CAPABILITIES_V9. If there is not enough space remaining in
15402 * the common pool to allocate the requested table size, due to allocating
15403 * table space to other RSS contexts, then the command will fail with
15404 * MC_CMD_ERR_ENOSPC.
15405 */
15406#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_OFST 12
15407#define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 4
15408
15409/* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */
15410#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
15411/* The handle of the new RSS context. This should be considered opaque to the
15412 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
15413 * handle.
15414 */
15415#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
15416#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
15417/* enum: guaranteed invalid RSS context handle value */
15418#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
15419
15420
15421/***********************************/
15422/* MC_CMD_RSS_CONTEXT_FREE
15423 * Free an RSS context.
15424 */
15425#define MC_CMD_RSS_CONTEXT_FREE 0x9f
15426#undef MC_CMD_0x9f_PRIVILEGE_CTG
15427
15428#define MC_CMD_0x9f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15429
15430/* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */
15431#define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
15432/* The handle of the RSS context */
15433#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
15434#define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4
15435
15436/* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */
15437#define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
15438
15439
15440/***********************************/
15441/* MC_CMD_RSS_CONTEXT_SET_KEY
15442 * Set the Toeplitz hash key for an RSS context.
15443 */
15444#define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
15445#undef MC_CMD_0xa0_PRIVILEGE_CTG
15446
15447#define MC_CMD_0xa0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15448
15449/* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */
15450#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44
15451/* The handle of the RSS context */
15452#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
15453#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4
15454/* The 40-byte Toeplitz hash key (TBD endianness issues?) */
15455#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
15456#define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40
15457
15458/* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */
15459#define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
15460
15461
15462/***********************************/
15463/* MC_CMD_RSS_CONTEXT_GET_KEY
15464 * Get the Toeplitz hash key for an RSS context.
15465 */
15466#define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
15467#undef MC_CMD_0xa1_PRIVILEGE_CTG
15468
15469#define MC_CMD_0xa1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15470
15471/* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */
15472#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
15473/* The handle of the RSS context */
15474#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
15475#define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4
15476
15477/* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */
15478#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44
15479/* The 40-byte Toeplitz hash key (TBD endianness issues?) */
15480#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
15481#define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40
15482
15483
15484/***********************************/
15485/* MC_CMD_RSS_CONTEXT_SET_TABLE
15486 * Set the indirection table for an RSS context. This command should only be
15487 * used with indirection tables containing 128 entries, which is the default
15488 * when the RSS context is allocated without specifying a table size.
15489 */
15490#define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
15491#undef MC_CMD_0xa2_PRIVILEGE_CTG
15492
15493#define MC_CMD_0xa2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15494
15495/* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */
15496#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132
15497/* The handle of the RSS context */
15498#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
15499#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
15500/* The 128-byte indirection table (1 byte per entry) */
15501#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
15502#define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128
15503
15504/* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */
15505#define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
15506
15507
15508/***********************************/
15509/* MC_CMD_RSS_CONTEXT_GET_TABLE
15510 * Get the indirection table for an RSS context. This command should only be
15511 * used with indirection tables containing 128 entries, which is the default
15512 * when the RSS context is allocated without specifying a table size.
15513 */
15514#define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
15515#undef MC_CMD_0xa3_PRIVILEGE_CTG
15516
15517#define MC_CMD_0xa3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15518
15519/* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */
15520#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
15521/* The handle of the RSS context */
15522#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
15523#define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
15524
15525/* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */
15526#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132
15527/* The 128-byte indirection table (1 byte per entry) */
15528#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
15529#define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128
15530
15531
15532/***********************************/
15533/* MC_CMD_RSS_CONTEXT_WRITE_TABLE
15534 * Write a portion of a selectable-size indirection table for an RSS context.
15535 * This command must be used instead of MC_CMD_RSS_CONTEXT_SET_TABLE if the
15536 * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
15537 */
15538#define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e
15539#undef MC_CMD_0x13e_PRIVILEGE_CTG
15540
15541#define MC_CMD_0x13e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15542
15543/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN msgrequest */
15544#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMIN 8
15545#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX 252
15546#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LENMAX_MCDI2 1020
15547#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num))
15548#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4)
15549/* The handle of the RSS context */
15550#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_OFST 0
15551#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 4
15552/* An array of index-value pairs to be written to the table. Structure is
15553 * MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY.
15554 */
15555#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 4
15556#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 4
15557#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MINNUM 1
15558#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM 62
15559#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_MAXNUM_MCDI2 254
15560
15561/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT msgresponse */
15562#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT_LEN 0
15563
15564/* MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY structuredef */
15565#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 4
15566/* The index of the table entry to be written. */
15567#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_OFST 0
15568#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LEN 2
15569#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LBN 0
15570#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_WIDTH 16
15571/* The value to write into the table entry. */
15572#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_OFST 2
15573#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LEN 2
15574#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_LBN 16
15575#define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_VALUE_WIDTH 16
15576
15577
15578/***********************************/
15579/* MC_CMD_RSS_CONTEXT_READ_TABLE
15580 * Read a portion of a selectable-size indirection table for an RSS context.
15581 * This command must be used instead of MC_CMD_RSS_CONTEXT_GET_TABLE if the
15582 * RSS_SELECTABLE_TABLE_SIZE bit is set in MC_CMD_GET_CAPABILITIES.
15583 */
15584#define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f
15585#undef MC_CMD_0x13f_PRIVILEGE_CTG
15586
15587#define MC_CMD_0x13f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15588
15589/* MC_CMD_RSS_CONTEXT_READ_TABLE_IN msgrequest */
15590#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMIN 6
15591#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX 252
15592#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LENMAX_MCDI2 1020
15593#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num))
15594#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2)
15595/* The handle of the RSS context */
15596#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_OFST 0
15597#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 4
15598/* An array containing the indices of the entries to be read. */
15599#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 4
15600#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_LEN 2
15601#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MINNUM 1
15602#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM 124
15603#define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_MAXNUM_MCDI2 508
15604
15605/* MC_CMD_RSS_CONTEXT_READ_TABLE_OUT msgresponse */
15606#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMIN 2
15607#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX 252
15608#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LENMAX_MCDI2 1020
15609#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LEN(num) (0+2*(num))
15610#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2)
15611/* A buffer containing the requested entries read from the table. */
15612#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_OFST 0
15613#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_LEN 2
15614#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MINNUM 1
15615#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM 126
15616#define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_MAXNUM_MCDI2 510
15617
15618
15619/***********************************/
15620/* MC_CMD_RSS_CONTEXT_SET_FLAGS
15621 * Set various control flags for an RSS context.
15622 */
15623#define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
15624#undef MC_CMD_0xe1_PRIVILEGE_CTG
15625
15626#define MC_CMD_0xe1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15627
15628/* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */
15629#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8
15630/* The handle of the RSS context */
15631#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
15632#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
15633/* Hash control flags. The _EN bits are always supported, but new modes are
15634 * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES:
15635 * in this case, the MODE fields may be set to non-zero values, and will take
15636 * effect regardless of the settings of the _EN flags. See the RSS_MODE
15637 * structure for the meaning of the mode bits. Drivers must check the
15638 * capability before trying to set any _MODE fields, as older firmware will
15639 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
15640 * the case where all the _MODE flags are zero, the _EN flags take effect,
15641 * providing backward compatibility for existing drivers. (Setting all _MODE
15642 * *and* all _EN flags to zero is valid, to disable RSS spreading for that
15643 * particular packet type.)
15644 */
15645#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
15646#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
15647#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 4
15648#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
15649#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
15650#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 4
15651#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
15652#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
15653#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 4
15654#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2
15655#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
15656#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 4
15657#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3
15658#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
15659#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 4
15660#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
15661#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
15662#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 4
15663#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN 8
15664#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
15665#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 4
15666#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_LBN 12
15667#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
15668#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 4
15669#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN 16
15670#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
15671#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 4
15672#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN 20
15673#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
15674#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 4
15675#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_LBN 24
15676#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
15677#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 4
15678#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN 28
15679#define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
15680
15681/* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */
15682#define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
15683
15684
15685/***********************************/
15686/* MC_CMD_RSS_CONTEXT_GET_FLAGS
15687 * Get various control flags for an RSS context.
15688 */
15689#define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
15690#undef MC_CMD_0xe2_PRIVILEGE_CTG
15691
15692#define MC_CMD_0xe2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15693
15694/* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */
15695#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
15696/* The handle of the RSS context */
15697#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
15698#define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
15699
15700/* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */
15701#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8
15702/* Hash control flags. If all _MODE bits are zero (which will always be true
15703 * for older firmware which does not report the ADDITIONAL_RSS_MODES
15704 * capability), the _EN bits report the state. If any _MODE bits are non-zero
15705 * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES)
15706 * then the _EN bits should be disregarded, although the _MODE flags are
15707 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
15708 * context and in the case where the _EN flags were used in the SET. This
15709 * provides backward compatibility: old drivers will not be attempting to
15710 * derive any meaning from the _MODE bits (and can never set them to any value
15711 * not representable by the _EN bits); new drivers can always determine the
15712 * mode by looking only at the _MODE bits; the value returned by a GET can
15713 * always be used for a SET regardless of old/new driver vs. old/new firmware.
15714 */
15715#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
15716#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
15717#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 4
15718#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
15719#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
15720#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 4
15721#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
15722#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
15723#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 4
15724#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2
15725#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
15726#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 4
15727#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3
15728#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
15729#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 4
15730#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
15731#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
15732#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 4
15733#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN 8
15734#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
15735#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 4
15736#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN 12
15737#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
15738#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 4
15739#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN 16
15740#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
15741#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 4
15742#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN 20
15743#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
15744#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 4
15745#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN 24
15746#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
15747#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4
15748#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28
15749#define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
15750
15751
15752/***********************************/
15753/* MC_CMD_VPORT_ADD_MAC_ADDRESS
15754 * Add a MAC address to a v-port
15755 */
15756#define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
15757#undef MC_CMD_0xa8_PRIVILEGE_CTG
15758
15759#define MC_CMD_0xa8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15760
15761/* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */
15762#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10
15763/* The handle of the v-port */
15764#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
15765#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4
15766/* MAC address to add */
15767#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
15768#define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6
15769
15770/* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */
15771#define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
15772
15773
15774/***********************************/
15775/* MC_CMD_VPORT_DEL_MAC_ADDRESS
15776 * Delete a MAC address from a v-port
15777 */
15778#define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
15779#undef MC_CMD_0xa9_PRIVILEGE_CTG
15780
15781#define MC_CMD_0xa9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15782
15783/* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */
15784#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10
15785/* The handle of the v-port */
15786#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
15787#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4
15788/* MAC address to add */
15789#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
15790#define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6
15791
15792/* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */
15793#define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
15794
15795
15796/***********************************/
15797/* MC_CMD_VPORT_GET_MAC_ADDRESSES
15798 * Delete a MAC address from a v-port
15799 */
15800#define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
15801#undef MC_CMD_0xaa_PRIVILEGE_CTG
15802
15803#define MC_CMD_0xaa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15804
15805/* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */
15806#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
15807/* The handle of the v-port */
15808#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
15809#define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4
15810
15811/* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */
15812#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
15813#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250
15814#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX_MCDI2 1018
15815#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
15816#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6)
15817/* The number of MAC addresses returned */
15818#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
15819#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
15820/* Array of MAC addresses */
15821#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
15822#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6
15823#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
15824#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41
15825#define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM_MCDI2 169
15826
15827
15828/***********************************/
15829/* MC_CMD_VPORT_RECONFIGURE
15830 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
15831 * has already been passed to another function (v-port's user), then that
15832 * function will be reset before applying the changes.
15833 */
15834#define MC_CMD_VPORT_RECONFIGURE 0xeb
15835#undef MC_CMD_0xeb_PRIVILEGE_CTG
15836
15837#define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15838
15839/* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */
15840#define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44
15841/* The handle of the v-port */
15842#define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
15843#define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4
15844/* Flags requesting what should be changed. */
15845#define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
15846#define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
15847#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 4
15848#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
15849#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1
15850#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 4
15851#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1
15852#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1
15853/* The number of VLAN tags to insert/remove. An error will be returned if
15854 * incompatible with the number of VLAN tags specified for the upstream
15855 * v-switch.
15856 */
15857#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8
15858#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4
15859/* The actual VLAN tags to insert/remove */
15860#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12
15861#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
15862#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_OFST 12
15863#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
15864#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16
15865#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_OFST 12
15866#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16
15867#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16
15868/* The number of MAC addresses to add */
15869#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16
15870#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4
15871/* MAC addresses to add */
15872#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20
15873#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6
15874#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
15875
15876/* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */
15877#define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
15878#define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
15879#define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
15880#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_OFST 0
15881#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
15882#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1
15883
15884
15885/***********************************/
15886/* MC_CMD_EVB_PORT_QUERY
15887 * read some config of v-port.
15888 */
15889#define MC_CMD_EVB_PORT_QUERY 0x62
15890#undef MC_CMD_0x62_PRIVILEGE_CTG
15891
15892#define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15893
15894/* MC_CMD_EVB_PORT_QUERY_IN msgrequest */
15895#define MC_CMD_EVB_PORT_QUERY_IN_LEN 4
15896/* The handle of the v-port */
15897#define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0
15898#define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4
15899
15900/* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */
15901#define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8
15902/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */
15903#define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0
15904#define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4
15905/* The number of VLAN tags that may be used on a v-adaptor connected to this
15906 * EVB port.
15907 */
15908#define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4
15909#define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
15910
15911
15912/***********************************/
15913/* MC_CMD_GET_CLOCK
15914 * Return the system and PDCPU clock frequencies.
15915 */
15916#define MC_CMD_GET_CLOCK 0xac
15917#undef MC_CMD_0xac_PRIVILEGE_CTG
15918
15919#define MC_CMD_0xac_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15920
15921/* MC_CMD_GET_CLOCK_IN msgrequest */
15922#define MC_CMD_GET_CLOCK_IN_LEN 0
15923
15924/* MC_CMD_GET_CLOCK_OUT msgresponse */
15925#define MC_CMD_GET_CLOCK_OUT_LEN 8
15926/* System frequency, MHz */
15927#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
15928#define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4
15929/* DPCPU frequency, MHz */
15930#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
15931#define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4
15932
15933
15934/***********************************/
15935/* MC_CMD_TRIGGER_INTERRUPT
15936 * Trigger an interrupt by prodding the BIU.
15937 */
15938#define MC_CMD_TRIGGER_INTERRUPT 0xe3
15939#undef MC_CMD_0xe3_PRIVILEGE_CTG
15940
15941#define MC_CMD_0xe3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
15942
15943/* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */
15944#define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
15945/* Interrupt level relative to base for function. */
15946#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
15947#define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4
15948
15949/* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */
15950#define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
15951
15952
15953/***********************************/
15954/* MC_CMD_SHMBOOT_OP
15955 * Special operations to support (for now) shmboot.
15956 */
15957#define MC_CMD_SHMBOOT_OP 0xe6
15958#undef MC_CMD_0xe6_PRIVILEGE_CTG
15959
15960#define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
15961
15962/* MC_CMD_SHMBOOT_OP_IN msgrequest */
15963#define MC_CMD_SHMBOOT_OP_IN_LEN 4
15964/* Identifies the operation to perform */
15965#define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0
15966#define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4
15967/* enum: Copy slave_data section to the slave core. (Greenport only) */
15968#define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0
15969
15970/* MC_CMD_SHMBOOT_OP_OUT msgresponse */
15971#define MC_CMD_SHMBOOT_OP_OUT_LEN 0
15972
15973
15974/***********************************/
15975/* MC_CMD_SET_PSU
15976 * Adjusts power supply parameters. This is a warranty-voiding operation.
15977 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if
15978 * the parameter is out of range.
15979 */
15980#define MC_CMD_SET_PSU 0xea
15981#undef MC_CMD_0xea_PRIVILEGE_CTG
15982
15983#define MC_CMD_0xea_PRIVILEGE_CTG SRIOV_CTG_INSECURE
15984
15985/* MC_CMD_SET_PSU_IN msgrequest */
15986#define MC_CMD_SET_PSU_IN_LEN 12
15987#define MC_CMD_SET_PSU_IN_PARAM_OFST 0
15988#define MC_CMD_SET_PSU_IN_PARAM_LEN 4
15989#define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
15990#define MC_CMD_SET_PSU_IN_RAIL_OFST 4
15991#define MC_CMD_SET_PSU_IN_RAIL_LEN 4
15992#define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
15993#define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
15994/* desired value, eg voltage in mV */
15995#define MC_CMD_SET_PSU_IN_VALUE_OFST 8
15996#define MC_CMD_SET_PSU_IN_VALUE_LEN 4
15997
15998/* MC_CMD_SET_PSU_OUT msgresponse */
15999#define MC_CMD_SET_PSU_OUT_LEN 0
16000
16001
16002/***********************************/
16003/* MC_CMD_GET_FUNCTION_INFO
16004 * Get function information. PF and VF number.
16005 */
16006#define MC_CMD_GET_FUNCTION_INFO 0xec
16007#undef MC_CMD_0xec_PRIVILEGE_CTG
16008
16009#define MC_CMD_0xec_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16010
16011/* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */
16012#define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
16013
16014/* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */
16015#define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8
16016#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
16017#define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4
16018#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
16019#define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4
16020
16021
16022/***********************************/
16023/* MC_CMD_ENABLE_OFFLINE_BIST
16024 * Enters offline BIST mode. All queues are torn down, chip enters quiescent
16025 * mode, calling function gets exclusive MCDI ownership. The only way out is
16026 * reboot.
16027 */
16028#define MC_CMD_ENABLE_OFFLINE_BIST 0xed
16029#undef MC_CMD_0xed_PRIVILEGE_CTG
16030
16031#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN
16032
16033/* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */
16034#define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
16035
16036/* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */
16037#define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
16038
16039
16040/***********************************/
16041/* MC_CMD_READ_FUSES
16042 * Read data programmed into the device One-Time-Programmable (OTP) Fuses
16043 */
16044#define MC_CMD_READ_FUSES 0xf0
16045#undef MC_CMD_0xf0_PRIVILEGE_CTG
16046
16047#define MC_CMD_0xf0_PRIVILEGE_CTG SRIOV_CTG_INSECURE
16048
16049/* MC_CMD_READ_FUSES_IN msgrequest */
16050#define MC_CMD_READ_FUSES_IN_LEN 8
16051/* Offset in OTP to read */
16052#define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
16053#define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4
16054/* Length of data to read in bytes */
16055#define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
16056#define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4
16057
16058/* MC_CMD_READ_FUSES_OUT msgresponse */
16059#define MC_CMD_READ_FUSES_OUT_LENMIN 4
16060#define MC_CMD_READ_FUSES_OUT_LENMAX 252
16061#define MC_CMD_READ_FUSES_OUT_LENMAX_MCDI2 1020
16062#define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
16063#define MC_CMD_READ_FUSES_OUT_DATA_NUM(len) (((len)-4)/1)
16064/* Length of returned OTP data in bytes */
16065#define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
16066#define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4
16067/* Returned data */
16068#define MC_CMD_READ_FUSES_OUT_DATA_OFST 4
16069#define MC_CMD_READ_FUSES_OUT_DATA_LEN 1
16070#define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
16071#define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248
16072#define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM_MCDI2 1016
16073
16074
16075/***********************************/
16076/* MC_CMD_LICENSING
16077 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
16078 * - not used for V3 licensing
16079 */
16080#define MC_CMD_LICENSING 0xf3
16081#undef MC_CMD_0xf3_PRIVILEGE_CTG
16082
16083#define MC_CMD_0xf3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16084
16085/* MC_CMD_LICENSING_IN msgrequest */
16086#define MC_CMD_LICENSING_IN_LEN 4
16087/* identifies the type of operation requested */
16088#define MC_CMD_LICENSING_IN_OP_OFST 0
16089#define MC_CMD_LICENSING_IN_OP_LEN 4
16090/* enum: re-read and apply licenses after a license key partition update; note
16091 * that this operation returns a zero-length response
16092 */
16093#define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
16094/* enum: report counts of installed licenses */
16095#define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
16096
16097/* MC_CMD_LICENSING_OUT msgresponse */
16098#define MC_CMD_LICENSING_OUT_LEN 28
16099/* count of application keys which are valid */
16100#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
16101#define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4
16102/* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with
16103 * MC_CMD_FC_OP_LICENSE)
16104 */
16105#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
16106#define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4
16107/* count of application keys which are invalid due to being blacklisted */
16108#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8
16109#define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4
16110/* count of application keys which are invalid due to being unverifiable */
16111#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12
16112#define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4
16113/* count of application keys which are invalid due to being for the wrong node
16114 */
16115#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16
16116#define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4
16117/* licensing state (for diagnostics; the exact meaning of the bits in this
16118 * field are private to the firmware)
16119 */
16120#define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20
16121#define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4
16122/* licensing subsystem self-test report (for manftest) */
16123#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24
16124#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
16125/* enum: licensing subsystem self-test failed */
16126#define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
16127/* enum: licensing subsystem self-test passed */
16128#define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
16129
16130
16131/***********************************/
16132/* MC_CMD_LICENSING_V3
16133 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
16134 * - V3 licensing (Medford)
16135 */
16136#define MC_CMD_LICENSING_V3 0xd0
16137#undef MC_CMD_0xd0_PRIVILEGE_CTG
16138
16139#define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16140
16141/* MC_CMD_LICENSING_V3_IN msgrequest */
16142#define MC_CMD_LICENSING_V3_IN_LEN 4
16143/* identifies the type of operation requested */
16144#define MC_CMD_LICENSING_V3_IN_OP_OFST 0
16145#define MC_CMD_LICENSING_V3_IN_OP_LEN 4
16146/* enum: re-read and apply licenses after a license key partition update; note
16147 * that this operation returns a zero-length response
16148 */
16149#define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
16150/* enum: report counts of installed licenses Returns EAGAIN if license
16151 * processing (updating) has been started but not yet completed.
16152 */
16153#define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
16154
16155/* MC_CMD_LICENSING_V3_OUT msgresponse */
16156#define MC_CMD_LICENSING_V3_OUT_LEN 88
16157/* count of keys which are valid */
16158#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
16159#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4
16160/* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with
16161 * MC_CMD_FC_OP_LICENSE)
16162 */
16163#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
16164#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4
16165/* count of keys which are invalid due to being unverifiable */
16166#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8
16167#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4
16168/* count of keys which are invalid due to being for the wrong node */
16169#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12
16170#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4
16171/* licensing state (for diagnostics; the exact meaning of the bits in this
16172 * field are private to the firmware)
16173 */
16174#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16
16175#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4
16176/* licensing subsystem self-test report (for manftest) */
16177#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20
16178#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
16179/* enum: licensing subsystem self-test failed */
16180#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
16181/* enum: licensing subsystem self-test passed */
16182#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
16183/* bitmask of licensed applications */
16184#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24
16185#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8
16186#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24
16187#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28
16188/* reserved for future use */
16189#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32
16190#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24
16191/* bitmask of licensed features */
16192#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56
16193#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8
16194#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56
16195#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60
16196/* reserved for future use */
16197#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64
16198#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24
16199
16200
16201/***********************************/
16202/* MC_CMD_LICENSING_GET_ID_V3
16203 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license
16204 * partition - V3 licensing (Medford)
16205 */
16206#define MC_CMD_LICENSING_GET_ID_V3 0xd1
16207#undef MC_CMD_0xd1_PRIVILEGE_CTG
16208
16209#define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16210
16211/* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */
16212#define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0
16213
16214/* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */
16215#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8
16216#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252
16217#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX_MCDI2 1020
16218#define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num))
16219#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_NUM(len) (((len)-8)/1)
16220/* type of license (eg 3) */
16221#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
16222#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4
16223/* length of the license ID (in bytes) */
16224#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4
16225#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4
16226/* the unique license ID of the adapter */
16227#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8
16228#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1
16229#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0
16230#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244
16231#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM_MCDI2 1012
16232
16233
16234/***********************************/
16235/* MC_CMD_GET_LICENSED_APP_STATE
16236 * Query the state of an individual licensed application. (Note that the actual
16237 * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation
16238 * or a reboot of the MC.) Not used for V3 licensing
16239 */
16240#define MC_CMD_GET_LICENSED_APP_STATE 0xf5
16241#undef MC_CMD_0xf5_PRIVILEGE_CTG
16242
16243#define MC_CMD_0xf5_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16244
16245/* MC_CMD_GET_LICENSED_APP_STATE_IN msgrequest */
16246#define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
16247/* application ID to query (LICENSED_APP_ID_xxx) */
16248#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
16249#define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4
16250
16251/* MC_CMD_GET_LICENSED_APP_STATE_OUT msgresponse */
16252#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
16253/* state of this application */
16254#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
16255#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
16256/* enum: no (or invalid) license is present for the application */
16257#define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
16258/* enum: a valid license is present for the application */
16259#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
16260
16261
16262/***********************************/
16263/* MC_CMD_GET_LICENSED_V3_APP_STATE
16264 * Query the state of an individual licensed application. (Note that the actual
16265 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
16266 * operation or a reboot of the MC.) Used for V3 licensing (Medford)
16267 */
16268#define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
16269#undef MC_CMD_0xd2_PRIVILEGE_CTG
16270
16271#define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16272
16273/* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */
16274#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8
16275/* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit
16276 * mask
16277 */
16278#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
16279#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8
16280#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
16281#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
16282
16283/* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */
16284#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
16285/* state of this application */
16286#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0
16287#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4
16288/* enum: no (or invalid) license is present for the application */
16289#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
16290/* enum: a valid license is present for the application */
16291#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1
16292
16293
16294/***********************************/
16295/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES
16296 * Query the state of an one or more licensed features. (Note that the actual
16297 * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE
16298 * operation or a reboot of the MC.) Used for V3 licensing (Medford)
16299 */
16300#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
16301#undef MC_CMD_0xd3_PRIVILEGE_CTG
16302
16303#define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16304
16305/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */
16306#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8
16307/* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or
16308 * more bits set
16309 */
16310#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
16311#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8
16312#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
16313#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
16314
16315/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */
16316#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8
16317/* states of these features - bit set for licensed, clear for not licensed */
16318#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
16319#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8
16320#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
16321#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
16322
16323
16324/***********************************/
16325/* MC_CMD_LICENSED_APP_OP
16326 * Perform an action for an individual licensed application - not used for V3
16327 * licensing.
16328 */
16329#define MC_CMD_LICENSED_APP_OP 0xf6
16330#undef MC_CMD_0xf6_PRIVILEGE_CTG
16331
16332#define MC_CMD_0xf6_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16333
16334/* MC_CMD_LICENSED_APP_OP_IN msgrequest */
16335#define MC_CMD_LICENSED_APP_OP_IN_LENMIN 8
16336#define MC_CMD_LICENSED_APP_OP_IN_LENMAX 252
16337#define MC_CMD_LICENSED_APP_OP_IN_LENMAX_MCDI2 1020
16338#define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
16339#define MC_CMD_LICENSED_APP_OP_IN_ARGS_NUM(len) (((len)-8)/4)
16340/* application ID */
16341#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
16342#define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4
16343/* the type of operation requested */
16344#define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
16345#define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4
16346/* enum: validate application */
16347#define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
16348/* enum: mask application */
16349#define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
16350/* arguments specific to this particular operation */
16351#define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8
16352#define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
16353#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
16354#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM 61
16355#define MC_CMD_LICENSED_APP_OP_IN_ARGS_MAXNUM_MCDI2 253
16356
16357/* MC_CMD_LICENSED_APP_OP_OUT msgresponse */
16358#define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
16359#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX 252
16360#define MC_CMD_LICENSED_APP_OP_OUT_LENMAX_MCDI2 1020
16361#define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
16362#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4)
16363/* result specific to this particular operation */
16364#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
16365#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
16366#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
16367#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM 63
16368#define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MAXNUM_MCDI2 255
16369
16370/* MC_CMD_LICENSED_APP_OP_VALIDATE_IN msgrequest */
16371#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_LEN 72
16372/* application ID */
16373#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0
16374#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4
16375/* the type of operation requested */
16376#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4
16377#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4
16378/* validation challenge */
16379#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_OFST 8
16380#define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_CHALLENGE_LEN 64
16381
16382/* MC_CMD_LICENSED_APP_OP_VALIDATE_OUT msgresponse */
16383#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_LEN 68
16384/* feature expiry (time_t) */
16385#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0
16386#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4
16387/* validation response */
16388#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4
16389#define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_LEN 64
16390
16391/* MC_CMD_LICENSED_APP_OP_MASK_IN msgrequest */
16392#define MC_CMD_LICENSED_APP_OP_MASK_IN_LEN 12
16393/* application ID */
16394#define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0
16395#define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4
16396/* the type of operation requested */
16397#define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4
16398#define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4
16399/* flag */
16400#define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_OFST 8
16401#define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4
16402
16403/* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */
16404#define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0
16405
16406
16407/***********************************/
16408/* MC_CMD_LICENSED_V3_VALIDATE_APP
16409 * Perform validation for an individual licensed application - V3 licensing
16410 * (Medford)
16411 */
16412#define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
16413#undef MC_CMD_0xd4_PRIVILEGE_CTG
16414
16415#define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16416
16417/* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */
16418#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 56
16419/* challenge for validation (384 bits) */
16420#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0
16421#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 48
16422/* application ID expressed as a single bit mask */
16423#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 48
16424#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8
16425#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 48
16426#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 52
16427
16428/* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */
16429#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 116
16430/* validation response to challenge in the form of ECDSA signature consisting
16431 * of two 384-bit integers, r and s, in big-endian order. The signature signs a
16432 * SHA-384 digest of a message constructed from the concatenation of the input
16433 * message and the remaining fields of this output message, e.g. challenge[48
16434 * bytes] ... expiry_time[4 bytes] ...
16435 */
16436#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0
16437#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 96
16438/* application expiry time */
16439#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 96
16440#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4
16441/* application expiry units */
16442#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100
16443#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4
16444/* enum: expiry units are accounting units */
16445#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
16446/* enum: expiry units are calendar days */
16447#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
16448/* base MAC address of the NIC stored in NVRAM (note that this is a constant
16449 * value for a given NIC regardless which function is calling, effectively this
16450 * is PF0 base MAC address)
16451 */
16452#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_OFST 104
16453#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_BASE_MACADDR_LEN 6
16454/* MAC address of v-adaptor associated with the client. If no such v-adapator
16455 * exists, then the field is filled with 0xFF.
16456 */
16457#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110
16458#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6
16459
16460
16461/***********************************/
16462/* MC_CMD_LICENSED_V3_MASK_FEATURES
16463 * Mask features - V3 licensing (Medford)
16464 */
16465#define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
16466#undef MC_CMD_0xd5_PRIVILEGE_CTG
16467
16468#define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
16469
16470/* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */
16471#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12
16472/* mask to be applied to features to be changed */
16473#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
16474#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8
16475#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
16476#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
16477/* whether to turn on or turn off the masked features */
16478#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8
16479#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
16480/* enum: turn the features off */
16481#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
16482/* enum: turn the features back on */
16483#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1
16484
16485/* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */
16486#define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0
16487
16488
16489/***********************************/
16490/* MC_CMD_LICENSING_V3_TEMPORARY
16491 * Perform operations to support installation of a single temporary license in
16492 * the adapter, in addition to those found in the licensing partition. See
16493 * SF-116124-SW for an overview of how this could be used. The license is
16494 * stored in MC persistent data and so will survive a MC reboot, but will be
16495 * erased when the adapter is power cycled
16496 */
16497#define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
16498#undef MC_CMD_0xd6_PRIVILEGE_CTG
16499
16500#define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
16501
16502/* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */
16503#define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4
16504/* operation code */
16505#define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0
16506#define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4
16507/* enum: install a new license, overwriting any existing temporary license.
16508 * This is an asynchronous operation owing to the time taken to validate an
16509 * ECDSA license
16510 */
16511#define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
16512/* enum: clear the license immediately rather than waiting for the next power
16513 * cycle
16514 */
16515#define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
16516/* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET
16517 * operation
16518 */
16519#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2
16520
16521/* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */
16522#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164
16523#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0
16524#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4
16525/* ECDSA license and signature */
16526#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4
16527#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_LEN 160
16528
16529/* MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR msgrequest */
16530#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4
16531#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0
16532#define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4
16533
16534/* MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS msgrequest */
16535#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4
16536#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0
16537#define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4
16538
16539/* MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS msgresponse */
16540#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LEN 12
16541/* status code */
16542#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0
16543#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4
16544/* enum: finished validating and installing license */
16545#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
16546/* enum: license validation and installation in progress */
16547#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
16548/* enum: licensing error. More specific error messages are not provided to
16549 * avoid exposing details of the licensing system to the client
16550 */
16551#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
16552/* bitmask of licensed features */
16553#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
16554#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8
16555#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
16556#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8
16557
16558
16559/***********************************/
16560/* MC_CMD_SET_PARSER_DISP_CONFIG
16561 * Change configuration related to the parser-dispatcher subsystem.
16562 */
16563#define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
16564#undef MC_CMD_0xf9_PRIVILEGE_CTG
16565
16566#define MC_CMD_0xf9_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16567
16568/* MC_CMD_SET_PARSER_DISP_CONFIG_IN msgrequest */
16569#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMIN 12
16570#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX 252
16571#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LENMAX_MCDI2 1020
16572#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
16573#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4)
16574/* the type of configuration setting to change */
16575#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
16576#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
16577/* enum: Per-TXQ enable for multicast UDP destination lookup for possible
16578 * internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.)
16579 */
16580#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
16581/* enum: Per-v-adaptor enable for suppression of self-transmissions on the
16582 * internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single
16583 * boolean.)
16584 */
16585#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
16586/* handle for the entity to update: queue handle, EVB port ID, etc. depending
16587 * on the type of configuration setting being changed
16588 */
16589#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
16590#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
16591/* new value: the details depend on the type of configuration setting being
16592 * changed
16593 */
16594#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_OFST 8
16595#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
16596#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MINNUM 1
16597#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM 61
16598#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_MAXNUM_MCDI2 253
16599
16600/* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */
16601#define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
16602
16603
16604/***********************************/
16605/* MC_CMD_GET_PARSER_DISP_CONFIG
16606 * Read configuration related to the parser-dispatcher subsystem.
16607 */
16608#define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
16609#undef MC_CMD_0xfa_PRIVILEGE_CTG
16610
16611#define MC_CMD_0xfa_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16612
16613/* MC_CMD_GET_PARSER_DISP_CONFIG_IN msgrequest */
16614#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_LEN 8
16615/* the type of configuration setting to read */
16616#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
16617#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
16618/* Enum values, see field(s): */
16619/* MC_CMD_SET_PARSER_DISP_CONFIG/MC_CMD_SET_PARSER_DISP_CONFIG_IN/TYPE */
16620/* handle for the entity to query: queue handle, EVB port ID, etc. depending on
16621 * the type of configuration setting being read
16622 */
16623#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
16624#define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
16625
16626/* MC_CMD_GET_PARSER_DISP_CONFIG_OUT msgresponse */
16627#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4
16628#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX 252
16629#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMAX_MCDI2 1020
16630#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
16631#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4)
16632/* current value: the details depend on the type of configuration setting being
16633 * read
16634 */
16635#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0
16636#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4
16637#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1
16638#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63
16639#define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM_MCDI2 255
16640
16641
16642/***********************************/
16643/* MC_CMD_GET_PORT_MODES
16644 * Find out about available port modes
16645 */
16646#define MC_CMD_GET_PORT_MODES 0xff
16647#undef MC_CMD_0xff_PRIVILEGE_CTG
16648
16649#define MC_CMD_0xff_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16650
16651/* MC_CMD_GET_PORT_MODES_IN msgrequest */
16652#define MC_CMD_GET_PORT_MODES_IN_LEN 0
16653
16654/* MC_CMD_GET_PORT_MODES_OUT msgresponse */
16655#define MC_CMD_GET_PORT_MODES_OUT_LEN 12
16656/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*)
16657 * that are supported for customer use in production firmware.
16658 */
16659#define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0
16660#define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4
16661/* Default (canonical) board mode */
16662#define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4
16663#define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4
16664/* Current board mode */
16665#define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8
16666#define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4
16667
16668/* MC_CMD_GET_PORT_MODES_OUT_V2 msgresponse */
16669#define MC_CMD_GET_PORT_MODES_OUT_V2_LEN 16
16670/* Bitmask of port modes available on the board (indexed by TLV_PORT_MODE_*)
16671 * that are supported for customer use in production firmware.
16672 */
16673#define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_OFST 0
16674#define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_LEN 4
16675/* Default (canonical) board mode */
16676#define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_OFST 4
16677#define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_LEN 4
16678/* Current board mode */
16679#define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_OFST 8
16680#define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_LEN 4
16681/* Bitmask of engineering port modes available on the board (indexed by
16682 * TLV_PORT_MODE_*). A superset of MC_CMD_GET_PORT_MODES_OUT/MODES that
16683 * contains all modes implemented in firmware for a particular board. Modes
16684 * listed in MODES are considered production modes and should be exposed in
16685 * userland tools. Modes listed in ENGINEERING_MODES, but not in MODES
16686 * should be considered hidden (not to be exposed in userland tools) and for
16687 * engineering use only. There are no other semantic differences and any mode
16688 * listed in either MODES or ENGINEERING_MODES can be set on the board.
16689 */
16690#define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_OFST 12
16691#define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_LEN 4
16692
16693
16694/***********************************/
16695/* MC_CMD_OVERRIDE_PORT_MODE
16696 * Override flash config port mode for subsequent MC reboot(s). Override data
16697 * is stored in the presistent data section of DMEM and activated on next MC
16698 * warm reboot. A cold reboot resets the override. It is assumed that a
16699 * sufficient number of PFs are available and that port mapping is valid for
16700 * the new port mode, as the override does not affect PF configuration.
16701 */
16702#define MC_CMD_OVERRIDE_PORT_MODE 0x137
16703#undef MC_CMD_0x137_PRIVILEGE_CTG
16704
16705#define MC_CMD_0x137_PRIVILEGE_CTG SRIOV_CTG_ADMIN
16706
16707/* MC_CMD_OVERRIDE_PORT_MODE_IN msgrequest */
16708#define MC_CMD_OVERRIDE_PORT_MODE_IN_LEN 8
16709#define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_OFST 0
16710#define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_LEN 4
16711#define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_OFST 0
16712#define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_LBN 0
16713#define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_WIDTH 1
16714/* New mode (TLV_PORT_MODE_*) to set, if override enabled */
16715#define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_OFST 4
16716#define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_LEN 4
16717
16718/* MC_CMD_OVERRIDE_PORT_MODE_OUT msgresponse */
16719#define MC_CMD_OVERRIDE_PORT_MODE_OUT_LEN 0
16720
16721
16722/***********************************/
16723/* MC_CMD_GET_WORKAROUNDS
16724 * Read the list of all implemented and all currently enabled workarounds. The
16725 * enums here must correspond with those in MC_CMD_WORKAROUND.
16726 */
16727#define MC_CMD_GET_WORKAROUNDS 0x59
16728#undef MC_CMD_0x59_PRIVILEGE_CTG
16729
16730#define MC_CMD_0x59_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16731
16732/* MC_CMD_GET_WORKAROUNDS_OUT msgresponse */
16733#define MC_CMD_GET_WORKAROUNDS_OUT_LEN 8
16734/* Each workaround is represented by a single bit according to the enums below.
16735 */
16736#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
16737#define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4
16738#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
16739#define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4
16740/* enum: Bug 17230 work around. */
16741#define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
16742/* enum: Bug 35388 work around (unsafe EVQ writes). */
16743#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
16744/* enum: Bug35017 workaround (A64 tables must be identity map) */
16745#define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
16746/* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
16747#define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
16748/* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
16749 * - before adding code that queries this workaround, remember that there's
16750 * released Monza firmware that doesn't understand MC_CMD_WORKAROUND_BUG42008,
16751 * and will hence (incorrectly) report that the bug doesn't exist.
16752 */
16753#define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
16754/* enum: Bug 26807 features present in firmware (multicast filter chaining) */
16755#define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
16756/* enum: Bug 61265 work around (broken EVQ TMR writes). */
16757#define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
16758
16759
16760/***********************************/
16761/* MC_CMD_PRIVILEGE_MASK
16762 * Read/set privileges of an arbitrary PCIe function
16763 */
16764#define MC_CMD_PRIVILEGE_MASK 0x5a
16765#undef MC_CMD_0x5a_PRIVILEGE_CTG
16766
16767#define MC_CMD_0x5a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16768
16769/* MC_CMD_PRIVILEGE_MASK_IN msgrequest */
16770#define MC_CMD_PRIVILEGE_MASK_IN_LEN 8
16771/* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
16772 * 1,3 = 0x00030001
16773 */
16774#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
16775#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
16776#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_OFST 0
16777#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
16778#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16
16779#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_OFST 0
16780#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16
16781#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16
16782#define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
16783/* New privilege mask to be set. The mask will only be changed if the MSB is
16784 * set to 1.
16785 */
16786#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
16787#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
16788#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
16789#define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
16790#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
16791#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
16792#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
16793/* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */
16794#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
16795#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
16796#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
16797#define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
16798#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
16799#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
16800/* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC
16801 * adress.
16802 */
16803#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
16804/* enum: Privilege that allows a Function to change the MAC address configured
16805 * in its associated vAdapter/vPort.
16806 */
16807#define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
16808/* enum: Privilege that allows a Function to install filters that specify VLANs
16809 * that are not in the permit list for the associated vPort. This privilege is
16810 * primarily to support ESX where vPorts are created that restrict traffic to
16811 * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT.
16812 */
16813#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
16814/* enum: Privilege for insecure commands. Commands that belong to this group
16815 * are not permitted on secure adapters regardless of the privilege mask.
16816 */
16817#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
16818/* enum: Trusted Server Adapter (TSA) / ServerLock. Privilege for
16819 * administrator-level operations that are not allowed from the local host once
16820 * an adapter has Bound to a remote ServerLock Controller (see doxbox
16821 * SF-117064-DG for background).
16822 */
16823#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
16824/* enum: Set this bit to indicate that a new privilege mask is to be set,
16825 * otherwise the command will only read the existing mask.
16826 */
16827#define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
16828
16829/* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */
16830#define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
16831/* For an admin function, always all the privileges are reported. */
16832#define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
16833#define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4
16834
16835
16836/***********************************/
16837/* MC_CMD_LINK_STATE_MODE
16838 * Read/set link state mode of a VF
16839 */
16840#define MC_CMD_LINK_STATE_MODE 0x5c
16841#undef MC_CMD_0x5c_PRIVILEGE_CTG
16842
16843#define MC_CMD_0x5c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
16844
16845/* MC_CMD_LINK_STATE_MODE_IN msgrequest */
16846#define MC_CMD_LINK_STATE_MODE_IN_LEN 8
16847/* The target function to have its link state mode read or set, must be a VF
16848 * e.g. VF 1,3 = 0x00030001
16849 */
16850#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
16851#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
16852#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_OFST 0
16853#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
16854#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_WIDTH 16
16855#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_OFST 0
16856#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_LBN 16
16857#define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_WIDTH 16
16858/* New link state mode to be set */
16859#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
16860#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
16861#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
16862#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
16863#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
16864/* enum: Use this value to just read the existing setting without modifying it.
16865 */
16866#define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
16867
16868/* MC_CMD_LINK_STATE_MODE_OUT msgresponse */
16869#define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
16870#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
16871#define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4
16872
16873
16874/***********************************/
16875/* MC_CMD_FUSE_DIAGS
16876 * Additional fuse diagnostics
16877 */
16878#define MC_CMD_FUSE_DIAGS 0x102
16879#undef MC_CMD_0x102_PRIVILEGE_CTG
16880
16881#define MC_CMD_0x102_PRIVILEGE_CTG SRIOV_CTG_INSECURE
16882
16883/* MC_CMD_FUSE_DIAGS_IN msgrequest */
16884#define MC_CMD_FUSE_DIAGS_IN_LEN 0
16885
16886/* MC_CMD_FUSE_DIAGS_OUT msgresponse */
16887#define MC_CMD_FUSE_DIAGS_OUT_LEN 48
16888/* Total number of mismatched bits between pairs in area 0 */
16889#define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0
16890#define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4
16891/* Total number of unexpectedly clear (set in B but not A) bits in area 0 */
16892#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4
16893#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4
16894/* Total number of unexpectedly clear (set in A but not B) bits in area 0 */
16895#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_OFST 8
16896#define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4
16897/* Checksum of data after logical OR of pairs in area 0 */
16898#define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_OFST 12
16899#define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4
16900/* Total number of mismatched bits between pairs in area 1 */
16901#define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_OFST 16
16902#define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4
16903/* Total number of unexpectedly clear (set in B but not A) bits in area 1 */
16904#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_OFST 20
16905#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4
16906/* Total number of unexpectedly clear (set in A but not B) bits in area 1 */
16907#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_OFST 24
16908#define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4
16909/* Checksum of data after logical OR of pairs in area 1 */
16910#define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_OFST 28
16911#define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4
16912/* Total number of mismatched bits between pairs in area 2 */
16913#define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_OFST 32
16914#define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4
16915/* Total number of unexpectedly clear (set in B but not A) bits in area 2 */
16916#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_OFST 36
16917#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4
16918/* Total number of unexpectedly clear (set in A but not B) bits in area 2 */
16919#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_OFST 40
16920#define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4
16921/* Checksum of data after logical OR of pairs in area 2 */
16922#define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44
16923#define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4
16924
16925
16926/***********************************/
16927/* MC_CMD_PRIVILEGE_MODIFY
16928 * Modify the privileges of a set of PCIe functions. Note that this operation
16929 * only effects non-admin functions unless the admin privilege itself is
16930 * included in one of the masks provided.
16931 */
16932#define MC_CMD_PRIVILEGE_MODIFY 0x60
16933#undef MC_CMD_0x60_PRIVILEGE_CTG
16934
16935#define MC_CMD_0x60_PRIVILEGE_CTG SRIOV_CTG_ADMIN
16936
16937/* MC_CMD_PRIVILEGE_MODIFY_IN msgrequest */
16938#define MC_CMD_PRIVILEGE_MODIFY_IN_LEN 16
16939/* The groups of functions to have their privilege masks modified. */
16940#define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0
16941#define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4
16942#define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
16943#define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
16944#define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
16945#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
16946#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
16947#define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
16948/* For VFS_OF_PF specify the PF, for ONE specify the target function */
16949#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
16950#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4
16951#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_OFST 4
16952#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0
16953#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_WIDTH 16
16954#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_OFST 4
16955#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_LBN 16
16956#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_WIDTH 16
16957/* Privileges to be added to the target functions. For privilege definitions
16958 * refer to the command MC_CMD_PRIVILEGE_MASK
16959 */
16960#define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_OFST 8
16961#define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4
16962/* Privileges to be removed from the target functions. For privilege
16963 * definitions refer to the command MC_CMD_PRIVILEGE_MASK
16964 */
16965#define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_OFST 12
16966#define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4
16967
16968/* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */
16969#define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0
16970
16971
16972/* TUNNEL_ENCAP_UDP_PORT_ENTRY structuredef */
16973#define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
16974/* UDP port (the standard ports are named below but any port may be used) */
16975#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
16976#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2
16977/* enum: the IANA allocated UDP port for VXLAN */
16978#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
16979/* enum: the IANA allocated UDP port for Geneve */
16980#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
16981#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
16982#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16
16983/* tunnel encapsulation protocol (only those named below are supported) */
16984#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2
16985#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2
16986/* enum: This port will be used for VXLAN on both IPv4 and IPv6 */
16987#define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
16988/* enum: This port will be used for Geneve on both IPv4 and IPv6 */
16989#define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
16990#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16
16991#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16
16992
16993
16994/***********************************/
16995/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS
16996 * Configure UDP ports for tunnel encapsulation hardware acceleration. The
16997 * parser-dispatcher will attempt to parse traffic on these ports as tunnel
16998 * encapsulation PDUs and filter them using the tunnel encapsulation filter
16999 * chain rather than the standard filter chain. Note that this command can
17000 * cause all functions to see a reset. (Available on Medford only.)
17001 */
17002#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
17003#undef MC_CMD_0x117_PRIVILEGE_CTG
17004
17005#define MC_CMD_0x117_PRIVILEGE_CTG SRIOV_CTG_ADMIN
17006
17007/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN msgrequest */
17008#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
17009#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX 68
17010#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX_MCDI2 68
17011#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
17012#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4)
17013/* Flags */
17014#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
17015#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_LEN 2
17016#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_OFST 0
17017#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
17018#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_WIDTH 1
17019/* The number of entries in the ENTRIES array */
17020#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST 2
17021#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN 2
17022/* Entries defining the UDP port to protocol mapping, each laid out as a
17023 * TUNNEL_ENCAP_UDP_PORT_ENTRY
17024 */
17025#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
17026#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
17027#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
17028#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM 16
17029#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM_MCDI2 16
17030
17031/* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT msgresponse */
17032#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN 2
17033/* Flags */
17034#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
17035#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_LEN 2
17036#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 0
17037#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
17038#define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1
17039
17040
17041/***********************************/
17042/* MC_CMD_VNIC_ENCAP_RULE_ADD
17043 * Add a rule for detecting encapsulations in the VNIC stage. Currently this only affects checksum validation in VNIC RX - on TX the send descriptor explicitly specifies encapsulation. These rules are per-VNIC, i.e. only apply to the current driver. If a rule matches, then the packet is considered to have the corresponding encapsulation type, and the inner packet is parsed. It is up to the driver to ensure that overlapping rules are not inserted. (If a packet would match multiple rules, a random one of them will be used.) A rule with the exact same match criteria may not be inserted twice (EALREADY). Only a limited number MATCH_FLAGS values are supported, use MC_CMD_GET_PARSER_DISP_INFO with OP OP_GET_SUPPORTED_VNIC_ENCAP_RULE_MATCHES to get a list of supported combinations. Each driver may only have a limited set of active rules - returns ENOSPC if the caller's table is full.
17044 */
17045#define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d
17046#undef MC_CMD_0x16d_PRIVILEGE_CTG
17047
17048#define MC_CMD_0x16d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
17049
17050/* MC_CMD_VNIC_ENCAP_RULE_ADD_IN msgrequest */
17051#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_LEN 36
17052/* Set to MAE_MPORT_SELECTOR_ASSIGNED. In the future this may be relaxed. */
17053#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_OFST 0
17054#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_LEN 4
17055/* Any non-zero bits other than the ones named below or an unsupported
17056 * combination will cause the NIC to return EOPNOTSUPP. In the future more
17057 * flags may be added.
17058 */
17059#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_OFST 4
17060#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_LEN 4
17061#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_OFST 4
17062#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_LBN 0
17063#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_WIDTH 1
17064#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_OFST 4
17065#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_LBN 1
17066#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_WIDTH 1
17067#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_OFST 4
17068#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_LBN 2
17069#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_WIDTH 1
17070#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_OFST 4
17071#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_LBN 3
17072#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_WIDTH 1
17073#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_OFST 4
17074#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_LBN 4
17075#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_WIDTH 1
17076/* Only if MATCH_ETHER_TYPE is set. Ethertype value as bytes in network order.
17077 * Currently only IPv4 (0x0800) and IPv6 (0x86DD) ethertypes may be used.
17078 */
17079#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_OFST 8
17080#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ETHER_TYPE_LEN 2
17081/* Only if MATCH_OUTER_VLAN is set. VID value as bytes in network order.
17082 * (Deprecated)
17083 */
17084#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_LBN 80
17085#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WIDTH 12
17086/* Only if MATCH_OUTER_VLAN is set. Aligned wrapper for OUTER_VLAN_VID. */
17087#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_OFST 10
17088#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_WORD_LEN 2
17089#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_OFST 10
17090#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_LBN 0
17091#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_WIDTH 12
17092/* Only if MATCH_DST_IP is set. IP address as bytes in network order. In the
17093 * case of IPv4, the IP should be in the first 4 bytes and all other bytes
17094 * should be zero.
17095 */
17096#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_OFST 12
17097#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_IP_LEN 16
17098/* Only if MATCH_IP_PROTO is set. Currently only UDP proto (17) may be used. */
17099#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_OFST 28
17100#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_IP_PROTO_LEN 1
17101/* Actions that should be applied to packets match the rule. */
17102#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_OFST 29
17103#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ACTION_FLAGS_LEN 1
17104#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_OFST 29
17105#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_LBN 0
17106#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_WIDTH 1
17107/* Only if MATCH_DST_PORT is set. Port number as bytes in network order. */
17108#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_OFST 30
17109#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_DST_PORT_LEN 2
17110/* Resulting encapsulation type, as per MAE_MCDI_ENCAP_TYPE enumeration. */
17111#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_OFST 32
17112#define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_LEN 4
17113
17114/* MC_CMD_VNIC_ENCAP_RULE_ADD_OUT msgresponse */
17115#define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_LEN 4
17116/* Handle to inserted rule. Used for removing the rule. */
17117#define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_OFST 0
17118#define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_LEN 4
17119
17120
17121/***********************************/
17122/* MC_CMD_VNIC_ENCAP_RULE_REMOVE
17123 * Remove a VNIC encapsulation rule. Packets which would have previously matched the rule will then be considered as unencapsulated. Returns EALREADY if the input HANDLE doesn't correspond to an existing rule.
17124 */
17125#define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e
17126#undef MC_CMD_0x16e_PRIVILEGE_CTG
17127
17128#define MC_CMD_0x16e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
17129
17130/* MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN msgrequest */
17131#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_LEN 4
17132/* Handle which was returned by MC_CMD_VNIC_ENCAP_RULE_ADD. */
17133#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_OFST 0
17134#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_LEN 4
17135
17136/* MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT msgresponse */
17137#define MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT_LEN 0
17138
17139/* FUNCTION_PERSONALITY structuredef: The meanings of the personalities are
17140 * defined in SF-120734-TC with more information in SF-122717-TC.
17141 */
17142#define FUNCTION_PERSONALITY_LEN 4
17143#define FUNCTION_PERSONALITY_ID_OFST 0
17144#define FUNCTION_PERSONALITY_ID_LEN 4
17145/* enum: Function has no assigned personality */
17146#define FUNCTION_PERSONALITY_NULL 0x0
17147/* enum: Function has an EF100-style function control window and VI windows
17148 * with both EF100 and vDPA doorbells.
17149 */
17150#define FUNCTION_PERSONALITY_EF100 0x1
17151/* enum: Function has virtio net device configuration registers and doorbells
17152 * for virtio queue pairs.
17153 */
17154#define FUNCTION_PERSONALITY_VIRTIO_NET 0x2
17155/* enum: Function has virtio block device configuration registers and a
17156 * doorbell for a single virtqueue.
17157 */
17158#define FUNCTION_PERSONALITY_VIRTIO_BLK 0x3
17159/* enum: Function is a Xilinx acceleration device - management function */
17160#define FUNCTION_PERSONALITY_ACCEL_MGMT 0x4
17161/* enum: Function is a Xilinx acceleration device - user function */
17162#define FUNCTION_PERSONALITY_ACCEL_USR 0x5
17163#define FUNCTION_PERSONALITY_ID_LBN 0
17164#define FUNCTION_PERSONALITY_ID_WIDTH 32
17165
17166/* PCIE_FUNCTION structuredef: Structure representing a PCIe function ID
17167 * (interface/PF/VF tuple)
17168 */
17169#define PCIE_FUNCTION_LEN 8
17170/* PCIe PF function number */
17171#define PCIE_FUNCTION_PF_OFST 0
17172#define PCIE_FUNCTION_PF_LEN 2
17173/* enum: Wildcard value representing any available function (e.g in resource
17174 * allocation requests)
17175 */
17176#define PCIE_FUNCTION_PF_ANY 0xfffe
17177/* enum: Value representing invalid (null) function */
17178#define PCIE_FUNCTION_PF_NULL 0xffff
17179#define PCIE_FUNCTION_PF_LBN 0
17180#define PCIE_FUNCTION_PF_WIDTH 16
17181/* PCIe VF Function number (PF relative) */
17182#define PCIE_FUNCTION_VF_OFST 2
17183#define PCIE_FUNCTION_VF_LEN 2
17184/* enum: Wildcard value representing any available function (e.g in resource
17185 * allocation requests)
17186 */
17187#define PCIE_FUNCTION_VF_ANY 0xfffe
17188/* enum: Function is a PF (when PF != PF_NULL) or invalid function (when PF ==
17189 * PF_NULL)
17190 */
17191#define PCIE_FUNCTION_VF_NULL 0xffff
17192#define PCIE_FUNCTION_VF_LBN 16
17193#define PCIE_FUNCTION_VF_WIDTH 16
17194/* PCIe interface of the function */
17195#define PCIE_FUNCTION_INTF_OFST 4
17196#define PCIE_FUNCTION_INTF_LEN 4
17197/* enum: Host PCIe interface */
17198#define PCIE_FUNCTION_INTF_HOST 0x0
17199/* enum: Application Processor interface */
17200#define PCIE_FUNCTION_INTF_AP 0x1
17201#define PCIE_FUNCTION_INTF_LBN 32
17202#define PCIE_FUNCTION_INTF_WIDTH 32
17203
17204#endif /* MCDI_PCOL_H */
17205

source code of linux/drivers/net/ethernet/sfc/siena/mcdi_pcol.h