1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * DWMAC4 Header file.
4 *
5 * Copyright (C) 2015 STMicroelectronics Ltd
6 *
7 * Author: Alexandre Torgue <alexandre.torgue@st.com>
8 */
9
10#ifndef __DWMAC4_H__
11#define __DWMAC4_H__
12
13#include "common.h"
14
15/* MAC registers */
16#define GMAC_CONFIG 0x00000000
17#define GMAC_EXT_CONFIG 0x00000004
18#define GMAC_PACKET_FILTER 0x00000008
19#define GMAC_HASH_TAB(x) (0x10 + (x) * 4)
20#define GMAC_RX_FLOW_CTRL 0x00000090
21#define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4)
22#define GMAC_TXQ_PRTY_MAP0 0x98
23#define GMAC_TXQ_PRTY_MAP1 0x9C
24#define GMAC_RXQ_CTRL0 0x000000a0
25#define GMAC_RXQ_CTRL1 0x000000a4
26#define GMAC_RXQ_CTRL2 0x000000a8
27#define GMAC_RXQ_CTRL3 0x000000ac
28#define GMAC_INT_STATUS 0x000000b0
29#define GMAC_INT_EN 0x000000b4
30#define GMAC_PCS_BASE 0x000000e0
31#define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
32#define GMAC_PMT 0x000000c0
33#define GMAC_DEBUG 0x00000114
34#define GMAC_HW_FEATURE0 0x0000011c
35#define GMAC_HW_FEATURE1 0x00000120
36#define GMAC_HW_FEATURE2 0x00000124
37#define GMAC_HW_FEATURE3 0x00000128
38#define GMAC_MDIO_ADDR 0x00000200
39#define GMAC_MDIO_DATA 0x00000204
40#define GMAC_GPIO_STATUS 0x0000020C
41#define GMAC_ARP_ADDR 0x00000210
42#define GMAC_EXT_CFG1 0x00000238
43#define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)
44#define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
45#define GMAC_L3L4_CTRL(reg) (0x900 + (reg) * 0x30)
46#define GMAC_L4_ADDR(reg) (0x904 + (reg) * 0x30)
47#define GMAC_L3_ADDR0(reg) (0x910 + (reg) * 0x30)
48#define GMAC_L3_ADDR1(reg) (0x914 + (reg) * 0x30)
49#define GMAC_TIMESTAMP_STATUS 0x00000b20
50
51/* RX Queues Routing */
52#define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
53#define GMAC_RXQCTRL_AVCPQ_SHIFT 0
54#define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4)
55#define GMAC_RXQCTRL_PTPQ_SHIFT 4
56#define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8)
57#define GMAC_RXQCTRL_DCBCPQ_SHIFT 8
58#define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12)
59#define GMAC_RXQCTRL_UPQ_SHIFT 12
60#define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16)
61#define GMAC_RXQCTRL_MCBCQ_SHIFT 16
62#define GMAC_RXQCTRL_MCBCQEN BIT(20)
63#define GMAC_RXQCTRL_MCBCQEN_SHIFT 20
64#define GMAC_RXQCTRL_TACPQE BIT(21)
65#define GMAC_RXQCTRL_TACPQE_SHIFT 21
66#define GMAC_RXQCTRL_FPRQ GENMASK(26, 24)
67
68/* MAC Packet Filtering */
69#define GMAC_PACKET_FILTER_PR BIT(0)
70#define GMAC_PACKET_FILTER_HMC BIT(2)
71#define GMAC_PACKET_FILTER_PM BIT(4)
72#define GMAC_PACKET_FILTER_PCF BIT(7)
73#define GMAC_PACKET_FILTER_HPF BIT(10)
74#define GMAC_PACKET_FILTER_VTFE BIT(16)
75#define GMAC_PACKET_FILTER_IPFE BIT(20)
76#define GMAC_PACKET_FILTER_RA BIT(31)
77
78#define GMAC_MAX_PERFECT_ADDRESSES 128
79
80/* MAC RX Queue Enable */
81#define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
82#define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
83#define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1)
84
85/* MAC Flow Control RX */
86#define GMAC_RX_FLOW_CTRL_RFE BIT(0)
87
88/* RX Queues Priorities */
89#define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
90#define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8)
91
92/* TX Queues Priorities */
93#define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
94#define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8)
95
96/* MAC Flow Control TX */
97#define GMAC_TX_FLOW_CTRL_TFE BIT(1)
98#define GMAC_TX_FLOW_CTRL_PT_SHIFT 16
99
100/* MAC Interrupt bitmap*/
101#define GMAC_INT_RGSMIIS BIT(0)
102#define GMAC_INT_PCS_LINK BIT(1)
103#define GMAC_INT_PCS_ANE BIT(2)
104#define GMAC_INT_PCS_PHYIS BIT(3)
105#define GMAC_INT_PMT_EN BIT(4)
106#define GMAC_INT_LPI_EN BIT(5)
107#define GMAC_INT_TSIE BIT(12)
108
109#define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \
110 GMAC_INT_PCS_ANE)
111
112#define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN | \
113 GMAC_INT_TSIE)
114
115enum dwmac4_irq_status {
116 time_stamp_irq = 0x00001000,
117 mmc_rx_csum_offload_irq = 0x00000800,
118 mmc_tx_irq = 0x00000400,
119 mmc_rx_irq = 0x00000200,
120 mmc_irq = 0x00000100,
121 lpi_irq = 0x00000020,
122 pmt_irq = 0x00000010,
123};
124
125/* MAC PMT bitmap */
126enum power_event {
127 pointer_reset = 0x80000000,
128 global_unicast = 0x00000200,
129 wake_up_rx_frame = 0x00000040,
130 magic_frame = 0x00000020,
131 wake_up_frame_en = 0x00000004,
132 magic_pkt_en = 0x00000002,
133 power_down = 0x00000001,
134};
135
136/* Energy Efficient Ethernet (EEE) for GMAC4
137 *
138 * LPI status, timer and control register offset
139 * For LPI control and status bit definitions, see common.h.
140 */
141#define GMAC4_LPI_CTRL_STATUS 0xd0
142#define GMAC4_LPI_TIMER_CTRL 0xd4
143#define GMAC4_LPI_ENTRY_TIMER 0xd8
144#define GMAC4_MAC_ONEUS_TIC_COUNTER 0xdc
145
146/* MAC Debug bitmap */
147#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
148#define GMAC_DEBUG_TFCSTS_SHIFT 17
149#define GMAC_DEBUG_TFCSTS_IDLE 0
150#define GMAC_DEBUG_TFCSTS_WAIT 1
151#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
152#define GMAC_DEBUG_TFCSTS_XFER 3
153#define GMAC_DEBUG_TPESTS BIT(16)
154#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
155#define GMAC_DEBUG_RFCFCSTS_SHIFT 1
156#define GMAC_DEBUG_RPESTS BIT(0)
157
158/* MAC config */
159#define GMAC_CONFIG_ARPEN BIT(31)
160#define GMAC_CONFIG_SARC GENMASK(30, 28)
161#define GMAC_CONFIG_SARC_SHIFT 28
162#define GMAC_CONFIG_IPC BIT(27)
163#define GMAC_CONFIG_IPG GENMASK(26, 24)
164#define GMAC_CONFIG_IPG_SHIFT 24
165#define GMAC_CONFIG_2K BIT(22)
166#define GMAC_CONFIG_ACS BIT(20)
167#define GMAC_CONFIG_BE BIT(18)
168#define GMAC_CONFIG_JD BIT(17)
169#define GMAC_CONFIG_JE BIT(16)
170#define GMAC_CONFIG_PS BIT(15)
171#define GMAC_CONFIG_FES BIT(14)
172#define GMAC_CONFIG_FES_SHIFT 14
173#define GMAC_CONFIG_DM BIT(13)
174#define GMAC_CONFIG_LM BIT(12)
175#define GMAC_CONFIG_DCRS BIT(9)
176#define GMAC_CONFIG_TE BIT(1)
177#define GMAC_CONFIG_RE BIT(0)
178
179/* MAC extended config */
180#define GMAC_CONFIG_EIPG GENMASK(29, 25)
181#define GMAC_CONFIG_EIPG_SHIFT 25
182#define GMAC_CONFIG_EIPG_EN BIT(24)
183#define GMAC_CONFIG_HDSMS GENMASK(22, 20)
184#define GMAC_CONFIG_HDSMS_SHIFT 20
185#define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT)
186
187/* MAC HW features0 bitmap */
188#define GMAC_HW_FEAT_SAVLANINS BIT(27)
189#define GMAC_HW_FEAT_ADDMAC BIT(18)
190#define GMAC_HW_FEAT_RXCOESEL BIT(16)
191#define GMAC_HW_FEAT_TXCOSEL BIT(14)
192#define GMAC_HW_FEAT_EEESEL BIT(13)
193#define GMAC_HW_FEAT_TSSEL BIT(12)
194#define GMAC_HW_FEAT_ARPOFFSEL BIT(9)
195#define GMAC_HW_FEAT_MMCSEL BIT(8)
196#define GMAC_HW_FEAT_MGKSEL BIT(7)
197#define GMAC_HW_FEAT_RWKSEL BIT(6)
198#define GMAC_HW_FEAT_SMASEL BIT(5)
199#define GMAC_HW_FEAT_VLHASH BIT(4)
200#define GMAC_HW_FEAT_PCSSEL BIT(3)
201#define GMAC_HW_FEAT_HDSEL BIT(2)
202#define GMAC_HW_FEAT_GMIISEL BIT(1)
203#define GMAC_HW_FEAT_MIISEL BIT(0)
204
205/* MAC HW features1 bitmap */
206#define GMAC_HW_FEAT_L3L4FNUM GENMASK(30, 27)
207#define GMAC_HW_HASH_TB_SZ GENMASK(25, 24)
208#define GMAC_HW_FEAT_AVSEL BIT(20)
209#define GMAC_HW_TSOEN BIT(18)
210#define GMAC_HW_FEAT_SPHEN BIT(17)
211#define GMAC_HW_ADDR64 GENMASK(15, 14)
212#define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)
213#define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)
214
215/* MAC HW features2 bitmap */
216#define GMAC_HW_FEAT_AUXSNAPNUM GENMASK(30, 28)
217#define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24)
218#define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)
219#define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)
220#define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6)
221#define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0)
222
223/* MAC HW features3 bitmap */
224#define GMAC_HW_FEAT_ASP GENMASK(29, 28)
225#define GMAC_HW_FEAT_TBSSEL BIT(27)
226#define GMAC_HW_FEAT_FPESEL BIT(26)
227#define GMAC_HW_FEAT_ESTWID GENMASK(21, 20)
228#define GMAC_HW_FEAT_ESTDEP GENMASK(19, 17)
229#define GMAC_HW_FEAT_ESTSEL BIT(16)
230#define GMAC_HW_FEAT_FRPES GENMASK(14, 13)
231#define GMAC_HW_FEAT_FRPBS GENMASK(12, 11)
232#define GMAC_HW_FEAT_FRPSEL BIT(10)
233#define GMAC_HW_FEAT_DVLAN BIT(5)
234#define GMAC_HW_FEAT_NRVF GENMASK(2, 0)
235
236/* MAC extended config 1 */
237#define GMAC_CONFIG1_SAVE_EN BIT(24)
238#define GMAC_CONFIG1_SPLM(v) FIELD_PREP(GENMASK(9, 8), v)
239
240/* GMAC GPIO Status reg */
241#define GMAC_GPO0 BIT(16)
242#define GMAC_GPO1 BIT(17)
243#define GMAC_GPO2 BIT(18)
244#define GMAC_GPO3 BIT(19)
245
246/* MAC HW ADDR regs */
247#define GMAC_HI_DCS GENMASK(18, 16)
248#define GMAC_HI_DCS_SHIFT 16
249#define GMAC_HI_REG_AE BIT(31)
250
251/* L3/L4 Filters regs */
252#define GMAC_L4DPIM0 BIT(21)
253#define GMAC_L4DPM0 BIT(20)
254#define GMAC_L4SPIM0 BIT(19)
255#define GMAC_L4SPM0 BIT(18)
256#define GMAC_L4PEN0 BIT(16)
257#define GMAC_L3DAIM0 BIT(5)
258#define GMAC_L3DAM0 BIT(4)
259#define GMAC_L3SAIM0 BIT(3)
260#define GMAC_L3SAM0 BIT(2)
261#define GMAC_L3PEN0 BIT(0)
262#define GMAC_L4DP0 GENMASK(31, 16)
263#define GMAC_L4DP0_SHIFT 16
264#define GMAC_L4SP0 GENMASK(15, 0)
265
266/* MAC Timestamp Status */
267#define GMAC_TIMESTAMP_AUXTSTRIG BIT(2)
268#define GMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25)
269#define GMAC_TIMESTAMP_ATSNS_SHIFT 25
270
271/* MTL registers */
272#define MTL_OPERATION_MODE 0x00000c00
273#define MTL_FRPE BIT(15)
274#define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)
275#define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
276#define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
277#define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
278#define MTL_OPERATION_SCHALG_SP (0x3 << 5)
279#define MTL_OPERATION_RAA BIT(2)
280#define MTL_OPERATION_RAA_SP (0x0 << 2)
281#define MTL_OPERATION_RAA_WSP (0x1 << 2)
282
283#define MTL_INT_STATUS 0x00000c20
284#define MTL_INT_QX(x) BIT(x)
285
286#define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */
287#define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */
288#define MTL_RXQ_DMA_QXMDMACH_MASK(x) (0xf << 8 * (x))
289#define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q)))
290
291#define MTL_CHAN_BASE_ADDR 0x00000d00
292#define MTL_CHAN_BASE_OFFSET 0x40
293
294static inline u32 mtl_chanx_base_addr(const struct dwmac4_addrs *addrs,
295 const u32 x)
296{
297 u32 addr;
298
299 if (addrs)
300 addr = addrs->mtl_chan + (x * addrs->mtl_chan_offset);
301 else
302 addr = MTL_CHAN_BASE_ADDR + (x * MTL_CHAN_BASE_OFFSET);
303
304 return addr;
305}
306
307#define MTL_CHAN_TX_OP_MODE(addrs, x) mtl_chanx_base_addr(addrs, x)
308#define MTL_CHAN_TX_DEBUG(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x8)
309#define MTL_CHAN_INT_CTRL(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x2c)
310#define MTL_CHAN_RX_OP_MODE(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x30)
311#define MTL_CHAN_RX_DEBUG(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x38)
312
313#define MTL_OP_MODE_RSF BIT(5)
314#define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2)
315#define MTL_OP_MODE_TXQEN_AV BIT(2)
316#define MTL_OP_MODE_TXQEN BIT(3)
317#define MTL_OP_MODE_TSF BIT(1)
318
319#define MTL_OP_MODE_TQS_MASK GENMASK(24, 16)
320#define MTL_OP_MODE_TQS_SHIFT 16
321
322#define MTL_OP_MODE_TTC_MASK 0x70
323#define MTL_OP_MODE_TTC_SHIFT 4
324
325#define MTL_OP_MODE_TTC_32 0
326#define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT)
327#define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
328#define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT)
329#define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT)
330#define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT)
331#define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT)
332#define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT)
333
334#define MTL_OP_MODE_RQS_MASK GENMASK(29, 20)
335#define MTL_OP_MODE_RQS_SHIFT 20
336
337#define MTL_OP_MODE_RFD_MASK GENMASK(19, 14)
338#define MTL_OP_MODE_RFD_SHIFT 14
339
340#define MTL_OP_MODE_RFA_MASK GENMASK(13, 8)
341#define MTL_OP_MODE_RFA_SHIFT 8
342
343#define MTL_OP_MODE_EHFC BIT(7)
344
345#define MTL_OP_MODE_RTC_MASK GENMASK(1, 0)
346#define MTL_OP_MODE_RTC_SHIFT 0
347
348#define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT)
349#define MTL_OP_MODE_RTC_64 0
350#define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
351#define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT)
352
353/* MTL ETS Control register */
354#define MTL_ETS_CTRL_BASE_ADDR 0x00000d10
355#define MTL_ETS_CTRL_BASE_OFFSET 0x40
356
357static inline u32 mtl_etsx_ctrl_base_addr(const struct dwmac4_addrs *addrs,
358 const u32 x)
359{
360 u32 addr;
361
362 if (addrs)
363 addr = addrs->mtl_ets_ctrl + (x * addrs->mtl_ets_ctrl_offset);
364 else
365 addr = MTL_ETS_CTRL_BASE_ADDR + (x * MTL_ETS_CTRL_BASE_OFFSET);
366
367 return addr;
368}
369
370#define MTL_ETS_CTRL_CC BIT(3)
371#define MTL_ETS_CTRL_AVALG BIT(2)
372
373/* MTL Queue Quantum Weight */
374#define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18
375#define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40
376
377static inline u32 mtl_txqx_weight_base_addr(const struct dwmac4_addrs *addrs,
378 const u32 x)
379{
380 u32 addr;
381
382 if (addrs)
383 addr = addrs->mtl_txq_weight + (x * addrs->mtl_txq_weight_offset);
384 else
385 addr = MTL_TXQ_WEIGHT_BASE_ADDR + (x * MTL_TXQ_WEIGHT_BASE_OFFSET);
386
387 return addr;
388}
389
390#define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0)
391
392/* MTL sendSlopeCredit register */
393#define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c
394#define MTL_SEND_SLP_CRED_OFFSET 0x40
395
396static inline u32 mtl_send_slp_credx_base_addr(const struct dwmac4_addrs *addrs,
397 const u32 x)
398{
399 u32 addr;
400
401 if (addrs)
402 addr = addrs->mtl_send_slp_cred + (x * addrs->mtl_send_slp_cred_offset);
403 else
404 addr = MTL_SEND_SLP_CRED_BASE_ADDR + (x * MTL_SEND_SLP_CRED_OFFSET);
405
406 return addr;
407}
408
409#define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0)
410
411/* MTL hiCredit register */
412#define MTL_HIGH_CRED_BASE_ADDR 0x00000d20
413#define MTL_HIGH_CRED_OFFSET 0x40
414
415static inline u32 mtl_high_credx_base_addr(const struct dwmac4_addrs *addrs,
416 const u32 x)
417{
418 u32 addr;
419
420 if (addrs)
421 addr = addrs->mtl_high_cred + (x * addrs->mtl_high_cred_offset);
422 else
423 addr = MTL_HIGH_CRED_BASE_ADDR + (x * MTL_HIGH_CRED_OFFSET);
424
425 return addr;
426}
427
428#define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0)
429
430/* MTL loCredit register */
431#define MTL_LOW_CRED_BASE_ADDR 0x00000d24
432#define MTL_LOW_CRED_OFFSET 0x40
433
434static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs,
435 const u32 x)
436{
437 u32 addr;
438
439 if (addrs)
440 addr = addrs->mtl_low_cred + (x * addrs->mtl_low_cred_offset);
441 else
442 addr = MTL_LOW_CRED_BASE_ADDR + (x * MTL_LOW_CRED_OFFSET);
443
444 return addr;
445}
446
447#define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0)
448
449/* MTL debug */
450#define MTL_DEBUG_TXSTSFSTS BIT(5)
451#define MTL_DEBUG_TXFSTS BIT(4)
452#define MTL_DEBUG_TWCSTS BIT(3)
453
454/* MTL debug: Tx FIFO Read Controller Status */
455#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
456#define MTL_DEBUG_TRCSTS_SHIFT 1
457#define MTL_DEBUG_TRCSTS_IDLE 0
458#define MTL_DEBUG_TRCSTS_READ 1
459#define MTL_DEBUG_TRCSTS_TXW 2
460#define MTL_DEBUG_TRCSTS_WRITE 3
461#define MTL_DEBUG_TXPAUSED BIT(0)
462
463/* MAC debug: GMII or MII Transmit Protocol Engine Status */
464#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
465#define MTL_DEBUG_RXFSTS_SHIFT 4
466#define MTL_DEBUG_RXFSTS_EMPTY 0
467#define MTL_DEBUG_RXFSTS_BT 1
468#define MTL_DEBUG_RXFSTS_AT 2
469#define MTL_DEBUG_RXFSTS_FULL 3
470#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
471#define MTL_DEBUG_RRCSTS_SHIFT 1
472#define MTL_DEBUG_RRCSTS_IDLE 0
473#define MTL_DEBUG_RRCSTS_RDATA 1
474#define MTL_DEBUG_RRCSTS_RSTAT 2
475#define MTL_DEBUG_RRCSTS_FLUSH 3
476#define MTL_DEBUG_RWCSTS BIT(0)
477
478/* MTL interrupt */
479#define MTL_RX_OVERFLOW_INT_EN BIT(24)
480#define MTL_RX_OVERFLOW_INT BIT(16)
481
482/* Default operating mode of the MAC */
483#define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \
484 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \
485 GMAC_CONFIG_JE)
486
487/* To dump the core regs excluding the Address Registers */
488#define GMAC_REG_NUM 132
489
490/* MTL debug */
491#define MTL_DEBUG_TXSTSFSTS BIT(5)
492#define MTL_DEBUG_TXFSTS BIT(4)
493#define MTL_DEBUG_TWCSTS BIT(3)
494
495/* MTL debug: Tx FIFO Read Controller Status */
496#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
497#define MTL_DEBUG_TRCSTS_SHIFT 1
498#define MTL_DEBUG_TRCSTS_IDLE 0
499#define MTL_DEBUG_TRCSTS_READ 1
500#define MTL_DEBUG_TRCSTS_TXW 2
501#define MTL_DEBUG_TRCSTS_WRITE 3
502#define MTL_DEBUG_TXPAUSED BIT(0)
503
504/* MAC debug: GMII or MII Transmit Protocol Engine Status */
505#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
506#define MTL_DEBUG_RXFSTS_SHIFT 4
507#define MTL_DEBUG_RXFSTS_EMPTY 0
508#define MTL_DEBUG_RXFSTS_BT 1
509#define MTL_DEBUG_RXFSTS_AT 2
510#define MTL_DEBUG_RXFSTS_FULL 3
511#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
512#define MTL_DEBUG_RRCSTS_SHIFT 1
513#define MTL_DEBUG_RRCSTS_IDLE 0
514#define MTL_DEBUG_RRCSTS_RDATA 1
515#define MTL_DEBUG_RRCSTS_RSTAT 2
516#define MTL_DEBUG_RRCSTS_FLUSH 3
517#define MTL_DEBUG_RWCSTS BIT(0)
518
519/* SGMII/RGMII status register */
520#define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
521#define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
522#define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
523#define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
524#define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
525#define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17
526#define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
527#define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
528#define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)
529/* LNKSPEED */
530#define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2
531#define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1
532#define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0
533
534extern const struct stmmac_dma_ops dwmac4_dma_ops;
535extern const struct stmmac_dma_ops dwmac410_dma_ops;
536#endif /* __DWMAC4_H__ */
537

source code of linux/drivers/net/ethernet/stmicro/stmmac/dwmac4.h