| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Texas Instruments ICSSG Ethernet driver |
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| 3 | * |
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| 4 | * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __NET_TI_ICSSG_SWITCH_MAP_H |
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| 9 | #define __NET_TI_ICSSG_SWITCH_MAP_H |
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| 10 | |
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| 11 | /************************* Ethernet Switch Constants *********************/ |
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| 12 | |
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| 13 | /* if bucket size is changed in firmware then this too should be changed |
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| 14 | * because it directly impacts FDB ageing calculation |
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| 15 | */ |
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| 16 | #define NUMBER_OF_FDB_BUCKET_ENTRIES (4) |
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| 17 | |
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| 18 | /* This is fixed in ICSSG */ |
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| 19 | #define SIZE_OF_FDB (2048) |
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| 20 | |
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| 21 | #define FW_LINK_SPEED_1G (0x00) |
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| 22 | #define FW_LINK_SPEED_100M (0x01) |
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| 23 | #define FW_LINK_SPEED_10M (0x02) |
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| 24 | #define FW_LINK_SPEED_HD (0x80) |
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| 25 | |
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| 26 | /* Time after which FDB entries are checked for aged out values. |
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| 27 | * Values are in nanoseconds |
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| 28 | */ |
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| 29 | #define FDB_AGEING_TIMEOUT_OFFSET 0x0014 |
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| 30 | |
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| 31 | /* Default VLAN tag for Host Port */ |
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| 32 | #define HOST_PORT_DF_VLAN_OFFSET 0x001C |
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| 33 | |
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| 34 | /* Same as HOST_PORT_DF_VLAN_OFFSET */ |
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| 35 | #define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET |
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| 36 | |
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| 37 | /* Default VLAN tag for P1 Port */ |
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| 38 | #define P1_PORT_DF_VLAN_OFFSET 0x0020 |
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| 39 | |
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| 40 | /* Same as P1_PORT_DF_VLAN_OFFSET */ |
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| 41 | #define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET |
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| 42 | |
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| 43 | /* default VLAN tag for P2 Port */ |
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| 44 | #define P2_PORT_DF_VLAN_OFFSET 0x0024 |
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| 45 | |
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| 46 | /* Same as P2_PORT_DF_VLAN_OFFSET */ |
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| 47 | #define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET |
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| 48 | |
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| 49 | /* VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000 */ |
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| 50 | #define VLAN_STATIC_REG_TABLE_OFFSET 0x0100 |
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| 51 | |
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| 52 | /* VLAN-FID Table offset for EMAC */ |
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| 53 | #define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET |
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| 54 | |
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| 55 | /* Packet descriptor Q reserved memory */ |
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| 56 | #define PORT_DESC0_HI 0x2104 |
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| 57 | |
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| 58 | /* Packet descriptor Q reserved memory */ |
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| 59 | #define PORT_DESC0_LO 0x2F6C |
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| 60 | |
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| 61 | /* Packet descriptor Q reserved memory */ |
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| 62 | #define PORT_DESC1_HI 0x3DD4 |
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| 63 | |
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| 64 | /* Packet descriptor Q reserved memory */ |
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| 65 | #define PORT_DESC1_LO 0x4C3C |
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| 66 | |
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| 67 | /* Packet descriptor Q reserved memory */ |
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| 68 | #define HOST_DESC0_HI 0x5AA4 |
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| 69 | |
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| 70 | /* Packet descriptor Q reserved memory */ |
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| 71 | #define HOST_DESC0_LO 0x5F0C |
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| 72 | |
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| 73 | /* Packet descriptor Q reserved memory */ |
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| 74 | #define HOST_DESC1_HI 0x6374 |
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| 75 | |
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| 76 | /* Packet descriptor Q reserved memory */ |
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| 77 | #define HOST_DESC1_LO 0x67DC |
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| 78 | |
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| 79 | /* Special packet descriptor Q reserved memory */ |
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| 80 | #define HOST_SPPD0 0x7AAC |
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| 81 | |
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| 82 | /* Special acket descriptor Q reserved memory */ |
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| 83 | #define HOST_SPPD1 0x7EAC |
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| 84 | |
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| 85 | /* IEP count cycle counter*/ |
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| 86 | #define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC |
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| 87 | |
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| 88 | /* IEP count hi roll over count */ |
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| 89 | #define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET 0x83F4 |
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| 90 | |
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| 91 | /* IEP count hi sw counter */ |
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| 92 | #define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8 |
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| 93 | |
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| 94 | /* Set clock descriptor */ |
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| 95 | #define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET 0x83FC |
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| 96 | |
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| 97 | /* IEP count syncout reduction factor */ |
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| 98 | #define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C |
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| 99 | |
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| 100 | /* IEP count syncout reduction counter */ |
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| 101 | #define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440 |
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| 102 | |
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| 103 | /* IEP count syncout start time cycle counter */ |
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| 104 | #define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444 |
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| 105 | |
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| 106 | /* Control variable to generate SYNC1 */ |
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| 107 | #define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C |
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| 108 | |
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| 109 | /* SystemTime Sync0 periodicity */ |
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| 110 | #define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450 |
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| 111 | |
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| 112 | /* pktTxDelay for P1 = link speed dependent p1 mac delay + p1 phy delay */ |
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| 113 | #define TIMESYNC_FW_WC_PKTTXDELAY_P1_OFFSET 0x8454 |
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| 114 | |
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| 115 | /* pktTxDelay for P2 = link speed dependent p2 mac delay + p2 phy delay */ |
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| 116 | #define TIMESYNC_FW_WC_PKTTXDELAY_P2_OFFSET 0x8458 |
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| 117 | |
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| 118 | /* Set clock operation done signal for next task */ |
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| 119 | #define TIMESYNC_FW_SIG_PNFW_OFFSET 0x845C |
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| 120 | |
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| 121 | /* Set clock operation done signal for next task */ |
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| 122 | #define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8460 |
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| 123 | |
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| 124 | /* New list is copied at this time */ |
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| 125 | #define TAS_CONFIG_CHANGE_TIME 0x000C |
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| 126 | |
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| 127 | /* config change error counter */ |
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| 128 | #define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0014 |
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| 129 | |
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| 130 | /* TAS List update pending flag */ |
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| 131 | #define TAS_CONFIG_PENDING 0x0018 |
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| 132 | |
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| 133 | /* TAS list update trigger flag */ |
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| 134 | #define TAS_CONFIG_CHANGE 0x0019 |
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| 135 | |
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| 136 | /* List length for new TAS schedule */ |
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| 137 | #define TAS_ADMIN_LIST_LENGTH 0x001A |
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| 138 | |
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| 139 | /* Currently active TAS list index */ |
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| 140 | #define TAS_ACTIVE_LIST_INDEX 0x001B |
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| 141 | |
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| 142 | /* Cycle time for the new TAS schedule */ |
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| 143 | #define TAS_ADMIN_CYCLE_TIME 0x001C |
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| 144 | |
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| 145 | /* Cycle counts remaining till the TAS list update */ |
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| 146 | #define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0020 |
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| 147 | |
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| 148 | /* Base Flow ID for sending Packets to Host for Slice0 */ |
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| 149 | #define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x0024 |
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| 150 | |
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| 151 | /* Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET */ |
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| 152 | #define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET |
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| 153 | |
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| 154 | /* Base Flow ID for sending mgmt and Tx TS to Host for Slice0 */ |
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| 155 | #define PSI_L_MGMT_FLOW_ID_OFFSET 0x0026 |
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| 156 | |
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| 157 | /* Same as PSI_L_MGMT_FLOW_ID_OFFSET */ |
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| 158 | #define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET PSI_L_MGMT_FLOW_ID_OFFSET |
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| 159 | |
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| 160 | /* Queue number for Special Packets written here */ |
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| 161 | #define SPL_PKT_DEFAULT_PRIORITY 0x0028 |
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| 162 | |
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| 163 | /* Express Preemptible Queue Mask */ |
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| 164 | #define EXPRESS_PRE_EMPTIVE_Q_MASK 0x0029 |
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| 165 | |
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| 166 | /* Port1/Port2 Default Queue number for untagged Packets, only 1B is used */ |
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| 167 | #define QUEUE_NUM_UNTAGGED 0x002A |
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| 168 | |
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| 169 | /* Stores the table used for priority regeneration. 1B per PCP/Queue */ |
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| 170 | #define PORT_Q_PRIORITY_REGEN_OFFSET 0x002C |
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| 171 | |
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| 172 | /* For marking Packet as priority/express (this feature is disabled) or |
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| 173 | * cut-through/S&F. |
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| 174 | */ |
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| 175 | #define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0034 |
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| 176 | |
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| 177 | /* Stores the table used for priority mapping. 1B per PCP/Queue */ |
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| 178 | #define PORT_Q_PRIORITY_MAPPING_OFFSET 0x003C |
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| 179 | |
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| 180 | /* Used to notify the FW of the current link speed */ |
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| 181 | #define PORT_LINK_SPEED_OFFSET 0x00A8 |
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| 182 | |
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| 183 | /* TAS gate mask for windows list0 */ |
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| 184 | #define TAS_GATE_MASK_LIST0 0x0100 |
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| 185 | |
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| 186 | /* TAS gate mask for windows list1 */ |
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| 187 | #define TAS_GATE_MASK_LIST1 0x0350 |
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| 188 | |
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| 189 | /* Memory to Enable/Disable Preemption on TX side */ |
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| 190 | #define PRE_EMPTION_ENABLE_TX 0x05A0 |
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| 191 | |
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| 192 | /* Active State of Preemption on TX side */ |
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| 193 | #define PRE_EMPTION_ACTIVE_TX 0x05A1 |
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| 194 | |
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| 195 | /* Memory to Enable/Disable Verify State Machine Preemption */ |
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| 196 | #define PRE_EMPTION_ENABLE_VERIFY 0x05A2 |
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| 197 | |
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| 198 | /* Verify Status of State Machine */ |
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| 199 | #define PRE_EMPTION_VERIFY_STATUS 0x05A3 |
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| 200 | |
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| 201 | /* Non Final Fragment Size supported by Link Partner */ |
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| 202 | #define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x05A4 |
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| 203 | |
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| 204 | /* Non Final Fragment Size supported by Firmware */ |
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| 205 | #define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x05A6 |
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| 206 | |
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| 207 | /* Time in ms the State machine waits for respond Packet */ |
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| 208 | #define PRE_EMPTION_VERIFY_TIME 0x05A8 |
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| 209 | |
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| 210 | /* Memory used for R30 related management commands */ |
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| 211 | #define MGR_R30_CMD_OFFSET 0x05AC |
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| 212 | |
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| 213 | /* HW Buffer Pool0 base address */ |
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| 214 | #define BUFFER_POOL_0_ADDR_OFFSET 0x05BC |
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| 215 | |
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| 216 | /* 16B for Host Egress MSMC Q (Pre-emptible) context */ |
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| 217 | #define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x0684 |
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| 218 | |
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| 219 | /* Buffer for 8 FDB entries to be added by 'Add Multiple FDB entries IOCTL' */ |
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| 220 | #define FDB_CMD_BUFFER 0x0894 |
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| 221 | |
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| 222 | /* TAS queue max sdu length list */ |
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| 223 | #define TAS_QUEUE_MAX_SDU_LIST 0x08FA |
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| 224 | |
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| 225 | /* Used by FW to generate random number with the SEED value */ |
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| 226 | #define HD_RAND_SEED_OFFSET 0x0934 |
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| 227 | |
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| 228 | /* 16B for Host Egress MSMC Q (Express) context */ |
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| 229 | #define HOST_RX_Q_EXP_CONTEXT_OFFSET 0x0940 |
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| 230 | |
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| 231 | /* Start of 32 bits PA_STAT counters */ |
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| 232 | #define PA_STAT_32b_START_OFFSET 0x0080 |
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| 233 | |
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| 234 | #endif /* __NET_TI_ICSSG_SWITCH_MAP_H */ |
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| 235 | |
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