1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2023 Linaro Ltd. */
4
5#include <linux/types.h>
6
7#include "../gsi.h"
8#include "../reg.h"
9#include "../gsi_reg.h"
10
11REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
12 0x0000c020 + 0x1000 * GSI_EE_AP);
13
14REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
15 0x0000c024 + 0x1000 * GSI_EE_AP);
16
17static const u32 reg_ch_c_cntxt_0_fmask[] = {
18 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
19 [CHTYPE_DIR] = BIT(3),
20 [CH_EE] = GENMASK(7, 4),
21 [CHID] = GENMASK(12, 8),
22 /* Bit 13 reserved */
23 [ERINDEX] = GENMASK(18, 14),
24 /* Bit 19 reserved */
25 [CHSTATE] = GENMASK(23, 20),
26 [ELEMENT_SIZE] = GENMASK(31, 24),
27};
28
29REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
30 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
31
32static const u32 reg_ch_c_cntxt_1_fmask[] = {
33 [CH_R_LENGTH] = GENMASK(15, 0),
34 /* Bits 16-31 reserved */
35};
36
37REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
38 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
39
40REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
41
42REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
43
44static const u32 reg_ch_c_qos_fmask[] = {
45 [WRR_WEIGHT] = GENMASK(3, 0),
46 /* Bits 4-7 reserved */
47 [MAX_PREFETCH] = BIT(8),
48 [USE_DB_ENG] = BIT(9),
49 /* Bits 10-31 reserved */
50};
51
52REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
53
54static const u32 reg_error_log_fmask[] = {
55 [ERR_ARG3] = GENMASK(3, 0),
56 [ERR_ARG2] = GENMASK(7, 4),
57 [ERR_ARG1] = GENMASK(11, 8),
58 [ERR_CODE] = GENMASK(15, 12),
59 /* Bits 16-18 reserved */
60 [ERR_VIRT_IDX] = GENMASK(23, 19),
61 [ERR_TYPE] = GENMASK(27, 24),
62 [ERR_EE] = GENMASK(31, 28),
63};
64
65REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
66 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
67
68REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
69 0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
70
71REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
72 0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
73
74REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
75 0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
76
77static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
78 [EV_CHTYPE] = GENMASK(3, 0),
79 [EV_EE] = GENMASK(7, 4),
80 [EV_EVCHID] = GENMASK(15, 8),
81 [EV_INTYPE] = BIT(16),
82 /* Bits 17-19 reserved */
83 [EV_CHSTATE] = GENMASK(23, 20),
84 [EV_ELEMENT_SIZE] = GENMASK(31, 24),
85};
86
87REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
88 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
89
90static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
91 [R_LENGTH] = GENMASK(15, 0),
92};
93
94REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
95 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
96
97REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
98 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
99
100REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
101 0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
102
103REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
104 0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
105
106static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
107 [EV_MODT] = GENMASK(15, 0),
108 [EV_MODC] = GENMASK(23, 16),
109 [EV_MOD_CNT] = GENMASK(31, 24),
110};
111
112REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
113 0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
114
115REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
116 0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
117
118REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
119 0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
120
121REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
122 0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
123
124REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
125 0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
126
127REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
128 0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
129
130REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
131 0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
132
133REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
134 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
135
136REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
137 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
138
139REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
140 0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
141
142static const u32 reg_gsi_status_fmask[] = {
143 [ENABLED] = BIT(0),
144 /* Bits 1-31 reserved */
145};
146
147REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
148
149static const u32 reg_ch_cmd_fmask[] = {
150 [CH_CHID] = GENMASK(7, 0),
151 /* Bits 8-23 reserved */
152 [CH_OPCODE] = GENMASK(31, 24),
153};
154
155REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
156
157static const u32 reg_ev_ch_cmd_fmask[] = {
158 [EV_CHID] = GENMASK(7, 0),
159 /* Bits 8-23 reserved */
160 [EV_OPCODE] = GENMASK(31, 24),
161};
162
163REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
164
165static const u32 reg_generic_cmd_fmask[] = {
166 [GENERIC_OPCODE] = GENMASK(4, 0),
167 [GENERIC_CHID] = GENMASK(9, 5),
168 [GENERIC_EE] = GENMASK(13, 10),
169 /* Bits 14-31 reserved */
170};
171
172REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
173
174REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
175
176REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
177
178REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
179
180REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
181
182REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
183 0x0001f098 + 0x4000 * GSI_EE_AP);
184
185REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
186 0x0001f09c + 0x4000 * GSI_EE_AP);
187
188REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
189 0x0001f0a0 + 0x4000 * GSI_EE_AP);
190
191REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
192 0x0001f0a4 + 0x4000 * GSI_EE_AP);
193
194REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
195
196REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
197 0x0001f0b8 + 0x4000 * GSI_EE_AP);
198
199REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
200 0x0001f0c0 + 0x4000 * GSI_EE_AP);
201
202REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
203
204REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
205
206REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
207
208REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
209
210REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
211
212REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
213
214static const u32 reg_cntxt_intset_fmask[] = {
215 [INTYPE] = BIT(0)
216 /* Bits 1-31 reserved */
217};
218
219REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
220
221REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
222
223REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
224
225static const u32 reg_cntxt_scratch_0_fmask[] = {
226 [INTER_EE_RESULT] = GENMASK(2, 0),
227 /* Bits 3-4 reserved */
228 [GENERIC_EE_RESULT] = GENMASK(7, 5),
229 /* Bits 8-31 reserved */
230};
231
232REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
233
234static const struct reg *reg_array[] = {
235 [INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
236 [INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
237 [CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
238 [CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
239 [CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
240 [CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
241 [CH_C_QOS] = &reg_ch_c_qos,
242 [CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
243 [CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
244 [CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
245 [CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
246 [EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
247 [EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
248 [EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
249 [EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
250 [EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
251 [EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
252 [EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
253 [EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
254 [EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
255 [EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
256 [EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
257 [EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
258 [EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
259 [CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
260 [EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
261 [GSI_STATUS] = &reg_gsi_status,
262 [CH_CMD] = &reg_ch_cmd,
263 [EV_CH_CMD] = &reg_ev_ch_cmd,
264 [GENERIC_CMD] = &reg_generic_cmd,
265 [CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
266 [CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
267 [CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
268 [CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
269 [CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
270 [CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
271 [CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
272 [CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
273 [CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
274 [CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
275 [CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
276 [CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
277 [CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
278 [CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
279 [CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
280 [CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
281 [CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
282 [CNTXT_INTSET] = &reg_cntxt_intset,
283 [ERROR_LOG] = &reg_error_log,
284 [ERROR_LOG_CLR] = &reg_error_log_clr,
285 [CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
286};
287
288const struct regs gsi_regs_v3_1 = {
289 .reg_count = ARRAY_SIZE(reg_array),
290 .reg = reg_array,
291};
292

source code of linux/drivers/net/ipa/reg/gsi_reg-v3.1.c