1 | // SPDX-License-Identifier: GPL-2.0 |
2 | |
3 | /* Copyright (C) 2023 Linaro Ltd. */ |
4 | |
5 | #include <linux/types.h> |
6 | |
7 | #include "../gsi.h" |
8 | #include "../reg.h" |
9 | #include "../gsi_reg.h" |
10 | |
11 | REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk, |
12 | 0x0000c020 + 0x1000 * GSI_EE_AP); |
13 | |
14 | REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk, |
15 | 0x0000c024 + 0x1000 * GSI_EE_AP); |
16 | |
17 | static const u32 reg_ch_c_cntxt_0_fmask[] = { |
18 | [CHTYPE_PROTOCOL] = GENMASK(2, 0), |
19 | [CHTYPE_DIR] = BIT(3), |
20 | [CH_EE] = GENMASK(7, 4), |
21 | [CHID] = GENMASK(12, 8), |
22 | /* Bit 13 reserved */ |
23 | [ERINDEX] = GENMASK(18, 14), |
24 | /* Bit 19 reserved */ |
25 | [CHSTATE] = GENMASK(23, 20), |
26 | [ELEMENT_SIZE] = GENMASK(31, 24), |
27 | }; |
28 | |
29 | REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0, |
30 | 0x0001c000 + 0x4000 * GSI_EE_AP, 0x80); |
31 | |
32 | static const u32 reg_ch_c_cntxt_1_fmask[] = { |
33 | [CH_R_LENGTH] = GENMASK(15, 0), |
34 | /* Bits 16-31 reserved */ |
35 | }; |
36 | |
37 | REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1, |
38 | 0x0001c004 + 0x4000 * GSI_EE_AP, 0x80); |
39 | |
40 | REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80); |
41 | |
42 | REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80); |
43 | |
44 | static const u32 reg_ch_c_qos_fmask[] = { |
45 | [WRR_WEIGHT] = GENMASK(3, 0), |
46 | /* Bits 4-7 reserved */ |
47 | [MAX_PREFETCH] = BIT(8), |
48 | [USE_DB_ENG] = BIT(9), |
49 | /* Bits 10-31 reserved */ |
50 | }; |
51 | |
52 | REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80); |
53 | |
54 | static const u32 reg_error_log_fmask[] = { |
55 | [ERR_ARG3] = GENMASK(3, 0), |
56 | [ERR_ARG2] = GENMASK(7, 4), |
57 | [ERR_ARG1] = GENMASK(11, 8), |
58 | [ERR_CODE] = GENMASK(15, 12), |
59 | /* Bits 16-18 reserved */ |
60 | [ERR_VIRT_IDX] = GENMASK(23, 19), |
61 | [ERR_TYPE] = GENMASK(27, 24), |
62 | [ERR_EE] = GENMASK(31, 28), |
63 | }; |
64 | |
65 | REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0, |
66 | 0x0001c060 + 0x4000 * GSI_EE_AP, 0x80); |
67 | |
68 | REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1, |
69 | 0x0001c064 + 0x4000 * GSI_EE_AP, 0x80); |
70 | |
71 | REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2, |
72 | 0x0001c068 + 0x4000 * GSI_EE_AP, 0x80); |
73 | |
74 | REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3, |
75 | 0x0001c06c + 0x4000 * GSI_EE_AP, 0x80); |
76 | |
77 | static const u32 reg_ev_ch_e_cntxt_0_fmask[] = { |
78 | [EV_CHTYPE] = GENMASK(3, 0), |
79 | [EV_EE] = GENMASK(7, 4), |
80 | [EV_EVCHID] = GENMASK(15, 8), |
81 | [EV_INTYPE] = BIT(16), |
82 | /* Bits 17-19 reserved */ |
83 | [EV_CHSTATE] = GENMASK(23, 20), |
84 | [EV_ELEMENT_SIZE] = GENMASK(31, 24), |
85 | }; |
86 | |
87 | REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0, |
88 | 0x0001d000 + 0x4000 * GSI_EE_AP, 0x80); |
89 | |
90 | static const u32 reg_ev_ch_e_cntxt_1_fmask[] = { |
91 | [R_LENGTH] = GENMASK(15, 0), |
92 | }; |
93 | |
94 | REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1, |
95 | 0x0001d004 + 0x4000 * GSI_EE_AP, 0x80); |
96 | |
97 | REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2, |
98 | 0x0001d008 + 0x4000 * GSI_EE_AP, 0x80); |
99 | |
100 | REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3, |
101 | 0x0001d00c + 0x4000 * GSI_EE_AP, 0x80); |
102 | |
103 | REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4, |
104 | 0x0001d010 + 0x4000 * GSI_EE_AP, 0x80); |
105 | |
106 | static const u32 reg_ev_ch_e_cntxt_8_fmask[] = { |
107 | [EV_MODT] = GENMASK(15, 0), |
108 | [EV_MODC] = GENMASK(23, 16), |
109 | [EV_MOD_CNT] = GENMASK(31, 24), |
110 | }; |
111 | |
112 | REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8, |
113 | 0x0001d020 + 0x4000 * GSI_EE_AP, 0x80); |
114 | |
115 | REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9, |
116 | 0x0001d024 + 0x4000 * GSI_EE_AP, 0x80); |
117 | |
118 | REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10, |
119 | 0x0001d028 + 0x4000 * GSI_EE_AP, 0x80); |
120 | |
121 | REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11, |
122 | 0x0001d02c + 0x4000 * GSI_EE_AP, 0x80); |
123 | |
124 | REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12, |
125 | 0x0001d030 + 0x4000 * GSI_EE_AP, 0x80); |
126 | |
127 | REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13, |
128 | 0x0001d034 + 0x4000 * GSI_EE_AP, 0x80); |
129 | |
130 | REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0, |
131 | 0x0001d048 + 0x4000 * GSI_EE_AP, 0x80); |
132 | |
133 | REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1, |
134 | 0x0001d04c + 0x4000 * GSI_EE_AP, 0x80); |
135 | |
136 | REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0, |
137 | 0x0001e000 + 0x4000 * GSI_EE_AP, 0x08); |
138 | |
139 | REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0, |
140 | 0x0001e100 + 0x4000 * GSI_EE_AP, 0x08); |
141 | |
142 | static const u32 reg_gsi_status_fmask[] = { |
143 | [ENABLED] = BIT(0), |
144 | /* Bits 1-31 reserved */ |
145 | }; |
146 | |
147 | REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP); |
148 | |
149 | static const u32 reg_ch_cmd_fmask[] = { |
150 | [CH_CHID] = GENMASK(7, 0), |
151 | /* Bits 8-23 reserved */ |
152 | [CH_OPCODE] = GENMASK(31, 24), |
153 | }; |
154 | |
155 | REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP); |
156 | |
157 | static const u32 reg_ev_ch_cmd_fmask[] = { |
158 | [EV_CHID] = GENMASK(7, 0), |
159 | /* Bits 8-23 reserved */ |
160 | [EV_OPCODE] = GENMASK(31, 24), |
161 | }; |
162 | |
163 | REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP); |
164 | |
165 | static const u32 reg_generic_cmd_fmask[] = { |
166 | [GENERIC_OPCODE] = GENMASK(4, 0), |
167 | [GENERIC_CHID] = GENMASK(9, 5), |
168 | [GENERIC_EE] = GENMASK(13, 10), |
169 | /* Bits 14-31 reserved */ |
170 | }; |
171 | |
172 | REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP); |
173 | |
174 | static const u32 reg_hw_param_2_fmask[] = { |
175 | [IRAM_SIZE] = GENMASK(2, 0), |
176 | [NUM_CH_PER_EE] = GENMASK(7, 3), |
177 | [NUM_EV_PER_EE] = GENMASK(12, 8), |
178 | [GSI_CH_PEND_TRANSLATE] = BIT(13), |
179 | [GSI_CH_FULL_LOGIC] = BIT(14), |
180 | /* Bits 15-31 reserved */ |
181 | }; |
182 | |
183 | REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP); |
184 | |
185 | REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP); |
186 | |
187 | REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP); |
188 | |
189 | REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP); |
190 | |
191 | REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP); |
192 | |
193 | REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk, |
194 | 0x0001f098 + 0x4000 * GSI_EE_AP); |
195 | |
196 | REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk, |
197 | 0x0001f09c + 0x4000 * GSI_EE_AP); |
198 | |
199 | REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr, |
200 | 0x0001f0a0 + 0x4000 * GSI_EE_AP); |
201 | |
202 | REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr, |
203 | 0x0001f0a4 + 0x4000 * GSI_EE_AP); |
204 | |
205 | REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP); |
206 | |
207 | REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk, |
208 | 0x0001f0b8 + 0x4000 * GSI_EE_AP); |
209 | |
210 | REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr, |
211 | 0x0001f0c0 + 0x4000 * GSI_EE_AP); |
212 | |
213 | REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP); |
214 | |
215 | REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP); |
216 | |
217 | REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP); |
218 | |
219 | REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP); |
220 | |
221 | REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP); |
222 | |
223 | REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP); |
224 | |
225 | static const u32 reg_cntxt_intset_fmask[] = { |
226 | [INTYPE] = BIT(0) |
227 | /* Bits 1-31 reserved */ |
228 | }; |
229 | |
230 | REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP); |
231 | |
232 | REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP); |
233 | |
234 | REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP); |
235 | |
236 | static const u32 reg_cntxt_scratch_0_fmask[] = { |
237 | [INTER_EE_RESULT] = GENMASK(2, 0), |
238 | /* Bits 3-4 reserved */ |
239 | [GENERIC_EE_RESULT] = GENMASK(7, 5), |
240 | /* Bits 8-31 reserved */ |
241 | }; |
242 | |
243 | REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP); |
244 | |
245 | static const struct reg *reg_array[] = { |
246 | [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk, |
247 | [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk, |
248 | [CH_C_CNTXT_0] = ®_ch_c_cntxt_0, |
249 | [CH_C_CNTXT_1] = ®_ch_c_cntxt_1, |
250 | [CH_C_CNTXT_2] = ®_ch_c_cntxt_2, |
251 | [CH_C_CNTXT_3] = ®_ch_c_cntxt_3, |
252 | [CH_C_QOS] = ®_ch_c_qos, |
253 | [CH_C_SCRATCH_0] = ®_ch_c_scratch_0, |
254 | [CH_C_SCRATCH_1] = ®_ch_c_scratch_1, |
255 | [CH_C_SCRATCH_2] = ®_ch_c_scratch_2, |
256 | [CH_C_SCRATCH_3] = ®_ch_c_scratch_3, |
257 | [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0, |
258 | [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1, |
259 | [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2, |
260 | [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3, |
261 | [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4, |
262 | [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8, |
263 | [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9, |
264 | [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10, |
265 | [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11, |
266 | [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12, |
267 | [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13, |
268 | [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0, |
269 | [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1, |
270 | [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0, |
271 | [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0, |
272 | [GSI_STATUS] = ®_gsi_status, |
273 | [CH_CMD] = ®_ch_cmd, |
274 | [EV_CH_CMD] = ®_ev_ch_cmd, |
275 | [GENERIC_CMD] = ®_generic_cmd, |
276 | [HW_PARAM_2] = ®_hw_param_2, |
277 | [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq, |
278 | [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk, |
279 | [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq, |
280 | [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq, |
281 | [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk, |
282 | [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk, |
283 | [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr, |
284 | [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr, |
285 | [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq, |
286 | [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk, |
287 | [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr, |
288 | [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts, |
289 | [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en, |
290 | [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr, |
291 | [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts, |
292 | [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en, |
293 | [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr, |
294 | [CNTXT_INTSET] = ®_cntxt_intset, |
295 | [ERROR_LOG] = ®_error_log, |
296 | [ERROR_LOG_CLR] = ®_error_log_clr, |
297 | [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0, |
298 | }; |
299 | |
300 | const struct regs gsi_regs_v3_5_1 = { |
301 | .reg_count = ARRAY_SIZE(reg_array), |
302 | .reg = reg_array, |
303 | }; |
304 | |