1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2023 Linaro Ltd. */
4
5#include <linux/types.h>
6
7#include "../gsi.h"
8#include "../reg.h"
9#include "../gsi_reg.h"
10
11REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
12 0x0000c020 + 0x1000 * GSI_EE_AP);
13
14REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
15 0x0000c024 + 0x1000 * GSI_EE_AP);
16
17static const u32 reg_ch_c_cntxt_0_fmask[] = {
18 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
19 [CHTYPE_DIR] = BIT(3),
20 [CH_EE] = GENMASK(7, 4),
21 [CHID] = GENMASK(12, 8),
22 [CHTYPE_PROTOCOL_MSB] = BIT(13),
23 [ERINDEX] = GENMASK(18, 14),
24 /* Bit 19 reserved */
25 [CHSTATE] = GENMASK(23, 20),
26 [ELEMENT_SIZE] = GENMASK(31, 24),
27};
28
29REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
30 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
31
32static const u32 reg_ch_c_cntxt_1_fmask[] = {
33 [CH_R_LENGTH] = GENMASK(15, 0),
34 /* Bits 16-31 reserved */
35};
36
37REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
38 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
39
40REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
41
42REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
43
44static const u32 reg_ch_c_qos_fmask[] = {
45 [WRR_WEIGHT] = GENMASK(3, 0),
46 /* Bits 4-7 reserved */
47 [MAX_PREFETCH] = BIT(8),
48 [USE_DB_ENG] = BIT(9),
49 [PREFETCH_MODE] = GENMASK(13, 10),
50 /* Bits 14-15 reserved */
51 [EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
52 /* Bits 24-31 reserved */
53};
54
55REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
56
57static const u32 reg_error_log_fmask[] = {
58 [ERR_ARG3] = GENMASK(3, 0),
59 [ERR_ARG2] = GENMASK(7, 4),
60 [ERR_ARG1] = GENMASK(11, 8),
61 [ERR_CODE] = GENMASK(15, 12),
62 /* Bits 16-18 reserved */
63 [ERR_VIRT_IDX] = GENMASK(23, 19),
64 [ERR_TYPE] = GENMASK(27, 24),
65 [ERR_EE] = GENMASK(31, 28),
66};
67
68REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
69 0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
70
71REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
72 0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
73
74REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
75 0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
76
77REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
78 0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
79
80static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
81 [EV_CHTYPE] = GENMASK(3, 0),
82 [EV_EE] = GENMASK(7, 4),
83 [EV_EVCHID] = GENMASK(15, 8),
84 [EV_INTYPE] = BIT(16),
85 /* Bits 17-19 reserved */
86 [EV_CHSTATE] = GENMASK(23, 20),
87 [EV_ELEMENT_SIZE] = GENMASK(31, 24),
88};
89
90REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
91 0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
92
93static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
94 [R_LENGTH] = GENMASK(15, 0),
95};
96
97REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
98 0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
99
100REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
101 0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
102
103REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
104 0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
105
106REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
107 0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
108
109static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
110 [EV_MODT] = GENMASK(15, 0),
111 [EV_MODC] = GENMASK(23, 16),
112 [EV_MOD_CNT] = GENMASK(31, 24),
113};
114
115REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
116 0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
117
118REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
119 0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
120
121REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
122 0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
123
124REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
125 0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
126
127REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
128 0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
129
130REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
131 0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
132
133REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
134 0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
135
136REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
137 0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
138
139REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
140 0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
141
142REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
143 0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
144
145static const u32 reg_gsi_status_fmask[] = {
146 [ENABLED] = BIT(0),
147 /* Bits 1-31 reserved */
148};
149
150REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
151
152static const u32 reg_ch_cmd_fmask[] = {
153 [CH_CHID] = GENMASK(7, 0),
154 /* Bits 8-23 reserved */
155 [CH_OPCODE] = GENMASK(31, 24),
156};
157
158REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
159
160static const u32 reg_ev_ch_cmd_fmask[] = {
161 [EV_CHID] = GENMASK(7, 0),
162 /* Bits 8-23 reserved */
163 [EV_OPCODE] = GENMASK(31, 24),
164};
165
166REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
167
168static const u32 reg_generic_cmd_fmask[] = {
169 [GENERIC_OPCODE] = GENMASK(4, 0),
170 [GENERIC_CHID] = GENMASK(9, 5),
171 [GENERIC_EE] = GENMASK(13, 10),
172 /* Bits 14-31 reserved */
173};
174
175REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
176
177static const u32 reg_hw_param_2_fmask[] = {
178 [IRAM_SIZE] = GENMASK(2, 0),
179 [NUM_CH_PER_EE] = GENMASK(7, 3),
180 [NUM_EV_PER_EE] = GENMASK(12, 8),
181 [GSI_CH_PEND_TRANSLATE] = BIT(13),
182 [GSI_CH_FULL_LOGIC] = BIT(14),
183 [GSI_USE_SDMA] = BIT(15),
184 [GSI_SDMA_N_INT] = GENMASK(18, 16),
185 [GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
186 [GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
187 [GSI_USE_RD_WR_ENG] = BIT(30),
188 [GSI_USE_INTER_EE] = BIT(31),
189};
190
191REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
192
193REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
194
195REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
196
197REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
198
199REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
200
201REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
202 0x00012098 + 0x4000 * GSI_EE_AP);
203
204REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
205 0x0001209c + 0x4000 * GSI_EE_AP);
206
207REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
208 0x000120a0 + 0x4000 * GSI_EE_AP);
209
210REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
211 0x000120a4 + 0x4000 * GSI_EE_AP);
212
213REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
214
215REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
216 0x000120b8 + 0x4000 * GSI_EE_AP);
217
218REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
219 0x000120c0 + 0x4000 * GSI_EE_AP);
220
221REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
222
223REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
224
225REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
226
227REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
228
229REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
230
231REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
232
233static const u32 reg_cntxt_intset_fmask[] = {
234 [INTYPE] = BIT(0)
235 /* Bits 1-31 reserved */
236};
237
238REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
239
240REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
241
242REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
243
244static const u32 reg_cntxt_scratch_0_fmask[] = {
245 [INTER_EE_RESULT] = GENMASK(2, 0),
246 /* Bits 3-4 reserved */
247 [GENERIC_EE_RESULT] = GENMASK(7, 5),
248 /* Bits 8-31 reserved */
249};
250
251REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
252
253static const struct reg *reg_array[] = {
254 [INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
255 [INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
256 [CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
257 [CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
258 [CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
259 [CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
260 [CH_C_QOS] = &reg_ch_c_qos,
261 [CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
262 [CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
263 [CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
264 [CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
265 [EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
266 [EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
267 [EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
268 [EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
269 [EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
270 [EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
271 [EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
272 [EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
273 [EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
274 [EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
275 [EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
276 [EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
277 [EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
278 [CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
279 [EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
280 [GSI_STATUS] = &reg_gsi_status,
281 [CH_CMD] = &reg_ch_cmd,
282 [EV_CH_CMD] = &reg_ev_ch_cmd,
283 [GENERIC_CMD] = &reg_generic_cmd,
284 [HW_PARAM_2] = &reg_hw_param_2,
285 [CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
286 [CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
287 [CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
288 [CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
289 [CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
290 [CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
291 [CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
292 [CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
293 [CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
294 [CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
295 [CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
296 [CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
297 [CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
298 [CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
299 [CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
300 [CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
301 [CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
302 [CNTXT_INTSET] = &reg_cntxt_intset,
303 [ERROR_LOG] = &reg_error_log,
304 [ERROR_LOG_CLR] = &reg_error_log_clr,
305 [CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
306};
307
308const struct regs gsi_regs_v4_5 = {
309 .reg_count = ARRAY_SIZE(reg_array),
310 .reg = reg_array,
311};
312

source code of linux/drivers/net/ipa/reg/gsi_reg-v4.5.c