1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Driver for Microsemi VSC85xx PHYs
4 *
5 * Copyright (c) 2020 Microsemi Corporation
6 */
7
8#ifndef _MSCC_PHY_MACSEC_H_
9#define _MSCC_PHY_MACSEC_H_
10
11#include <net/macsec.h>
12
13#define MSCC_MS_MAX_FLOWS 16
14
15#define CONTROL_TYPE_EGRESS 0x6
16#define CONTROL_TYPE_INGRESS 0xf
17#define CONTROL_IV0 BIT(5)
18#define CONTROL_IV1 BIT(6)
19#define CONTROL_IV2 BIT(7)
20#define CONTROL_UPDATE_SEQ BIT(13)
21#define CONTROL_IV_IN_SEQ BIT(14)
22#define CONTROL_ENCRYPT_AUTH BIT(15)
23#define CONTROL_KEY_IN_CTX BIT(16)
24#define CONTROL_CRYPTO_ALG(x) ((x) << 17)
25#define CTRYPTO_ALG_AES_CTR_128 0x5
26#define CTRYPTO_ALG_AES_CTR_192 0x6
27#define CTRYPTO_ALG_AES_CTR_256 0x7
28#define CONTROL_DIGEST_TYPE(x) ((x) << 21)
29#define CONTROL_AUTH_ALG(x) ((x) << 23)
30#define AUTH_ALG_AES_GHAS 0x4
31#define CONTROL_AN(x) ((x) << 26)
32#define CONTROL_SEQ_TYPE(x) ((x) << 28)
33#define CONTROL_SEQ_MASK BIT(30)
34#define CONTROL_CONTEXT_ID BIT(31)
35
36enum mscc_macsec_destination_ports {
37 MSCC_MS_PORT_COMMON = 0,
38 MSCC_MS_PORT_RSVD = 1,
39 MSCC_MS_PORT_CONTROLLED = 2,
40 MSCC_MS_PORT_UNCONTROLLED = 3,
41};
42
43enum mscc_macsec_drop_actions {
44 MSCC_MS_ACTION_BYPASS_CRC = 0,
45 MSCC_MS_ACTION_BYPASS_BAD = 1,
46 MSCC_MS_ACTION_DROP = 2,
47 MSCC_MS_ACTION_BYPASS = 3,
48};
49
50enum mscc_macsec_flow_types {
51 MSCC_MS_FLOW_BYPASS = 0,
52 MSCC_MS_FLOW_DROP = 1,
53 MSCC_MS_FLOW_INGRESS = 2,
54 MSCC_MS_FLOW_EGRESS = 3,
55};
56
57enum mscc_macsec_validate_levels {
58 MSCC_MS_VALIDATE_DISABLED = 0,
59 MSCC_MS_VALIDATE_CHECK = 1,
60 MSCC_MS_VALIDATE_STRICT = 2,
61};
62
63enum macsec_bank {
64 FC_BUFFER = 0x04,
65 HOST_MAC = 0x05,
66 LINE_MAC = 0x06,
67 PROC_0 = 0x0e,
68 PROC_2 = 0x0f,
69 MACSEC_INGR = 0x38,
70 MACSEC_EGR = 0x3c,
71};
72
73struct macsec_flow {
74 struct list_head list;
75 enum mscc_macsec_destination_ports port;
76 enum macsec_bank bank;
77 u32 index;
78 int assoc_num;
79 bool has_transformation;
80
81 /* Highest takes precedence [0..15] */
82 u8 priority;
83
84 union {
85 struct macsec_rx_sa *rx_sa;
86 struct macsec_tx_sa *tx_sa;
87 };
88
89 /* Matching */
90 struct {
91 u8 sci:1;
92 u8 tagged:1;
93 u8 untagged:1;
94 u8 etype:1;
95 } match;
96
97 u16 etype;
98
99 /* Action */
100 struct {
101 u8 bypass:1;
102 u8 drop:1;
103 } action;
104};
105
106#define MSCC_EXT_PAGE_MACSEC_17 17
107#define MSCC_EXT_PAGE_MACSEC_18 18
108
109#define MSCC_EXT_PAGE_MACSEC_19 19
110#define MSCC_PHY_MACSEC_19_REG_ADDR(x) (x)
111#define MSCC_PHY_MACSEC_19_TARGET(x) ((x) << 12)
112#define MSCC_PHY_MACSEC_19_READ BIT(14)
113#define MSCC_PHY_MACSEC_19_CMD BIT(15)
114
115#define MSCC_EXT_PAGE_MACSEC_20 20
116#define MSCC_PHY_MACSEC_20_TARGET(x) (x)
117
118#define MSCC_MS_XFORM_REC(x, y) (((x) << 5) + (y))
119#define MSCC_MS_ENA_CFG 0x800
120#define MSCC_MS_FC_CFG 0x804
121#define MSCC_MS_SAM_MAC_SA_MATCH_LO(x) (0x1000 + ((x) << 4))
122#define MSCC_MS_SAM_MAC_SA_MATCH_HI(x) (0x1001 + ((x) << 4))
123#define MSCC_MS_SAM_MISC_MATCH(x) (0x1004 + ((x) << 4))
124#define MSCC_MS_SAM_MATCH_SCI_LO(x) (0x1005 + ((x) << 4))
125#define MSCC_MS_SAM_MATCH_SCI_HI(x) (0x1006 + ((x) << 4))
126#define MSCC_MS_SAM_MASK(x) (0x1007 + ((x) << 4))
127#define MSCC_MS_SAM_ENTRY_SET1 0x1808
128#define MSCC_MS_SAM_ENTRY_CLEAR1 0x180c
129#define MSCC_MS_SAM_FLOW_CTRL(x) (0x1c00 + (x))
130#define MSCC_MS_SAM_CP_TAG 0x1e40
131#define MSCC_MS_SAM_NM_FLOW_NCP 0x1e51
132#define MSCC_MS_SAM_NM_FLOW_CP 0x1e52
133#define MSCC_MS_MISC_CONTROL 0x1e5f
134#define MSCC_MS_COUNT_CONTROL 0x3204
135#define MSCC_MS_PARAMS2_IG_CC_CONTROL 0x3a10
136#define MSCC_MS_PARAMS2_IG_CP_TAG 0x3a14
137#define MSCC_MS_VLAN_MTU_CHECK(x) (0x3c40 + (x))
138#define MSCC_MS_NON_VLAN_MTU_CHECK 0x3c48
139#define MSCC_MS_PP_CTRL 0x3c4b
140#define MSCC_MS_STATUS_CONTEXT_CTRL 0x3d02
141#define MSCC_MS_INTR_CTRL_STATUS 0x3d04
142#define MSCC_MS_BLOCK_CTX_UPDATE 0x3d0c
143#define MSCC_MS_AIC_CTRL 0x3e02
144
145/* MACSEC_ENA_CFG */
146#define MSCC_MS_ENA_CFG_CLK_ENA BIT(0)
147#define MSCC_MS_ENA_CFG_SW_RST BIT(1)
148#define MSCC_MS_ENA_CFG_MACSEC_BYPASS_ENA BIT(8)
149#define MSCC_MS_ENA_CFG_MACSEC_ENA BIT(9)
150#define MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE(x) ((x) << 10)
151#define MSCC_MS_ENA_CFG_MACSEC_SPEED_MODE_M GENMASK(12, 10)
152
153/* MACSEC_FC_CFG */
154#define MSCC_MS_FC_CFG_FCBUF_ENA BIT(0)
155#define MSCC_MS_FC_CFG_USE_PKT_EXPANSION_INDICATION BIT(1)
156#define MSCC_MS_FC_CFG_LOW_THRESH(x) ((x) << 4)
157#define MSCC_MS_FC_CFG_LOW_THRESH_M GENMASK(7, 4)
158#define MSCC_MS_FC_CFG_HIGH_THRESH(x) ((x) << 8)
159#define MSCC_MS_FC_CFG_HIGH_THRESH_M GENMASK(11, 8)
160#define MSCC_MS_FC_CFG_LOW_BYTES_VAL(x) ((x) << 12)
161#define MSCC_MS_FC_CFG_LOW_BYTES_VAL_M GENMASK(14, 12)
162#define MSCC_MS_FC_CFG_HIGH_BYTES_VAL(x) ((x) << 16)
163#define MSCC_MS_FC_CFG_HIGH_BYTES_VAL_M GENMASK(18, 16)
164
165/* MSCC_MS_SAM_MAC_SA_MATCH_HI */
166#define MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE(x) ((x) << 16)
167#define MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE_M GENMASK(31, 16)
168
169/* MACSEC_SAM_MISC_MATCH */
170#define MSCC_MS_SAM_MISC_MATCH_VLAN_VALID BIT(0)
171#define MSCC_MS_SAM_MISC_MATCH_QINQ_FOUND BIT(1)
172#define MSCC_MS_SAM_MISC_MATCH_STAG_VALID BIT(2)
173#define MSCC_MS_SAM_MISC_MATCH_QTAG_VALID BIT(3)
174#define MSCC_MS_SAM_MISC_MATCH_VLAN_UP(x) ((x) << 4)
175#define MSCC_MS_SAM_MISC_MATCH_VLAN_UP_M GENMASK(6, 4)
176#define MSCC_MS_SAM_MISC_MATCH_CONTROL_PACKET BIT(7)
177#define MSCC_MS_SAM_MISC_MATCH_UNTAGGED BIT(8)
178#define MSCC_MS_SAM_MISC_MATCH_TAGGED BIT(9)
179#define MSCC_MS_SAM_MISC_MATCH_BAD_TAG BIT(10)
180#define MSCC_MS_SAM_MISC_MATCH_KAY_TAG BIT(11)
181#define MSCC_MS_SAM_MISC_MATCH_SOURCE_PORT(x) ((x) << 12)
182#define MSCC_MS_SAM_MISC_MATCH_SOURCE_PORT_M GENMASK(13, 12)
183#define MSCC_MS_SAM_MISC_MATCH_PRIORITY(x) ((x) << 16)
184#define MSCC_MS_SAM_MISC_MATCH_PRIORITY_M GENMASK(19, 16)
185#define MSCC_MS_SAM_MISC_MATCH_AN(x) ((x) << 24)
186#define MSCC_MS_SAM_MISC_MATCH_TCI(x) ((x) << 26)
187
188/* MACSEC_SAM_MASK */
189#define MSCC_MS_SAM_MASK_MAC_SA_MASK(x) (x)
190#define MSCC_MS_SAM_MASK_MAC_SA_MASK_M GENMASK(5, 0)
191#define MSCC_MS_SAM_MASK_MAC_DA_MASK(x) ((x) << 6)
192#define MSCC_MS_SAM_MASK_MAC_DA_MASK_M GENMASK(11, 6)
193#define MSCC_MS_SAM_MASK_MAC_ETYPE_MASK BIT(12)
194#define MSCC_MS_SAM_MASK_VLAN_VLD_MASK BIT(13)
195#define MSCC_MS_SAM_MASK_QINQ_FOUND_MASK BIT(14)
196#define MSCC_MS_SAM_MASK_STAG_VLD_MASK BIT(15)
197#define MSCC_MS_SAM_MASK_QTAG_VLD_MASK BIT(16)
198#define MSCC_MS_SAM_MASK_VLAN_UP_MASK BIT(17)
199#define MSCC_MS_SAM_MASK_VLAN_ID_MASK BIT(18)
200#define MSCC_MS_SAM_MASK_SOURCE_PORT_MASK BIT(19)
201#define MSCC_MS_SAM_MASK_CTL_PACKET_MASK BIT(20)
202#define MSCC_MS_SAM_MASK_VLAN_UP_INNER_MASK BIT(21)
203#define MSCC_MS_SAM_MASK_VLAN_ID_INNER_MASK BIT(22)
204#define MSCC_MS_SAM_MASK_SCI_MASK BIT(23)
205#define MSCC_MS_SAM_MASK_AN_MASK(x) ((x) << 24)
206#define MSCC_MS_SAM_MASK_TCI_MASK(x) ((x) << 26)
207
208/* MACSEC_SAM_FLOW_CTRL_EGR */
209#define MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE(x) (x)
210#define MSCC_MS_SAM_FLOW_CTRL_FLOW_TYPE_M GENMASK(1, 0)
211#define MSCC_MS_SAM_FLOW_CTRL_DEST_PORT(x) ((x) << 2)
212#define MSCC_MS_SAM_FLOW_CTRL_DEST_PORT_M GENMASK(3, 2)
213#define MSCC_MS_SAM_FLOW_CTRL_RESV_4 BIT(4)
214#define MSCC_MS_SAM_FLOW_CTRL_FLOW_CRYPT_AUTH BIT(5)
215#define MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION(x) ((x) << 6)
216#define MSCC_MS_SAM_FLOW_CTRL_DROP_ACTION_M GENMASK(7, 6)
217#define MSCC_MS_SAM_FLOW_CTRL_RESV_15_TO_8(x) ((x) << 8)
218#define MSCC_MS_SAM_FLOW_CTRL_RESV_15_TO_8_M GENMASK(15, 8)
219#define MSCC_MS_SAM_FLOW_CTRL_PROTECT_FRAME BIT(16)
220#define MSCC_MS_SAM_FLOW_CTRL_REPLAY_PROTECT BIT(16)
221#define MSCC_MS_SAM_FLOW_CTRL_SA_IN_USE BIT(17)
222#define MSCC_MS_SAM_FLOW_CTRL_INCLUDE_SCI BIT(18)
223#define MSCC_MS_SAM_FLOW_CTRL_USE_ES BIT(19)
224#define MSCC_MS_SAM_FLOW_CTRL_USE_SCB BIT(20)
225#define MSCC_MS_SAM_FLOW_CTRL_VALIDATE_FRAMES(x) ((x) << 19)
226#define MSCC_MS_SAM_FLOW_CTRL_TAG_BYPASS_SIZE(x) ((x) << 21)
227#define MSCC_MS_SAM_FLOW_CTRL_TAG_BYPASS_SIZE_M GENMASK(22, 21)
228#define MSCC_MS_SAM_FLOW_CTRL_RESV_23 BIT(23)
229#define MSCC_MS_SAM_FLOW_CTRL_CONFIDENTIALITY_OFFSET(x) ((x) << 24)
230#define MSCC_MS_SAM_FLOW_CTRL_CONFIDENTIALITY_OFFSET_M GENMASK(30, 24)
231#define MSCC_MS_SAM_FLOW_CTRL_CONF_PROTECT BIT(31)
232
233/* MACSEC_SAM_CP_TAG */
234#define MSCC_MS_SAM_CP_TAG_MAP_TBL(x) (x)
235#define MSCC_MS_SAM_CP_TAG_MAP_TBL_M GENMASK(23, 0)
236#define MSCC_MS_SAM_CP_TAG_DEF_UP(x) ((x) << 24)
237#define MSCC_MS_SAM_CP_TAG_DEF_UP_M GENMASK(26, 24)
238#define MSCC_MS_SAM_CP_TAG_STAG_UP_EN BIT(27)
239#define MSCC_MS_SAM_CP_TAG_QTAG_UP_EN BIT(28)
240#define MSCC_MS_SAM_CP_TAG_PARSE_QINQ BIT(29)
241#define MSCC_MS_SAM_CP_TAG_PARSE_STAG BIT(30)
242#define MSCC_MS_SAM_CP_TAG_PARSE_QTAG BIT(31)
243
244/* MACSEC_SAM_NM_FLOW_NCP */
245#define MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_FLOW_TYPE(x) (x)
246#define MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DEST_PORT(x) ((x) << 2)
247#define MSCC_MS_SAM_NM_FLOW_NCP_UNTAGGED_DROP_ACTION(x) ((x) << 6)
248#define MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_FLOW_TYPE(x) ((x) << 8)
249#define MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DEST_PORT(x) ((x) << 10)
250#define MSCC_MS_SAM_NM_FLOW_NCP_TAGGED_DROP_ACTION(x) ((x) << 14)
251#define MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_FLOW_TYPE(x) ((x) << 16)
252#define MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DEST_PORT(x) ((x) << 18)
253#define MSCC_MS_SAM_NM_FLOW_NCP_BADTAG_DROP_ACTION(x) ((x) << 22)
254#define MSCC_MS_SAM_NM_FLOW_NCP_KAY_FLOW_TYPE(x) ((x) << 24)
255#define MSCC_MS_SAM_NM_FLOW_NCP_KAY_DEST_PORT(x) ((x) << 26)
256#define MSCC_MS_SAM_NM_FLOW_NCP_KAY_DROP_ACTION(x) ((x) << 30)
257
258/* MACSEC_SAM_NM_FLOW_CP */
259#define MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_FLOW_TYPE(x) (x)
260#define MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DEST_PORT(x) ((x) << 2)
261#define MSCC_MS_SAM_NM_FLOW_CP_UNTAGGED_DROP_ACTION(x) ((x) << 6)
262#define MSCC_MS_SAM_NM_FLOW_CP_TAGGED_FLOW_TYPE(x) ((x) << 8)
263#define MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DEST_PORT(x) ((x) << 10)
264#define MSCC_MS_SAM_NM_FLOW_CP_TAGGED_DROP_ACTION(x) ((x) << 14)
265#define MSCC_MS_SAM_NM_FLOW_CP_BADTAG_FLOW_TYPE(x) ((x) << 16)
266#define MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DEST_PORT(x) ((x) << 18)
267#define MSCC_MS_SAM_NM_FLOW_CP_BADTAG_DROP_ACTION(x) ((x) << 22)
268#define MSCC_MS_SAM_NM_FLOW_CP_KAY_FLOW_TYPE(x) ((x) << 24)
269#define MSCC_MS_SAM_NM_FLOW_CP_KAY_DEST_PORT(x) ((x) << 26)
270#define MSCC_MS_SAM_NM_FLOW_CP_KAY_DROP_ACTION(x) ((x) << 30)
271
272/* MACSEC_MISC_CONTROL */
273#define MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX(x) (x)
274#define MSCC_MS_MISC_CONTROL_MC_LATENCY_FIX_M GENMASK(5, 0)
275#define MSCC_MS_MISC_CONTROL_STATIC_BYPASS BIT(8)
276#define MSCC_MS_MISC_CONTROL_NM_MACSEC_EN BIT(9)
277#define MSCC_MS_MISC_CONTROL_VALIDATE_FRAMES(x) ((x) << 10)
278#define MSCC_MS_MISC_CONTROL_VALIDATE_FRAMES_M GENMASK(11, 10)
279#define MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE(x) ((x) << 24)
280#define MSCC_MS_MISC_CONTROL_XFORM_REC_SIZE_M GENMASK(25, 24)
281
282/* MACSEC_COUNT_CONTROL */
283#define MSCC_MS_COUNT_CONTROL_RESET_ALL BIT(0)
284#define MSCC_MS_COUNT_CONTROL_DEBUG_ACCESS BIT(1)
285#define MSCC_MS_COUNT_CONTROL_SATURATE_CNTRS BIT(2)
286#define MSCC_MS_COUNT_CONTROL_AUTO_CNTR_RESET BIT(3)
287
288/* MACSEC_PARAMS2_IG_CC_CONTROL */
289#define MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_CTRL_ACT BIT(14)
290#define MSCC_MS_PARAMS2_IG_CC_CONTROL_NON_MATCH_ACT BIT(15)
291
292/* MACSEC_PARAMS2_IG_CP_TAG */
293#define MSCC_MS_PARAMS2_IG_CP_TAG_MAP_TBL(x) (x)
294#define MSCC_MS_PARAMS2_IG_CP_TAG_MAP_TBL_M GENMASK(23, 0)
295#define MSCC_MS_PARAMS2_IG_CP_TAG_DEF_UP(x) ((x) << 24)
296#define MSCC_MS_PARAMS2_IG_CP_TAG_DEF_UP_M GENMASK(26, 24)
297#define MSCC_MS_PARAMS2_IG_CP_TAG_STAG_UP_EN BIT(27)
298#define MSCC_MS_PARAMS2_IG_CP_TAG_QTAG_UP_EN BIT(28)
299#define MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QINQ BIT(29)
300#define MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_STAG BIT(30)
301#define MSCC_MS_PARAMS2_IG_CP_TAG_PARSE_QTAG BIT(31)
302
303/* MACSEC_VLAN_MTU_CHECK */
304#define MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE(x) (x)
305#define MSCC_MS_VLAN_MTU_CHECK_MTU_COMPARE_M GENMASK(14, 0)
306#define MSCC_MS_VLAN_MTU_CHECK_MTU_COMP_DROP BIT(15)
307
308/* MACSEC_NON_VLAN_MTU_CHECK */
309#define MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE(x) (x)
310#define MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMPARE_M GENMASK(14, 0)
311#define MSCC_MS_NON_VLAN_MTU_CHECK_NV_MTU_COMP_DROP BIT(15)
312
313/* MACSEC_PP_CTRL */
314#define MSCC_MS_PP_CTRL_MACSEC_OCTET_INCR_MODE BIT(0)
315
316/* MACSEC_INTR_CTRL_STATUS */
317#define MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS(x) (x)
318#define MSCC_MS_INTR_CTRL_STATUS_INTR_CLR_STATUS_M GENMASK(15, 0)
319#define MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE(x) ((x) << 16)
320#define MSCC_MS_INTR_CTRL_STATUS_INTR_ENABLE_M GENMASK(31, 16)
321#define MACSEC_INTR_CTRL_STATUS_ROLLOVER BIT(5)
322
323#endif /* _MSCC_PHY_MACSEC_H_ */
324

source code of linux/drivers/net/phy/mscc/mscc_macsec.h