| 1 | /* SPDX-License-Identifier: ISC */ |
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| 2 | /* Copyright (C) 2023 MediaTek Inc. */ |
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| 3 | |
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| 4 | #ifndef __MT7925_REGS_H |
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| 5 | #define __MT7925_REGS_H |
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| 6 | |
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| 7 | #include "../mt792x_regs.h" |
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| 8 | |
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| 9 | #define MT_MDP_BASE 0x820cc800 |
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| 10 | #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) |
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| 11 | |
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| 12 | #define MT_MDP_DCR0 MT_MDP(0x000) |
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| 13 | #define MT_MDP_DCR0_DAMSDU_EN BIT(15) |
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| 14 | #define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19) |
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| 15 | |
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| 16 | #define MT_MDP_DCR1 MT_MDP(0x004) |
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| 17 | #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3) |
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| 18 | |
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| 19 | #define MT_MDP_BNRCFR0(_band) MT_MDP(0x090 + ((_band) << 8)) |
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| 20 | #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4) |
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| 21 | #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6) |
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| 22 | #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8) |
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| 23 | |
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| 24 | #define MT_MDP_BNRCFR1(_band) MT_MDP(0x094 + ((_band) << 8)) |
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| 25 | #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22) |
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| 26 | #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27) |
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| 27 | #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29) |
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| 28 | #define MT_MDP_TO_HIF 0 |
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| 29 | #define MT_MDP_TO_WM 1 |
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| 30 | |
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| 31 | #define MT_WFDMA0_HOST_INT_ENA MT_WFDMA0(0x204) |
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| 32 | #define MT_WFDMA0_HOST_INT_DIS MT_WFDMA0(0x22c) |
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| 33 | #define HOST_RX_DONE_INT_ENA4 BIT(12) |
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| 34 | #define HOST_RX_DONE_INT_ENA5 BIT(13) |
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| 35 | #define HOST_RX_DONE_INT_ENA6 BIT(14) |
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| 36 | #define HOST_RX_DONE_INT_ENA7 BIT(15) |
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| 37 | #define HOST_RX_DONE_INT_ENA8 BIT(16) |
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| 38 | #define HOST_RX_DONE_INT_ENA9 BIT(17) |
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| 39 | #define HOST_RX_DONE_INT_ENA10 BIT(18) |
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| 40 | #define HOST_RX_DONE_INT_ENA11 BIT(19) |
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| 41 | #define HOST_TX_DONE_INT_ENA15 BIT(25) |
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| 42 | #define HOST_TX_DONE_INT_ENA16 BIT(26) |
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| 43 | #define HOST_TX_DONE_INT_ENA17 BIT(27) |
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| 44 | |
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| 45 | /* WFDMA interrupt */ |
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| 46 | #define MT_INT_RX_DONE_DATA HOST_RX_DONE_INT_ENA2 |
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| 47 | #define MT_INT_RX_DONE_WM HOST_RX_DONE_INT_ENA0 |
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| 48 | #define MT_INT_RX_DONE_WM2 HOST_RX_DONE_INT_ENA1 |
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| 49 | #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_DATA | \ |
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| 50 | MT_INT_RX_DONE_WM | \ |
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| 51 | MT_INT_RX_DONE_WM2) |
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| 52 | |
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| 53 | #define MT_INT_TX_DONE_MCU_WM (HOST_TX_DONE_INT_ENA15 | \ |
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| 54 | HOST_TX_DONE_INT_ENA17) |
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| 55 | |
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| 56 | #define MT_INT_TX_DONE_FWDL HOST_TX_DONE_INT_ENA16 |
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| 57 | #define MT_INT_TX_DONE_BAND0 HOST_TX_DONE_INT_ENA0 |
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| 58 | |
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| 59 | #define MT_INT_TX_DONE_MCU (MT_INT_TX_DONE_MCU_WM | \ |
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| 60 | MT_INT_TX_DONE_FWDL) |
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| 61 | #define MT_INT_TX_DONE_ALL (MT_INT_TX_DONE_MCU_WM | \ |
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| 62 | MT_INT_TX_DONE_BAND0 | \ |
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| 63 | GENMASK(18, 4)) |
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| 64 | |
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| 65 | #define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500) |
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| 66 | |
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| 67 | #define MT_INFRA_CFG_BASE 0xd1000 |
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| 68 | #define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs)) |
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| 69 | |
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| 70 | #define MT_HIF_REMAP_L1 0x155024 |
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| 71 | #define MT_HIF_REMAP_L1_MASK GENMASK(31, 16) |
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| 72 | #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) |
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| 73 | #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) |
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| 74 | #define MT_HIF_REMAP_BASE_L1 0x130000 |
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| 75 | |
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| 76 | #define MT_HIF_REMAP_L2 0x0120 |
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| 77 | #if IS_ENABLED(CONFIG_MT76_DEV) |
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| 78 | #define MT_HIF_REMAP_BASE_L2 (0x7c500000 - (0x7c000000 - 0x18000000)) |
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| 79 | #else |
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| 80 | #define MT_HIF_REMAP_BASE_L2 0x18500000 |
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| 81 | #endif |
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| 82 | |
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| 83 | #define MT_WFSYS_SW_RST_B 0x7c000140 |
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| 84 | |
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| 85 | #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x370) |
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| 86 | #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0) |
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| 87 | |
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| 88 | #define MT_WTBL_UPDATE MT_WTBLON_TOP(0x380) |
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| 89 | #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0) |
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| 90 | #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(14) |
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| 91 | |
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| 92 | #endif |
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| 93 | |
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