1/* SPDX-License-Identifier: GPL-2.0-only
2 *
3 * Copyright (c) 2021, MediaTek Inc.
4 * Copyright (c) 2021-2022, Intel Corporation.
5 *
6 * Authors:
7 * Haijun Liu <haijun.liu@mediatek.com>
8 * Moises Veleta <moises.veleta@intel.com>
9 * Ricardo Martinez <ricardo.martinez@linux.intel.com>
10 *
11 * Contributors:
12 * Amir Hanania <amir.hanania@intel.com>
13 * Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 * Sreehari Kancharla <sreehari.kancharla@intel.com>
15 */
16
17#ifndef __T7XX_CLDMA_H__
18#define __T7XX_CLDMA_H__
19
20#include <linux/bits.h>
21#include <linux/types.h>
22
23#define CLDMA_TXQ_NUM 8
24#define CLDMA_RXQ_NUM 8
25#define CLDMA_ALL_Q GENMASK(7, 0)
26
27/* Interrupt status bits */
28#define EMPTY_STATUS_BITMASK GENMASK(15, 8)
29#define TXRX_STATUS_BITMASK GENMASK(7, 0)
30#define EQ_STA_BIT_OFFSET 8
31#define L2_INT_BIT_COUNT 16
32#define EQ_STA_BIT(index) (BIT((index) + EQ_STA_BIT_OFFSET) & EMPTY_STATUS_BITMASK)
33
34#define TQ_ERR_INT_BITMASK GENMASK(23, 16)
35#define TQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24)
36
37#define RQ_ERR_INT_BITMASK GENMASK(23, 16)
38#define RQ_ACTIVE_START_ERR_INT_BITMASK GENMASK(31, 24)
39
40#define CLDMA0_AO_BASE 0x10049000
41#define CLDMA0_PD_BASE 0x1021d000
42#define CLDMA1_AO_BASE 0x1004b000
43#define CLDMA1_PD_BASE 0x1021f000
44
45#define CLDMA_R_AO_BASE 0x10023000
46#define CLDMA_R_PD_BASE 0x1023d000
47
48/* CLDMA TX */
49#define REG_CLDMA_UL_START_ADDRL_0 0x0004
50#define REG_CLDMA_UL_START_ADDRH_0 0x0008
51#define REG_CLDMA_UL_CURRENT_ADDRL_0 0x0044
52#define REG_CLDMA_UL_CURRENT_ADDRH_0 0x0048
53#define REG_CLDMA_UL_STATUS 0x0084
54#define REG_CLDMA_UL_START_CMD 0x0088
55#define REG_CLDMA_UL_RESUME_CMD 0x008c
56#define REG_CLDMA_UL_STOP_CMD 0x0090
57#define REG_CLDMA_UL_ERROR 0x0094
58#define REG_CLDMA_UL_CFG 0x0098
59#define UL_CFG_BIT_MODE_36 BIT(5)
60#define UL_CFG_BIT_MODE_40 BIT(6)
61#define UL_CFG_BIT_MODE_64 BIT(7)
62#define UL_CFG_BIT_MODE_MASK GENMASK(7, 5)
63
64#define REG_CLDMA_UL_MEM 0x009c
65#define UL_MEM_CHECK_DIS BIT(0)
66
67/* CLDMA RX */
68#define REG_CLDMA_DL_START_CMD 0x05bc
69#define REG_CLDMA_DL_RESUME_CMD 0x05c0
70#define REG_CLDMA_DL_STOP_CMD 0x05c4
71#define REG_CLDMA_DL_MEM 0x0508
72#define DL_MEM_CHECK_DIS BIT(0)
73
74#define REG_CLDMA_DL_CFG 0x0404
75#define DL_CFG_UP_HW_LAST BIT(2)
76#define DL_CFG_BIT_MODE_36 BIT(10)
77#define DL_CFG_BIT_MODE_40 BIT(11)
78#define DL_CFG_BIT_MODE_64 BIT(12)
79#define DL_CFG_BIT_MODE_MASK GENMASK(12, 10)
80
81#define REG_CLDMA_DL_START_ADDRL_0 0x0478
82#define REG_CLDMA_DL_START_ADDRH_0 0x047c
83#define REG_CLDMA_DL_CURRENT_ADDRL_0 0x04b8
84#define REG_CLDMA_DL_CURRENT_ADDRH_0 0x04bc
85#define REG_CLDMA_DL_STATUS 0x04f8
86
87/* CLDMA MISC */
88#define REG_CLDMA_L2TISAR0 0x0810
89#define REG_CLDMA_L2TISAR1 0x0814
90#define REG_CLDMA_L2TIMR0 0x0818
91#define REG_CLDMA_L2TIMR1 0x081c
92#define REG_CLDMA_L2TIMCR0 0x0820
93#define REG_CLDMA_L2TIMCR1 0x0824
94#define REG_CLDMA_L2TIMSR0 0x0828
95#define REG_CLDMA_L2TIMSR1 0x082c
96#define REG_CLDMA_L3TISAR0 0x0830
97#define REG_CLDMA_L3TISAR1 0x0834
98#define REG_CLDMA_L2RISAR0 0x0850
99#define REG_CLDMA_L2RISAR1 0x0854
100#define REG_CLDMA_L3RISAR0 0x0870
101#define REG_CLDMA_L3RISAR1 0x0874
102#define REG_CLDMA_IP_BUSY 0x08b4
103#define IP_BUSY_WAKEUP BIT(0)
104#define CLDMA_L2TISAR0_ALL_INT_MASK GENMASK(15, 0)
105#define CLDMA_L2RISAR0_ALL_INT_MASK GENMASK(15, 0)
106
107/* CLDMA MISC */
108#define REG_CLDMA_L2RIMR0 0x0858
109#define REG_CLDMA_L2RIMR1 0x085c
110#define REG_CLDMA_L2RIMCR0 0x0860
111#define REG_CLDMA_L2RIMCR1 0x0864
112#define REG_CLDMA_L2RIMSR0 0x0868
113#define REG_CLDMA_L2RIMSR1 0x086c
114#define REG_CLDMA_BUSY_MASK 0x0954
115#define BUSY_MASK_PCIE BIT(0)
116#define BUSY_MASK_AP BIT(1)
117#define BUSY_MASK_MD BIT(2)
118
119#define REG_CLDMA_INT_MASK 0x0960
120
121/* CLDMA RESET */
122#define REG_INFRA_RST4_SET 0x0730
123#define RST4_CLDMA1_SW_RST_SET BIT(20)
124
125#define REG_INFRA_RST4_CLR 0x0734
126#define RST4_CLDMA1_SW_RST_CLR BIT(20)
127
128#define REG_INFRA_RST2_SET 0x0140
129#define RST2_PMIC_SW_RST_SET BIT(18)
130
131#define REG_INFRA_RST2_CLR 0x0144
132#define RST2_PMIC_SW_RST_CLR BIT(18)
133
134enum mtk_txrx {
135 MTK_TX,
136 MTK_RX,
137};
138
139enum t7xx_hw_mode {
140 MODE_BIT_32,
141 MODE_BIT_36,
142 MODE_BIT_40,
143 MODE_BIT_64,
144};
145
146struct t7xx_cldma_hw {
147 enum t7xx_hw_mode hw_mode;
148 void __iomem *ap_ao_base;
149 void __iomem *ap_pdn_base;
150 u32 phy_interrupt_id;
151};
152
153void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
154 enum mtk_txrx tx_rx);
155void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno,
156 enum mtk_txrx tx_rx);
157void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno,
158 enum mtk_txrx tx_rx);
159void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx);
160unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno,
161 enum mtk_txrx tx_rx);
162void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info);
163void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
164 enum mtk_txrx tx_rx);
165void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info);
166void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
167 enum mtk_txrx tx_rx);
168void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask);
169void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask);
170void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx);
171void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info,
172 unsigned int qno, u64 address, enum mtk_txrx tx_rx);
173void t7xx_cldma_hw_reset(void __iomem *ao_base);
174void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx);
175unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask,
176 enum mtk_txrx tx_rx);
177void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info);
178void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info);
179bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno);
180#endif
181

source code of linux/drivers/net/wwan/t7xx/t7xx_cldma.h