1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* |
3 | * cpcihp_zt5550.h |
4 | * |
5 | * Intel/Ziatech ZT5550 CompactPCI Host Controller driver definitions |
6 | * |
7 | * Copyright 2002 SOMA Networks, Inc. |
8 | * Copyright 2001 Intel San Luis Obispo |
9 | * Copyright 2000,2001 MontaVista Software Inc. |
10 | * |
11 | * Send feedback to <scottm@somanetworks.com> |
12 | */ |
13 | |
14 | #ifndef _CPCIHP_ZT5550_H |
15 | #define _CPCIHP_ZT5550_H |
16 | |
17 | /* Direct registers */ |
18 | #define CSR_HCINDEX 0x00 |
19 | #define CSR_HCDATA 0x04 |
20 | #define CSR_INTSTAT 0x08 |
21 | #define CSR_INTMASK 0x09 |
22 | #define CSR_CNT0CMD 0x0C |
23 | #define CSR_CNT1CMD 0x0E |
24 | #define CSR_CNT0 0x10 |
25 | #define CSR_CNT1 0x14 |
26 | |
27 | /* Masks for interrupt bits in CSR_INTMASK direct register */ |
28 | #define CNT0_INT_MASK 0x01 |
29 | #define CNT1_INT_MASK 0x02 |
30 | #define ENUM_INT_MASK 0x04 |
31 | #define ALL_DIRECT_INTS_MASK 0x07 |
32 | |
33 | /* Indexed registers (through CSR_INDEX, CSR_DATA) */ |
34 | #define HC_INT_MASK_REG 0x04 |
35 | #define HC_STATUS_REG 0x08 |
36 | #define HC_CMD_REG 0x0C |
37 | #define ARB_CONFIG_GNT_REG 0x10 |
38 | #define ARB_CONFIG_CFG_REG 0x12 |
39 | #define ARB_CONFIG_REG 0x10 |
40 | #define ISOL_CONFIG_REG 0x18 |
41 | #define FAULT_STATUS_REG 0x20 |
42 | #define FAULT_CONFIG_REG 0x24 |
43 | #define WD_CONFIG_REG 0x2C |
44 | #define HC_DIAG_REG 0x30 |
45 | #define SERIAL_COMM_REG 0x34 |
46 | #define SERIAL_OUT_REG 0x38 |
47 | #define SERIAL_IN_REG 0x3C |
48 | |
49 | /* Masks for interrupt bits in HC_INT_MASK_REG indexed register */ |
50 | #define SERIAL_INT_MASK 0x01 |
51 | #define FAULT_INT_MASK 0x02 |
52 | #define HCF_INT_MASK 0x04 |
53 | #define ALL_INDEXED_INTS_MASK 0x07 |
54 | |
55 | /* Digital I/O port storing ENUM# */ |
56 | #define ENUM_PORT 0xE1 |
57 | /* Mask to get to the ENUM# bit on the bus */ |
58 | #define ENUM_MASK 0x40 |
59 | |
60 | #endif /* _CPCIHP_ZT5550_H */ |
61 | |