1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. |
4 | */ |
5 | |
6 | #include <linux/pci.h> |
7 | #include <linux/of.h> |
8 | #include <linux/of_irq.h> |
9 | #include <linux/bitfield.h> |
10 | #include <linux/bits.h> |
11 | #include "pci.h" |
12 | |
13 | #define OF_PCI_ADDRESS_CELLS 3 |
14 | #define OF_PCI_SIZE_CELLS 2 |
15 | #define OF_PCI_MAX_INT_PIN 4 |
16 | |
17 | struct of_pci_addr_pair { |
18 | u32 phys_addr[OF_PCI_ADDRESS_CELLS]; |
19 | u32 size[OF_PCI_SIZE_CELLS]; |
20 | }; |
21 | |
22 | /* |
23 | * Each entry in the ranges table is a tuple containing the child address, |
24 | * the parent address, and the size of the region in the child address space. |
25 | * Thus, for PCI, in each entry parent address is an address on the primary |
26 | * side and the child address is the corresponding address on the secondary |
27 | * side. |
28 | */ |
29 | struct of_pci_range { |
30 | u32 child_addr[OF_PCI_ADDRESS_CELLS]; |
31 | u32 parent_addr[OF_PCI_ADDRESS_CELLS]; |
32 | u32 size[OF_PCI_SIZE_CELLS]; |
33 | }; |
34 | |
35 | #define OF_PCI_ADDR_SPACE_IO 0x1 |
36 | #define OF_PCI_ADDR_SPACE_MEM32 0x2 |
37 | #define OF_PCI_ADDR_SPACE_MEM64 0x3 |
38 | |
39 | #define OF_PCI_ADDR_FIELD_NONRELOC BIT(31) |
40 | #define OF_PCI_ADDR_FIELD_SS GENMASK(25, 24) |
41 | #define OF_PCI_ADDR_FIELD_PREFETCH BIT(30) |
42 | #define OF_PCI_ADDR_FIELD_BUS GENMASK(23, 16) |
43 | #define OF_PCI_ADDR_FIELD_DEV GENMASK(15, 11) |
44 | #define OF_PCI_ADDR_FIELD_FUNC GENMASK(10, 8) |
45 | #define OF_PCI_ADDR_FIELD_REG GENMASK(7, 0) |
46 | |
47 | enum of_pci_prop_compatible { |
48 | PROP_COMPAT_PCI_VVVV_DDDD, |
49 | PROP_COMPAT_PCICLASS_CCSSPP, |
50 | PROP_COMPAT_PCICLASS_CCSS, |
51 | PROP_COMPAT_NUM, |
52 | }; |
53 | |
54 | static void of_pci_set_address(struct pci_dev *pdev, u32 *prop, u64 addr, |
55 | u32 reg_num, u32 flags, bool reloc) |
56 | { |
57 | prop[0] = FIELD_PREP(OF_PCI_ADDR_FIELD_BUS, pdev->bus->number) | |
58 | FIELD_PREP(OF_PCI_ADDR_FIELD_DEV, PCI_SLOT(pdev->devfn)) | |
59 | FIELD_PREP(OF_PCI_ADDR_FIELD_FUNC, PCI_FUNC(pdev->devfn)); |
60 | prop[0] |= flags | reg_num; |
61 | if (!reloc) { |
62 | prop[0] |= OF_PCI_ADDR_FIELD_NONRELOC; |
63 | prop[1] = upper_32_bits(addr); |
64 | prop[2] = lower_32_bits(addr); |
65 | } |
66 | } |
67 | |
68 | static int of_pci_get_addr_flags(struct resource *res, u32 *flags) |
69 | { |
70 | u32 ss; |
71 | |
72 | if (res->flags & IORESOURCE_IO) |
73 | ss = OF_PCI_ADDR_SPACE_IO; |
74 | else if (res->flags & IORESOURCE_MEM_64) |
75 | ss = OF_PCI_ADDR_SPACE_MEM64; |
76 | else if (res->flags & IORESOURCE_MEM) |
77 | ss = OF_PCI_ADDR_SPACE_MEM32; |
78 | else |
79 | return -EINVAL; |
80 | |
81 | *flags = 0; |
82 | if (res->flags & IORESOURCE_PREFETCH) |
83 | *flags |= OF_PCI_ADDR_FIELD_PREFETCH; |
84 | |
85 | *flags |= FIELD_PREP(OF_PCI_ADDR_FIELD_SS, ss); |
86 | |
87 | return 0; |
88 | } |
89 | |
90 | static int of_pci_prop_bus_range(struct pci_dev *pdev, |
91 | struct of_changeset *ocs, |
92 | struct device_node *np) |
93 | { |
94 | u32 bus_range[] = { pdev->subordinate->busn_res.start, |
95 | pdev->subordinate->busn_res.end }; |
96 | |
97 | return of_changeset_add_prop_u32_array(ocs, np, prop_name: "bus-range" , array: bus_range, |
98 | ARRAY_SIZE(bus_range)); |
99 | } |
100 | |
101 | static int of_pci_prop_ranges(struct pci_dev *pdev, struct of_changeset *ocs, |
102 | struct device_node *np) |
103 | { |
104 | struct of_pci_range *rp; |
105 | struct resource *res; |
106 | int i, j, ret; |
107 | u32 flags, num; |
108 | u64 val64; |
109 | |
110 | if (pci_is_bridge(dev: pdev)) { |
111 | num = PCI_BRIDGE_RESOURCE_NUM; |
112 | res = &pdev->resource[PCI_BRIDGE_RESOURCES]; |
113 | } else { |
114 | num = PCI_STD_NUM_BARS; |
115 | res = &pdev->resource[PCI_STD_RESOURCES]; |
116 | } |
117 | |
118 | rp = kcalloc(n: num, size: sizeof(*rp), GFP_KERNEL); |
119 | if (!rp) |
120 | return -ENOMEM; |
121 | |
122 | for (i = 0, j = 0; j < num; j++) { |
123 | if (!resource_size(res: &res[j])) |
124 | continue; |
125 | |
126 | if (of_pci_get_addr_flags(res: &res[j], flags: &flags)) |
127 | continue; |
128 | |
129 | val64 = res[j].start; |
130 | of_pci_set_address(pdev, prop: rp[i].parent_addr, addr: val64, reg_num: 0, flags, |
131 | reloc: false); |
132 | if (pci_is_bridge(dev: pdev)) { |
133 | memcpy(rp[i].child_addr, rp[i].parent_addr, |
134 | sizeof(rp[i].child_addr)); |
135 | } else { |
136 | /* |
137 | * For endpoint device, the lower 64-bits of child |
138 | * address is always zero. |
139 | */ |
140 | rp[i].child_addr[0] = j; |
141 | } |
142 | |
143 | val64 = resource_size(res: &res[j]); |
144 | rp[i].size[0] = upper_32_bits(val64); |
145 | rp[i].size[1] = lower_32_bits(val64); |
146 | |
147 | i++; |
148 | } |
149 | |
150 | ret = of_changeset_add_prop_u32_array(ocs, np, prop_name: "ranges" , array: (u32 *)rp, |
151 | sz: i * sizeof(*rp) / sizeof(u32)); |
152 | kfree(objp: rp); |
153 | |
154 | return ret; |
155 | } |
156 | |
157 | static int of_pci_prop_reg(struct pci_dev *pdev, struct of_changeset *ocs, |
158 | struct device_node *np) |
159 | { |
160 | struct of_pci_addr_pair reg = { 0 }; |
161 | |
162 | /* configuration space */ |
163 | of_pci_set_address(pdev, prop: reg.phys_addr, addr: 0, reg_num: 0, flags: 0, reloc: true); |
164 | |
165 | return of_changeset_add_prop_u32_array(ocs, np, prop_name: "reg" , array: (u32 *)®, |
166 | sz: sizeof(reg) / sizeof(u32)); |
167 | } |
168 | |
169 | static int of_pci_prop_interrupts(struct pci_dev *pdev, |
170 | struct of_changeset *ocs, |
171 | struct device_node *np) |
172 | { |
173 | int ret; |
174 | u8 pin; |
175 | |
176 | ret = pci_read_config_byte(dev: pdev, PCI_INTERRUPT_PIN, val: &pin); |
177 | if (ret != 0) |
178 | return ret; |
179 | |
180 | if (!pin) |
181 | return 0; |
182 | |
183 | return of_changeset_add_prop_u32(ocs, np, prop_name: "interrupts" , val: (u32)pin); |
184 | } |
185 | |
186 | static int of_pci_prop_intr_map(struct pci_dev *pdev, struct of_changeset *ocs, |
187 | struct device_node *np) |
188 | { |
189 | u32 i, addr_sz[OF_PCI_MAX_INT_PIN] = { 0 }, map_sz = 0; |
190 | struct of_phandle_args out_irq[OF_PCI_MAX_INT_PIN]; |
191 | __be32 laddr[OF_PCI_ADDRESS_CELLS] = { 0 }; |
192 | u32 int_map_mask[] = { 0xffff00, 0, 0, 7 }; |
193 | struct device_node *pnode; |
194 | struct pci_dev *child; |
195 | u32 *int_map, *mapp; |
196 | int ret; |
197 | u8 pin; |
198 | |
199 | pnode = pci_device_to_OF_node(pdev: pdev->bus->self); |
200 | if (!pnode) |
201 | pnode = pci_bus_to_OF_node(bus: pdev->bus); |
202 | |
203 | if (!pnode) { |
204 | pci_err(pdev, "failed to get parent device node" ); |
205 | return -EINVAL; |
206 | } |
207 | |
208 | laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8)); |
209 | for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) { |
210 | i = pin - 1; |
211 | out_irq[i].np = pnode; |
212 | out_irq[i].args_count = 1; |
213 | out_irq[i].args[0] = pin; |
214 | ret = of_irq_parse_raw(addr: laddr, out_irq: &out_irq[i]); |
215 | if (ret) { |
216 | out_irq[i].np = NULL; |
217 | pci_dbg(pdev, "parse irq %d failed, ret %d" , pin, ret); |
218 | continue; |
219 | } |
220 | of_property_read_u32(np: out_irq[i].np, propname: "#address-cells" , |
221 | out_value: &addr_sz[i]); |
222 | } |
223 | |
224 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { |
225 | for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) { |
226 | i = pci_swizzle_interrupt_pin(dev: child, pin) - 1; |
227 | if (!out_irq[i].np) |
228 | continue; |
229 | map_sz += 5 + addr_sz[i] + out_irq[i].args_count; |
230 | } |
231 | } |
232 | |
233 | /* |
234 | * Parsing interrupt failed for all pins. In this case, it does not |
235 | * need to generate interrupt-map property. |
236 | */ |
237 | if (!map_sz) |
238 | return 0; |
239 | |
240 | int_map = kcalloc(n: map_sz, size: sizeof(u32), GFP_KERNEL); |
241 | mapp = int_map; |
242 | |
243 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { |
244 | for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) { |
245 | i = pci_swizzle_interrupt_pin(dev: child, pin) - 1; |
246 | if (!out_irq[i].np) |
247 | continue; |
248 | |
249 | *mapp = (child->bus->number << 16) | |
250 | (child->devfn << 8); |
251 | mapp += OF_PCI_ADDRESS_CELLS; |
252 | *mapp = pin; |
253 | mapp++; |
254 | *mapp = out_irq[i].np->phandle; |
255 | mapp++; |
256 | if (addr_sz[i]) { |
257 | ret = of_property_read_u32_array(np: out_irq[i].np, |
258 | propname: "reg" , out_values: mapp, |
259 | sz: addr_sz[i]); |
260 | if (ret) |
261 | goto failed; |
262 | } |
263 | mapp += addr_sz[i]; |
264 | memcpy(mapp, out_irq[i].args, |
265 | out_irq[i].args_count * sizeof(u32)); |
266 | mapp += out_irq[i].args_count; |
267 | } |
268 | } |
269 | |
270 | ret = of_changeset_add_prop_u32_array(ocs, np, prop_name: "interrupt-map" , array: int_map, |
271 | sz: map_sz); |
272 | if (ret) |
273 | goto failed; |
274 | |
275 | ret = of_changeset_add_prop_u32(ocs, np, prop_name: "#interrupt-cells" , val: 1); |
276 | if (ret) |
277 | goto failed; |
278 | |
279 | ret = of_changeset_add_prop_u32_array(ocs, np, prop_name: "interrupt-map-mask" , |
280 | array: int_map_mask, |
281 | ARRAY_SIZE(int_map_mask)); |
282 | if (ret) |
283 | goto failed; |
284 | |
285 | kfree(objp: int_map); |
286 | return 0; |
287 | |
288 | failed: |
289 | kfree(objp: int_map); |
290 | return ret; |
291 | } |
292 | |
293 | static int of_pci_prop_compatible(struct pci_dev *pdev, |
294 | struct of_changeset *ocs, |
295 | struct device_node *np) |
296 | { |
297 | const char *compat_strs[PROP_COMPAT_NUM] = { 0 }; |
298 | int i, ret; |
299 | |
300 | compat_strs[PROP_COMPAT_PCI_VVVV_DDDD] = |
301 | kasprintf(GFP_KERNEL, fmt: "pci%x,%x" , pdev->vendor, pdev->device); |
302 | compat_strs[PROP_COMPAT_PCICLASS_CCSSPP] = |
303 | kasprintf(GFP_KERNEL, fmt: "pciclass,%06x" , pdev->class); |
304 | compat_strs[PROP_COMPAT_PCICLASS_CCSS] = |
305 | kasprintf(GFP_KERNEL, fmt: "pciclass,%04x" , pdev->class >> 8); |
306 | |
307 | ret = of_changeset_add_prop_string_array(ocs, np, prop_name: "compatible" , |
308 | str_array: compat_strs, sz: PROP_COMPAT_NUM); |
309 | for (i = 0; i < PROP_COMPAT_NUM; i++) |
310 | kfree(objp: compat_strs[i]); |
311 | |
312 | return ret; |
313 | } |
314 | |
315 | int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, |
316 | struct device_node *np) |
317 | { |
318 | int ret; |
319 | |
320 | /* |
321 | * The added properties will be released when the |
322 | * changeset is destroyed. |
323 | */ |
324 | if (pci_is_bridge(dev: pdev)) { |
325 | ret = of_changeset_add_prop_string(ocs, np, prop_name: "device_type" , |
326 | str: "pci" ); |
327 | if (ret) |
328 | return ret; |
329 | |
330 | ret = of_pci_prop_bus_range(pdev, ocs, np); |
331 | if (ret) |
332 | return ret; |
333 | |
334 | ret = of_pci_prop_intr_map(pdev, ocs, np); |
335 | if (ret) |
336 | return ret; |
337 | } |
338 | |
339 | ret = of_pci_prop_ranges(pdev, ocs, np); |
340 | if (ret) |
341 | return ret; |
342 | |
343 | ret = of_changeset_add_prop_u32(ocs, np, prop_name: "#address-cells" , |
344 | OF_PCI_ADDRESS_CELLS); |
345 | if (ret) |
346 | return ret; |
347 | |
348 | ret = of_changeset_add_prop_u32(ocs, np, prop_name: "#size-cells" , |
349 | OF_PCI_SIZE_CELLS); |
350 | if (ret) |
351 | return ret; |
352 | |
353 | ret = of_pci_prop_reg(pdev, ocs, np); |
354 | if (ret) |
355 | return ret; |
356 | |
357 | ret = of_pci_prop_compatible(pdev, ocs, np); |
358 | if (ret) |
359 | return ret; |
360 | |
361 | ret = of_pci_prop_interrupts(pdev, ocs, np); |
362 | if (ret) |
363 | return ret; |
364 | |
365 | return 0; |
366 | } |
367 | |