1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* Support routines for initializing a PCI subsystem
4	*
5	* Extruded from code written by
6	* Dave Rusling (david.rusling@reo.mts.dec.com)
7	* David Mosberger (davidm@cs.arizona.edu)
8	* David Miller (davem@redhat.com)
9	*
10	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
11	* PCI-PCI bridges cleanup, sorted resource allocation.
12	* Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13	* Converted to allocation in 3 passes, which gives
14	* tighter packing. Prefetchable range support.
15	*/
16
17	#include <linux/bitops.h>
18	#include <linux/init.h>
19	#include <linux/kernel.h>
20	#include <linux/module.h>
21	#include <linux/pci.h>
22	#include <linux/errno.h>
23	#include <linux/ioport.h>
24	#include <linux/cache.h>
25	#include <linux/limits.h>
26	#include <linux/sizes.h>
27	#include <linux/slab.h>
28	#include <linux/acpi.h>
29	#include "pci.h"
30
31	unsigned int pci_flags;
32	EXPORT_SYMBOL_GPL(pci_flags);
33
34	struct pci_dev_resource {
35	struct list_head list;
36	struct resource *res;
37	struct pci_dev *dev;
38	resource_size_t start;
39	resource_size_t end;
40	resource_size_t add_size;
41	resource_size_t min_align;
42	unsigned long flags;
43	};
44
45	static void free_list(struct list_head *head)
46	{
47	struct pci_dev_resource *dev_res, *tmp;
48
49	list_for_each_entry_safe(dev_res, tmp, head, list) {
50	list_del(entry: &dev_res->list);
51	kfree(objp: dev_res);
52	}
53	}
54
55	/**
56	* add_to_list() - Add a new resource tracker to the list
57	* @head: Head of the list
58	* @dev: Device to which the resource belongs
59	* @res: Resource to be tracked
60	* @add_size: Additional size to be optionally added to the resource
61	* @min_align: Minimum memory window alignment
62	*/
63	static int add_to_list(struct list_head *head, struct pci_dev *dev,
64	struct resource *res, resource_size_t add_size,
65	resource_size_t min_align)
66	{
67	struct pci_dev_resource *tmp;
68
69	tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
70	if (!tmp)
71	return -ENOMEM;
72
73	tmp->res = res;
74	tmp->dev = dev;
75	tmp->start = res->start;
76	tmp->end = res->end;
77	tmp->flags = res->flags;
78	tmp->add_size = add_size;
79	tmp->min_align = min_align;
80
81	list_add(new: &tmp->list, head);
82
83	return 0;
84	}
85
86	static void remove_from_list(struct list_head *head, struct resource *res)
87	{
88	struct pci_dev_resource *dev_res, *tmp;
89
90	list_for_each_entry_safe(dev_res, tmp, head, list) {
91	if (dev_res->res == res) {
92	list_del(entry: &dev_res->list);
93	kfree(objp: dev_res);
94	break;
95	}
96	}
97	}
98
99	static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
100	struct resource *res)
101	{
102	struct pci_dev_resource *dev_res;
103
104	list_for_each_entry(dev_res, head, list) {
105	if (dev_res->res == res)
106	return dev_res;
107	}
108
109	return NULL;
110	}
111
112	static resource_size_t get_res_add_size(struct list_head *head,
113	struct resource *res)
114	{
115	struct pci_dev_resource *dev_res;
116
117	dev_res = res_to_dev_res(head, res);
118	return dev_res ? dev_res->add_size : 0;
119	}
120
121	static resource_size_t get_res_add_align(struct list_head *head,
122	struct resource *res)
123	{
124	struct pci_dev_resource *dev_res;
125
126	dev_res = res_to_dev_res(head, res);
127	return dev_res ? dev_res->min_align : 0;
128	}
129
130	static void restore_dev_resource(struct pci_dev_resource *dev_res)
131	{
132	struct resource *res = dev_res->res;
133
134	res->start = dev_res->start;
135	res->end = dev_res->end;
136	res->flags = dev_res->flags;
137	}
138
139	static bool pdev_resources_assignable(struct pci_dev *dev)
140	{
141	u16 class = dev->class >> 8, command;
142
143	/* Don't touch classless devices or host bridges or IOAPICs */
144	if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
145	return false;
146
147	/* Don't touch IOAPIC devices already enabled by firmware */
148	if (class == PCI_CLASS_SYSTEM_PIC) {
149	pci_read_config_word(dev, PCI_COMMAND, val: &command);
150	if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
151	return false;
152	}
153
154	return true;
155	}
156
157	/* Sort resources by alignment */
158	static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
159	{
160	struct resource *r;
161	int i;
162
163	if (!pdev_resources_assignable(dev))
164	return;
165
166	pci_dev_for_each_resource(dev, r, i) {
167	const char *r_name = pci_resource_name(dev, i);
168	struct pci_dev_resource *dev_res, *tmp;
169	resource_size_t r_align;
170	struct list_head *n;
171
172	if (r->flags & IORESOURCE_PCI_FIXED)
173	continue;
174
175	if (!(r->flags) || r->parent)
176	continue;
177
178	r_align = pci_resource_alignment(dev, res: r);
179	if (!r_align) {
180	pci_warn(dev, "%s %pR: alignment must not be zero\n",
181	r_name, r);
182	continue;
183	}
184
185	tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
186	if (!tmp)
187	panic(fmt: "%s: kzalloc() failed!\n", __func__);
188	tmp->res = r;
189	tmp->dev = dev;
190	tmp->start = r->start;
191	tmp->end = r->end;
192	tmp->flags = r->flags;
193
194	/* Fallback is smallest one or list is empty */
195	n = head;
196	list_for_each_entry(dev_res, head, list) {
197	resource_size_t align;
198
199	align = pci_resource_alignment(dev: dev_res->dev,
200	res: dev_res->res);
201
202	if (r_align > align) {
203	n = &dev_res->list;
204	break;
205	}
206	}
207	/* Insert it just before n */
208	list_add_tail(new: &tmp->list, head: n);
209	}
210	}
211
212	bool pci_resource_is_optional(const struct pci_dev *dev, int resno)
213	{
214	const struct resource *res = pci_resource_n(dev, resno);
215
216	if (pci_resource_is_iov(resno))
217	return true;
218	if (resno == PCI_ROM_RESOURCE && !(res->flags & IORESOURCE_ROM_ENABLE))
219	return true;
220
221	return false;
222	}
223
224	static inline void reset_resource(struct resource *res)
225	{
226	res->start = 0;
227	res->end = 0;
228	res->flags = 0;
229	}
230
231	/**
232	* reassign_resources_sorted() - Satisfy any additional resource requests
233	*
234	* @realloc_head: Head of the list tracking requests requiring
235	* additional resources
236	* @head: Head of the list tracking requests with allocated
237	* resources
238	*
239	* Walk through each element of the realloc_head and try to procure additional
240	* resources for the element, provided the element is in the head list.
241	*/
242	static void reassign_resources_sorted(struct list_head *realloc_head,
243	struct list_head *head)
244	{
245	struct pci_dev_resource *add_res, *tmp;
246	struct pci_dev_resource *dev_res;
247	struct pci_dev *dev;
248	struct resource *res;
249	const char *res_name;
250	resource_size_t add_size, align;
251	int idx;
252
253	list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
254	bool found_match = false;
255
256	res = add_res->res;
257	dev = add_res->dev;
258	idx = pci_resource_num(dev, res);
259
260	/*
261	* Skip resource that failed the earlier assignment and is
262	* not optional as it would just fail again.
263	*/
264	if (!res->parent && resource_size(res) &&
265	!pci_resource_is_optional(dev, resno: idx))
266	goto out;
267
268	/* Skip this resource if not found in head list */
269	list_for_each_entry(dev_res, head, list) {
270	if (dev_res->res == res) {
271	found_match = true;
272	break;
273	}
274	}
275	if (!found_match) /* Just skip */
276	continue;
277
278	res_name = pci_resource_name(dev, i: idx);
279	add_size = add_res->add_size;
280	align = add_res->min_align;
281	if (!res->parent) {
282	resource_set_range(res, start: align,
283	size: resource_size(res) + add_size);
284	if (pci_assign_resource(dev, i: idx)) {
285	pci_dbg(dev,
286	"%s %pR: ignoring failure in optional allocation\n",
287	res_name, res);
288	}
289	} else if (add_size > 0) {
290	res->flags |= add_res->flags &
291	(IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
292	if (pci_reassign_resource(dev, i: idx, add_size, align))
293	pci_info(dev, "%s %pR: failed to add optional %llx\n",
294	res_name, res,
295	(unsigned long long) add_size);
296	}
297	out:
298	list_del(entry: &add_res->list);
299	kfree(objp: add_res);
300	}
301	}
302
303	/**
304	* assign_requested_resources_sorted() - Satisfy resource requests
305	*
306	* @head: Head of the list tracking requests for resources
307	* @fail_head: Head of the list tracking requests that could not be
308	* allocated
309	* @optional: Assign also optional resources
310	*
311	* Satisfy resource requests of each element in the list. Add requests that
312	* could not be satisfied to the failed_list.
313	*/
314	static void assign_requested_resources_sorted(struct list_head *head,
315	struct list_head *fail_head,
316	bool optional)
317	{
318	struct pci_dev_resource *dev_res;
319	struct resource *res;
320	struct pci_dev *dev;
321	bool optional_res;
322	int idx;
323
324	list_for_each_entry(dev_res, head, list) {
325	res = dev_res->res;
326	dev = dev_res->dev;
327	idx = pci_resource_num(dev, res);
328	optional_res = pci_resource_is_optional(dev, resno: idx);
329
330	if (!resource_size(res))
331	continue;
332
333	if (!optional && optional_res)
334	continue;
335
336	if (pci_assign_resource(dev, i: idx)) {
337	if (fail_head) {
338	add_to_list(head: fail_head, dev, res,
339	add_size: 0 /* don't care */,
340	min_align: 0 /* don't care */);
341	}
342	}
343	}
344	}
345
346	static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
347	{
348	struct pci_dev_resource *fail_res;
349	unsigned long mask = 0;
350
351	/* Check failed type */
352	list_for_each_entry(fail_res, fail_head, list)
353	mask |= fail_res->flags;
354
355	/*
356	* One pref failed resource will set IORESOURCE_MEM, as we can
357	* allocate pref in non-pref range. Will release all assigned
358	* non-pref sibling resources according to that bit.
359	*/
360	return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
361	}
362
363	static bool pci_need_to_release(unsigned long mask, struct resource *res)
364	{
365	if (res->flags & IORESOURCE_IO)
366	return !!(mask & IORESOURCE_IO);
367
368	/* Check pref at first */
369	if (res->flags & IORESOURCE_PREFETCH) {
370	if (mask & IORESOURCE_PREFETCH)
371	return true;
372	/* Count pref if its parent is non-pref */
373	else if ((mask & IORESOURCE_MEM) &&
374	!(res->parent->flags & IORESOURCE_PREFETCH))
375	return true;
376	else
377	return false;
378	}
379
380	if (res->flags & IORESOURCE_MEM)
381	return !!(mask & IORESOURCE_MEM);
382
383	return false; /* Should not get here */
384	}
385
386	/* Return: @true if assignment of a required resource failed. */
387	static bool pci_required_resource_failed(struct list_head *fail_head)
388	{
389	struct pci_dev_resource *fail_res;
390
391	list_for_each_entry(fail_res, fail_head, list) {
392	int idx = pci_resource_num(dev: fail_res->dev, res: fail_res->res);
393
394	if (!pci_resource_is_optional(dev: fail_res->dev, resno: idx))
395	return true;
396	}
397	return false;
398	}
399
400	static void __assign_resources_sorted(struct list_head *head,
401	struct list_head *realloc_head,
402	struct list_head *fail_head)
403	{
404	/*
405	* Should not assign requested resources at first. They could be
406	* adjacent, so later reassign can not reallocate them one by one in
407	* parent resource window.
408	*
409	* Try to assign required and any optional resources at beginning
410	* (add_size included). If all required resources were successfully
411	* assigned, get out early. If could not do that, we still try to
412	* assign required at first, then try to reassign some optional
413	* resources.
414	*
415	* Separate three resource type checking if we need to release
416	* assigned resource after requested + add_size try.
417	*
418	* 1. If IO port assignment fails, will release assigned IO
419	* port.
420	* 2. If pref MMIO assignment fails, release assigned pref
421	* MMIO. If assigned pref MMIO's parent is non-pref MMIO
422	* and non-pref MMIO assignment fails, will release that
423	* assigned pref MMIO.
424	* 3. If non-pref MMIO assignment fails or pref MMIO
425	* assignment fails, will release assigned non-pref MMIO.
426	*/
427	LIST_HEAD(save_head);
428	LIST_HEAD(local_fail_head);
429	LIST_HEAD(dummy_head);
430	struct pci_dev_resource *save_res;
431	struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
432	struct resource *res;
433	struct pci_dev *dev;
434	const char *res_name;
435	int idx;
436	unsigned long fail_type;
437	resource_size_t add_align, align;
438
439	if (!realloc_head)
440	realloc_head = &dummy_head;
441
442	/* Check if optional add_size is there */
443	if (list_empty(head: realloc_head))
444	goto assign;
445
446	/* Save original start, end, flags etc at first */
447	list_for_each_entry(dev_res, head, list) {
448	if (add_to_list(head: &save_head, dev: dev_res->dev, res: dev_res->res, add_size: 0, min_align: 0)) {
449	free_list(head: &save_head);
450	goto assign;
451	}
452	}
453
454	/* Update res in head list with add_size in realloc_head list */
455	list_for_each_entry_safe(dev_res, tmp_res, head, list) {
456	res = dev_res->res;
457
458	res->end += get_res_add_size(head: realloc_head, res);
459
460	/*
461	* There are two kinds of additional resources in the list:
462	* 1. bridge resource -- IORESOURCE_STARTALIGN
463	* 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
464	* Here just fix the additional alignment for bridge
465	*/
466	if (!(res->flags & IORESOURCE_STARTALIGN))
467	continue;
468
469	add_align = get_res_add_align(head: realloc_head, res);
470
471	/*
472	* The "head" list is sorted by alignment so resources with
473	* bigger alignment will be assigned first. After we
474	* change the alignment of a dev_res in "head" list, we
475	* need to reorder the list by alignment to make it
476	* consistent.
477	*/
478	if (add_align > res->start) {
479	resource_set_range(res, start: add_align, size: resource_size(res));
480
481	list_for_each_entry(dev_res2, head, list) {
482	align = pci_resource_alignment(dev: dev_res2->dev,
483	res: dev_res2->res);
484	if (add_align > align) {
485	list_move_tail(list: &dev_res->list,
486	head: &dev_res2->list);
487	break;
488	}
489	}
490	}
491
492	}
493
494	assign:
495	assign_requested_resources_sorted(head, fail_head: &local_fail_head, optional: true);
496
497	/* All non-optional resources assigned? */
498	if (list_empty(head: &local_fail_head)) {
499	/* Remove head list from realloc_head list */
500	list_for_each_entry(dev_res, head, list)
501	remove_from_list(head: realloc_head, res: dev_res->res);
502	free_list(head: &save_head);
503	goto out;
504	}
505
506	/* Without realloc_head and only optional fails, nothing more to do. */
507	if (!pci_required_resource_failed(fail_head: &local_fail_head) &&
508	list_empty(head: realloc_head)) {
509	list_for_each_entry(save_res, &save_head, list) {
510	struct resource *res = save_res->res;
511
512	if (res->parent)
513	continue;
514
515	restore_dev_resource(dev_res: save_res);
516	}
517	free_list(head: &local_fail_head);
518	free_list(head: &save_head);
519	goto out;
520	}
521
522	/* Check failed type */
523	fail_type = pci_fail_res_type_mask(fail_head: &local_fail_head);
524	/* Remove not need to be released assigned res from head list etc */
525	list_for_each_entry_safe(dev_res, tmp_res, head, list) {
526	res = dev_res->res;
527
528	if (res->parent && !pci_need_to_release(mask: fail_type, res)) {
529	/* Remove it from realloc_head list */
530	remove_from_list(head: realloc_head, res);
531	remove_from_list(head: &save_head, res);
532	list_del(entry: &dev_res->list);
533	kfree(objp: dev_res);
534	}
535	}
536
537	free_list(head: &local_fail_head);
538	/* Release assigned resource */
539	list_for_each_entry(dev_res, head, list) {
540	res = dev_res->res;
541	dev = dev_res->dev;
542
543	if (!res->parent)
544	continue;
545
546	idx = pci_resource_num(dev, res);
547	res_name = pci_resource_name(dev, i: idx);
548	pci_dbg(dev, "%s %pR: releasing\n", res_name, res);
549
550	release_resource(new: res);
551	restore_dev_resource(dev_res);
552	}
553	/* Restore start/end/flags from saved list */
554	list_for_each_entry(save_res, &save_head, list)
555	restore_dev_resource(dev_res: save_res);
556	free_list(head: &save_head);
557
558	/* Satisfy the must-have resource requests */
559	assign_requested_resources_sorted(head, NULL, optional: false);
560
561	/* Try to satisfy any additional optional resource requests */
562	if (!list_empty(head: realloc_head))
563	reassign_resources_sorted(realloc_head, head);
564
565	out:
566	/* Reset any failed resource, cannot use fail_head as it can be NULL. */
567	list_for_each_entry(dev_res, head, list) {
568	res = dev_res->res;
569	dev = dev_res->dev;
570
571	if (res->parent)
572	continue;
573
574	if (fail_head) {
575	add_to_list(head: fail_head, dev, res,
576	add_size: 0 /* don't care */,
577	min_align: 0 /* don't care */);
578	}
579
580	reset_resource(res);
581	}
582
583	free_list(head);
584	}
585
586	static void pdev_assign_resources_sorted(struct pci_dev *dev,
587	struct list_head *add_head,
588	struct list_head *fail_head)
589	{
590	LIST_HEAD(head);
591
592	pdev_sort_resources(dev, head: &head);
593	__assign_resources_sorted(head: &head, realloc_head: add_head, fail_head);
594
595	}
596
597	static void pbus_assign_resources_sorted(const struct pci_bus *bus,
598	struct list_head *realloc_head,
599	struct list_head *fail_head)
600	{
601	struct pci_dev *dev;
602	LIST_HEAD(head);
603
604	list_for_each_entry(dev, &bus->devices, bus_list)
605	pdev_sort_resources(dev, head: &head);
606
607	__assign_resources_sorted(head: &head, realloc_head, fail_head);
608	}
609
610	void pci_setup_cardbus(struct pci_bus *bus)
611	{
612	struct pci_dev *bridge = bus->self;
613	struct resource *res;
614	struct pci_bus_region region;
615
616	pci_info(bridge, "CardBus bridge to %pR\n",
617	&bus->busn_res);
618
619	res = bus->resource[0];
620	pcibios_resource_to_bus(bus: bridge->bus, region: &region, res);
621	if (res->flags & IORESOURCE_IO) {
622	/*
623	* The IO resource is allocated a range twice as large as it
624	* would normally need. This allows us to set both IO regs.
625	*/
626	pci_info(bridge, " bridge window %pR\n", res);
627	pci_write_config_dword(dev: bridge, PCI_CB_IO_BASE_0,
628	val: region.start);
629	pci_write_config_dword(dev: bridge, PCI_CB_IO_LIMIT_0,
630	val: region.end);
631	}
632
633	res = bus->resource[1];
634	pcibios_resource_to_bus(bus: bridge->bus, region: &region, res);
635	if (res->flags & IORESOURCE_IO) {
636	pci_info(bridge, " bridge window %pR\n", res);
637	pci_write_config_dword(dev: bridge, PCI_CB_IO_BASE_1,
638	val: region.start);
639	pci_write_config_dword(dev: bridge, PCI_CB_IO_LIMIT_1,
640	val: region.end);
641	}
642
643	res = bus->resource[2];
644	pcibios_resource_to_bus(bus: bridge->bus, region: &region, res);
645	if (res->flags & IORESOURCE_MEM) {
646	pci_info(bridge, " bridge window %pR\n", res);
647	pci_write_config_dword(dev: bridge, PCI_CB_MEMORY_BASE_0,
648	val: region.start);
649	pci_write_config_dword(dev: bridge, PCI_CB_MEMORY_LIMIT_0,
650	val: region.end);
651	}
652
653	res = bus->resource[3];
654	pcibios_resource_to_bus(bus: bridge->bus, region: &region, res);
655	if (res->flags & IORESOURCE_MEM) {
656	pci_info(bridge, " bridge window %pR\n", res);
657	pci_write_config_dword(dev: bridge, PCI_CB_MEMORY_BASE_1,
658	val: region.start);
659	pci_write_config_dword(dev: bridge, PCI_CB_MEMORY_LIMIT_1,
660	val: region.end);
661	}
662	}
663	EXPORT_SYMBOL(pci_setup_cardbus);
664
665	/*
666	* Initialize bridges with base/limit values we have collected. PCI-to-PCI
667	* Bridge Architecture Specification rev. 1.1 (1998) requires that if there
668	* are no I/O ports or memory behind the bridge, the corresponding range
669	* must be turned off by writing base value greater than limit to the
670	* bridge's base/limit registers.
671	*
672	* Note: care must be taken when updating I/O base/limit registers of
673	* bridges which support 32-bit I/O. This update requires two config space
674	* writes, so it's quite possible that an I/O window of the bridge will
675	* have some undesirable address (e.g. 0) after the first write. Ditto
676	* 64-bit prefetchable MMIO.
677	*/
678	static void pci_setup_bridge_io(struct pci_dev *bridge)
679	{
680	struct resource *res;
681	const char *res_name;
682	struct pci_bus_region region;
683	unsigned long io_mask;
684	u8 io_base_lo, io_limit_lo;
685	u16 l;
686	u32 io_upper16;
687
688	io_mask = PCI_IO_RANGE_MASK;
689	if (bridge->io_window_1k)
690	io_mask = PCI_IO_1K_RANGE_MASK;
691
692	/* Set up the top and bottom of the PCI I/O segment for this bus */
693	res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
694	res_name = pci_resource_name(dev: bridge, PCI_BRIDGE_IO_WINDOW);
695	pcibios_resource_to_bus(bus: bridge->bus, region: &region, res);
696	if (res->flags & IORESOURCE_IO) {
697	pci_read_config_word(dev: bridge, PCI_IO_BASE, val: &l);
698	io_base_lo = (region.start >> 8) & io_mask;
699	io_limit_lo = (region.end >> 8) & io_mask;
700	l = ((u16) io_limit_lo << 8) | io_base_lo;
701	/* Set up upper 16 bits of I/O base/limit */
702	io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
703	pci_info(bridge, " %s %pR\n", res_name, res);
704	} else {
705	/* Clear upper 16 bits of I/O base/limit */
706	io_upper16 = 0;
707	l = 0x00f0;
708	}
709	/* Temporarily disable the I/O range before updating PCI_IO_BASE */
710	pci_write_config_dword(dev: bridge, PCI_IO_BASE_UPPER16, val: 0x0000ffff);
711	/* Update lower 16 bits of I/O base/limit */
712	pci_write_config_word(dev: bridge, PCI_IO_BASE, val: l);
713	/* Update upper 16 bits of I/O base/limit */
714	pci_write_config_dword(dev: bridge, PCI_IO_BASE_UPPER16, val: io_upper16);
715	}
716
717	static void pci_setup_bridge_mmio(struct pci_dev *bridge)
718	{
719	struct resource *res;
720	const char *res_name;
721	struct pci_bus_region region;
722	u32 l;
723
724	/* Set up the top and bottom of the PCI Memory segment for this bus */
725	res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
726	res_name = pci_resource_name(dev: bridge, PCI_BRIDGE_MEM_WINDOW);
727	pcibios_resource_to_bus(bus: bridge->bus, region: &region, res);
728	if (res->flags & IORESOURCE_MEM) {
729	l = (region.start >> 16) & 0xfff0;
730	l |= region.end & 0xfff00000;
731	pci_info(bridge, " %s %pR\n", res_name, res);
732	} else {
733	l = 0x0000fff0;
734	}
735	pci_write_config_dword(dev: bridge, PCI_MEMORY_BASE, val: l);
736	}
737
738	static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
739	{
740	struct resource *res;
741	const char *res_name;
742	struct pci_bus_region region;
743	u32 l, bu, lu;
744
745	/*
746	* Clear out the upper 32 bits of PREF limit. If
747	* PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
748	* PREF range, which is ok.
749	*/
750	pci_write_config_dword(dev: bridge, PCI_PREF_LIMIT_UPPER32, val: 0);
751
752	/* Set up PREF base/limit */
753	bu = lu = 0;
754	res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
755	res_name = pci_resource_name(dev: bridge, PCI_BRIDGE_PREF_MEM_WINDOW);
756	pcibios_resource_to_bus(bus: bridge->bus, region: &region, res);
757	if (res->flags & IORESOURCE_PREFETCH) {
758	l = (region.start >> 16) & 0xfff0;
759	l |= region.end & 0xfff00000;
760	if (res->flags & IORESOURCE_MEM_64) {
761	bu = upper_32_bits(region.start);
762	lu = upper_32_bits(region.end);
763	}
764	pci_info(bridge, " %s %pR\n", res_name, res);
765	} else {
766	l = 0x0000fff0;
767	}
768	pci_write_config_dword(dev: bridge, PCI_PREF_MEMORY_BASE, val: l);
769
770	/* Set the upper 32 bits of PREF base & limit */
771	pci_write_config_dword(dev: bridge, PCI_PREF_BASE_UPPER32, val: bu);
772	pci_write_config_dword(dev: bridge, PCI_PREF_LIMIT_UPPER32, val: lu);
773	}
774
775	static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
776	{
777	struct pci_dev *bridge = bus->self;
778
779	pci_info(bridge, "PCI bridge to %pR\n", &bus->busn_res);
780
781	if (type & IORESOURCE_IO)
782	pci_setup_bridge_io(bridge);
783
784	if (type & IORESOURCE_MEM)
785	pci_setup_bridge_mmio(bridge);
786
787	if (type & IORESOURCE_PREFETCH)
788	pci_setup_bridge_mmio_pref(bridge);
789
790	pci_write_config_word(dev: bridge, PCI_BRIDGE_CONTROL, val: bus->bridge_ctl);
791	}
792
793	void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
794	{
795	}
796
797	static void pci_setup_bridge(struct pci_bus *bus)
798	{
799	unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
800	IORESOURCE_PREFETCH;
801
802	pcibios_setup_bridge(bus, type);
803	__pci_setup_bridge(bus, type);
804	}
805
806
807	int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
808	{
809	if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
810	return 0;
811
812	if (pci_claim_resource(bridge, i) == 0)
813	return 0; /* Claimed the window */
814
815	if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
816	return 0;
817
818	if (!pci_bus_clip_resource(dev: bridge, idx: i))
819	return -EINVAL; /* Clipping didn't change anything */
820
821	switch (i) {
822	case PCI_BRIDGE_IO_WINDOW:
823	pci_setup_bridge_io(bridge);
824	break;
825	case PCI_BRIDGE_MEM_WINDOW:
826	pci_setup_bridge_mmio(bridge);
827	break;
828	case PCI_BRIDGE_PREF_MEM_WINDOW:
829	pci_setup_bridge_mmio_pref(bridge);
830	break;
831	default:
832	return -EINVAL;
833	}
834
835	if (pci_claim_resource(bridge, i) == 0)
836	return 0; /* Claimed a smaller window */
837
838	return -EINVAL;
839	}
840
841	/*
842	* Check whether the bridge supports optional I/O and prefetchable memory
843	* ranges. If not, the respective base/limit registers must be read-only
844	* and read as 0.
845	*/
846	static void pci_bridge_check_ranges(struct pci_bus *bus)
847	{
848	struct pci_dev *bridge = bus->self;
849	struct resource *b_res;
850
851	b_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
852	b_res->flags |= IORESOURCE_MEM;
853
854	if (bridge->io_window) {
855	b_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
856	b_res->flags |= IORESOURCE_IO;
857	}
858
859	if (bridge->pref_window) {
860	b_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
861	b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
862	if (bridge->pref_64_window) {
863	b_res->flags |= IORESOURCE_MEM_64 |
864	PCI_PREF_RANGE_TYPE_64;
865	}
866	}
867	}
868
869	/*
870	* Helper function for sizing routines. Assigned resources have non-NULL
871	* parent resource.
872	*
873	* Return first unassigned resource of the correct type. If there is none,
874	* return first assigned resource of the correct type. If none of the
875	* above, return NULL.
876	*
877	* Returning an assigned resource of the correct type allows the caller to
878	* distinguish between already assigned and no resource of the correct type.
879	*/
880	static struct resource *find_bus_resource_of_type(struct pci_bus *bus,
881	unsigned long type_mask,
882	unsigned long type)
883	{
884	struct resource *r, *r_assigned = NULL;
885
886	pci_bus_for_each_resource(bus, r) {
887	if (r == &ioport_resource || r == &iomem_resource)
888	continue;
889	if (r && (r->flags & type_mask) == type && !r->parent)
890	return r;
891	if (r && (r->flags & type_mask) == type && !r_assigned)
892	r_assigned = r;
893	}
894	return r_assigned;
895	}
896
897	static resource_size_t calculate_iosize(resource_size_t size,
898	resource_size_t min_size,
899	resource_size_t size1,
900	resource_size_t add_size,
901	resource_size_t children_add_size,
902	resource_size_t old_size,
903	resource_size_t align)
904	{
905	if (size < min_size)
906	size = min_size;
907	if (old_size == 1)
908	old_size = 0;
909	/*
910	* To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
911	* struct pci_bus.
912	*/
913	#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
914	size = (size & 0xff) + ((size & ~0xffUL) << 2);
915	#endif
916	size = size + size1;
917
918	size = max(size, add_size) + children_add_size;
919	return ALIGN(max(size, old_size), align);
920	}
921
922	static resource_size_t calculate_memsize(resource_size_t size,
923	resource_size_t min_size,
924	resource_size_t add_size,
925	resource_size_t children_add_size,
926	resource_size_t old_size,
927	resource_size_t align)
928	{
929	if (size < min_size)
930	size = min_size;
931	if (old_size == 1)
932	old_size = 0;
933
934	size = max(size, add_size) + children_add_size;
935	return ALIGN(max(size, old_size), align);
936	}
937
938	resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
939	unsigned long type)
940	{
941	return 1;
942	}
943
944	#define PCI_P2P_DEFAULT_MEM_ALIGN SZ_1M
945	#define PCI_P2P_DEFAULT_IO_ALIGN SZ_4K
946	#define PCI_P2P_DEFAULT_IO_ALIGN_1K SZ_1K
947
948	static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
949	{
950	resource_size_t align = 1, arch_align;
951
952	if (type & IORESOURCE_MEM)
953	align = PCI_P2P_DEFAULT_MEM_ALIGN;
954	else if (type & IORESOURCE_IO) {
955	/*
956	* Per spec, I/O windows are 4K-aligned, but some bridges have
957	* an extension to support 1K alignment.
958	*/
959	if (bus->self && bus->self->io_window_1k)
960	align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
961	else
962	align = PCI_P2P_DEFAULT_IO_ALIGN;
963	}
964
965	arch_align = pcibios_window_alignment(bus, type);
966	return max(align, arch_align);
967	}
968
969	/**
970	* pbus_size_io() - Size the I/O window of a given bus
971	*
972	* @bus: The bus
973	* @min_size: The minimum I/O window that must be allocated
974	* @add_size: Additional optional I/O window
975	* @realloc_head: Track the additional I/O window on this list
976	*
977	* Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
978	* windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
979	* devices are limited to 256 bytes. We must be careful with the ISA
980	* aliasing though.
981	*/
982	static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
983	resource_size_t add_size,
984	struct list_head *realloc_head)
985	{
986	struct pci_dev *dev;
987	struct resource *b_res = find_bus_resource_of_type(bus, IORESOURCE_IO,
988	IORESOURCE_IO);
989	resource_size_t size = 0, size0 = 0, size1 = 0;
990	resource_size_t children_add_size = 0;
991	resource_size_t min_align, align;
992
993	if (!b_res)
994	return;
995
996	/* If resource is already assigned, nothing more to do */
997	if (b_res->parent)
998	return;
999
1000	min_align = window_alignment(bus, IORESOURCE_IO);
1001	list_for_each_entry(dev, &bus->devices, bus_list) {
1002	struct resource *r;
1003
1004	pci_dev_for_each_resource(dev, r) {
1005	unsigned long r_size;
1006
1007	if (r->parent || !(r->flags & IORESOURCE_IO))
1008	continue;
1009	r_size = resource_size(res: r);
1010
1011	if (r_size < SZ_1K)
1012	/* Might be re-aligned for ISA */
1013	size += r_size;
1014	else
1015	size1 += r_size;
1016
1017	align = pci_resource_alignment(dev, res: r);
1018	if (align > min_align)
1019	min_align = align;
1020
1021	if (realloc_head)
1022	children_add_size += get_res_add_size(head: realloc_head, res: r);
1023	}
1024	}
1025
1026	size0 = calculate_iosize(size, min_size, size1, add_size: 0, children_add_size: 0,
1027	old_size: resource_size(res: b_res), align: min_align);
1028
1029	size1 = size0;
1030	if (realloc_head && (add_size > 0 || children_add_size > 0)) {
1031	size1 = calculate_iosize(size, min_size, size1, add_size,
1032	children_add_size, old_size: resource_size(res: b_res),
1033	align: min_align);
1034	}
1035
1036	if (!size0 && !size1) {
1037	if (bus->self && (b_res->start || b_res->end))
1038	pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1039	b_res, &bus->busn_res);
1040	b_res->flags = 0;
1041	return;
1042	}
1043
1044	resource_set_range(res: b_res, start: min_align, size: size0);
1045	b_res->flags |= IORESOURCE_STARTALIGN;
1046	if (bus->self && size1 > size0 && realloc_head) {
1047	add_to_list(head: realloc_head, dev: bus->self, res: b_res, add_size: size1-size0,
1048	min_align);
1049	pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n",
1050	b_res, &bus->busn_res,
1051	(unsigned long long) size1 - size0);
1052	}
1053	}
1054
1055	static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
1056	int max_order)
1057	{
1058	resource_size_t align = 0;
1059	resource_size_t min_align = 0;
1060	int order;
1061
1062	for (order = 0; order <= max_order; order++) {
1063	resource_size_t align1 = 1;
1064
1065	align1 <<= order + __ffs(SZ_1M);
1066
1067	if (!align)
1068	min_align = align1;
1069	else if (ALIGN(align + min_align, min_align) < align1)
1070	min_align = align1 >> 1;
1071	align += aligns[order];
1072	}
1073
1074	return min_align;
1075	}
1076
1077	/**
1078	* pbus_upstream_space_available - Check no upstream resource limits allocation
1079	* @bus: The bus
1080	* @mask: Mask the resource flag, then compare it with type
1081	* @type: The type of resource from bridge
1082	* @size: The size required from the bridge window
1083	* @align: Required alignment for the resource
1084	*
1085	* Checks that @size can fit inside the upstream bridge resources that are
1086	* already assigned.
1087	*
1088	* Return: %true if enough space is available on all assigned upstream
1089	* resources.
1090	*/
1091	static bool pbus_upstream_space_available(struct pci_bus *bus, unsigned long mask,
1092	unsigned long type, resource_size_t size,
1093	resource_size_t align)
1094	{
1095	struct resource_constraint constraint = {
1096	.max = RESOURCE_SIZE_MAX,
1097	.align = align,
1098	};
1099	struct pci_bus *downstream = bus;
1100	struct resource *r;
1101
1102	while ((bus = bus->parent)) {
1103	if (pci_is_root_bus(pbus: bus))
1104	break;
1105
1106	pci_bus_for_each_resource(bus, r) {
1107	if (!r || !r->parent || (r->flags & mask) != type)
1108	continue;
1109
1110	if (resource_size(res: r) >= size) {
1111	struct resource gap = {};
1112
1113	if (find_resource_space(root: r, new: &gap, size, constraint: &constraint) == 0) {
1114	gap.flags = type;
1115	pci_dbg(bus->self,
1116	"Assigned bridge window %pR to %pR free space at %pR\n",
1117	r, &bus->busn_res, &gap);
1118	return true;
1119	}
1120	}
1121
1122	if (bus->self) {
1123	pci_info(bus->self,
1124	"Assigned bridge window %pR to %pR cannot fit 0x%llx required for %s bridging to %pR\n",
1125	r, &bus->busn_res,
1126	(unsigned long long)size,
1127	pci_name(downstream->self),
1128	&downstream->busn_res);
1129	}
1130
1131	return false;
1132	}
1133	}
1134
1135	return true;
1136	}
1137
1138	/**
1139	* pbus_size_mem() - Size the memory window of a given bus
1140	*
1141	* @bus: The bus
1142	* @mask: Mask the resource flag, then compare it with type
1143	* @type: The type of free resource from bridge
1144	* @type2: Second match type
1145	* @type3: Third match type
1146	* @min_size: The minimum memory window that must be allocated
1147	* @add_size: Additional optional memory window
1148	* @realloc_head: Track the additional memory window on this list
1149	*
1150	* Calculate the size of the bus and minimal alignment which guarantees
1151	* that all child resources fit in this size.
1152	*
1153	* Return -ENOSPC if there's no available bus resource of the desired
1154	* type. Otherwise, set the bus resource start/end to indicate the
1155	* required size, add things to realloc_head (if supplied), and return 0.
1156	*/
1157	static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
1158	unsigned long type, unsigned long type2,
1159	unsigned long type3, resource_size_t min_size,
1160	resource_size_t add_size,
1161	struct list_head *realloc_head)
1162	{
1163	struct pci_dev *dev;
1164	resource_size_t min_align, win_align, align, size, size0, size1 = 0;
1165	resource_size_t aligns[28]; /* Alignments from 1MB to 128TB */
1166	int order, max_order;
1167	struct resource *b_res = find_bus_resource_of_type(bus,
1168	type_mask: mask | IORESOURCE_PREFETCH, type);
1169	resource_size_t children_add_size = 0;
1170	resource_size_t children_add_align = 0;
1171	resource_size_t add_align = 0;
1172
1173	if (!b_res)
1174	return -ENOSPC;
1175
1176	/* If resource is already assigned, nothing more to do */
1177	if (b_res->parent)
1178	return 0;
1179
1180	memset(aligns, 0, sizeof(aligns));
1181	max_order = 0;
1182	size = 0;
1183
1184	list_for_each_entry(dev, &bus->devices, bus_list) {
1185	struct resource *r;
1186	int i;
1187
1188	pci_dev_for_each_resource(dev, r, i) {
1189	const char *r_name = pci_resource_name(dev, i);
1190	resource_size_t r_size;
1191
1192	if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1193	((r->flags & mask) != type &&
1194	(r->flags & mask) != type2 &&
1195	(r->flags & mask) != type3))
1196	continue;
1197	r_size = resource_size(res: r);
1198
1199	/* Put SRIOV requested res to the optional list */
1200	if (realloc_head && pci_resource_is_optional(dev, resno: i)) {
1201	add_align = max(pci_resource_alignment(dev, r), add_align);
1202	add_to_list(head: realloc_head, dev, res: r, add_size: 0, min_align: 0 /* Don't care */);
1203	children_add_size += r_size;
1204	continue;
1205	}
1206
1207	/*
1208	* aligns[0] is for 1MB (since bridge memory
1209	* windows are always at least 1MB aligned), so
1210	* keep "order" from being negative for smaller
1211	* resources.
1212	*/
1213	align = pci_resource_alignment(dev, res: r);
1214	order = __ffs(align) - __ffs(SZ_1M);
1215	if (order < 0)
1216	order = 0;
1217	if (order >= ARRAY_SIZE(aligns)) {
1218	pci_warn(dev, "%s %pR: disabling; bad alignment %#llx\n",
1219	r_name, r, (unsigned long long) align);
1220	r->flags = 0;
1221	continue;
1222	}
1223	size += max(r_size, align);
1224	/*
1225	* Exclude ranges with size > align from calculation of
1226	* the alignment.
1227	*/
1228	if (r_size <= align)
1229	aligns[order] += align;
1230	if (order > max_order)
1231	max_order = order;
1232
1233	if (realloc_head) {
1234	children_add_size += get_res_add_size(head: realloc_head, res: r);
1235	children_add_align = get_res_add_align(head: realloc_head, res: r);
1236	add_align = max(add_align, children_add_align);
1237	}
1238	}
1239	}
1240
1241	win_align = window_alignment(bus, type: b_res->flags);
1242	min_align = calculate_mem_align(aligns, max_order);
1243	min_align = max(min_align, win_align);
1244	size0 = calculate_memsize(size, min_size, add_size: 0, children_add_size: 0, old_size: resource_size(res: b_res), align: min_align);
1245
1246	if (bus->self && size0 &&
1247	!pbus_upstream_space_available(bus, mask: mask | IORESOURCE_PREFETCH, type,
1248	size: size0, align: min_align)) {
1249	min_align = 1ULL << (max_order + __ffs(SZ_1M));
1250	min_align = max(min_align, win_align);
1251	size0 = calculate_memsize(size, min_size, add_size: 0, children_add_size: 0, old_size: resource_size(res: b_res), align: win_align);
1252	pci_info(bus->self, "bridge window %pR to %pR requires relaxed alignment rules\n",
1253	b_res, &bus->busn_res);
1254	}
1255
1256	if (realloc_head && (add_size > 0 || children_add_size > 0)) {
1257	add_align = max(min_align, add_align);
1258	size1 = calculate_memsize(size, min_size, add_size, children_add_size,
1259	old_size: resource_size(res: b_res), align: add_align);
1260
1261	if (bus->self && size1 &&
1262	!pbus_upstream_space_available(bus, mask: mask | IORESOURCE_PREFETCH, type,
1263	size: size1, align: add_align)) {
1264	min_align = 1ULL << (max_order + __ffs(SZ_1M));
1265	min_align = max(min_align, win_align);
1266	size1 = calculate_memsize(size, min_size, add_size, children_add_size,
1267	old_size: resource_size(res: b_res), align: win_align);
1268	pci_info(bus->self,
1269	"bridge window %pR to %pR requires relaxed alignment rules\n",
1270	b_res, &bus->busn_res);
1271	}
1272	}
1273
1274	if (!size0 && !size1) {
1275	if (bus->self && (b_res->start || b_res->end))
1276	pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1277	b_res, &bus->busn_res);
1278	b_res->flags = 0;
1279	return 0;
1280	}
1281
1282	resource_set_range(res: b_res, start: min_align, size: size0);
1283	b_res->flags |= IORESOURCE_STARTALIGN;
1284	if (bus->self && size1 > size0 && realloc_head) {
1285	add_to_list(head: realloc_head, dev: bus->self, res: b_res, add_size: size1-size0, min_align: add_align);
1286	pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1287	b_res, &bus->busn_res,
1288	(unsigned long long) (size1 - size0),
1289	(unsigned long long) add_align);
1290	}
1291	return 0;
1292	}
1293
1294	unsigned long pci_cardbus_resource_alignment(struct resource *res)
1295	{
1296	if (res->flags & IORESOURCE_IO)
1297	return pci_cardbus_io_size;
1298	if (res->flags & IORESOURCE_MEM)
1299	return pci_cardbus_mem_size;
1300	return 0;
1301	}
1302
1303	static void pci_bus_size_cardbus(struct pci_bus *bus,
1304	struct list_head *realloc_head)
1305	{
1306	struct pci_dev *bridge = bus->self;
1307	struct resource *b_res;
1308	resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1309	u16 ctrl;
1310
1311	b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW];
1312	if (b_res->parent)
1313	goto handle_b_res_1;
1314	/*
1315	* Reserve some resources for CardBus. We reserve a fixed amount
1316	* of bus space for CardBus bridges.
1317	*/
1318	resource_set_range(res: b_res, start: pci_cardbus_io_size, size: pci_cardbus_io_size);
1319	b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1320	if (realloc_head) {
1321	b_res->end -= pci_cardbus_io_size;
1322	add_to_list(head: realloc_head, dev: bridge, res: b_res, add_size: pci_cardbus_io_size,
1323	min_align: pci_cardbus_io_size);
1324	}
1325
1326	handle_b_res_1:
1327	b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW];
1328	if (b_res->parent)
1329	goto handle_b_res_2;
1330	resource_set_range(res: b_res, start: pci_cardbus_io_size, size: pci_cardbus_io_size);
1331	b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1332	if (realloc_head) {
1333	b_res->end -= pci_cardbus_io_size;
1334	add_to_list(head: realloc_head, dev: bridge, res: b_res, add_size: pci_cardbus_io_size,
1335	min_align: pci_cardbus_io_size);
1336	}
1337
1338	handle_b_res_2:
1339	/* MEM1 must not be pref MMIO */
1340	pci_read_config_word(dev: bridge, PCI_CB_BRIDGE_CONTROL, val: &ctrl);
1341	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1342	ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1343	pci_write_config_word(dev: bridge, PCI_CB_BRIDGE_CONTROL, val: ctrl);
1344	pci_read_config_word(dev: bridge, PCI_CB_BRIDGE_CONTROL, val: &ctrl);
1345	}
1346
1347	/* Check whether prefetchable memory is supported by this bridge. */
1348	pci_read_config_word(dev: bridge, PCI_CB_BRIDGE_CONTROL, val: &ctrl);
1349	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1350	ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1351	pci_write_config_word(dev: bridge, PCI_CB_BRIDGE_CONTROL, val: ctrl);
1352	pci_read_config_word(dev: bridge, PCI_CB_BRIDGE_CONTROL, val: &ctrl);
1353	}
1354
1355	b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW];
1356	if (b_res->parent)
1357	goto handle_b_res_3;
1358	/*
1359	* If we have prefetchable memory support, allocate two regions.
1360	* Otherwise, allocate one region of twice the size.
1361	*/
1362	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1363	resource_set_range(res: b_res, start: pci_cardbus_mem_size,
1364	size: pci_cardbus_mem_size);
1365	b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1366	IORESOURCE_STARTALIGN;
1367	if (realloc_head) {
1368	b_res->end -= pci_cardbus_mem_size;
1369	add_to_list(head: realloc_head, dev: bridge, res: b_res,
1370	add_size: pci_cardbus_mem_size, min_align: pci_cardbus_mem_size);
1371	}
1372
1373	/* Reduce that to half */
1374	b_res_3_size = pci_cardbus_mem_size;
1375	}
1376
1377	handle_b_res_3:
1378	b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW];
1379	if (b_res->parent)
1380	goto handle_done;
1381	resource_set_range(res: b_res, start: pci_cardbus_mem_size, size: b_res_3_size);
1382	b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1383	if (realloc_head) {
1384	b_res->end -= b_res_3_size;
1385	add_to_list(head: realloc_head, dev: bridge, res: b_res, add_size: b_res_3_size,
1386	min_align: pci_cardbus_mem_size);
1387	}
1388
1389	handle_done:
1390	;
1391	}
1392
1393	void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1394	{
1395	struct pci_dev *dev;
1396	unsigned long mask, prefmask, type2 = 0, type3 = 0;
1397	resource_size_t additional_io_size = 0, additional_mmio_size = 0,
1398	additional_mmio_pref_size = 0;
1399	struct resource *pref;
1400	struct pci_host_bridge *host;
1401	int hdr_type, ret;
1402
1403	list_for_each_entry(dev, &bus->devices, bus_list) {
1404	struct pci_bus *b = dev->subordinate;
1405	if (!b)
1406	continue;
1407
1408	switch (dev->hdr_type) {
1409	case PCI_HEADER_TYPE_CARDBUS:
1410	pci_bus_size_cardbus(bus: b, realloc_head);
1411	break;
1412
1413	case PCI_HEADER_TYPE_BRIDGE:
1414	default:
1415	__pci_bus_size_bridges(bus: b, realloc_head);
1416	break;
1417	}
1418	}
1419
1420	/* The root bus? */
1421	if (pci_is_root_bus(pbus: bus)) {
1422	host = to_pci_host_bridge(bus->bridge);
1423	if (!host->size_windows)
1424	return;
1425	pci_bus_for_each_resource(bus, pref)
1426	if (pref && (pref->flags & IORESOURCE_PREFETCH))
1427	break;
1428	hdr_type = -1; /* Intentionally invalid - not a PCI device. */
1429	} else {
1430	pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
1431	hdr_type = bus->self->hdr_type;
1432	}
1433
1434	switch (hdr_type) {
1435	case PCI_HEADER_TYPE_CARDBUS:
1436	/* Don't size CardBuses yet */
1437	break;
1438
1439	case PCI_HEADER_TYPE_BRIDGE:
1440	pci_bridge_check_ranges(bus);
1441	if (bus->self->is_hotplug_bridge) {
1442	additional_io_size = pci_hotplug_io_size;
1443	additional_mmio_size = pci_hotplug_mmio_size;
1444	additional_mmio_pref_size = pci_hotplug_mmio_pref_size;
1445	}
1446	fallthrough;
1447	default:
1448	pbus_size_io(bus, min_size: realloc_head ? 0 : additional_io_size,
1449	add_size: additional_io_size, realloc_head);
1450
1451	/*
1452	* If there's a 64-bit prefetchable MMIO window, compute
1453	* the size required to put all 64-bit prefetchable
1454	* resources in it.
1455	*/
1456	mask = IORESOURCE_MEM;
1457	prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1458	if (pref && (pref->flags & IORESOURCE_MEM_64)) {
1459	prefmask |= IORESOURCE_MEM_64;
1460	ret = pbus_size_mem(bus, mask: prefmask, type: prefmask,
1461	type2: prefmask, type3: prefmask,
1462	min_size: realloc_head ? 0 : additional_mmio_pref_size,
1463	add_size: additional_mmio_pref_size, realloc_head);
1464
1465	/*
1466	* If successful, all non-prefetchable resources
1467	* and any 32-bit prefetchable resources will go in
1468	* the non-prefetchable window.
1469	*/
1470	if (ret == 0) {
1471	mask = prefmask;
1472	type2 = prefmask & ~IORESOURCE_MEM_64;
1473	type3 = prefmask & ~IORESOURCE_PREFETCH;
1474	}
1475	}
1476
1477	/*
1478	* If there is no 64-bit prefetchable window, compute the
1479	* size required to put all prefetchable resources in the
1480	* 32-bit prefetchable window (if there is one).
1481	*/
1482	if (!type2) {
1483	prefmask &= ~IORESOURCE_MEM_64;
1484	ret = pbus_size_mem(bus, mask: prefmask, type: prefmask,
1485	type2: prefmask, type3: prefmask,
1486	min_size: realloc_head ? 0 : additional_mmio_pref_size,
1487	add_size: additional_mmio_pref_size, realloc_head);
1488
1489	/*
1490	* If successful, only non-prefetchable resources
1491	* will go in the non-prefetchable window.
1492	*/
1493	if (ret == 0)
1494	mask = prefmask;
1495	else
1496	additional_mmio_size += additional_mmio_pref_size;
1497
1498	type2 = type3 = IORESOURCE_MEM;
1499	}
1500
1501	/*
1502	* Compute the size required to put everything else in the
1503	* non-prefetchable window. This includes:
1504	*
1505	* - all non-prefetchable resources
1506	* - 32-bit prefetchable resources if there's a 64-bit
1507	* prefetchable window or no prefetchable window at all
1508	* - 64-bit prefetchable resources if there's no prefetchable
1509	* window at all
1510	*
1511	* Note that the strategy in __pci_assign_resource() must match
1512	* that used here. Specifically, we cannot put a 32-bit
1513	* prefetchable resource in a 64-bit prefetchable window.
1514	*/
1515	pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1516	min_size: realloc_head ? 0 : additional_mmio_size,
1517	add_size: additional_mmio_size, realloc_head);
1518	break;
1519	}
1520	}
1521
1522	void pci_bus_size_bridges(struct pci_bus *bus)
1523	{
1524	__pci_bus_size_bridges(bus, NULL);
1525	}
1526	EXPORT_SYMBOL(pci_bus_size_bridges);
1527
1528	static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1529	{
1530	struct resource *parent_r;
1531	unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1532	IORESOURCE_PREFETCH;
1533
1534	pci_bus_for_each_resource(b, parent_r) {
1535	if (!parent_r)
1536	continue;
1537
1538	if ((r->flags & mask) == (parent_r->flags & mask) &&
1539	resource_contains(r1: parent_r, r2: r))
1540	request_resource(root: parent_r, new: r);
1541	}
1542	}
1543
1544	/*
1545	* Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
1546	* skipped by pbus_assign_resources_sorted().
1547	*/
1548	static void pdev_assign_fixed_resources(struct pci_dev *dev)
1549	{
1550	struct resource *r;
1551
1552	pci_dev_for_each_resource(dev, r) {
1553	struct pci_bus *b;
1554
1555	if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1556	!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1557	continue;
1558
1559	b = dev->bus;
1560	while (b && !r->parent) {
1561	assign_fixed_resource_on_bus(b, r);
1562	b = b->parent;
1563	}
1564	}
1565	}
1566
1567	void __pci_bus_assign_resources(const struct pci_bus *bus,
1568	struct list_head *realloc_head,
1569	struct list_head *fail_head)
1570	{
1571	struct pci_bus *b;
1572	struct pci_dev *dev;
1573
1574	pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1575
1576	list_for_each_entry(dev, &bus->devices, bus_list) {
1577	pdev_assign_fixed_resources(dev);
1578
1579	b = dev->subordinate;
1580	if (!b)
1581	continue;
1582
1583	__pci_bus_assign_resources(bus: b, realloc_head, fail_head);
1584
1585	switch (dev->hdr_type) {
1586	case PCI_HEADER_TYPE_BRIDGE:
1587	if (!pci_is_enabled(pdev: dev))
1588	pci_setup_bridge(bus: b);
1589	break;
1590
1591	case PCI_HEADER_TYPE_CARDBUS:
1592	pci_setup_cardbus(b);
1593	break;
1594
1595	default:
1596	pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1597	pci_domain_nr(b), b->number);
1598	break;
1599	}
1600	}
1601	}
1602
1603	void pci_bus_assign_resources(const struct pci_bus *bus)
1604	{
1605	__pci_bus_assign_resources(bus, NULL, NULL);
1606	}
1607	EXPORT_SYMBOL(pci_bus_assign_resources);
1608
1609	static void pci_claim_device_resources(struct pci_dev *dev)
1610	{
1611	int i;
1612
1613	for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1614	struct resource *r = &dev->resource[i];
1615
1616	if (!r->flags || r->parent)
1617	continue;
1618
1619	pci_claim_resource(dev, i);
1620	}
1621	}
1622
1623	static void pci_claim_bridge_resources(struct pci_dev *dev)
1624	{
1625	int i;
1626
1627	for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1628	struct resource *r = &dev->resource[i];
1629
1630	if (!r->flags || r->parent)
1631	continue;
1632
1633	pci_claim_bridge_resource(bridge: dev, i);
1634	}
1635	}
1636
1637	static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1638	{
1639	struct pci_dev *dev;
1640	struct pci_bus *child;
1641
1642	list_for_each_entry(dev, &b->devices, bus_list) {
1643	pci_claim_device_resources(dev);
1644
1645	child = dev->subordinate;
1646	if (child)
1647	pci_bus_allocate_dev_resources(b: child);
1648	}
1649	}
1650
1651	static void pci_bus_allocate_resources(struct pci_bus *b)
1652	{
1653	struct pci_bus *child;
1654
1655	/*
1656	* Carry out a depth-first search on the PCI bus tree to allocate
1657	* bridge apertures. Read the programmed bridge bases and
1658	* recursively claim the respective bridge resources.
1659	*/
1660	if (b->self) {
1661	pci_read_bridge_bases(child: b);
1662	pci_claim_bridge_resources(dev: b->self);
1663	}
1664
1665	list_for_each_entry(child, &b->children, node)
1666	pci_bus_allocate_resources(b: child);
1667	}
1668
1669	void pci_bus_claim_resources(struct pci_bus *b)
1670	{
1671	pci_bus_allocate_resources(b);
1672	pci_bus_allocate_dev_resources(b);
1673	}
1674	EXPORT_SYMBOL(pci_bus_claim_resources);
1675
1676	static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1677	struct list_head *add_head,
1678	struct list_head *fail_head)
1679	{
1680	struct pci_bus *b;
1681
1682	pdev_assign_resources_sorted(dev: (struct pci_dev *)bridge,
1683	add_head, fail_head);
1684
1685	b = bridge->subordinate;
1686	if (!b)
1687	return;
1688
1689	__pci_bus_assign_resources(bus: b, realloc_head: add_head, fail_head);
1690
1691	switch (bridge->class >> 8) {
1692	case PCI_CLASS_BRIDGE_PCI:
1693	pci_setup_bridge(bus: b);
1694	break;
1695
1696	case PCI_CLASS_BRIDGE_CARDBUS:
1697	pci_setup_cardbus(b);
1698	break;
1699
1700	default:
1701	pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1702	pci_domain_nr(b), b->number);
1703	break;
1704	}
1705	}
1706
1707	#define PCI_RES_TYPE_MASK \
1708	(IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
1709	IORESOURCE_MEM_64)
1710
1711	static void pci_bridge_release_resources(struct pci_bus *bus,
1712	unsigned long type)
1713	{
1714	struct pci_dev *dev = bus->self;
1715	struct resource *r;
1716	unsigned int old_flags;
1717	struct resource *b_res;
1718	int idx = 1;
1719
1720	b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1721
1722	/*
1723	* 1. If IO port assignment fails, release bridge IO port.
1724	* 2. If non pref MMIO assignment fails, release bridge nonpref MMIO.
1725	* 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit,
1726	* release bridge pref MMIO.
1727	* 4. If pref MMIO assignment fails, and bridge pref is 32bit,
1728	* release bridge pref MMIO.
1729	* 5. If pref MMIO assignment fails, and bridge pref is not
1730	* assigned, release bridge nonpref MMIO.
1731	*/
1732	if (type & IORESOURCE_IO)
1733	idx = 0;
1734	else if (!(type & IORESOURCE_PREFETCH))
1735	idx = 1;
1736	else if ((type & IORESOURCE_MEM_64) &&
1737	(b_res[2].flags & IORESOURCE_MEM_64))
1738	idx = 2;
1739	else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1740	(b_res[2].flags & IORESOURCE_PREFETCH))
1741	idx = 2;
1742	else
1743	idx = 1;
1744
1745	r = &b_res[idx];
1746
1747	if (!r->parent)
1748	return;
1749
1750	/* If there are children, release them all */
1751	release_child_resources(new: r);
1752	if (!release_resource(new: r)) {
1753	type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1754	pci_info(dev, "resource %d %pR released\n",
1755	PCI_BRIDGE_RESOURCES + idx, r);
1756	/* Keep the old size */
1757	resource_set_range(res: r, start: 0, size: resource_size(res: r));
1758	r->flags = 0;
1759
1760	/* Avoiding touch the one without PREF */
1761	if (type & IORESOURCE_PREFETCH)
1762	type = IORESOURCE_PREFETCH;
1763	__pci_setup_bridge(bus, type);
1764	/* For next child res under same bridge */
1765	r->flags = old_flags;
1766	}
1767	}
1768
1769	enum release_type {
1770	leaf_only,
1771	whole_subtree,
1772	};
1773
1774	/*
1775	* Try to release PCI bridge resources from leaf bridge, so we can allocate
1776	* a larger window later.
1777	*/
1778	static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1779	unsigned long type,
1780	enum release_type rel_type)
1781	{
1782	struct pci_dev *dev;
1783	bool is_leaf_bridge = true;
1784
1785	list_for_each_entry(dev, &bus->devices, bus_list) {
1786	struct pci_bus *b = dev->subordinate;
1787	if (!b)
1788	continue;
1789
1790	is_leaf_bridge = false;
1791
1792	if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1793	continue;
1794
1795	if (rel_type == whole_subtree)
1796	pci_bus_release_bridge_resources(bus: b, type,
1797	rel_type: whole_subtree);
1798	}
1799
1800	if (pci_is_root_bus(pbus: bus))
1801	return;
1802
1803	if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1804	return;
1805
1806	if ((rel_type == whole_subtree) || is_leaf_bridge)
1807	pci_bridge_release_resources(bus, type);
1808	}
1809
1810	static void pci_bus_dump_res(struct pci_bus *bus)
1811	{
1812	struct resource *res;
1813	int i;
1814
1815	pci_bus_for_each_resource(bus, res, i) {
1816	if (!res || !res->end || !res->flags)
1817	continue;
1818
1819	dev_info(&bus->dev, "resource %d %pR\n", i, res);
1820	}
1821	}
1822
1823	static void pci_bus_dump_resources(struct pci_bus *bus)
1824	{
1825	struct pci_bus *b;
1826	struct pci_dev *dev;
1827
1828
1829	pci_bus_dump_res(bus);
1830
1831	list_for_each_entry(dev, &bus->devices, bus_list) {
1832	b = dev->subordinate;
1833	if (!b)
1834	continue;
1835
1836	pci_bus_dump_resources(bus: b);
1837	}
1838	}
1839
1840	static int pci_bus_get_depth(struct pci_bus *bus)
1841	{
1842	int depth = 0;
1843	struct pci_bus *child_bus;
1844
1845	list_for_each_entry(child_bus, &bus->children, node) {
1846	int ret;
1847
1848	ret = pci_bus_get_depth(bus: child_bus);
1849	if (ret + 1 > depth)
1850	depth = ret + 1;
1851	}
1852
1853	return depth;
1854	}
1855
1856	/*
1857	* -1: undefined, will auto detect later
1858	* 0: disabled by user
1859	* 1: disabled by auto detect
1860	* 2: enabled by user
1861	* 3: enabled by auto detect
1862	*/
1863	enum enable_type {
1864	undefined = -1,
1865	user_disabled,
1866	auto_disabled,
1867	user_enabled,
1868	auto_enabled,
1869	};
1870
1871	static enum enable_type pci_realloc_enable = undefined;
1872	void __init pci_realloc_get_opt(char *str)
1873	{
1874	if (!strncmp(str, "off", 3))
1875	pci_realloc_enable = user_disabled;
1876	else if (!strncmp(str, "on", 2))
1877	pci_realloc_enable = user_enabled;
1878	}
1879	static bool pci_realloc_enabled(enum enable_type enable)
1880	{
1881	return enable >= user_enabled;
1882	}
1883
1884	#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1885	static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1886	{
1887	int i;
1888	bool *unassigned = data;
1889
1890	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1891	struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES];
1892	struct pci_bus_region region;
1893
1894	/* Not assigned or rejected by kernel? */
1895	if (!r->flags)
1896	continue;
1897
1898	pcibios_resource_to_bus(bus: dev->bus, region: &region, res: r);
1899	if (!region.start) {
1900	*unassigned = true;
1901	return 1; /* Return early from pci_walk_bus() */
1902	}
1903	}
1904
1905	return 0;
1906	}
1907
1908	static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1909	enum enable_type enable_local)
1910	{
1911	bool unassigned = false;
1912	struct pci_host_bridge *host;
1913
1914	if (enable_local != undefined)
1915	return enable_local;
1916
1917	host = pci_find_host_bridge(bus);
1918	if (host->preserve_config)
1919	return auto_disabled;
1920
1921	pci_walk_bus(top: bus, cb: iov_resources_unassigned, userdata: &unassigned);
1922	if (unassigned)
1923	return auto_enabled;
1924
1925	return enable_local;
1926	}
1927	#else
1928	static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1929	enum enable_type enable_local)
1930	{
1931	return enable_local;
1932	}
1933	#endif
1934
1935	static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res,
1936	struct list_head *add_list,
1937	resource_size_t new_size)
1938	{
1939	resource_size_t add_size, size = resource_size(res);
1940
1941	if (res->parent)
1942	return;
1943
1944	if (!new_size)
1945	return;
1946
1947	if (new_size > size) {
1948	add_size = new_size - size;
1949	pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1950	&add_size);
1951	} else if (new_size < size) {
1952	add_size = size - new_size;
1953	pci_dbg(bridge, "bridge window %pR shrunken by %pa\n", res,
1954	&add_size);
1955	} else {
1956	return;
1957	}
1958
1959	resource_set_size(res, size: new_size);
1960
1961	/* If the resource is part of the add_list, remove it now */
1962	if (add_list)
1963	remove_from_list(head: add_list, res);
1964	}
1965
1966	static void remove_dev_resource(struct resource *avail, struct pci_dev *dev,
1967	struct resource *res)
1968	{
1969	resource_size_t size, align, tmp;
1970
1971	size = resource_size(res);
1972	if (!size)
1973	return;
1974
1975	align = pci_resource_alignment(dev, res);
1976	align = align ? ALIGN(avail->start, align) - avail->start : 0;
1977	tmp = align + size;
1978	avail->start = min(avail->start + tmp, avail->end + 1);
1979	}
1980
1981	static void remove_dev_resources(struct pci_dev *dev, struct resource *io,
1982	struct resource *mmio,
1983	struct resource *mmio_pref)
1984	{
1985	struct resource *res;
1986
1987	pci_dev_for_each_resource(dev, res) {
1988	if (resource_type(res) == IORESOURCE_IO) {
1989	remove_dev_resource(avail: io, dev, res);
1990	} else if (resource_type(res) == IORESOURCE_MEM) {
1991
1992	/*
1993	* Make sure prefetchable memory is reduced from
1994	* the correct resource. Specifically we put 32-bit
1995	* prefetchable memory in non-prefetchable window
1996	* if there is a 64-bit prefetchable window.
1997	*
1998	* See comments in __pci_bus_size_bridges() for
1999	* more information.
2000	*/
2001	if ((res->flags & IORESOURCE_PREFETCH) &&
2002	((res->flags & IORESOURCE_MEM_64) ==
2003	(mmio_pref->flags & IORESOURCE_MEM_64)))
2004	remove_dev_resource(avail: mmio_pref, dev, res);
2005	else
2006	remove_dev_resource(avail: mmio, dev, res);
2007	}
2008	}
2009	}
2010
2011	#define ALIGN_DOWN_IF_NONZERO(addr, align) \
2012	((align) ? ALIGN_DOWN((addr), (align)) : (addr))
2013
2014	/*
2015	* io, mmio and mmio_pref contain the total amount of bridge window space
2016	* available. This includes the minimal space needed to cover all the
2017	* existing devices on the bus and the possible extra space that can be
2018	* shared with the bridges.
2019	*/
2020	static void pci_bus_distribute_available_resources(struct pci_bus *bus,
2021	struct list_head *add_list,
2022	struct resource io,
2023	struct resource mmio,
2024	struct resource mmio_pref)
2025	{
2026	unsigned int normal_bridges = 0, hotplug_bridges = 0;
2027	struct resource *io_res, *mmio_res, *mmio_pref_res;
2028	struct pci_dev *dev, *bridge = bus->self;
2029	resource_size_t io_per_b, mmio_per_b, mmio_pref_per_b, align;
2030
2031	io_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
2032	mmio_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
2033	mmio_pref_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
2034
2035	/*
2036	* The alignment of this bridge is yet to be considered, hence it must
2037	* be done now before extending its bridge window.
2038	*/
2039	align = pci_resource_alignment(dev: bridge, res: io_res);
2040	if (!io_res->parent && align)
2041	io.start = min(ALIGN(io.start, align), io.end + 1);
2042
2043	align = pci_resource_alignment(dev: bridge, res: mmio_res);
2044	if (!mmio_res->parent && align)
2045	mmio.start = min(ALIGN(mmio.start, align), mmio.end + 1);
2046
2047	align = pci_resource_alignment(dev: bridge, res: mmio_pref_res);
2048	if (!mmio_pref_res->parent && align)
2049	mmio_pref.start = min(ALIGN(mmio_pref.start, align),
2050	mmio_pref.end + 1);
2051
2052	/*
2053	* Now that we have adjusted for alignment, update the bridge window
2054	* resources to fill as much remaining resource space as possible.
2055	*/
2056	adjust_bridge_window(bridge, res: io_res, add_list, new_size: resource_size(res: &io));
2057	adjust_bridge_window(bridge, res: mmio_res, add_list, new_size: resource_size(res: &mmio));
2058	adjust_bridge_window(bridge, res: mmio_pref_res, add_list,
2059	new_size: resource_size(res: &mmio_pref));
2060
2061	/*
2062	* Calculate how many hotplug bridges and normal bridges there
2063	* are on this bus. We will distribute the additional available
2064	* resources between hotplug bridges.
2065	*/
2066	for_each_pci_bridge(dev, bus) {
2067	if (dev->is_hotplug_bridge)
2068	hotplug_bridges++;
2069	else
2070	normal_bridges++;
2071	}
2072
2073	if (!(hotplug_bridges + normal_bridges))
2074	return;
2075
2076	/*
2077	* Calculate the amount of space we can forward from "bus" to any
2078	* downstream buses, i.e., the space left over after assigning the
2079	* BARs and windows on "bus".
2080	*/
2081	list_for_each_entry(dev, &bus->devices, bus_list) {
2082	if (!dev->is_virtfn)
2083	remove_dev_resources(dev, io: &io, mmio: &mmio, mmio_pref: &mmio_pref);
2084	}
2085
2086	/*
2087	* If there is at least one hotplug bridge on this bus it gets all
2088	* the extra resource space that was left after the reductions
2089	* above.
2090	*
2091	* If there are no hotplug bridges the extra resource space is
2092	* split between non-hotplug bridges. This is to allow possible
2093	* hotplug bridges below them to get the extra space as well.
2094	*/
2095	if (hotplug_bridges) {
2096	io_per_b = div64_ul(resource_size(&io), hotplug_bridges);
2097	mmio_per_b = div64_ul(resource_size(&mmio), hotplug_bridges);
2098	mmio_pref_per_b = div64_ul(resource_size(&mmio_pref),
2099	hotplug_bridges);
2100	} else {
2101	io_per_b = div64_ul(resource_size(&io), normal_bridges);
2102	mmio_per_b = div64_ul(resource_size(&mmio), normal_bridges);
2103	mmio_pref_per_b = div64_ul(resource_size(&mmio_pref),
2104	normal_bridges);
2105	}
2106
2107	for_each_pci_bridge(dev, bus) {
2108	struct resource *res;
2109	struct pci_bus *b;
2110
2111	b = dev->subordinate;
2112	if (!b)
2113	continue;
2114	if (hotplug_bridges && !dev->is_hotplug_bridge)
2115	continue;
2116
2117	res = &dev->resource[PCI_BRIDGE_IO_WINDOW];
2118
2119	/*
2120	* Make sure the split resource space is properly aligned
2121	* for bridge windows (align it down to avoid going above
2122	* what is available).
2123	*/
2124	align = pci_resource_alignment(dev, res);
2125	resource_set_size(res: &io, ALIGN_DOWN_IF_NONZERO(io_per_b, align));
2126
2127	/*
2128	* The x_per_b holds the extra resource space that can be
2129	* added for each bridge but there is the minimal already
2130	* reserved as well so adjust x.start down accordingly to
2131	* cover the whole space.
2132	*/
2133	io.start -= resource_size(res);
2134
2135	res = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
2136	align = pci_resource_alignment(dev, res);
2137	resource_set_size(res: &mmio,
2138	ALIGN_DOWN_IF_NONZERO(mmio_per_b,align));
2139	mmio.start -= resource_size(res);
2140
2141	res = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
2142	align = pci_resource_alignment(dev, res);
2143	resource_set_size(res: &mmio_pref,
2144	ALIGN_DOWN_IF_NONZERO(mmio_pref_per_b, align));
2145	mmio_pref.start -= resource_size(res);
2146
2147	pci_bus_distribute_available_resources(bus: b, add_list, io, mmio,
2148	mmio_pref);
2149
2150	io.start += io.end + 1;
2151	mmio.start += mmio.end + 1;
2152	mmio_pref.start += mmio_pref.end + 1;
2153	}
2154	}
2155
2156	static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
2157	struct list_head *add_list)
2158	{
2159	struct resource available_io, available_mmio, available_mmio_pref;
2160
2161	if (!bridge->is_hotplug_bridge)
2162	return;
2163
2164	pci_dbg(bridge, "distributing available resources\n");
2165
2166	/* Take the initial extra resources from the hotplug port */
2167	available_io = bridge->resource[PCI_BRIDGE_IO_WINDOW];
2168	available_mmio = bridge->resource[PCI_BRIDGE_MEM_WINDOW];
2169	available_mmio_pref = bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
2170
2171	pci_bus_distribute_available_resources(bus: bridge->subordinate,
2172	add_list, io: available_io,
2173	mmio: available_mmio,
2174	mmio_pref: available_mmio_pref);
2175	}
2176
2177	static bool pci_bridge_resources_not_assigned(struct pci_dev *dev)
2178	{
2179	const struct resource *r;
2180
2181	/*
2182	* If the child device's resources are not yet assigned it means we
2183	* are configuring them (not the boot firmware), so we should be
2184	* able to extend the upstream bridge resources in the same way we
2185	* do with the normal hotplug case.
2186	*/
2187	r = &dev->resource[PCI_BRIDGE_IO_WINDOW];
2188	if (r->flags && !(r->flags & IORESOURCE_STARTALIGN))
2189	return false;
2190	r = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
2191	if (r->flags && !(r->flags & IORESOURCE_STARTALIGN))
2192	return false;
2193	r = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
2194	if (r->flags && !(r->flags & IORESOURCE_STARTALIGN))
2195	return false;
2196
2197	return true;
2198	}
2199
2200	static void
2201	pci_root_bus_distribute_available_resources(struct pci_bus *bus,
2202	struct list_head *add_list)
2203	{
2204	struct pci_dev *dev, *bridge = bus->self;
2205
2206	for_each_pci_bridge(dev, bus) {
2207	struct pci_bus *b;
2208
2209	b = dev->subordinate;
2210	if (!b)
2211	continue;
2212
2213	/*
2214	* Need to check "bridge" here too because it is NULL
2215	* in case of root bus.
2216	*/
2217	if (bridge && pci_bridge_resources_not_assigned(dev))
2218	pci_bridge_distribute_available_resources(bridge: dev, add_list);
2219	else
2220	pci_root_bus_distribute_available_resources(bus: b, add_list);
2221	}
2222	}
2223
2224	static void pci_prepare_next_assign_round(struct list_head *fail_head,
2225	int tried_times,
2226	enum release_type rel_type)
2227	{
2228	struct pci_dev_resource *fail_res;
2229
2230	pr_info("PCI: No. %d try to assign unassigned res\n", tried_times + 1);
2231
2232	/*
2233	* Try to release leaf bridge's resources that aren't big
2234	* enough to contain child device resources.
2235	*/
2236	list_for_each_entry(fail_res, fail_head, list) {
2237	pci_bus_release_bridge_resources(bus: fail_res->dev->bus,
2238	type: fail_res->flags & PCI_RES_TYPE_MASK,
2239	rel_type);
2240	}
2241
2242	/* Restore size and flags */
2243	list_for_each_entry(fail_res, fail_head, list) {
2244	struct resource *res = fail_res->res;
2245	struct pci_dev *dev = fail_res->dev;
2246	int idx = pci_resource_num(dev, res);
2247
2248	restore_dev_resource(dev_res: fail_res);
2249
2250	if (!pci_is_bridge(dev))
2251	continue;
2252
2253	if (idx >= PCI_BRIDGE_RESOURCES &&
2254	idx <= PCI_BRIDGE_RESOURCE_END)
2255	res->flags = 0;
2256	}
2257
2258	free_list(head: fail_head);
2259	}
2260
2261	/*
2262	* First try will not touch PCI bridge res.
2263	* Second and later try will clear small leaf bridge res.
2264	* Will stop till to the max depth if can not find good one.
2265	*/
2266	void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
2267	{
2268	LIST_HEAD(realloc_head);
2269	/* List of resources that want additional resources */
2270	struct list_head *add_list = NULL;
2271	int tried_times = 0;
2272	enum release_type rel_type = leaf_only;
2273	LIST_HEAD(fail_head);
2274	int pci_try_num = 1;
2275	enum enable_type enable_local;
2276
2277	/* Don't realloc if asked to do so */
2278	enable_local = pci_realloc_detect(bus, enable_local: pci_realloc_enable);
2279	if (pci_realloc_enabled(enable: enable_local)) {
2280	int max_depth = pci_bus_get_depth(bus);
2281
2282	pci_try_num = max_depth + 1;
2283	dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n",
2284	max_depth, pci_try_num);
2285	}
2286
2287	while (1) {
2288	/*
2289	* Last try will use add_list, otherwise will try good to
2290	* have as must have, so can realloc parent bridge resource
2291	*/
2292	if (tried_times + 1 == pci_try_num)
2293	add_list = &realloc_head;
2294	/*
2295	* Depth first, calculate sizes and alignments of all
2296	* subordinate buses.
2297	*/
2298	__pci_bus_size_bridges(bus, realloc_head: add_list);
2299
2300	pci_root_bus_distribute_available_resources(bus, add_list);
2301
2302	/* Depth last, allocate resources and update the hardware. */
2303	__pci_bus_assign_resources(bus, realloc_head: add_list, fail_head: &fail_head);
2304	if (WARN_ON_ONCE(add_list && !list_empty(add_list)))
2305	free_list(head: add_list);
2306	tried_times++;
2307
2308	/* Any device complain? */
2309	if (list_empty(head: &fail_head))
2310	break;
2311
2312	if (tried_times >= pci_try_num) {
2313	if (enable_local == undefined) {
2314	dev_info(&bus->dev,
2315	"Some PCI device resources are unassigned, try booting with pci=realloc\n");
2316	} else if (enable_local == auto_enabled) {
2317	dev_info(&bus->dev,
2318	"Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
2319	}
2320	free_list(head: &fail_head);
2321	break;
2322	}
2323
2324	/* Third times and later will not check if it is leaf */
2325	if (tried_times + 1 > 2)
2326	rel_type = whole_subtree;
2327
2328	pci_prepare_next_assign_round(fail_head: &fail_head, tried_times, rel_type);
2329	}
2330
2331	pci_bus_dump_resources(bus);
2332	}
2333
2334	void pci_assign_unassigned_resources(void)
2335	{
2336	struct pci_bus *root_bus;
2337
2338	list_for_each_entry(root_bus, &pci_root_buses, node) {
2339	pci_assign_unassigned_root_bus_resources(bus: root_bus);
2340
2341	/* Make sure the root bridge has a companion ACPI device */
2342	if (ACPI_HANDLE(root_bus->bridge))
2343	acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
2344	}
2345	}
2346
2347	void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
2348	{
2349	struct pci_bus *parent = bridge->subordinate;
2350	/* List of resources that want additional resources */
2351	LIST_HEAD(add_list);
2352	int tried_times = 0;
2353	LIST_HEAD(fail_head);
2354	int ret;
2355
2356	while (1) {
2357	__pci_bus_size_bridges(bus: parent, realloc_head: &add_list);
2358
2359	/*
2360	* Distribute remaining resources (if any) equally between
2361	* hotplug bridges below. This makes it possible to extend
2362	* the hierarchy later without running out of resources.
2363	*/
2364	pci_bridge_distribute_available_resources(bridge, add_list: &add_list);
2365
2366	__pci_bridge_assign_resources(bridge, add_head: &add_list, fail_head: &fail_head);
2367	if (WARN_ON_ONCE(!list_empty(&add_list)))
2368	free_list(head: &add_list);
2369	tried_times++;
2370
2371	if (list_empty(head: &fail_head))
2372	break;
2373
2374	if (tried_times >= 2) {
2375	/* Still fail, don't need to try more */
2376	free_list(head: &fail_head);
2377	break;
2378	}
2379
2380	pci_prepare_next_assign_round(fail_head: &fail_head, tried_times,
2381	rel_type: whole_subtree);
2382	}
2383
2384	ret = pci_reenable_device(bridge);
2385	if (ret)
2386	pci_err(bridge, "Error reenabling bridge (%d)\n", ret);
2387	pci_set_master(dev: bridge);
2388	}
2389	EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2390
2391	int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2392	{
2393	struct pci_dev_resource *dev_res;
2394	struct pci_dev *next;
2395	LIST_HEAD(saved);
2396	LIST_HEAD(added);
2397	LIST_HEAD(failed);
2398	unsigned int i;
2399	int ret;
2400
2401	down_read(sem: &pci_bus_sem);
2402
2403	/* Walk to the root hub, releasing bridge BARs when possible */
2404	next = bridge;
2405	do {
2406	bridge = next;
2407	for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2408	i++) {
2409	struct resource *res = &bridge->resource[i];
2410	const char *res_name = pci_resource_name(dev: bridge, i);
2411
2412	if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2413	continue;
2414
2415	/* Ignore BARs which are still in use */
2416	if (res->child)
2417	continue;
2418
2419	ret = add_to_list(head: &saved, dev: bridge, res, add_size: 0, min_align: 0);
2420	if (ret)
2421	goto cleanup;
2422
2423	pci_info(bridge, "%s %pR: releasing\n", res_name, res);
2424
2425	if (res->parent)
2426	release_resource(new: res);
2427	res->start = 0;
2428	res->end = 0;
2429	break;
2430	}
2431	if (i == PCI_BRIDGE_RESOURCE_END)
2432	break;
2433
2434	next = bridge->bus ? bridge->bus->self : NULL;
2435	} while (next);
2436
2437	if (list_empty(head: &saved)) {
2438	up_read(sem: &pci_bus_sem);
2439	return -ENOENT;
2440	}
2441
2442	__pci_bus_size_bridges(bus: bridge->subordinate, realloc_head: &added);
2443	__pci_bridge_assign_resources(bridge, add_head: &added, fail_head: &failed);
2444	if (WARN_ON_ONCE(!list_empty(&added)))
2445	free_list(head: &added);
2446
2447	if (!list_empty(head: &failed)) {
2448	ret = -ENOSPC;
2449	goto cleanup;
2450	}
2451
2452	list_for_each_entry(dev_res, &saved, list) {
2453	/* Skip the bridge we just assigned resources for */
2454	if (bridge == dev_res->dev)
2455	continue;
2456
2457	bridge = dev_res->dev;
2458	pci_setup_bridge(bus: bridge->subordinate);
2459	}
2460
2461	free_list(head: &saved);
2462	up_read(sem: &pci_bus_sem);
2463	return 0;
2464
2465	cleanup:
2466	/* Restore size and flags */
2467	list_for_each_entry(dev_res, &failed, list)
2468	restore_dev_resource(dev_res);
2469	free_list(head: &failed);
2470
2471	/* Revert to the old configuration */
2472	list_for_each_entry(dev_res, &saved, list) {
2473	struct resource *res = dev_res->res;
2474
2475	bridge = dev_res->dev;
2476	i = pci_resource_num(dev: bridge, res);
2477
2478	restore_dev_resource(dev_res);
2479
2480	pci_claim_resource(bridge, i);
2481	pci_setup_bridge(bus: bridge->subordinate);
2482	}
2483	free_list(head: &saved);
2484	up_read(sem: &pci_bus_sem);
2485
2486	return ret;
2487	}
2488
2489	void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2490	{
2491	struct pci_dev *dev;
2492	/* List of resources that want additional resources */
2493	LIST_HEAD(add_list);
2494
2495	down_read(sem: &pci_bus_sem);
2496	for_each_pci_bridge(dev, bus)
2497	if (pci_has_subordinate(pci_dev: dev))
2498	__pci_bus_size_bridges(bus: dev->subordinate, realloc_head: &add_list);
2499	up_read(sem: &pci_bus_sem);
2500	__pci_bus_assign_resources(bus, realloc_head: &add_list, NULL);
2501	if (WARN_ON_ONCE(!list_empty(&add_list)))
2502	free_list(head: &add_list);
2503	}
2504	EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);
2505