1/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3#ifndef _LAN966X_SERDES_REGS_H_
4#define _LAN966X_SERDES_REGS_H_
5
6#include <linux/bitfield.h>
7#include <linux/types.h>
8#include <linux/bug.h>
9
10enum lan966x_target {
11 TARGET_HSIO = 32,
12 NUM_TARGETS = 66
13};
14
15#define __REG(...) __VA_ARGS__
16
17/* HSIO:SD:SD_CFG */
18#define HSIO_SD_CFG(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 0, 0, 1, 4)
19
20#define HSIO_SD_CFG_PHY_RESET BIT(27)
21#define HSIO_SD_CFG_PHY_RESET_SET(x)\
22 FIELD_PREP(HSIO_SD_CFG_PHY_RESET, x)
23#define HSIO_SD_CFG_PHY_RESET_GET(x)\
24 FIELD_GET(HSIO_SD_CFG_PHY_RESET, x)
25
26#define HSIO_SD_CFG_TX_RESET BIT(18)
27#define HSIO_SD_CFG_TX_RESET_SET(x)\
28 FIELD_PREP(HSIO_SD_CFG_TX_RESET, x)
29#define HSIO_SD_CFG_TX_RESET_GET(x)\
30 FIELD_GET(HSIO_SD_CFG_TX_RESET, x)
31
32#define HSIO_SD_CFG_TX_RATE GENMASK(17, 16)
33#define HSIO_SD_CFG_TX_RATE_SET(x)\
34 FIELD_PREP(HSIO_SD_CFG_TX_RATE, x)
35#define HSIO_SD_CFG_TX_RATE_GET(x)\
36 FIELD_GET(HSIO_SD_CFG_TX_RATE, x)
37
38#define HSIO_SD_CFG_TX_INVERT BIT(15)
39#define HSIO_SD_CFG_TX_INVERT_SET(x)\
40 FIELD_PREP(HSIO_SD_CFG_TX_INVERT, x)
41#define HSIO_SD_CFG_TX_INVERT_GET(x)\
42 FIELD_GET(HSIO_SD_CFG_TX_INVERT, x)
43
44#define HSIO_SD_CFG_TX_EN BIT(14)
45#define HSIO_SD_CFG_TX_EN_SET(x)\
46 FIELD_PREP(HSIO_SD_CFG_TX_EN, x)
47#define HSIO_SD_CFG_TX_EN_GET(x)\
48 FIELD_GET(HSIO_SD_CFG_TX_EN, x)
49
50#define HSIO_SD_CFG_TX_DATA_EN BIT(12)
51#define HSIO_SD_CFG_TX_DATA_EN_SET(x)\
52 FIELD_PREP(HSIO_SD_CFG_TX_DATA_EN, x)
53#define HSIO_SD_CFG_TX_DATA_EN_GET(x)\
54 FIELD_GET(HSIO_SD_CFG_TX_DATA_EN, x)
55
56#define HSIO_SD_CFG_TX_CM_EN BIT(11)
57#define HSIO_SD_CFG_TX_CM_EN_SET(x)\
58 FIELD_PREP(HSIO_SD_CFG_TX_CM_EN, x)
59#define HSIO_SD_CFG_TX_CM_EN_GET(x)\
60 FIELD_GET(HSIO_SD_CFG_TX_CM_EN, x)
61
62#define HSIO_SD_CFG_LANE_10BIT_SEL BIT(10)
63#define HSIO_SD_CFG_LANE_10BIT_SEL_SET(x)\
64 FIELD_PREP(HSIO_SD_CFG_LANE_10BIT_SEL, x)
65#define HSIO_SD_CFG_LANE_10BIT_SEL_GET(x)\
66 FIELD_GET(HSIO_SD_CFG_LANE_10BIT_SEL, x)
67
68#define HSIO_SD_CFG_RX_TERM_EN BIT(9)
69#define HSIO_SD_CFG_RX_TERM_EN_SET(x)\
70 FIELD_PREP(HSIO_SD_CFG_RX_TERM_EN, x)
71#define HSIO_SD_CFG_RX_TERM_EN_GET(x)\
72 FIELD_GET(HSIO_SD_CFG_RX_TERM_EN, x)
73
74#define HSIO_SD_CFG_RX_RESET BIT(8)
75#define HSIO_SD_CFG_RX_RESET_SET(x)\
76 FIELD_PREP(HSIO_SD_CFG_RX_RESET, x)
77#define HSIO_SD_CFG_RX_RESET_GET(x)\
78 FIELD_GET(HSIO_SD_CFG_RX_RESET, x)
79
80#define HSIO_SD_CFG_RX_RATE GENMASK(7, 6)
81#define HSIO_SD_CFG_RX_RATE_SET(x)\
82 FIELD_PREP(HSIO_SD_CFG_RX_RATE, x)
83#define HSIO_SD_CFG_RX_RATE_GET(x)\
84 FIELD_GET(HSIO_SD_CFG_RX_RATE, x)
85
86#define HSIO_SD_CFG_RX_PLL_EN BIT(5)
87#define HSIO_SD_CFG_RX_PLL_EN_SET(x)\
88 FIELD_PREP(HSIO_SD_CFG_RX_PLL_EN, x)
89#define HSIO_SD_CFG_RX_PLL_EN_GET(x)\
90 FIELD_GET(HSIO_SD_CFG_RX_PLL_EN, x)
91
92#define HSIO_SD_CFG_RX_INVERT BIT(3)
93#define HSIO_SD_CFG_RX_INVERT_SET(x)\
94 FIELD_PREP(HSIO_SD_CFG_RX_INVERT, x)
95#define HSIO_SD_CFG_RX_INVERT_GET(x)\
96 FIELD_GET(HSIO_SD_CFG_RX_INVERT, x)
97
98#define HSIO_SD_CFG_RX_DATA_EN BIT(2)
99#define HSIO_SD_CFG_RX_DATA_EN_SET(x)\
100 FIELD_PREP(HSIO_SD_CFG_RX_DATA_EN, x)
101#define HSIO_SD_CFG_RX_DATA_EN_GET(x)\
102 FIELD_GET(HSIO_SD_CFG_RX_DATA_EN, x)
103
104#define HSIO_SD_CFG_LANE_LOOPBK_EN BIT(0)
105#define HSIO_SD_CFG_LANE_LOOPBK_EN_SET(x)\
106 FIELD_PREP(HSIO_SD_CFG_LANE_LOOPBK_EN, x)
107#define HSIO_SD_CFG_LANE_LOOPBK_EN_GET(x)\
108 FIELD_GET(HSIO_SD_CFG_LANE_LOOPBK_EN, x)
109
110/* HSIO:SD:MPLL_CFG */
111#define HSIO_MPLL_CFG(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 8, 0, 1, 4)
112
113#define HSIO_MPLL_CFG_REF_SSP_EN BIT(18)
114#define HSIO_MPLL_CFG_REF_SSP_EN_SET(x)\
115 FIELD_PREP(HSIO_MPLL_CFG_REF_SSP_EN, x)
116#define HSIO_MPLL_CFG_REF_SSP_EN_GET(x)\
117 FIELD_GET(HSIO_MPLL_CFG_REF_SSP_EN, x)
118
119#define HSIO_MPLL_CFG_REF_CLKDIV2 BIT(17)
120#define HSIO_MPLL_CFG_REF_CLKDIV2_SET(x)\
121 FIELD_PREP(HSIO_MPLL_CFG_REF_CLKDIV2, x)
122#define HSIO_MPLL_CFG_REF_CLKDIV2_GET(x)\
123 FIELD_GET(HSIO_MPLL_CFG_REF_CLKDIV2, x)
124
125#define HSIO_MPLL_CFG_MPLL_EN BIT(16)
126#define HSIO_MPLL_CFG_MPLL_EN_SET(x)\
127 FIELD_PREP(HSIO_MPLL_CFG_MPLL_EN, x)
128#define HSIO_MPLL_CFG_MPLL_EN_GET(x)\
129 FIELD_GET(HSIO_MPLL_CFG_MPLL_EN, x)
130
131#define HSIO_MPLL_CFG_MPLL_MULTIPLIER GENMASK(6, 0)
132#define HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(x)\
133 FIELD_PREP(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)
134#define HSIO_MPLL_CFG_MPLL_MULTIPLIER_GET(x)\
135 FIELD_GET(HSIO_MPLL_CFG_MPLL_MULTIPLIER, x)
136
137/* HSIO:SD:SD_STAT */
138#define HSIO_SD_STAT(g) __REG(TARGET_HSIO, 0, 1, 8, g, 3, 32, 12, 0, 1, 4)
139
140#define HSIO_SD_STAT_MPLL_STATE BIT(6)
141#define HSIO_SD_STAT_MPLL_STATE_SET(x)\
142 FIELD_PREP(HSIO_SD_STAT_MPLL_STATE, x)
143#define HSIO_SD_STAT_MPLL_STATE_GET(x)\
144 FIELD_GET(HSIO_SD_STAT_MPLL_STATE, x)
145
146#define HSIO_SD_STAT_TX_STATE BIT(5)
147#define HSIO_SD_STAT_TX_STATE_SET(x)\
148 FIELD_PREP(HSIO_SD_STAT_TX_STATE, x)
149#define HSIO_SD_STAT_TX_STATE_GET(x)\
150 FIELD_GET(HSIO_SD_STAT_TX_STATE, x)
151
152#define HSIO_SD_STAT_TX_CM_STATE BIT(2)
153#define HSIO_SD_STAT_TX_CM_STATE_SET(x)\
154 FIELD_PREP(HSIO_SD_STAT_TX_CM_STATE, x)
155#define HSIO_SD_STAT_TX_CM_STATE_GET(x)\
156 FIELD_GET(HSIO_SD_STAT_TX_CM_STATE, x)
157
158#define HSIO_SD_STAT_RX_PLL_STATE BIT(0)
159#define HSIO_SD_STAT_RX_PLL_STATE_SET(x)\
160 FIELD_PREP(HSIO_SD_STAT_RX_PLL_STATE, x)
161#define HSIO_SD_STAT_RX_PLL_STATE_GET(x)\
162 FIELD_GET(HSIO_SD_STAT_RX_PLL_STATE, x)
163
164/* HSIO:HW_CFGSTAT:HW_CFG */
165#define HSIO_HW_CFG __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 0, 0, 1, 4)
166
167#define HSIO_HW_CFG_RGMII_1_CFG BIT(15)
168#define HSIO_HW_CFG_RGMII_1_CFG_SET(x)\
169 (((x) << 15) & GENMASK(15, 15))
170#define HSIO_HW_CFG_RGMII_1_CFG_GET(x)\
171 FIELD_GET(HSIO_HW_CFG_RGMII_1_CFG, x)
172
173#define HSIO_HW_CFG_RGMII_0_CFG BIT(14)
174#define HSIO_HW_CFG_RGMII_0_CFG_SET(x)\
175 (((x) << 14) & GENMASK(14, 14))
176#define HSIO_HW_CFG_RGMII_0_CFG_GET(x)\
177 FIELD_GET(HSIO_HW_CFG_RGMII_0_CFG, x)
178
179#define HSIO_HW_CFG_RGMII_ENA GENMASK(13, 12)
180#define HSIO_HW_CFG_RGMII_ENA_SET(x)\
181 (((x) << 12) & GENMASK(13, 12))
182#define HSIO_HW_CFG_RGMII_ENA_GET(x)\
183 FIELD_GET(HSIO_HW_CFG_RGMII_ENA, x)
184
185#define HSIO_HW_CFG_SD6G_0_CFG BIT(11)
186#define HSIO_HW_CFG_SD6G_0_CFG_SET(x)\
187 (((x) << 11) & GENMASK(11, 11))
188#define HSIO_HW_CFG_SD6G_0_CFG_GET(x)\
189 FIELD_GET(HSIO_HW_CFG_SD6G_0_CFG, x)
190
191#define HSIO_HW_CFG_SD6G_1_CFG BIT(10)
192#define HSIO_HW_CFG_SD6G_1_CFG_SET(x)\
193 (((x) << 10) & GENMASK(10, 10))
194#define HSIO_HW_CFG_SD6G_1_CFG_GET(x)\
195 FIELD_GET(HSIO_HW_CFG_SD6G_1_CFG, x)
196
197#define HSIO_HW_CFG_GMII_ENA GENMASK(9, 2)
198#define HSIO_HW_CFG_GMII_ENA_SET(x)\
199 (((x) << 2) & GENMASK(9, 2))
200#define HSIO_HW_CFG_GMII_ENA_GET(x)\
201 FIELD_GET(HSIO_HW_CFG_GMII_ENA, x)
202
203#define HSIO_HW_CFG_QSGMII_ENA GENMASK(1, 0)
204#define HSIO_HW_CFG_QSGMII_ENA_SET(x)\
205 ((x) & GENMASK(1, 0))
206#define HSIO_HW_CFG_QSGMII_ENA_GET(x)\
207 FIELD_GET(HSIO_HW_CFG_QSGMII_ENA, x)
208
209/* HSIO:HW_CFGSTAT:RGMII_CFG */
210#define HSIO_RGMII_CFG(r) __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 20, r, 2, 4)
211
212#define HSIO_RGMII_CFG_TX_CLK_CFG GENMASK(4, 2)
213#define HSIO_RGMII_CFG_TX_CLK_CFG_SET(x)\
214 FIELD_PREP(HSIO_RGMII_CFG_TX_CLK_CFG, x)
215#define HSIO_RGMII_CFG_TX_CLK_CFG_GET(x)\
216 FIELD_GET(HSIO_RGMII_CFG_TX_CLK_CFG, x)
217
218#define HSIO_RGMII_CFG_RGMII_TX_RST BIT(1)
219#define HSIO_RGMII_CFG_RGMII_TX_RST_SET(x)\
220 FIELD_PREP(HSIO_RGMII_CFG_RGMII_TX_RST, x)
221#define HSIO_RGMII_CFG_RGMII_TX_RST_GET(x)\
222 FIELD_GET(HSIO_RGMII_CFG_RGMII_TX_RST, x)
223
224#define HSIO_RGMII_CFG_RGMII_RX_RST BIT(0)
225#define HSIO_RGMII_CFG_RGMII_RX_RST_SET(x)\
226 FIELD_PREP(HSIO_RGMII_CFG_RGMII_RX_RST, x)
227#define HSIO_RGMII_CFG_RGMII_RX_RST_GET(x)\
228 FIELD_GET(HSIO_RGMII_CFG_RGMII_RX_RST, x)
229
230/* HSIO:HW_CFGSTAT:DLL_CFG */
231#define HSIO_DLL_CFG(r) __REG(TARGET_HSIO, 0, 1, 104, 0, 1, 52, 36, r, 4, 4)
232
233#define HSIO_DLL_CFG_DELAY_ENA BIT(2)
234#define HSIO_DLL_CFG_DELAY_ENA_SET(x)\
235 FIELD_PREP(HSIO_DLL_CFG_DELAY_ENA, x)
236#define HSIO_DLL_CFG_DELAY_ENA_GET(x)\
237 FIELD_GET(HSIO_DLL_CFG_DELAY_ENA, x)
238
239#define HSIO_DLL_CFG_DLL_ENA BIT(1)
240#define HSIO_DLL_CFG_DLL_ENA_SET(x)\
241 FIELD_PREP(HSIO_DLL_CFG_DLL_ENA, x)
242#define HSIO_DLL_CFG_DLL_ENA_GET(x)\
243 FIELD_GET(HSIO_DLL_CFG_DLL_ENA, x)
244
245#define HSIO_DLL_CFG_DLL_RST BIT(0)
246#define HSIO_DLL_CFG_DLL_RST_SET(x)\
247 FIELD_PREP(HSIO_DLL_CFG_DLL_RST, x)
248#define HSIO_DLL_CFG_DLL_RST_GET(x)\
249 FIELD_GET(HSIO_DLL_CFG_DLL_RST, x)
250
251#endif /* _LAN966X_HSIO_REGS_H_ */
252

source code of linux/drivers/phy/microchip/lan966x_serdes_regs.h