| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2023, Linaro Limited |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_ |
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| 7 | #define QCOM_PHY_QMP_PCS_UFS_V6_H_ |
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| 8 | |
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| 9 | /* Only for QMP V6 PHY - UFS PCS registers */ |
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| 10 | #define QPHY_V6_PCS_UFS_PHY_START 0x000 |
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| 11 | #define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004 |
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| 12 | #define QPHY_V6_PCS_UFS_SW_RESET 0x008 |
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| 13 | #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c |
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| 14 | #define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 |
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| 15 | #define QPHY_V6_PCS_UFS_PCS_CTRL1 0x020 |
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| 16 | #define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c |
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| 17 | #define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 |
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| 18 | #define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 |
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| 19 | #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 |
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| 20 | #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 |
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| 21 | #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc |
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| 22 | #define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c |
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| 23 | #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158 |
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| 24 | #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c |
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| 25 | #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184 |
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| 26 | #define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c |
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| 27 | #define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x178 |
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| 28 | #define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x174 |
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| 29 | #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8 |
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| 30 | #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4 |
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| 31 | #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc |
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| 32 | #define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220 |
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| 33 | |
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| 34 | #endif |
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| 35 | |
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