| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_PCS_V2_H_ |
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| 7 | #define QCOM_PHY_QMP_PCS_V2_H_ |
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| 8 | |
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| 9 | /* Only for QMP V2 PHY - PCS registers */ |
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| 10 | #define QPHY_V2_PCS_SW_RESET 0x000 |
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| 11 | #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004 |
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| 12 | #define QPHY_V2_PCS_START_CONTROL 0x008 |
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| 13 | #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024 |
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| 14 | #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028 |
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| 15 | #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054 |
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| 16 | #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058 |
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| 17 | #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060 |
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| 18 | #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064 |
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| 19 | #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c |
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| 20 | #define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x080 |
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| 21 | #define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x084 |
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| 22 | #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088 |
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| 23 | #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 |
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| 24 | #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 |
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| 25 | #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 |
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| 26 | #define QPHY_V2_PCS_FLL_CNTRL1 0x0c0 |
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| 27 | #define QPHY_V2_PCS_FLL_CNTRL2 0x0c4 |
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| 28 | #define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8 |
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| 29 | #define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc |
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| 30 | #define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0 |
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| 31 | #define QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL 0x0d4 |
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| 32 | #define QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0d8 |
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| 33 | #define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS 0x178 |
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| 34 | #define QPHY_V2_PCS_USB_PCS_STATUS 0x17c /* USB */ |
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| 35 | #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 |
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| 36 | #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac |
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| 37 | #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 |
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| 38 | #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc |
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| 39 | #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 |
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| 40 | |
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| 41 | #define QPHY_V2_PCS_PCI_PCS_STATUS 0x174 /* PCI */ |
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| 42 | |
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| 43 | #endif |
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| 44 | |
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