| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_PCS_V4_H_ |
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| 7 | #define QCOM_PHY_QMP_PCS_V4_H_ |
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| 8 | |
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| 9 | /* Only for QMP V4 PHY - USB/PCIe PCS registers */ |
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| 10 | #define QPHY_V4_PCS_SW_RESET 0x000 |
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| 11 | #define QPHY_V4_PCS_REVISION_ID0 0x004 |
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| 12 | #define QPHY_V4_PCS_REVISION_ID1 0x008 |
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| 13 | #define QPHY_V4_PCS_REVISION_ID2 0x00c |
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| 14 | #define QPHY_V4_PCS_REVISION_ID3 0x010 |
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| 15 | #define QPHY_V4_PCS_PCS_STATUS1 0x014 |
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| 16 | #define QPHY_V4_PCS_PCS_STATUS2 0x018 |
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| 17 | #define QPHY_V4_PCS_PCS_STATUS3 0x01c |
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| 18 | #define QPHY_V4_PCS_PCS_STATUS4 0x020 |
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| 19 | #define QPHY_V4_PCS_PCS_STATUS5 0x024 |
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| 20 | #define QPHY_V4_PCS_PCS_STATUS6 0x028 |
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| 21 | #define QPHY_V4_PCS_PCS_STATUS7 0x02c |
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| 22 | #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 |
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| 23 | #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 |
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| 24 | #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 |
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| 25 | #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c |
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| 26 | #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 |
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| 27 | #define QPHY_V4_PCS_START_CONTROL 0x044 |
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| 28 | #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 |
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| 29 | #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c |
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| 30 | #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 |
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| 31 | #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 |
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| 32 | #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 |
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| 33 | #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c |
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| 34 | #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 |
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| 35 | #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 |
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| 36 | #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 |
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| 37 | #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c |
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| 38 | #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 |
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| 39 | #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 |
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| 40 | #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 |
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| 41 | #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c |
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| 42 | #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 |
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| 43 | #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 |
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| 44 | #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 |
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| 45 | #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c |
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| 46 | #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 |
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| 47 | #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 |
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| 48 | #define QPHY_V4_PCS_FLL_CNTRL1 0x098 |
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| 49 | #define QPHY_V4_PCS_FLL_CNTRL2 0x09c |
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| 50 | #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 |
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| 51 | #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 |
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| 52 | #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 |
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| 53 | #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac |
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| 54 | #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 |
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| 55 | #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 |
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| 56 | #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 |
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| 57 | #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc |
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| 58 | #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 |
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| 59 | #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 |
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| 60 | #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 |
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| 61 | #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc |
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| 62 | #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 |
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| 63 | #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 |
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| 64 | #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 |
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| 65 | #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc |
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| 66 | #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 |
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| 67 | #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 |
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| 68 | #define QPHY_V4_PCS_BIST_CTRL 0x0e8 |
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| 69 | #define QPHY_V4_PCS_PRBS_POLY0 0x0ec |
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| 70 | #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 |
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| 71 | #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 |
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| 72 | #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 |
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| 73 | #define QPHY_V4_PCS_FIXED_PAT2 0x0fc |
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| 74 | #define QPHY_V4_PCS_FIXED_PAT3 0x100 |
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| 75 | #define QPHY_V4_PCS_FIXED_PAT4 0x104 |
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| 76 | #define QPHY_V4_PCS_FIXED_PAT5 0x108 |
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| 77 | #define QPHY_V4_PCS_FIXED_PAT6 0x10c |
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| 78 | #define QPHY_V4_PCS_FIXED_PAT7 0x110 |
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| 79 | #define QPHY_V4_PCS_FIXED_PAT8 0x114 |
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| 80 | #define QPHY_V4_PCS_FIXED_PAT9 0x118 |
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| 81 | #define QPHY_V4_PCS_FIXED_PAT10 0x11c |
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| 82 | #define QPHY_V4_PCS_FIXED_PAT11 0x120 |
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| 83 | #define QPHY_V4_PCS_FIXED_PAT12 0x124 |
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| 84 | #define QPHY_V4_PCS_FIXED_PAT13 0x128 |
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| 85 | #define QPHY_V4_PCS_FIXED_PAT14 0x12c |
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| 86 | #define QPHY_V4_PCS_FIXED_PAT15 0x130 |
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| 87 | #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 |
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| 88 | #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 |
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| 89 | #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c |
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| 90 | #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 |
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| 91 | #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 |
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| 92 | #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 |
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| 93 | #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c |
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| 94 | #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 |
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| 95 | #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 |
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| 96 | #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 |
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| 97 | #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c |
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| 98 | #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 |
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| 99 | #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 |
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| 100 | #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 |
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| 101 | #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c |
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| 102 | #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 |
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| 103 | #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 |
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| 104 | #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 |
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| 105 | #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c |
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| 106 | #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 |
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| 107 | #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 |
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| 108 | #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 |
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| 109 | #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c |
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| 110 | #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 |
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| 111 | #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 |
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| 112 | #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 |
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| 113 | #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c |
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| 114 | #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 |
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| 115 | #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 |
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| 116 | #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 |
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| 117 | #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac |
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| 118 | #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 |
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| 119 | #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 |
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| 120 | #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 |
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| 121 | #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc |
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| 122 | #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 |
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| 123 | #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 |
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| 124 | #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 |
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| 125 | #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc |
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| 126 | #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 |
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| 127 | #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 |
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| 128 | #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 |
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| 129 | #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc |
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| 130 | #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 |
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| 131 | #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 |
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| 132 | #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 |
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| 133 | #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec |
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| 134 | |
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| 135 | #endif |
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| 136 | |
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