| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_QSERDES_COM_V5_H_ |
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| 7 | #define QCOM_PHY_QMP_QSERDES_COM_V5_H_ |
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| 8 | |
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| 9 | /* Only for QMP V5 PHY - QSERDES COM registers */ |
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| 10 | #define QSERDES_V5_COM_ATB_SEL1 0x000 |
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| 11 | #define QSERDES_V5_COM_ATB_SEL2 0x004 |
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| 12 | #define QSERDES_V5_COM_FREQ_UPDATE 0x008 |
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| 13 | #define QSERDES_V5_COM_BG_TIMER 0x00c |
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| 14 | #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 |
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| 15 | #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014 |
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| 16 | #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018 |
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| 17 | #define QSERDES_V5_COM_SSC_PER1 0x01c |
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| 18 | #define QSERDES_V5_COM_SSC_PER2 0x020 |
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| 19 | #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 |
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| 20 | #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 |
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| 21 | #define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE0 0x02c |
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| 22 | #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 |
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| 23 | #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 |
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| 24 | #define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE1 0x038 |
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| 25 | #define QSERDES_V5_COM_POST_DIV 0x03c |
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| 26 | #define QSERDES_V5_COM_POST_DIV_MUX 0x040 |
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| 27 | #define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 |
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| 28 | #define QSERDES_V5_COM_CLK_ENABLE1 0x048 |
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| 29 | #define QSERDES_V5_COM_SYS_CLK_CTRL 0x04c |
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| 30 | #define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 |
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| 31 | #define QSERDES_V5_COM_PLL_EN 0x054 |
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| 32 | #define QSERDES_V5_COM_PLL_IVCO 0x058 |
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| 33 | #define QSERDES_V5_COM_CMN_IETRIM 0x05c |
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| 34 | #define QSERDES_V5_COM_CMN_IPTRIM 0x060 |
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| 35 | #define QSERDES_V5_COM_EP_CLOCK_DETECT_CTRL 0x064 |
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| 36 | #define QSERDES_V5_COM_SYSCLK_DET_COMP_STATUS 0x068 |
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| 37 | #define QSERDES_V5_COM_CLK_EP_DIV_MODE0 0x06c |
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| 38 | #define QSERDES_V5_COM_CLK_EP_DIV_MODE1 0x070 |
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| 39 | #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 |
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| 40 | #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 |
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| 41 | #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c |
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| 42 | #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 |
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| 43 | #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 |
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| 44 | #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 |
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| 45 | #define QSERDES_V5_COM_PLL_CNTRL 0x08c |
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| 46 | #define QSERDES_V5_COM_BIAS_EN_CTRL_BY_PSM 0x090 |
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| 47 | #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 |
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| 48 | #define QSERDES_V5_COM_CML_SYSCLK_SEL 0x098 |
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| 49 | #define QSERDES_V5_COM_RESETSM_CNTRL 0x09c |
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| 50 | #define QSERDES_V5_COM_RESETSM_CNTRL2 0x0a0 |
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| 51 | #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 |
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| 52 | #define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 |
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| 53 | #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac |
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| 54 | #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 |
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| 55 | #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 |
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| 56 | #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 |
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| 57 | #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc |
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| 58 | #define QSERDES_V5_COM_DEC_START_MSB_MODE0 0x0c0 |
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| 59 | #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 |
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| 60 | #define QSERDES_V5_COM_DEC_START_MSB_MODE1 0x0c8 |
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| 61 | #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc |
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| 62 | #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 |
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| 63 | #define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 |
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| 64 | #define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 |
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| 65 | #define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc |
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| 66 | #define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 |
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| 67 | #define QSERDES_V5_COM_INTEGLOOP_INITVAL 0x0e4 |
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| 68 | #define QSERDES_V5_COM_INTEGLOOP_EN 0x0e8 |
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| 69 | #define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0 0x0ec |
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| 70 | #define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 |
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| 71 | #define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 |
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| 72 | #define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 |
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| 73 | #define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc |
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| 74 | #define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN1 0x100 |
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| 75 | #define QSERDES_V5_COM_VCOCAL_DEADMAN_CTRL 0x104 |
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| 76 | #define QSERDES_V5_COM_VCO_TUNE_CTRL 0x108 |
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| 77 | #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c |
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| 78 | #define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 |
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| 79 | #define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 |
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| 80 | #define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 |
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| 81 | #define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c |
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| 82 | #define QSERDES_V5_COM_VCO_TUNE_INITVAL1 0x120 |
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| 83 | #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 |
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| 84 | #define QSERDES_V5_COM_VCO_TUNE_MINVAL1 0x128 |
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| 85 | #define QSERDES_V5_COM_VCO_TUNE_MINVAL2 0x12c |
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| 86 | #define QSERDES_V5_COM_VCO_TUNE_MAXVAL1 0x130 |
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| 87 | #define QSERDES_V5_COM_VCO_TUNE_MAXVAL2 0x134 |
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| 88 | #define QSERDES_V5_COM_VCO_TUNE_TIMER1 0x138 |
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| 89 | #define QSERDES_V5_COM_VCO_TUNE_TIMER2 0x13c |
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| 90 | #define QSERDES_V5_COM_CMN_STATUS 0x140 |
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| 91 | #define QSERDES_V5_COM_RESET_SM_STATUS 0x144 |
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| 92 | #define QSERDES_V5_COM_RESTRIM_CODE_STATUS 0x148 |
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| 93 | #define QSERDES_V5_COM_PLLCAL_CODE1_STATUS 0x14c |
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| 94 | #define QSERDES_V5_COM_PLLCAL_CODE2_STATUS 0x150 |
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| 95 | #define QSERDES_V5_COM_CLK_SELECT 0x154 |
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| 96 | #define QSERDES_V5_COM_HSCLK_SEL 0x158 |
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| 97 | #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c |
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| 98 | #define QSERDES_V5_COM_INTEGLOOP_BINCODE_STATUS 0x160 |
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| 99 | #define QSERDES_V5_COM_PLL_ANALOG 0x164 |
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| 100 | #define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 |
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| 101 | #define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c |
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| 102 | #define QSERDES_V5_COM_SW_RESET 0x170 |
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| 103 | #define QSERDES_V5_COM_CORE_CLK_EN 0x174 |
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| 104 | #define QSERDES_V5_COM_C_READY_STATUS 0x178 |
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| 105 | #define QSERDES_V5_COM_CMN_CONFIG 0x17c |
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| 106 | #define QSERDES_V5_COM_CMN_RATE_OVERRIDE 0x180 |
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| 107 | #define QSERDES_V5_COM_SVS_MODE_CLK_SEL 0x184 |
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| 108 | #define QSERDES_V5_COM_DEBUG_BUS0 0x188 |
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| 109 | #define QSERDES_V5_COM_DEBUG_BUS1 0x18c |
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| 110 | #define QSERDES_V5_COM_DEBUG_BUS2 0x190 |
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| 111 | #define QSERDES_V5_COM_DEBUG_BUS3 0x194 |
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| 112 | #define QSERDES_V5_COM_DEBUG_BUS_SEL 0x198 |
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| 113 | #define QSERDES_V5_COM_CMN_MISC1 0x19c |
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| 114 | #define QSERDES_V5_COM_CMN_MODE 0x1a0 |
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| 115 | #define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 |
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| 116 | #define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 |
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| 117 | #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac |
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| 118 | #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 |
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| 119 | #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 |
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| 120 | #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 |
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| 121 | #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc |
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| 122 | #define QSERDES_V5_COM_RESERVED_1 0x1c0 |
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| 123 | |
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| 124 | #endif |
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| 125 | |
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