| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_QSERDES_PLL_H_ |
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| 7 | #define QCOM_PHY_QMP_QSERDES_PLL_H_ |
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| 8 | |
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| 9 | /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ |
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| 10 | #define QSERDES_PLL_BG_TIMER 0x00c |
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| 11 | #define QSERDES_PLL_SSC_PER1 0x01c |
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| 12 | #define QSERDES_PLL_SSC_PER2 0x020 |
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| 13 | #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 |
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| 14 | #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 |
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| 15 | #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c |
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| 16 | #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 |
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| 17 | #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c |
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| 18 | #define QSERDES_PLL_CLK_ENABLE1 0x040 |
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| 19 | #define QSERDES_PLL_SYS_CLK_CTRL 0x044 |
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| 20 | #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 |
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| 21 | #define QSERDES_PLL_PLL_IVCO 0x050 |
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| 22 | #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 |
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| 23 | #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 |
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| 24 | #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 |
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| 25 | #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 |
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| 26 | #define QSERDES_PLL_BG_TRIM 0x074 |
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| 27 | #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 |
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| 28 | #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c |
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| 29 | #define QSERDES_PLL_CP_CTRL_MODE0 0x080 |
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| 30 | #define QSERDES_PLL_CP_CTRL_MODE1 0x084 |
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| 31 | #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 |
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| 32 | #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c |
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| 33 | #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 |
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| 34 | #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 |
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| 35 | #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 |
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| 36 | #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 |
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| 37 | #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 |
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| 38 | #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 |
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| 39 | #define QSERDES_PLL_DEC_START_MODE0 0x0cc |
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| 40 | #define QSERDES_PLL_DEC_START_MODE1 0x0d0 |
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| 41 | #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 |
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| 42 | #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc |
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| 43 | #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 |
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| 44 | #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 |
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| 45 | #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 |
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| 46 | #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec |
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| 47 | #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 |
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| 48 | #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 |
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| 49 | #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 |
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| 50 | #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c |
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| 51 | #define QSERDES_PLL_VCO_TUNE_MAP 0x120 |
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| 52 | #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 |
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| 53 | #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 |
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| 54 | #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c |
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| 55 | #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 |
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| 56 | #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c |
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| 57 | #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 |
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| 58 | #define QSERDES_PLL_CLK_SELECT 0x16c |
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| 59 | #define QSERDES_PLL_HSCLK_SEL 0x170 |
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| 60 | #define QSERDES_PLL_CORECLK_DIV 0x17c |
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| 61 | #define QSERDES_PLL_CORE_CLK_EN 0x184 |
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| 62 | #define QSERDES_PLL_CMN_CONFIG 0x18c |
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| 63 | #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 |
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| 64 | #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 |
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| 65 | |
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| 66 | #endif |
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| 67 | |
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