| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2023, Linaro Limited |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_ |
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| 7 | #define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_ |
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| 8 | |
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| 9 | #define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28 |
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| 10 | #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c |
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| 11 | #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30 |
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| 12 | #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34 |
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| 13 | #define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c |
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| 14 | #define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108 |
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| 15 | |
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| 16 | #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 |
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| 17 | #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 |
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| 18 | #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24 |
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| 19 | #define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION 0x28 |
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| 20 | #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54 |
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| 21 | #define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1 0x58 |
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| 22 | #define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0 0xc4 |
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| 23 | #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4 |
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| 24 | #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc |
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| 25 | #define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0 |
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| 26 | #define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4 |
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| 27 | #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 |
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| 28 | #define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc |
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| 29 | #define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0 |
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| 30 | #define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4 |
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| 31 | #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 |
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| 32 | #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c |
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| 33 | #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214 |
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| 34 | #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220 |
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| 35 | #define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238 |
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| 36 | #define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244 |
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| 37 | #define QSERDES_UFS_V6_RX_MODE_RATE3_B3 0x25c |
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| 38 | #define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260 |
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| 39 | #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264 |
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| 40 | #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270 |
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| 41 | #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280 |
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| 42 | #define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284 |
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| 43 | #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c |
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| 44 | #define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8 |
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| 45 | |
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| 46 | #endif |
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| 47 | |
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