| 1 | |
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| 2 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 3 | /* |
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| 4 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ |
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| 8 | #define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ |
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| 9 | |
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| 10 | /* Only for QMP V5 PHY - TX registers */ |
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| 11 | #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000 |
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| 12 | #define QSERDES_V5_TX_BIST_INVERT 0x004 |
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| 13 | #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008 |
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| 14 | #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c |
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| 15 | #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010 |
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| 16 | #define QSERDES_V5_TX_TX_DRV_LVL 0x014 |
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| 17 | #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018 |
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| 18 | #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c |
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| 19 | #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020 |
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| 20 | #define QSERDES_V5_TX_TX_BAND 0x024 |
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| 21 | #define QSERDES_V5_TX_SLEW_CNTL 0x028 |
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| 22 | #define QSERDES_V5_TX_INTERFACE_SELECT 0x02c |
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| 23 | #define QSERDES_V5_TX_LPB_EN 0x030 |
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| 24 | #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034 |
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| 25 | #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038 |
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| 26 | #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c |
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| 27 | #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040 |
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| 28 | #define QSERDES_V5_TX_PERL_LENGTH1 0x044 |
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| 29 | #define QSERDES_V5_TX_PERL_LENGTH2 0x048 |
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| 30 | #define QSERDES_V5_TX_SERDES_BYP_EN_OUT 0x04c |
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| 31 | #define QSERDES_V5_TX_DEBUG_BUS_SEL 0x050 |
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| 32 | #define QSERDES_V5_TX_TRANSCEIVER_BIAS_EN 0x054 |
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| 33 | #define QSERDES_V5_TX_HIGHZ_DRVR_EN 0x058 |
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| 34 | #define QSERDES_V5_TX_TX_POL_INV 0x05c |
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| 35 | #define QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN 0x060 |
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| 36 | #define QSERDES_V5_TX_BIST_PATTERN1 0x064 |
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| 37 | #define QSERDES_V5_TX_BIST_PATTERN2 0x068 |
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| 38 | #define QSERDES_V5_TX_BIST_PATTERN3 0x06c |
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| 39 | #define QSERDES_V5_TX_BIST_PATTERN4 0x070 |
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| 40 | #define QSERDES_V5_TX_BIST_PATTERN5 0x074 |
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| 41 | #define QSERDES_V5_TX_BIST_PATTERN6 0x078 |
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| 42 | #define QSERDES_V5_TX_BIST_PATTERN7 0x07c |
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| 43 | #define QSERDES_V5_TX_BIST_PATTERN8 0x080 |
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| 44 | #define QSERDES_V5_TX_LANE_MODE_1 0x084 |
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| 45 | #define QSERDES_V5_TX_LANE_MODE_2 0x088 |
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| 46 | #define QSERDES_V5_TX_LANE_MODE_3 0x08c |
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| 47 | #define QSERDES_V5_TX_LANE_MODE_4 0x090 |
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| 48 | #define QSERDES_V5_TX_LANE_MODE_5 0x094 |
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| 49 | #define QSERDES_V5_TX_ATB_SEL1 0x098 |
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| 50 | #define QSERDES_V5_TX_ATB_SEL2 0x09c |
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| 51 | #define QSERDES_V5_TX_RCV_DETECT_LVL 0x0a0 |
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| 52 | #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4 |
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| 53 | #define QSERDES_V5_TX_PRBS_SEED1 0x0a8 |
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| 54 | #define QSERDES_V5_TX_PRBS_SEED2 0x0ac |
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| 55 | #define QSERDES_V5_TX_PRBS_SEED3 0x0b0 |
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| 56 | #define QSERDES_V5_TX_PRBS_SEED4 0x0b4 |
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| 57 | #define QSERDES_V5_TX_RESET_GEN 0x0b8 |
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| 58 | #define QSERDES_V5_TX_RESET_GEN_MUXES 0x0bc |
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| 59 | #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0 |
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| 60 | #define QSERDES_V5_TX_TX_INTERFACE_MODE 0x0c4 |
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| 61 | #define QSERDES_V5_TX_VMODE_CTRL1 0x0c8 |
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| 62 | #define QSERDES_V5_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc |
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| 63 | #define QSERDES_V5_TX_BIST_STATUS 0x0d0 |
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| 64 | #define QSERDES_V5_TX_BIST_ERROR_COUNT1 0x0d4 |
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| 65 | #define QSERDES_V5_TX_BIST_ERROR_COUNT2 0x0d8 |
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| 66 | #define QSERDES_V5_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc |
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| 67 | #define QSERDES_V5_TX_LANE_DIG_CONFIG 0x0e0 |
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| 68 | #define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4 |
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| 69 | #define QSERDES_V5_TX_PRE_EMPH 0x0e8 |
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| 70 | #define QSERDES_V5_TX_SW_RESET 0x0ec |
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| 71 | #define QSERDES_V5_TX_DCC_OFFSET 0x0f0 |
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| 72 | #define QSERDES_V5_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4 |
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| 73 | #define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL1 0x0f8 |
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| 74 | #define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL2 0x0fc |
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| 75 | #define QSERDES_V5_TX_DIG_BKUP_CTRL 0x100 |
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| 76 | #define QSERDES_V5_TX_DEBUG_BUS0 0x104 |
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| 77 | #define QSERDES_V5_TX_DEBUG_BUS1 0x108 |
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| 78 | #define QSERDES_V5_TX_DEBUG_BUS2 0x10c |
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| 79 | #define QSERDES_V5_TX_DEBUG_BUS3 0x110 |
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| 80 | #define QSERDES_V5_TX_READ_EQCODE 0x114 |
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| 81 | #define QSERDES_V5_TX_READ_OFFSETCODE 0x118 |
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| 82 | #define QSERDES_V5_TX_IA_ERROR_COUNTER_LOW 0x11c |
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| 83 | #define QSERDES_V5_TX_IA_ERROR_COUNTER_HIGH 0x120 |
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| 84 | #define QSERDES_V5_TX_VGA_READ_CODE 0x124 |
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| 85 | #define QSERDES_V5_TX_VTH_READ_CODE 0x128 |
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| 86 | #define QSERDES_V5_TX_DFE_TAP1_READ_CODE 0x12c |
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| 87 | #define QSERDES_V5_TX_DFE_TAP2_READ_CODE 0x130 |
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| 88 | #define QSERDES_V5_TX_IDAC_STATUS_I 0x134 |
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| 89 | #define QSERDES_V5_TX_IDAC_STATUS_IBAR 0x138 |
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| 90 | #define QSERDES_V5_TX_IDAC_STATUS_Q 0x13c |
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| 91 | #define QSERDES_V5_TX_IDAC_STATUS_QBAR 0x140 |
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| 92 | #define QSERDES_V5_TX_IDAC_STATUS_A 0x144 |
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| 93 | #define QSERDES_V5_TX_IDAC_STATUS_ABAR 0x148 |
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| 94 | #define QSERDES_V5_TX_IDAC_STATUS_SM_ON 0x14c |
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| 95 | #define QSERDES_V5_TX_IDAC_STATUS_CAL_DONE 0x150 |
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| 96 | #define QSERDES_V5_TX_IDAC_STATUS_SIGNERROR 0x154 |
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| 97 | #define QSERDES_V5_TX_DCC_CAL_STATUS 0x158 |
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| 98 | #define QSERDES_V5_TX_DCC_READ_CODE_STATUS 0x15c |
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| 99 | |
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| 100 | /* Only for QMP V5 PHY - RX registers */ |
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| 101 | #define QSERDES_V5_RX_UCDR_FO_GAIN_HALF 0x000 |
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| 102 | #define QSERDES_V5_RX_UCDR_FO_GAIN_QUARTER 0x004 |
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| 103 | #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 |
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| 104 | #define QSERDES_V5_RX_UCDR_SO_GAIN_HALF 0x00c |
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| 105 | #define QSERDES_V5_RX_UCDR_SO_GAIN_QUARTER 0x010 |
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| 106 | #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 |
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| 107 | #define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_HALF 0x018 |
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| 108 | #define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c |
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| 109 | #define QSERDES_V5_RX_UCDR_SVS_FO_GAIN 0x020 |
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| 110 | #define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_HALF 0x024 |
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| 111 | #define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 |
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| 112 | #define QSERDES_V5_RX_UCDR_SVS_SO_GAIN 0x02c |
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| 113 | #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 |
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| 114 | #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 |
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| 115 | #define QSERDES_V5_RX_UCDR_FO_TO_SO_DELAY 0x038 |
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| 116 | #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c |
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| 117 | #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 |
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| 118 | #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 |
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| 119 | #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 |
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| 120 | #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c |
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| 121 | #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 |
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| 122 | #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 |
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| 123 | #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 |
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| 124 | #define QSERDES_V5_RX_AUX_CONTROL 0x05c |
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| 125 | #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 |
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| 126 | #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 |
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| 127 | #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 |
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| 128 | #define QSERDES_V5_RX_AC_JTAG_INITP 0x06c |
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| 129 | #define QSERDES_V5_RX_AC_JTAG_INITN 0x070 |
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| 130 | #define QSERDES_V5_RX_AC_JTAG_LVL 0x074 |
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| 131 | #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 |
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| 132 | #define QSERDES_V5_RX_AC_JTAG_RESET 0x07c |
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| 133 | #define QSERDES_V5_RX_RX_TERM_BW 0x080 |
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| 134 | #define QSERDES_V5_RX_RX_RCVR_IQ_EN 0x084 |
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| 135 | #define QSERDES_V5_RX_RX_IDAC_I_DC_OFFSETS 0x088 |
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| 136 | #define QSERDES_V5_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c |
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| 137 | #define QSERDES_V5_RX_RX_IDAC_Q_DC_OFFSETS 0x090 |
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| 138 | #define QSERDES_V5_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094 |
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| 139 | #define QSERDES_V5_RX_RX_IDAC_A_DC_OFFSETS 0x098 |
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| 140 | #define QSERDES_V5_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c |
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| 141 | #define QSERDES_V5_RX_RX_IDAC_EN 0x0a0 |
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| 142 | #define QSERDES_V5_RX_RX_IDAC_ENABLES 0x0a4 |
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| 143 | #define QSERDES_V5_RX_RX_IDAC_SIGN 0x0a8 |
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| 144 | #define QSERDES_V5_RX_RX_HIGHZ_HIGHRATE 0x0ac |
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| 145 | #define QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0 |
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| 146 | #define QSERDES_V5_RX_DFE_1 0x0b4 |
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| 147 | #define QSERDES_V5_RX_DFE_2 0x0b8 |
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| 148 | #define QSERDES_V5_RX_DFE_3 0x0bc |
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| 149 | #define QSERDES_V5_RX_DFE_4 0x0c0 |
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| 150 | #define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH1 0x0c4 |
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| 151 | #define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH2 0x0c8 |
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| 152 | #define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc |
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| 153 | #define QSERDES_V5_RX_TX_ADAPT_MAIN_THRESH 0x0d0 |
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| 154 | #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 |
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| 155 | #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 |
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| 156 | #define QSERDES_V5_RX_GM_CAL 0x0dc |
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| 157 | #define QSERDES_V5_RX_RX_VGA_GAIN2_LSB 0x0e0 |
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| 158 | #define QSERDES_V5_RX_RX_VGA_GAIN2_MSB 0x0e4 |
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| 159 | #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 |
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| 160 | #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec |
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| 161 | #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 |
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| 162 | #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 |
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| 163 | #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 |
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| 164 | #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc |
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| 165 | #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 |
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| 166 | #define QSERDES_V5_RX_RX_IDAC_ACCUMULATOR 0x104 |
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| 167 | #define QSERDES_V5_RX_RX_EQ_OFFSET_LSB 0x108 |
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| 168 | #define QSERDES_V5_RX_RX_EQ_OFFSET_MSB 0x10c |
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| 169 | #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 |
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| 170 | #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 |
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| 171 | #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 |
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| 172 | #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c |
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| 173 | #define QSERDES_V5_RX_SIGDET_LVL 0x120 |
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| 174 | #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 |
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| 175 | #define QSERDES_V5_RX_RX_BAND 0x128 |
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| 176 | #define QSERDES_V5_RX_CDR_FREEZE_UP_DN 0x12c |
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| 177 | #define QSERDES_V5_RX_CDR_RESET_OVERRIDE 0x130 |
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| 178 | #define QSERDES_V5_RX_RX_INTERFACE_MODE 0x134 |
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| 179 | #define QSERDES_V5_RX_JITTER_GEN_MODE 0x138 |
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| 180 | #define QSERDES_V5_RX_SJ_AMP1 0x13c |
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| 181 | #define QSERDES_V5_RX_SJ_AMP2 0x140 |
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| 182 | #define QSERDES_V5_RX_SJ_PER1 0x144 |
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| 183 | #define QSERDES_V5_RX_SJ_PER2 0x148 |
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| 184 | #define QSERDES_V5_RX_PPM_OFFSET1 0x14c |
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| 185 | #define QSERDES_V5_RX_PPM_OFFSET2 0x150 |
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| 186 | #define QSERDES_V5_RX_SIGN_PPM_PERIOD1 0x154 |
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| 187 | #define QSERDES_V5_RX_SIGN_PPM_PERIOD2 0x158 |
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| 188 | #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c |
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| 189 | #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 |
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| 190 | #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 |
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| 191 | #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 |
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| 192 | #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c |
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| 193 | #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 |
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| 194 | #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 |
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| 195 | #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 |
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| 196 | #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c |
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| 197 | #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 |
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| 198 | #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 |
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| 199 | #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 |
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| 200 | #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c |
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| 201 | #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 |
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| 202 | #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 |
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| 203 | #define QSERDES_V5_RX_PHPRE_CTRL 0x198 |
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| 204 | #define QSERDES_V5_RX_PHPRE_INITVAL 0x19c |
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| 205 | #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 |
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| 206 | #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 |
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| 207 | #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 |
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| 208 | #define QSERDES_V5_RX_DCC_CTRL2 0x1ac |
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| 209 | #define QSERDES_V5_RX_VTH_CODE 0x1b0 |
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| 210 | #define QSERDES_V5_RX_VTH_MIN_THRESH 0x1b4 |
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| 211 | #define QSERDES_V5_RX_VTH_MAX_THRESH 0x1b8 |
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| 212 | #define QSERDES_V5_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc |
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| 213 | #define QSERDES_V5_RX_PI_CTRL1 0x1c0 |
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| 214 | #define QSERDES_V5_RX_PI_CTRL2 0x1c4 |
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| 215 | #define QSERDES_V5_RX_PI_QUAD 0x1c8 |
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| 216 | #define QSERDES_V5_RX_IDATA1 0x1cc |
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| 217 | #define QSERDES_V5_RX_IDATA2 0x1d0 |
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| 218 | #define QSERDES_V5_RX_AUX_DATA1 0x1d4 |
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| 219 | #define QSERDES_V5_RX_AUX_DATA2 0x1d8 |
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| 220 | #define QSERDES_V5_RX_AC_JTAG_OUTP 0x1dc |
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| 221 | #define QSERDES_V5_RX_AC_JTAG_OUTN 0x1e0 |
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| 222 | #define QSERDES_V5_RX_RX_SIGDET 0x1e4 |
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| 223 | #define QSERDES_V5_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8 |
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| 224 | |
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| 225 | /* Only for QMP V5 UFS ? */ |
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| 226 | #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 |
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| 227 | #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c |
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| 228 | #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 |
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| 229 | #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 |
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| 230 | |
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| 231 | #endif |
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| 232 | |
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