| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_ |
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| 7 | #define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_ |
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| 8 | |
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| 9 | /* Only for QMP V5_20 PHY - TX registers */ |
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| 10 | #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 |
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| 11 | #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 |
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| 12 | #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 |
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| 13 | #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c |
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| 14 | #define QSERDES_V5_20_TX_LANE_MODE_3 0x80 |
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| 15 | #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90 |
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| 16 | #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0 |
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| 17 | #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc |
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| 18 | |
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| 19 | /* Only for QMP V5_20 PHY - RX registers */ |
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| 20 | #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 |
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| 21 | #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c |
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| 22 | #define QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3 0x01c |
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| 23 | #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 |
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| 24 | #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c |
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| 25 | #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 |
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| 26 | #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c |
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| 27 | #define QSERDES_V5_20_RX_DFE_1 0x088 |
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| 28 | #define QSERDES_V5_20_RX_DFE_2 0x08c |
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| 29 | #define QSERDES_V5_20_RX_DFE_3 0x090 |
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| 30 | #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 |
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| 31 | #define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1 0x0bc |
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| 32 | #define QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2 0x0c0 |
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| 33 | #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 |
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| 34 | #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 |
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| 35 | #define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1 0x0cc |
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| 36 | #define QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2 0x0d0 |
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| 37 | #define QSERDES_V5_20_RX_VGA_CAL_CNTRL1 0x0d4 |
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| 38 | #define QSERDES_V5_20_RX_VGA_CAL_CNTRL2 0x0d8 |
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| 39 | #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc |
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| 40 | #define QSERDES_V5_20_RX_GM_CAL 0x0ec |
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| 41 | #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2 0x100 |
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| 42 | #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3 0x104 |
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| 43 | #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 |
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| 44 | #define QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x118 |
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| 45 | #define QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x11c |
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| 46 | #define QSERDES_V5_20_RX_SIGDET_ENABLES 0x120 |
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| 47 | #define QSERDES_V5_20_RX_SIGDET_CNTRL 0x124 |
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| 48 | #define QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL 0x12c |
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| 49 | #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0 0x160 |
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| 50 | #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 |
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| 51 | #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 |
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| 52 | #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c |
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| 53 | #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4 0x170 |
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| 54 | #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 |
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| 55 | #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 |
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| 56 | #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c |
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| 57 | #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 |
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| 58 | #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 |
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| 59 | #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 |
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| 60 | #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c |
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| 61 | #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 |
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| 62 | #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 |
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| 63 | #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 |
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| 64 | #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c |
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| 65 | #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 |
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| 66 | #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 |
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| 67 | #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 |
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| 68 | #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac |
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| 69 | #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 |
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| 70 | #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 |
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| 71 | #define QSERDES_V5_20_RX_DFE_DAC_ENABLE2 0x1b8 |
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| 72 | #define QSERDES_V5_20_RX_DFE_EN_TIMER 0x1bc |
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| 73 | #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 |
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| 74 | #define QSERDES_V5_20_RX_DCC_CTRL1 0x1c4 |
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| 75 | #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 |
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| 76 | #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 |
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| 77 | #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc |
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| 78 | #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 |
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| 79 | #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 |
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| 80 | #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 |
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| 81 | #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 |
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| 82 | #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 |
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| 83 | #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 |
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| 84 | #define QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x238 |
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| 85 | |
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| 86 | #endif |
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| 87 | |
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