| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2023, Linaro Limited |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ |
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| 7 | #define QCOM_PHY_QMP_QSERDES_TXRX_USB_V6_H_ |
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| 8 | |
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| 9 | #define QSERDES_V6_TX_CLKBUF_ENABLE 0x08 |
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| 10 | #define QSERDES_V6_TX_TX_EMP_POST1_LVL 0x0c |
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| 11 | #define QSERDES_V6_TX_TX_DRV_LVL 0x14 |
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| 12 | #define QSERDES_V6_TX_RESET_TSYNC_EN 0x1c |
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| 13 | #define QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN 0x20 |
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| 14 | #define QSERDES_V6_TX_TX_BAND 0x24 |
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| 15 | #define QSERDES_V6_TX_INTERFACE_SELECT 0x2c |
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| 16 | #define QSERDES_V6_TX_RES_CODE_LANE_TX 0x34 |
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| 17 | #define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38 |
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| 18 | #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c |
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| 19 | #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40 |
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| 20 | #define QSERDES_V6_TX_TRANSCEIVER_BIAS_EN 0x54 |
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| 21 | #define QSERDES_V6_TX_HIGHZ_DRVR_EN 0x58 |
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| 22 | #define QSERDES_V6_TX_TX_POL_INV 0x5c |
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| 23 | #define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 |
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| 24 | #define QSERDES_V6_TX_BIST_PATTERN7 0x7c |
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| 25 | #define QSERDES_V6_TX_LANE_MODE_1 0x84 |
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| 26 | #define QSERDES_V6_TX_LANE_MODE_2 0x88 |
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| 27 | #define QSERDES_V6_TX_LANE_MODE_3 0x8c |
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| 28 | #define QSERDES_V6_TX_LANE_MODE_4 0x90 |
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| 29 | #define QSERDES_V6_TX_LANE_MODE_5 0x94 |
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| 30 | #define QSERDES_V6_TX_RCV_DETECT_LVL_2 0xa4 |
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| 31 | #define QSERDES_V6_TX_TRAN_DRVR_EMP_EN 0xc0 |
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| 32 | #define QSERDES_V6_TX_TX_INTERFACE_MODE 0xc4 |
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| 33 | #define QSERDES_V6_TX_VMODE_CTRL1 0xc8 |
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| 34 | #define QSERDES_V6_TX_PI_QEC_CTRL 0xe4 |
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| 35 | |
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| 36 | #define QSERDES_V6_RX_UCDR_FO_GAIN 0x08 |
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| 37 | #define QSERDES_V6_RX_UCDR_SO_GAIN 0x14 |
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| 38 | #define QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN 0x30 |
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| 39 | #define QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34 |
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| 40 | #define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c |
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| 41 | #define QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40 |
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| 42 | #define QSERDES_V6_RX_UCDR_PI_CONTROLS 0x44 |
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| 43 | #define QSERDES_V6_RX_UCDR_SB2_THRESH1 0x4c |
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| 44 | #define QSERDES_V6_RX_UCDR_SB2_THRESH2 0x50 |
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| 45 | #define QSERDES_V6_RX_UCDR_SB2_GAIN1 0x54 |
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| 46 | #define QSERDES_V6_RX_UCDR_SB2_GAIN2 0x58 |
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| 47 | #define QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE 0x60 |
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| 48 | #define QSERDES_V6_RX_TX_ADAPT_POST_THRESH 0xcc |
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| 49 | #define QSERDES_V6_RX_VGA_CAL_CNTRL1 0xd4 |
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| 50 | #define QSERDES_V6_RX_VGA_CAL_CNTRL2 0xd8 |
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| 51 | #define QSERDES_V6_RX_GM_CAL 0xdc |
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| 52 | #define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2 0xec |
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| 53 | #define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0 |
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| 54 | #define QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4 |
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| 55 | #define QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW 0xf8 |
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| 56 | #define QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH 0xfc |
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| 57 | #define QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 |
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| 58 | #define QSERDES_V6_RX_SIDGET_ENABLES 0x118 |
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| 59 | #define QSERDES_V6_RX_SIGDET_CNTRL 0x11c |
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| 60 | #define QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL 0x124 |
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| 61 | #define QSERDES_V6_RX_RX_MODE_00_LOW 0x15c |
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| 62 | #define QSERDES_V6_RX_RX_MODE_00_HIGH 0x160 |
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| 63 | #define QSERDES_V6_RX_RX_MODE_00_HIGH2 0x164 |
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| 64 | #define QSERDES_V6_RX_RX_MODE_00_HIGH3 0x168 |
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| 65 | #define QSERDES_V6_RX_RX_MODE_00_HIGH4 0x16c |
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| 66 | #define QSERDES_V6_RX_RX_MODE_01_LOW 0x170 |
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| 67 | #define QSERDES_V6_RX_RX_MODE_01_HIGH 0x174 |
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| 68 | #define QSERDES_V6_RX_RX_MODE_01_HIGH2 0x178 |
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| 69 | #define QSERDES_V6_RX_RX_MODE_01_HIGH3 0x17c |
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| 70 | #define QSERDES_V6_RX_RX_MODE_01_HIGH4 0x180 |
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| 71 | #define QSERDES_V6_RX_RX_MODE_10_LOW 0x184 |
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| 72 | #define QSERDES_V6_RX_RX_MODE_10_HIGH 0x188 |
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| 73 | #define QSERDES_V6_RX_RX_MODE_10_HIGH2 0x18c |
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| 74 | #define QSERDES_V6_RX_RX_MODE_10_HIGH3 0x190 |
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| 75 | #define QSERDES_V6_RX_RX_MODE_10_HIGH4 0x194 |
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| 76 | #define QSERDES_V6_RX_DFE_EN_TIMER 0x1a0 |
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| 77 | #define QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 |
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| 78 | #define QSERDES_V6_RX_DCC_CTRL1 0x1a8 |
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| 79 | #define QSERDES_V6_RX_VTH_CODE 0x1b0 |
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| 80 | #define QSERDES_V6_RX_SIGDET_CAL_CTRL1 0x1e4 |
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| 81 | #define QSERDES_V6_RX_SIGDET_CAL_TRIM 0x1f8 |
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| 82 | |
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| 83 | #endif |
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| 84 | |
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