1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (c) 2023, Linaro Limited |
4 | */ |
5 | |
6 | #ifndef QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_ |
7 | #define QCOM_PHY_QMP_QSERDES_TXRX_PCIE_V6_20_H_ |
8 | |
9 | #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 |
10 | #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 |
11 | #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac |
12 | #define QSERDES_V6_20_TX_LANE_MODE_1 0x78 |
13 | #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c |
14 | #define QSERDES_V6_20_TX_LANE_MODE_3 0x80 |
15 | |
16 | #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08 |
17 | #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c |
18 | #define QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2 0x18 |
19 | #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20 |
20 | #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34 |
21 | #define QSERDES_V6_20_RX_IVCM_CAL_CTRL2 0x9c |
22 | #define QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET 0xa0 |
23 | #define QSERDES_V6_20_RX_DFE_1 0xac |
24 | #define QSERDES_V6_20_RX_DFE_2 0xb0 |
25 | #define QSERDES_V6_20_RX_DFE_3 0xb4 |
26 | #define QSERDES_V6_20_RX_TX_ADPT_CTRL 0xd4 |
27 | #define QSERDES_V6_20_VGA_CAL_CNTRL1 0xe0 |
28 | #define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8 |
29 | #define QSERDES_V6_20_RX_GM_CAL 0x10c |
30 | #define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120 |
31 | #define QSERDES_V6_20_RX_SIGDET_ENABLES 0x148 |
32 | #define QSERDES_V6_20_RX_PHPRE_CTRL 0x188 |
33 | #define QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x194 |
34 | #define QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc |
35 | #define QSERDES_V6_20_RX_MODE_RATE2_B0 0x1f4 |
36 | #define QSERDES_V6_20_RX_MODE_RATE2_B1 0x1f8 |
37 | #define QSERDES_V6_20_RX_MODE_RATE2_B2 0x1fc |
38 | #define QSERDES_V6_20_RX_MODE_RATE2_B3 0x200 |
39 | #define QSERDES_V6_20_RX_MODE_RATE2_B4 0x204 |
40 | #define QSERDES_V6_20_RX_MODE_RATE2_B5 0x208 |
41 | #define QSERDES_V6_20_RX_MODE_RATE2_B6 0x20c |
42 | #define QSERDES_V6_20_RX_MODE_RATE3_B0 0x210 |
43 | #define QSERDES_V6_20_RX_MODE_RATE3_B1 0x214 |
44 | #define QSERDES_V6_20_RX_MODE_RATE3_B2 0x218 |
45 | #define QSERDES_V6_20_RX_MODE_RATE3_B3 0x21c |
46 | #define QSERDES_V6_20_RX_MODE_RATE3_B4 0x220 |
47 | #define QSERDES_V6_20_RX_MODE_RATE3_B5 0x224 |
48 | #define QSERDES_V6_20_RX_MODE_RATE3_B6 0x228 |
49 | #define QSERDES_V6_20_RX_BKUP_CTRL1 0x22c |
50 | |
51 | #endif |
52 | |