1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* R8A77995 processor support - PFC hardware block.
4	*
5	* Copyright (C) 2017 Renesas Electronics Corp.
6	*
7	* This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
8	*
9	* R-Car Gen3 processor support - PFC hardware block.
10	*
11	* Copyright (C) 2015 Renesas Electronics Corporation
12	*/
13
14	#include <linux/errno.h>
15	#include <linux/kernel.h>
16
17	#include "core.h"
18	#include "sh_pfc.h"
19
20	#define CPU_ALL_GP(fn, sfx) \
21	PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
22	PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
23	PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
24	PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
25	PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
26	PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
27	PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
28
29	#define CPU_ALL_NOGP(fn) \
30	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
31	PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
32	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
33	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
34	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
35	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
36	PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
37	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \
38	PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
39
40	/*
41	* F_() : just information
42	* FM() : macro for FN_xxx / xxx_MARK
43	*/
44
45	/* GPSR0 */
46	#define GPSR0_8 F_(MLB_SIG, IP0_27_24)
47	#define GPSR0_7 F_(MLB_DAT, IP0_23_20)
48	#define GPSR0_6 F_(MLB_CLK, IP0_19_16)
49	#define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
50	#define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
51	#define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
52	#define GPSR0_2 F_(IRQ0_A, IP0_3_0)
53	#define GPSR0_1 FM(USB0_OVC)
54	#define GPSR0_0 FM(USB0_PWEN)
55
56	/* GPSR1 */
57	#define GPSR1_31 F_(QPOLB, IP4_27_24)
58	#define GPSR1_30 F_(QPOLA, IP4_23_20)
59	#define GPSR1_29 F_(DU_CDE, IP4_19_16)
60	#define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
61	#define GPSR1_27 F_(DU_DISP, IP4_11_8)
62	#define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
63	#define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
64	#define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
65	#define GPSR1_23 F_(DU_DR7, IP3_27_24)
66	#define GPSR1_22 F_(DU_DR6, IP3_23_20)
67	#define GPSR1_21 F_(DU_DR5, IP3_19_16)
68	#define GPSR1_20 F_(DU_DR4, IP3_15_12)
69	#define GPSR1_19 F_(DU_DR3, IP3_11_8)
70	#define GPSR1_18 F_(DU_DR2, IP3_7_4)
71	#define GPSR1_17 F_(DU_DR1, IP3_3_0)
72	#define GPSR1_16 F_(DU_DR0, IP2_31_28)
73	#define GPSR1_15 F_(DU_DG7, IP2_27_24)
74	#define GPSR1_14 F_(DU_DG6, IP2_23_20)
75	#define GPSR1_13 F_(DU_DG5, IP2_19_16)
76	#define GPSR1_12 F_(DU_DG4, IP2_15_12)
77	#define GPSR1_11 F_(DU_DG3, IP2_11_8)
78	#define GPSR1_10 F_(DU_DG2, IP2_7_4)
79	#define GPSR1_9 F_(DU_DG1, IP2_3_0)
80	#define GPSR1_8 F_(DU_DG0, IP1_31_28)
81	#define GPSR1_7 F_(DU_DB7, IP1_27_24)
82	#define GPSR1_6 F_(DU_DB6, IP1_23_20)
83	#define GPSR1_5 F_(DU_DB5, IP1_19_16)
84	#define GPSR1_4 F_(DU_DB4, IP1_15_12)
85	#define GPSR1_3 F_(DU_DB3, IP1_11_8)
86	#define GPSR1_2 F_(DU_DB2, IP1_7_4)
87	#define GPSR1_1 F_(DU_DB1, IP1_3_0)
88	#define GPSR1_0 F_(DU_DB0, IP0_31_28)
89
90	/* GPSR2 */
91	#define GPSR2_31 F_(NFCE_N, IP8_19_16)
92	#define GPSR2_30 F_(NFCLE, IP8_15_12)
93	#define GPSR2_29 F_(NFALE, IP8_11_8)
94	#define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
95	#define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
96	#define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
97	#define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
98	#define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
99	#define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
100	#define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
101	#define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
102	#define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
103	#define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
104	#define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
105	#define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
106	#define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
107	#define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
108	#define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
109	#define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
110	#define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
111	#define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
112	#define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
113	#define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
114	#define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
115	#define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
116	#define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
117	#define GPSR2_5 FM(VI4_DATA4)
118	#define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
119	#define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
120	#define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
121	#define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
122	#define GPSR2_0 FM(VI4_CLK)
123
124	/* GPSR3 */
125	#define GPSR3_9 F_(NFDATA7, IP9_31_28)
126	#define GPSR3_8 F_(NFDATA6, IP9_27_24)
127	#define GPSR3_7 F_(NFDATA5, IP9_23_20)
128	#define GPSR3_6 F_(NFDATA4, IP9_19_16)
129	#define GPSR3_5 F_(NFDATA3, IP9_15_12)
130	#define GPSR3_4 F_(NFDATA2, IP9_11_8)
131	#define GPSR3_3 F_(NFDATA1, IP9_7_4)
132	#define GPSR3_2 F_(NFDATA0, IP9_3_0)
133	#define GPSR3_1 F_(NFWE_N, IP8_31_28)
134	#define GPSR3_0 F_(NFRE_N, IP8_27_24)
135
136	/* GPSR4 */
137	#define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
138	#define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
139	#define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
140	#define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
141	#define GPSR4_27 FM(TX2)
142	#define GPSR4_26 FM(RX2)
143	#define GPSR4_25 F_(SCK2, IP12_11_8)
144	#define GPSR4_24 F_(TX1_A, IP12_7_4)
145	#define GPSR4_23 F_(RX1_A, IP12_3_0)
146	#define GPSR4_22 F_(SCK1_A, IP11_31_28)
147	#define GPSR4_21 F_(TX0_A, IP11_27_24)
148	#define GPSR4_20 F_(RX0_A, IP11_23_20)
149	#define GPSR4_19 F_(SCK0_A, IP11_19_16)
150	#define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
151	#define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
152	#define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
153	#define GPSR4_15 FM(MSIOF0_RXD)
154	#define GPSR4_14 FM(MSIOF0_TXD)
155	#define GPSR4_13 FM(MSIOF0_SYNC)
156	#define GPSR4_12 FM(MSIOF0_SCK)
157	#define GPSR4_11 F_(SDA1, IP11_3_0)
158	#define GPSR4_10 F_(SCL1, IP10_31_28)
159	#define GPSR4_9 FM(SDA0)
160	#define GPSR4_8 FM(SCL0)
161	#define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
162	#define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
163	#define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
164	#define GPSR4_4 F_(SSI_WS34, IP10_15_12)
165	#define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
166	#define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
167	#define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
168	#define GPSR4_0 F_(NFRB_N, IP8_23_20)
169
170	/* GPSR5 */
171	#define GPSR5_20 FM(AVB0_LINK)
172	#define GPSR5_19 FM(AVB0_PHY_INT)
173	#define GPSR5_18 FM(AVB0_MAGIC)
174	#define GPSR5_17 FM(AVB0_MDC)
175	#define GPSR5_16 FM(AVB0_MDIO)
176	#define GPSR5_15 FM(AVB0_TXCREFCLK)
177	#define GPSR5_14 FM(AVB0_TD3)
178	#define GPSR5_13 FM(AVB0_TD2)
179	#define GPSR5_12 FM(AVB0_TD1)
180	#define GPSR5_11 FM(AVB0_TD0)
181	#define GPSR5_10 FM(AVB0_TXC)
182	#define GPSR5_9 FM(AVB0_TX_CTL)
183	#define GPSR5_8 FM(AVB0_RD3)
184	#define GPSR5_7 FM(AVB0_RD2)
185	#define GPSR5_6 FM(AVB0_RD1)
186	#define GPSR5_5 FM(AVB0_RD0)
187	#define GPSR5_4 FM(AVB0_RXC)
188	#define GPSR5_3 FM(AVB0_RX_CTL)
189	#define GPSR5_2 F_(CAN_CLK, IP12_23_20)
190	#define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
191	#define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
192
193	/* GPSR6 */
194	#define GPSR6_13 FM(RPC_INT_N)
195	#define GPSR6_12 FM(RPC_RESET_N)
196	#define GPSR6_11 FM(QSPI1_SSL)
197	#define GPSR6_10 FM(QSPI1_IO3)
198	#define GPSR6_9 FM(QSPI1_IO2)
199	#define GPSR6_8 FM(QSPI1_MISO_IO1)
200	#define GPSR6_7 FM(QSPI1_MOSI_IO0)
201	#define GPSR6_6 FM(QSPI1_SPCLK)
202	#define GPSR6_5 FM(QSPI0_SSL)
203	#define GPSR6_4 FM(QSPI0_IO3)
204	#define GPSR6_3 FM(QSPI0_IO2)
205	#define GPSR6_2 FM(QSPI0_MISO_IO1)
206	#define GPSR6_1 FM(QSPI0_MOSI_IO0)
207	#define GPSR6_0 FM(QSPI0_SPCLK)
208
209	/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
210	#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211	#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212	#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213	#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214	#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215	#define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216	#define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217	#define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218	#define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219	#define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220	#define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221	#define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222	#define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223	#define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224	#define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225	#define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226	#define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227	#define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228	#define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229	#define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230	#define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231	#define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232	#define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233	#define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234	#define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235	#define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236	#define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237	#define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238	#define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239	#define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240	#define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241	#define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242
243	/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
244	#define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245	#define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246	#define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247	#define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248	#define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249	#define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250	#define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251	#define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252	#define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253	#define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254	#define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255	#define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256	#define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257	#define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258	#define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259	#define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260	#define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261	#define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262	#define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263	#define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264	#define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265	#define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266	#define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267	#define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268	#define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269	#define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270	#define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271	#define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272	#define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273	#define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274	#define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275	#define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276
277	/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
278	#define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279	#define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280	#define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281	#define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282	#define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283	#define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284	#define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285	#define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286	#define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287	#define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288	#define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289	#define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290	#define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291	#define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292	#define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293	#define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294	#define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295	#define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296	#define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297	#define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298	#define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299	#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300	#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301	#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302	#define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303	#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304	#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305	#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306	#define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307	#define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308	#define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309	#define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310
311	/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
312	#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313	#define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314	#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315	#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316	#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317	#define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318	#define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319	#define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320	#define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321	#define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322
323	#define PINMUX_GPSR \
324	\
325	GPSR1_31 GPSR2_31 GPSR4_31 \
326	GPSR1_30 GPSR2_30 GPSR4_30 \
327	GPSR1_29 GPSR2_29 GPSR4_29 \
328	GPSR1_28 GPSR2_28 GPSR4_28 \
329	GPSR1_27 GPSR2_27 GPSR4_27 \
330	GPSR1_26 GPSR2_26 GPSR4_26 \
331	GPSR1_25 GPSR2_25 GPSR4_25 \
332	GPSR1_24 GPSR2_24 GPSR4_24 \
333	GPSR1_23 GPSR2_23 GPSR4_23 \
334	GPSR1_22 GPSR2_22 GPSR4_22 \
335	GPSR1_21 GPSR2_21 GPSR4_21 \
336	GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \
337	GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \
338	GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \
339	GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \
340	GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \
341	GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \
342	GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \
343	GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \
344	GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \
345	GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \
346	GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \
347	GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
348	GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
349	GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
350	GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
351	GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
352	GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
353	GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
354	GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
355	GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
356	GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
357
358	#define PINMUX_IPSR \
359	\
360	FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
361	FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
362	FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
363	FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
364	FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
365	FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
366	FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
367	FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
368	\
369	FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
370	FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
371	FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
372	FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
373	FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
374	FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
375	FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
376	FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
377	\
378	FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
379	FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
380	FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
381	FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
382	FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
383	FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
384	FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
385	FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
386	\
387	FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \
388	FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \
389	FM(IP12_11_8) IP12_11_8 \
390	FM(IP12_15_12) IP12_15_12 \
391	FM(IP12_19_16) IP12_19_16 \
392	FM(IP12_23_20) IP12_23_20 \
393	FM(IP12_27_24) IP12_27_24 \
394	FM(IP12_31_28) IP12_31_28 \
395
396	/* The bit numbering in MOD_SEL fields is reversed */
397	#define REV4(f0, f1, f2, f3) f0 f2 f1 f3
398
399	/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
400	#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
401	#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
402	#define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
403	#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
404	#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
405	#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
406	#define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0))
407	#define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0))
408	#define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
409	#define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
410	#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
411	#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
412	#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
413	#define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1)
414	#define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1)
415	#define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1)
416	#define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1)
417	#define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1)
418	#define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
419	#define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
420	#define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1)
421	#define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
422
423	#define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1)
424	#define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1)
425	#define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
426	#define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
427	#define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
428	#define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
429
430
431	#define PINMUX_MOD_SELS \
432	\
433	MOD_SEL1_31 \
434	MOD_SEL0_30 MOD_SEL1_30 \
435	MOD_SEL0_29 MOD_SEL1_29 \
436	MOD_SEL0_28 MOD_SEL1_28 \
437	MOD_SEL0_27 MOD_SEL1_27 \
438	MOD_SEL0_26 MOD_SEL1_26 \
439	MOD_SEL0_25 \
440	MOD_SEL0_24_23 \
441	MOD_SEL0_22_21 \
442	MOD_SEL0_20_19 \
443	MOD_SEL0_18_17 \
444	MOD_SEL0_15 \
445	MOD_SEL0_14 \
446	MOD_SEL0_13 \
447	MOD_SEL0_12 \
448	MOD_SEL0_11 \
449	MOD_SEL0_10 \
450	MOD_SEL0_5 \
451	MOD_SEL0_4 \
452	MOD_SEL0_3 \
453	MOD_SEL0_2 \
454	MOD_SEL0_1 \
455	MOD_SEL0_0
456
457	enum {
458	PINMUX_RESERVED = 0,
459
460	PINMUX_DATA_BEGIN,
461	GP_ALL(DATA),
462	PINMUX_DATA_END,
463
464	#define F_(x, y)
465	#define FM(x) FN_##x,
466	PINMUX_FUNCTION_BEGIN,
467	GP_ALL(FN),
468	PINMUX_GPSR
469	PINMUX_IPSR
470	PINMUX_MOD_SELS
471	PINMUX_FUNCTION_END,
472	#undef F_
473	#undef FM
474
475	#define F_(x, y)
476	#define FM(x) x##_MARK,
477	PINMUX_MARK_BEGIN,
478	PINMUX_GPSR
479	PINMUX_IPSR
480	PINMUX_MOD_SELS
481	PINMUX_MARK_END,
482	#undef F_
483	#undef FM
484	};
485
486	static const u16 pinmux_data[] = {
487	PINMUX_DATA_GP_ALL(),
488
489	PINMUX_SINGLE(USB0_OVC),
490	PINMUX_SINGLE(USB0_PWEN),
491	PINMUX_SINGLE(VI4_DATA4),
492	PINMUX_SINGLE(VI4_CLK),
493	PINMUX_SINGLE(TX2),
494	PINMUX_SINGLE(RX2),
495	PINMUX_SINGLE(AVB0_LINK),
496	PINMUX_SINGLE(AVB0_PHY_INT),
497	PINMUX_SINGLE(AVB0_MAGIC),
498	PINMUX_SINGLE(AVB0_MDC),
499	PINMUX_SINGLE(AVB0_MDIO),
500	PINMUX_SINGLE(AVB0_TXCREFCLK),
501	PINMUX_SINGLE(AVB0_TD3),
502	PINMUX_SINGLE(AVB0_TD2),
503	PINMUX_SINGLE(AVB0_TD1),
504	PINMUX_SINGLE(AVB0_TD0),
505	PINMUX_SINGLE(AVB0_TXC),
506	PINMUX_SINGLE(AVB0_TX_CTL),
507	PINMUX_SINGLE(AVB0_RD3),
508	PINMUX_SINGLE(AVB0_RD2),
509	PINMUX_SINGLE(AVB0_RD1),
510	PINMUX_SINGLE(AVB0_RD0),
511	PINMUX_SINGLE(AVB0_RXC),
512	PINMUX_SINGLE(AVB0_RX_CTL),
513	PINMUX_SINGLE(RPC_INT_N),
514	PINMUX_SINGLE(RPC_RESET_N),
515	PINMUX_SINGLE(QSPI1_SSL),
516	PINMUX_SINGLE(QSPI1_IO3),
517	PINMUX_SINGLE(QSPI1_IO2),
518	PINMUX_SINGLE(QSPI1_MISO_IO1),
519	PINMUX_SINGLE(QSPI1_MOSI_IO0),
520	PINMUX_SINGLE(QSPI1_SPCLK),
521	PINMUX_SINGLE(QSPI0_SSL),
522	PINMUX_SINGLE(QSPI0_IO3),
523	PINMUX_SINGLE(QSPI0_IO2),
524	PINMUX_SINGLE(QSPI0_MISO_IO1),
525	PINMUX_SINGLE(QSPI0_MOSI_IO0),
526	PINMUX_SINGLE(QSPI0_SPCLK),
527	PINMUX_SINGLE(SCL0),
528	PINMUX_SINGLE(SDA0),
529	PINMUX_SINGLE(MSIOF0_RXD),
530	PINMUX_SINGLE(MSIOF0_TXD),
531	PINMUX_SINGLE(MSIOF0_SYNC),
532	PINMUX_SINGLE(MSIOF0_SCK),
533
534	/* IPSR0 */
535	PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
536	PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
537
538	PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
539
540	PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
541	PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
542
543	PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
544	PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
545
546	PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
547	PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
548	PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
549
550	PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
551	PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
552	PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
553	PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
554
555	PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
556	PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
557	PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
558	PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
559
560	PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
561	PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
562	PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
563
564	/* IPSR1 */
565	PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
566	PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
567	PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
568
569	PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
570	PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
571	PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
572
573	PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3),
574	PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3),
575	PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1),
576
577	PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
578	PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
579	PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
580
581	PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
582	PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
583	PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
584
585	PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
586	PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
587	PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
588
589	PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
590	PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
591	PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
592
593	PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
594	PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
595	PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
596
597	/* IPSR2 */
598	PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1),
599	PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9),
600	PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1),
601
602	PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2),
603	PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10),
604
605	PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3),
606	PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11),
607	PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0),
608
609	PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
610	PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
611	PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
612
613	PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
614	PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
615	PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
616
617	PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
618	PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
619	PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
620
621	PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
622	PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
623	PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
624
625	PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
626	PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
627	PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
628
629	/* IPSR3 */
630	PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
631	PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
632	PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
633
634	PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
635	PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
636	PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
637
638	PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3),
639	PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19),
640	PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2),
641
642	PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
643	PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
644	PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
645
646	PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
647	PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
648	PINMUX_IPSR_GPSR(IP3_19_16, NMI),
649
650	PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
651	PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
652	PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
653
654	PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
655	PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
656	PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
657
658	PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
659	PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
660
661	/* IPSR4 */
662	PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
663	PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
664	PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
665
666	PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC),
667	PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS),
668	PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0),
669
670	PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP),
671	PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE),
672	PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2),
673
674	PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
675	PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
676	PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
677	PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
678
679	PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
680	PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
681	PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
682
683	PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
684	PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
685
686	PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
687	PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
688
689	PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
690	PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
691
692	/* IPSR5 */
693	PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1),
694	PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0),
695
696	PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2),
697	PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0),
698
699	PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3),
700	PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0),
701
702	PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
703	PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
704
705	PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
706	PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
707
708	PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
709	PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
710
711	PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
712
713	PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
714	PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
715	PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
716
717	/* IPSR6 */
718	PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10),
719	PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0),
720
721	PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11),
722	PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0),
723
724	PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12),
725	PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0),
726
727	PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
728	PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
729	PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
730
731	PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
732	PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
733	PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
734
735	PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
736	PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
737
738	PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
739	PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
740
741	PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
742	PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
743
744	/* IPSR7 */
745	PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
746	PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
747
748	PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19),
749	PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1),
750	PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15),
751
752	PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20),
753	PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0),
754	PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14),
755
756	PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
757	PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
758
759	PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
760	PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
761	PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
762
763	PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
764	PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
765	PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
766
767	PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
768
769	PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
770	PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
771	PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
772
773	PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
774	PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
775	PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
776
777	/* IPSR8 */
778	PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD),
779	PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB),
780	PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0),
781	PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK),
782	PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8),
783
784	PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB),
785	PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1),
786	PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N),
787	PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0),
788
789	PINMUX_IPSR_GPSR(IP8_11_8, NFALE),
790	PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1),
791	PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1),
792	PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1),
793
794	PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
795	PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
796	PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
797	PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
798
799	PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
800	PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
801	PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
802
803	PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
804	PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
805	PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
806
807	PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
808	PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
809
810	PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
811	PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
812
813	/* IPSR9 */
814	PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0),
815	PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0),
816
817	PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1),
818	PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1),
819
820	PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2),
821	PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2),
822
823	PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
824	PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
825
826	PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
827	PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
828
829	PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
830	PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
831
832	PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
833	PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
834
835	PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
836	PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
837
838	/* IPSR10 */
839	PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA),
840	PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1),
841
842	PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34),
843	PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0),
844
845	PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
846	PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
847
848	PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34),
849	PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0),
850
851	PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0),
852	PINMUX_IPSR_GPSR(IP10_19_16, HSCK0),
853	PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT),
854	PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1),
855	PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1),
856
857	PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0),
858	PINMUX_IPSR_GPSR(IP10_23_20, HTX0),
859	PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0),
860	PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1),
861
862	PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0),
863	PINMUX_IPSR_GPSR(IP10_27_24, HRX0),
864	PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
865	PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1),
866
867	PINMUX_IPSR_GPSR(IP10_31_28, SCL1),
868	PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N),
869
870	/* IPSR11 */
871	PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
872	PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N),
873
874	PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
875	PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
876
877	PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
878	PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
879
880	PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD),
881	PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
882
883	PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0),
884	PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC),
885	PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
886
887	PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0),
888	PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1),
889	PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
890
891	PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
892	PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2),
893	PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1),
894
895	PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0),
896	PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2),
897	PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B),
898	PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1),
899	PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1),
900
901	/* IPSR12 */
902	PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0),
903	PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N),
904	PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
905
906	PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
907	PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N),
908	PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
909
910	PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
911	PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
912	PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
913
914	PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A),
915	PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
916	PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N),
917
918	PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A),
919	PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
920	PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N),
921
922	PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK),
923	PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
924	PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1),
925	PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1),
926
927	PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0),
928	PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX),
929	PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1),
930
931	PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0),
932	PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX),
933	PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1),
934
935	/* IPSR13 */
936	PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0),
937	PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX),
938	PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A),
939
940	PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0),
941	PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX),
942	PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
943	};
944
945	/*
946	* Pins not associated with a GPIO port.
947	*/
948	enum {
949	GP_ASSIGN_LAST(),
950	NOGP_ALL(),
951	};
952
953	static const struct sh_pfc_pin pinmux_pins[] = {
954	PINMUX_GPIO_GP_ALL(),
955	PINMUX_NOGP_ALL(),
956	};
957
958	/* - AUDIO CLOCK ------------------------------------------------------------- */
959	static const unsigned int audio_clk_a_pins[] = {
960	/* CLK A */
961	RCAR_GP_PIN(4, 1),
962	};
963	static const unsigned int audio_clk_a_mux[] = {
964	AUDIO_CLKA_MARK,
965	};
966	static const unsigned int audio_clk_b_pins[] = {
967	/* CLK B */
968	RCAR_GP_PIN(2, 27),
969	};
970	static const unsigned int audio_clk_b_mux[] = {
971	AUDIO_CLKB_MARK,
972	};
973	static const unsigned int audio_clkout_pins[] = {
974	/* CLKOUT */
975	RCAR_GP_PIN(4, 5),
976	};
977	static const unsigned int audio_clkout_mux[] = {
978	AUDIO_CLKOUT_MARK,
979	};
980	static const unsigned int audio_clkout1_pins[] = {
981	/* CLKOUT1 */
982	RCAR_GP_PIN(4, 22),
983	};
984	static const unsigned int audio_clkout1_mux[] = {
985	AUDIO_CLKOUT1_MARK,
986	};
987
988	/* - EtherAVB --------------------------------------------------------------- */
989	static const unsigned int avb0_link_pins[] = {
990	/* AVB0_LINK */
991	RCAR_GP_PIN(5, 20),
992	};
993	static const unsigned int avb0_link_mux[] = {
994	AVB0_LINK_MARK,
995	};
996	static const unsigned int avb0_magic_pins[] = {
997	/* AVB0_MAGIC */
998	RCAR_GP_PIN(5, 18),
999	};
1000	static const unsigned int avb0_magic_mux[] = {
1001	AVB0_MAGIC_MARK,
1002	};
1003	static const unsigned int avb0_phy_int_pins[] = {
1004	/* AVB0_PHY_INT */
1005	RCAR_GP_PIN(5, 19),
1006	};
1007	static const unsigned int avb0_phy_int_mux[] = {
1008	AVB0_PHY_INT_MARK,
1009	};
1010	static const unsigned int avb0_mdio_pins[] = {
1011	/* AVB0_MDC, AVB0_MDIO */
1012	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
1013	};
1014	static const unsigned int avb0_mdio_mux[] = {
1015	AVB0_MDC_MARK, AVB0_MDIO_MARK,
1016	};
1017	static const unsigned int avb0_mii_pins[] = {
1018	/*
1019	* AVB0_TX_CTL, AVB0_TXC, AVB0_TD0,
1020	* AVB0_TD1, AVB0_TD2, AVB0_TD3,
1021	* AVB0_RX_CTL, AVB0_RXC, AVB0_RD0,
1022	* AVB0_RD1, AVB0_RD2, AVB0_RD3,
1023	* AVB0_TXCREFCLK
1024	*/
1025	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1026	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1027	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1028	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1029	RCAR_GP_PIN(5, 15),
1030	};
1031	static const unsigned int avb0_mii_mux[] = {
1032	AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
1033	AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
1034	AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
1035	AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
1036	AVB0_TXCREFCLK_MARK,
1037	};
1038	static const unsigned int avb0_avtp_pps_a_pins[] = {
1039	/* AVB0_AVTP_PPS_A */
1040	RCAR_GP_PIN(5, 2),
1041	};
1042	static const unsigned int avb0_avtp_pps_a_mux[] = {
1043	AVB0_AVTP_PPS_A_MARK,
1044	};
1045	static const unsigned int avb0_avtp_match_a_pins[] = {
1046	/* AVB0_AVTP_MATCH_A */
1047	RCAR_GP_PIN(5, 1),
1048	};
1049	static const unsigned int avb0_avtp_match_a_mux[] = {
1050	AVB0_AVTP_MATCH_A_MARK,
1051	};
1052	static const unsigned int avb0_avtp_capture_a_pins[] = {
1053	/* AVB0_AVTP_CAPTURE_A */
1054	RCAR_GP_PIN(5, 0),
1055	};
1056	static const unsigned int avb0_avtp_capture_a_mux[] = {
1057	AVB0_AVTP_CAPTURE_A_MARK,
1058	};
1059	static const unsigned int avb0_avtp_pps_b_pins[] = {
1060	/* AVB0_AVTP_PPS_B */
1061	RCAR_GP_PIN(4, 16),
1062	};
1063	static const unsigned int avb0_avtp_pps_b_mux[] = {
1064	AVB0_AVTP_PPS_B_MARK,
1065	};
1066	static const unsigned int avb0_avtp_match_b_pins[] = {
1067	/* AVB0_AVTP_MATCH_B */
1068	RCAR_GP_PIN(4, 18),
1069	};
1070	static const unsigned int avb0_avtp_match_b_mux[] = {
1071	AVB0_AVTP_MATCH_B_MARK,
1072	};
1073	static const unsigned int avb0_avtp_capture_b_pins[] = {
1074	/* AVB0_AVTP_CAPTURE_B */
1075	RCAR_GP_PIN(4, 17),
1076	};
1077	static const unsigned int avb0_avtp_capture_b_mux[] = {
1078	AVB0_AVTP_CAPTURE_B_MARK,
1079	};
1080
1081	/* - CAN ------------------------------------------------------------------ */
1082	static const unsigned int can0_data_a_pins[] = {
1083	/* TX, RX */
1084	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1085	};
1086	static const unsigned int can0_data_a_mux[] = {
1087	CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1088	};
1089	static const unsigned int can0_data_b_pins[] = {
1090	/* TX, RX */
1091	RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
1092	};
1093	static const unsigned int can0_data_b_mux[] = {
1094	CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1095	};
1096	static const unsigned int can1_data_a_pins[] = {
1097	/* TX, RX */
1098	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1099	};
1100	static const unsigned int can1_data_a_mux[] = {
1101	CAN1_TX_A_MARK, CAN1_RX_A_MARK,
1102	};
1103	static const unsigned int can1_data_b_pins[] = {
1104	/* TX, RX */
1105	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
1106	};
1107	static const unsigned int can1_data_b_mux[] = {
1108	CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1109	};
1110
1111	/* - CAN Clock -------------------------------------------------------------- */
1112	static const unsigned int can_clk_pins[] = {
1113	/* CLK */
1114	RCAR_GP_PIN(5, 2),
1115	};
1116	static const unsigned int can_clk_mux[] = {
1117	CAN_CLK_MARK,
1118	};
1119
1120	/* - CAN FD ----------------------------------------------------------------- */
1121	static const unsigned int canfd0_data_pins[] = {
1122	/* TX, RX */
1123	RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1124	};
1125	static const unsigned int canfd0_data_mux[] = {
1126	CANFD0_TX_MARK, CANFD0_RX_MARK,
1127	};
1128	static const unsigned int canfd1_data_pins[] = {
1129	/* TX, RX */
1130	RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1131	};
1132	static const unsigned int canfd1_data_mux[] = {
1133	CANFD1_TX_MARK, CANFD1_RX_MARK,
1134	};
1135
1136	/* - DU --------------------------------------------------------------------- */
1137	static const unsigned int du_rgb666_pins[] = {
1138	/* R[7:2], G[7:2], B[7:2] */
1139	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1140	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1141	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1142	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1143	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1144	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1145	};
1146	static const unsigned int du_rgb666_mux[] = {
1147	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1148	DU_DR3_MARK, DU_DR2_MARK,
1149	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1150	DU_DG3_MARK, DU_DG2_MARK,
1151	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1152	DU_DB3_MARK, DU_DB2_MARK,
1153	};
1154	static const unsigned int du_rgb888_pins[] = {
1155	/* R[7:0], G[7:0], B[7:0] */
1156	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1157	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1158	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1159	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1160	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1161	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1162	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1163	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1164	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1165	};
1166	static const unsigned int du_rgb888_mux[] = {
1167	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1168	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1169	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1170	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1171	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1172	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1173	};
1174	static const unsigned int du_clk_in_1_pins[] = {
1175	/* CLKIN */
1176	RCAR_GP_PIN(1, 28),
1177	};
1178	static const unsigned int du_clk_in_1_mux[] = {
1179	DU_DOTCLKIN1_MARK
1180	};
1181	static const unsigned int du_clk_out_0_pins[] = {
1182	/* CLKOUT */
1183	RCAR_GP_PIN(1, 24),
1184	};
1185	static const unsigned int du_clk_out_0_mux[] = {
1186	DU_DOTCLKOUT0_MARK
1187	};
1188	static const unsigned int du_sync_pins[] = {
1189	/* VSYNC, HSYNC */
1190	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1191	};
1192	static const unsigned int du_sync_mux[] = {
1193	DU_VSYNC_MARK, DU_HSYNC_MARK
1194	};
1195	static const unsigned int du_disp_cde_pins[] = {
1196	/* DISP_CDE */
1197	RCAR_GP_PIN(1, 28),
1198	};
1199	static const unsigned int du_disp_cde_mux[] = {
1200	DU_DISP_CDE_MARK,
1201	};
1202	static const unsigned int du_cde_pins[] = {
1203	/* CDE */
1204	RCAR_GP_PIN(1, 29),
1205	};
1206	static const unsigned int du_cde_mux[] = {
1207	DU_CDE_MARK,
1208	};
1209	static const unsigned int du_disp_pins[] = {
1210	/* DISP */
1211	RCAR_GP_PIN(1, 27),
1212	};
1213	static const unsigned int du_disp_mux[] = {
1214	DU_DISP_MARK,
1215	};
1216
1217	/* - I2C -------------------------------------------------------------------- */
1218	static const unsigned int i2c0_pins[] = {
1219	/* SCL, SDA */
1220	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1221	};
1222	static const unsigned int i2c0_mux[] = {
1223	SCL0_MARK, SDA0_MARK,
1224	};
1225	static const unsigned int i2c1_pins[] = {
1226	/* SCL, SDA */
1227	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1228	};
1229	static const unsigned int i2c1_mux[] = {
1230	SCL1_MARK, SDA1_MARK,
1231	};
1232	static const unsigned int i2c2_a_pins[] = {
1233	/* SCL, SDA */
1234	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1235	};
1236	static const unsigned int i2c2_a_mux[] = {
1237	SCL2_A_MARK, SDA2_A_MARK,
1238	};
1239	static const unsigned int i2c2_b_pins[] = {
1240	/* SCL, SDA */
1241	RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
1242	};
1243	static const unsigned int i2c2_b_mux[] = {
1244	SCL2_B_MARK, SDA2_B_MARK,
1245	};
1246	static const unsigned int i2c3_a_pins[] = {
1247	/* SCL, SDA */
1248	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1249	};
1250	static const unsigned int i2c3_a_mux[] = {
1251	SCL3_A_MARK, SDA3_A_MARK,
1252	};
1253	static const unsigned int i2c3_b_pins[] = {
1254	/* SCL, SDA */
1255	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1256	};
1257	static const unsigned int i2c3_b_mux[] = {
1258	SCL3_B_MARK, SDA3_B_MARK,
1259	};
1260
1261	/* - MLB+ ------------------------------------------------------------------- */
1262	static const unsigned int mlb_3pin_pins[] = {
1263	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7),
1264	};
1265	static const unsigned int mlb_3pin_mux[] = {
1266	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
1267	};
1268
1269	/* - MMC ------------------------------------------------------------------- */
1270	static const unsigned int mmc_data_pins[] = {
1271	/* D[0:7] */
1272	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1273	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1274	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1275	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1276	};
1277	static const unsigned int mmc_data_mux[] = {
1278	MMC_D0_MARK, MMC_D1_MARK,
1279	MMC_D2_MARK, MMC_D3_MARK,
1280	MMC_D4_MARK, MMC_D5_MARK,
1281	MMC_D6_MARK, MMC_D7_MARK,
1282	};
1283	static const unsigned int mmc_ctrl_pins[] = {
1284	/* CLK, CMD */
1285	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1286	};
1287	static const unsigned int mmc_ctrl_mux[] = {
1288	MMC_CLK_MARK, MMC_CMD_MARK,
1289	};
1290
1291	/* - MSIOF0 ----------------------------------------------------------------- */
1292	static const unsigned int msiof0_clk_pins[] = {
1293	/* SCK */
1294	RCAR_GP_PIN(4, 12),
1295	};
1296
1297	static const unsigned int msiof0_clk_mux[] = {
1298	MSIOF0_SCK_MARK,
1299	};
1300
1301	static const unsigned int msiof0_sync_pins[] = {
1302	/* SYNC */
1303	RCAR_GP_PIN(4, 13),
1304	};
1305
1306	static const unsigned int msiof0_sync_mux[] = {
1307	MSIOF0_SYNC_MARK,
1308	};
1309
1310	static const unsigned int msiof0_ss1_pins[] = {
1311	/* SS1 */
1312	RCAR_GP_PIN(4, 20),
1313	};
1314
1315	static const unsigned int msiof0_ss1_mux[] = {
1316	MSIOF0_SS1_MARK,
1317	};
1318
1319	static const unsigned int msiof0_ss2_pins[] = {
1320	/* SS2 */
1321	RCAR_GP_PIN(4, 21),
1322	};
1323
1324	static const unsigned int msiof0_ss2_mux[] = {
1325	MSIOF0_SS2_MARK,
1326	};
1327
1328	static const unsigned int msiof0_txd_pins[] = {
1329	/* TXD */
1330	RCAR_GP_PIN(4, 14),
1331	};
1332
1333	static const unsigned int msiof0_txd_mux[] = {
1334	MSIOF0_TXD_MARK,
1335	};
1336
1337	static const unsigned int msiof0_rxd_pins[] = {
1338	/* RXD */
1339	RCAR_GP_PIN(4, 15),
1340	};
1341
1342	static const unsigned int msiof0_rxd_mux[] = {
1343	MSIOF0_RXD_MARK,
1344	};
1345
1346	/* - MSIOF1 ----------------------------------------------------------------- */
1347	static const unsigned int msiof1_clk_pins[] = {
1348	/* SCK */
1349	RCAR_GP_PIN(4, 16),
1350	};
1351
1352	static const unsigned int msiof1_clk_mux[] = {
1353	MSIOF1_SCK_MARK,
1354	};
1355
1356	static const unsigned int msiof1_sync_pins[] = {
1357	/* SYNC */
1358	RCAR_GP_PIN(4, 19),
1359	};
1360
1361	static const unsigned int msiof1_sync_mux[] = {
1362	MSIOF1_SYNC_MARK,
1363	};
1364
1365	static const unsigned int msiof1_ss1_pins[] = {
1366	/* SS1 */
1367	RCAR_GP_PIN(4, 25),
1368	};
1369
1370	static const unsigned int msiof1_ss1_mux[] = {
1371	MSIOF1_SS1_MARK,
1372	};
1373
1374	static const unsigned int msiof1_ss2_pins[] = {
1375	/* SS2 */
1376	RCAR_GP_PIN(4, 22),
1377	};
1378
1379	static const unsigned int msiof1_ss2_mux[] = {
1380	MSIOF1_SS2_MARK,
1381	};
1382
1383	static const unsigned int msiof1_txd_pins[] = {
1384	/* TXD */
1385	RCAR_GP_PIN(4, 17),
1386	};
1387
1388	static const unsigned int msiof1_txd_mux[] = {
1389	MSIOF1_TXD_MARK,
1390	};
1391
1392	static const unsigned int msiof1_rxd_pins[] = {
1393	/* RXD */
1394	RCAR_GP_PIN(4, 18),
1395	};
1396
1397	static const unsigned int msiof1_rxd_mux[] = {
1398	MSIOF1_RXD_MARK,
1399	};
1400
1401	/* - MSIOF2 ----------------------------------------------------------------- */
1402	static const unsigned int msiof2_clk_pins[] = {
1403	/* SCK */
1404	RCAR_GP_PIN(0, 3),
1405	};
1406
1407	static const unsigned int msiof2_clk_mux[] = {
1408	MSIOF2_SCK_MARK,
1409	};
1410
1411	static const unsigned int msiof2_sync_a_pins[] = {
1412	/* SYNC */
1413	RCAR_GP_PIN(0, 6),
1414	};
1415
1416	static const unsigned int msiof2_sync_a_mux[] = {
1417	MSIOF2_SYNC_A_MARK,
1418	};
1419
1420	static const unsigned int msiof2_sync_b_pins[] = {
1421	/* SYNC */
1422	RCAR_GP_PIN(0, 2),
1423	};
1424
1425	static const unsigned int msiof2_sync_b_mux[] = {
1426	MSIOF2_SYNC_B_MARK,
1427	};
1428
1429	static const unsigned int msiof2_ss1_pins[] = {
1430	/* SS1 */
1431	RCAR_GP_PIN(0, 7),
1432	};
1433
1434	static const unsigned int msiof2_ss1_mux[] = {
1435	MSIOF2_SS1_MARK,
1436	};
1437
1438	static const unsigned int msiof2_ss2_pins[] = {
1439	/* SS2 */
1440	RCAR_GP_PIN(0, 8),
1441	};
1442
1443	static const unsigned int msiof2_ss2_mux[] = {
1444	MSIOF2_SS2_MARK,
1445	};
1446
1447	static const unsigned int msiof2_txd_pins[] = {
1448	/* TXD */
1449	RCAR_GP_PIN(0, 4),
1450	};
1451
1452	static const unsigned int msiof2_txd_mux[] = {
1453	MSIOF2_TXD_MARK,
1454	};
1455
1456	static const unsigned int msiof2_rxd_pins[] = {
1457	/* RXD */
1458	RCAR_GP_PIN(0, 5),
1459	};
1460
1461	static const unsigned int msiof2_rxd_mux[] = {
1462	MSIOF2_RXD_MARK,
1463	};
1464
1465	/* - MSIOF3 ----------------------------------------------------------------- */
1466	static const unsigned int msiof3_clk_a_pins[] = {
1467	/* SCK */
1468	RCAR_GP_PIN(2, 24),
1469	};
1470
1471	static const unsigned int msiof3_clk_a_mux[] = {
1472	MSIOF3_SCK_A_MARK,
1473	};
1474
1475	static const unsigned int msiof3_sync_a_pins[] = {
1476	/* SYNC */
1477	RCAR_GP_PIN(2, 21),
1478	};
1479
1480	static const unsigned int msiof3_sync_a_mux[] = {
1481	MSIOF3_SYNC_A_MARK,
1482	};
1483
1484	static const unsigned int msiof3_ss1_a_pins[] = {
1485	/* SS1 */
1486	RCAR_GP_PIN(2, 14),
1487	};
1488
1489	static const unsigned int msiof3_ss1_a_mux[] = {
1490	MSIOF3_SS1_A_MARK,
1491	};
1492
1493	static const unsigned int msiof3_ss2_a_pins[] = {
1494	/* SS2 */
1495	RCAR_GP_PIN(2, 10),
1496	};
1497
1498	static const unsigned int msiof3_ss2_a_mux[] = {
1499	MSIOF3_SS2_A_MARK,
1500	};
1501
1502	static const unsigned int msiof3_txd_a_pins[] = {
1503	/* TXD */
1504	RCAR_GP_PIN(2, 22),
1505	};
1506
1507	static const unsigned int msiof3_txd_a_mux[] = {
1508	MSIOF3_TXD_A_MARK,
1509	};
1510
1511	static const unsigned int msiof3_rxd_a_pins[] = {
1512	/* RXD */
1513	RCAR_GP_PIN(2, 23),
1514	};
1515
1516	static const unsigned int msiof3_rxd_a_mux[] = {
1517	MSIOF3_RXD_A_MARK,
1518	};
1519
1520	static const unsigned int msiof3_clk_b_pins[] = {
1521	/* SCK */
1522	RCAR_GP_PIN(1, 8),
1523	};
1524
1525	static const unsigned int msiof3_clk_b_mux[] = {
1526	MSIOF3_SCK_B_MARK,
1527	};
1528
1529	static const unsigned int msiof3_sync_b_pins[] = {
1530	/* SYNC */
1531	RCAR_GP_PIN(1, 9),
1532	};
1533
1534	static const unsigned int msiof3_sync_b_mux[] = {
1535	MSIOF3_SYNC_B_MARK,
1536	};
1537
1538	static const unsigned int msiof3_ss1_b_pins[] = {
1539	/* SS1 */
1540	RCAR_GP_PIN(1, 6),
1541	};
1542
1543	static const unsigned int msiof3_ss1_b_mux[] = {
1544	MSIOF3_SS1_B_MARK,
1545	};
1546
1547	static const unsigned int msiof3_ss2_b_pins[] = {
1548	/* SS2 */
1549	RCAR_GP_PIN(1, 7),
1550	};
1551
1552	static const unsigned int msiof3_ss2_b_mux[] = {
1553	MSIOF3_SS2_B_MARK,
1554	};
1555
1556	static const unsigned int msiof3_txd_b_pins[] = {
1557	/* TXD */
1558	RCAR_GP_PIN(1, 0),
1559	};
1560
1561	static const unsigned int msiof3_txd_b_mux[] = {
1562	MSIOF3_TXD_B_MARK,
1563	};
1564
1565	static const unsigned int msiof3_rxd_b_pins[] = {
1566	/* RXD */
1567	RCAR_GP_PIN(1, 1),
1568	};
1569
1570	static const unsigned int msiof3_rxd_b_mux[] = {
1571	MSIOF3_RXD_B_MARK,
1572	};
1573
1574	/* - PWM0 ------------------------------------------------------------------ */
1575	static const unsigned int pwm0_a_pins[] = {
1576	/* PWM */
1577	RCAR_GP_PIN(2, 1),
1578	};
1579
1580	static const unsigned int pwm0_a_mux[] = {
1581	PWM0_A_MARK,
1582	};
1583
1584	static const unsigned int pwm0_b_pins[] = {
1585	/* PWM */
1586	RCAR_GP_PIN(1, 18),
1587	};
1588
1589	static const unsigned int pwm0_b_mux[] = {
1590	PWM0_B_MARK,
1591	};
1592
1593	static const unsigned int pwm0_c_pins[] = {
1594	/* PWM */
1595	RCAR_GP_PIN(2, 29),
1596	};
1597
1598	static const unsigned int pwm0_c_mux[] = {
1599	PWM0_C_MARK,
1600	};
1601
1602	/* - PWM1 ------------------------------------------------------------------ */
1603	static const unsigned int pwm1_a_pins[] = {
1604	/* PWM */
1605	RCAR_GP_PIN(2, 2),
1606	};
1607
1608	static const unsigned int pwm1_a_mux[] = {
1609	PWM1_A_MARK,
1610	};
1611
1612	static const unsigned int pwm1_b_pins[] = {
1613	/* PWM */
1614	RCAR_GP_PIN(1, 19),
1615	};
1616
1617	static const unsigned int pwm1_b_mux[] = {
1618	PWM1_B_MARK,
1619	};
1620
1621	static const unsigned int pwm1_c_pins[] = {
1622	/* PWM */
1623	RCAR_GP_PIN(2, 30),
1624	};
1625
1626	static const unsigned int pwm1_c_mux[] = {
1627	PWM1_C_MARK,
1628	};
1629
1630	/* - PWM2 ------------------------------------------------------------------ */
1631	static const unsigned int pwm2_a_pins[] = {
1632	/* PWM */
1633	RCAR_GP_PIN(2, 3),
1634	};
1635
1636	static const unsigned int pwm2_a_mux[] = {
1637	PWM2_A_MARK,
1638	};
1639
1640	static const unsigned int pwm2_b_pins[] = {
1641	/* PWM */
1642	RCAR_GP_PIN(1, 22),
1643	};
1644
1645	static const unsigned int pwm2_b_mux[] = {
1646	PWM2_B_MARK,
1647	};
1648
1649	static const unsigned int pwm2_c_pins[] = {
1650	/* PWM */
1651	RCAR_GP_PIN(2, 31),
1652	};
1653
1654	static const unsigned int pwm2_c_mux[] = {
1655	PWM2_C_MARK,
1656	};
1657
1658	/* - PWM3 ------------------------------------------------------------------ */
1659	static const unsigned int pwm3_a_pins[] = {
1660	/* PWM */
1661	RCAR_GP_PIN(2, 4),
1662	};
1663
1664	static const unsigned int pwm3_a_mux[] = {
1665	PWM3_A_MARK,
1666	};
1667
1668	static const unsigned int pwm3_b_pins[] = {
1669	/* PWM */
1670	RCAR_GP_PIN(1, 27),
1671	};
1672
1673	static const unsigned int pwm3_b_mux[] = {
1674	PWM3_B_MARK,
1675	};
1676
1677	static const unsigned int pwm3_c_pins[] = {
1678	/* PWM */
1679	RCAR_GP_PIN(4, 0),
1680	};
1681
1682	static const unsigned int pwm3_c_mux[] = {
1683	PWM3_C_MARK,
1684	};
1685
1686	/* - QSPI0 ------------------------------------------------------------------ */
1687	static const unsigned int qspi0_ctrl_pins[] = {
1688	/* QSPI0_SPCLK, QSPI0_SSL */
1689	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
1690	};
1691	static const unsigned int qspi0_ctrl_mux[] = {
1692	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1693	};
1694	/* - QSPI1 ------------------------------------------------------------------ */
1695	static const unsigned int qspi1_ctrl_pins[] = {
1696	/* QSPI1_SPCLK, QSPI1_SSL */
1697	RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 11),
1698	};
1699	static const unsigned int qspi1_ctrl_mux[] = {
1700	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1701	};
1702
1703	/* - RPC -------------------------------------------------------------------- */
1704	static const unsigned int rpc_clk_pins[] = {
1705	/* Octal-SPI flash: C/SCLK */
1706	/* HyperFlash: CK, CK# */
1707	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 6),
1708	};
1709	static const unsigned int rpc_clk_mux[] = {
1710	QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1711	};
1712	static const unsigned int rpc_ctrl_pins[] = {
1713	/* Octal-SPI flash: S#/CS, DQS */
1714	/* HyperFlash: CS#, RDS */
1715	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11),
1716	};
1717	static const unsigned int rpc_ctrl_mux[] = {
1718	QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1719	};
1720	static const unsigned int rpc_data_pins[] = {
1721	/* DQ[0:7] */
1722	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
1723	RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
1724	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 8),
1725	RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 10),
1726	};
1727	static const unsigned int rpc_data_mux[] = {
1728	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1729	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1730	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1731	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1732	};
1733	static const unsigned int rpc_reset_pins[] = {
1734	/* RPC_RESET# */
1735	RCAR_GP_PIN(6, 12),
1736	};
1737	static const unsigned int rpc_reset_mux[] = {
1738	RPC_RESET_N_MARK,
1739	};
1740	static const unsigned int rpc_int_pins[] = {
1741	/* RPC_INT# */
1742	RCAR_GP_PIN(6, 13),
1743	};
1744	static const unsigned int rpc_int_mux[] = {
1745	RPC_INT_N_MARK,
1746	};
1747
1748	/* - SCIF0 ------------------------------------------------------------------ */
1749	static const unsigned int scif0_data_a_pins[] = {
1750	/* RX, TX */
1751	RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1752	};
1753	static const unsigned int scif0_data_a_mux[] = {
1754	RX0_A_MARK, TX0_A_MARK,
1755	};
1756	static const unsigned int scif0_clk_a_pins[] = {
1757	/* SCK */
1758	RCAR_GP_PIN(4, 19),
1759	};
1760	static const unsigned int scif0_clk_a_mux[] = {
1761	SCK0_A_MARK,
1762	};
1763	static const unsigned int scif0_data_b_pins[] = {
1764	/* RX, TX */
1765	RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
1766	};
1767	static const unsigned int scif0_data_b_mux[] = {
1768	RX0_B_MARK, TX0_B_MARK,
1769	};
1770	static const unsigned int scif0_clk_b_pins[] = {
1771	/* SCK */
1772	RCAR_GP_PIN(5, 2),
1773	};
1774	static const unsigned int scif0_clk_b_mux[] = {
1775	SCK0_B_MARK,
1776	};
1777	static const unsigned int scif0_ctrl_pins[] = {
1778	/* RTS, CTS */
1779	RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1780	};
1781	static const unsigned int scif0_ctrl_mux[] = {
1782	RTS0_N_MARK, CTS0_N_MARK,
1783	};
1784	/* - SCIF1 ------------------------------------------------------------------ */
1785	static const unsigned int scif1_data_a_pins[] = {
1786	/* RX, TX */
1787	RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
1788	};
1789	static const unsigned int scif1_data_a_mux[] = {
1790	RX1_A_MARK, TX1_A_MARK,
1791	};
1792	static const unsigned int scif1_clk_a_pins[] = {
1793	/* SCK */
1794	RCAR_GP_PIN(4, 22),
1795	};
1796	static const unsigned int scif1_clk_a_mux[] = {
1797	SCK1_A_MARK,
1798	};
1799	static const unsigned int scif1_data_b_pins[] = {
1800	/* RX, TX */
1801	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
1802	};
1803	static const unsigned int scif1_data_b_mux[] = {
1804	RX1_B_MARK, TX1_B_MARK,
1805	};
1806	static const unsigned int scif1_clk_b_pins[] = {
1807	/* SCK */
1808	RCAR_GP_PIN(2, 25),
1809	};
1810	static const unsigned int scif1_clk_b_mux[] = {
1811	SCK1_B_MARK,
1812	};
1813	static const unsigned int scif1_ctrl_pins[] = {
1814	/* RTS, CTS */
1815	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1816	};
1817	static const unsigned int scif1_ctrl_mux[] = {
1818	RTS1_N_MARK, CTS1_N_MARK,
1819	};
1820
1821	/* - SCIF2 ------------------------------------------------------------------ */
1822	static const unsigned int scif2_data_pins[] = {
1823	/* RX, TX */
1824	RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
1825	};
1826	static const unsigned int scif2_data_mux[] = {
1827	RX2_MARK, TX2_MARK,
1828	};
1829	static const unsigned int scif2_clk_pins[] = {
1830	/* SCK */
1831	RCAR_GP_PIN(4, 25),
1832	};
1833	static const unsigned int scif2_clk_mux[] = {
1834	SCK2_MARK,
1835	};
1836	/* - SCIF3 ------------------------------------------------------------------ */
1837	static const unsigned int scif3_data_a_pins[] = {
1838	/* RX, TX */
1839	RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
1840	};
1841	static const unsigned int scif3_data_a_mux[] = {
1842	RX3_A_MARK, TX3_A_MARK,
1843	};
1844	static const unsigned int scif3_clk_a_pins[] = {
1845	/* SCK */
1846	RCAR_GP_PIN(2, 30),
1847	};
1848	static const unsigned int scif3_clk_a_mux[] = {
1849	SCK3_A_MARK,
1850	};
1851	static const unsigned int scif3_data_b_pins[] = {
1852	/* RX, TX */
1853	RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
1854	};
1855	static const unsigned int scif3_data_b_mux[] = {
1856	RX3_B_MARK, TX3_B_MARK,
1857	};
1858	static const unsigned int scif3_clk_b_pins[] = {
1859	/* SCK */
1860	RCAR_GP_PIN(1, 29),
1861	};
1862	static const unsigned int scif3_clk_b_mux[] = {
1863	SCK3_B_MARK,
1864	};
1865	/* - SCIF4 ------------------------------------------------------------------ */
1866	static const unsigned int scif4_data_a_pins[] = {
1867	/* RX, TX */
1868	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1869	};
1870	static const unsigned int scif4_data_a_mux[] = {
1871	RX4_A_MARK, TX4_A_MARK,
1872	};
1873	static const unsigned int scif4_clk_a_pins[] = {
1874	/* SCK */
1875	RCAR_GP_PIN(2, 6),
1876	};
1877	static const unsigned int scif4_clk_a_mux[] = {
1878	SCK4_A_MARK,
1879	};
1880	static const unsigned int scif4_data_b_pins[] = {
1881	/* RX, TX */
1882	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1883	};
1884	static const unsigned int scif4_data_b_mux[] = {
1885	RX4_B_MARK, TX4_B_MARK,
1886	};
1887	static const unsigned int scif4_clk_b_pins[] = {
1888	/* SCK */
1889	RCAR_GP_PIN(1, 15),
1890	};
1891	static const unsigned int scif4_clk_b_mux[] = {
1892	SCK4_B_MARK,
1893	};
1894	/* - SCIF5 ------------------------------------------------------------------ */
1895	static const unsigned int scif5_data_a_pins[] = {
1896	/* RX, TX */
1897	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1898	};
1899	static const unsigned int scif5_data_a_mux[] = {
1900	RX5_A_MARK, TX5_A_MARK,
1901	};
1902	static const unsigned int scif5_clk_a_pins[] = {
1903	/* SCK */
1904	RCAR_GP_PIN(0, 6),
1905	};
1906	static const unsigned int scif5_clk_a_mux[] = {
1907	SCK5_A_MARK,
1908	};
1909	static const unsigned int scif5_data_b_pins[] = {
1910	/* RX, TX */
1911	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1912	};
1913	static const unsigned int scif5_data_b_mux[] = {
1914	RX5_B_MARK, TX5_B_MARK,
1915	};
1916	static const unsigned int scif5_clk_b_pins[] = {
1917	/* SCK */
1918	RCAR_GP_PIN(1, 3),
1919	};
1920	static const unsigned int scif5_clk_b_mux[] = {
1921	SCK5_B_MARK,
1922	};
1923	/* - SCIF Clock ------------------------------------------------------------- */
1924	static const unsigned int scif_clk_pins[] = {
1925	/* SCIF_CLK */
1926	RCAR_GP_PIN(2, 27),
1927	};
1928	static const unsigned int scif_clk_mux[] = {
1929	SCIF_CLK_MARK,
1930	};
1931
1932	/* - SSI ---------------------------------------------------------------*/
1933	static const unsigned int ssi3_data_pins[] = {
1934	/* SDATA */
1935	RCAR_GP_PIN(4, 3),
1936	};
1937	static const unsigned int ssi3_data_mux[] = {
1938	SSI_SDATA3_MARK,
1939	};
1940	static const unsigned int ssi34_ctrl_pins[] = {
1941	/* SCK, WS */
1942	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
1943	};
1944	static const unsigned int ssi34_ctrl_mux[] = {
1945	SSI_SCK34_MARK, SSI_WS34_MARK,
1946	};
1947	static const unsigned int ssi4_ctrl_a_pins[] = {
1948	/* SCK, WS */
1949	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1950	};
1951	static const unsigned int ssi4_ctrl_a_mux[] = {
1952	SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
1953	};
1954	static const unsigned int ssi4_data_a_pins[] = {
1955	/* SDATA */
1956	RCAR_GP_PIN(4, 6),
1957	};
1958	static const unsigned int ssi4_data_a_mux[] = {
1959	SSI_SDATA4_A_MARK,
1960	};
1961	static const unsigned int ssi4_ctrl_b_pins[] = {
1962	/* SCK, WS */
1963	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
1964	};
1965	static const unsigned int ssi4_ctrl_b_mux[] = {
1966	SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
1967	};
1968	static const unsigned int ssi4_data_b_pins[] = {
1969	/* SDATA */
1970	RCAR_GP_PIN(2, 16),
1971	};
1972	static const unsigned int ssi4_data_b_mux[] = {
1973	SSI_SDATA4_B_MARK,
1974	};
1975
1976	/* - USB0 ------------------------------------------------------------------- */
1977	static const unsigned int usb0_pins[] = {
1978	/* PWEN, OVC */
1979	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1980	};
1981	static const unsigned int usb0_mux[] = {
1982	USB0_PWEN_MARK, USB0_OVC_MARK,
1983	};
1984
1985	/* - VIN4 ------------------------------------------------------------------- */
1986	static const unsigned int vin4_data18_pins[] = {
1987	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1988	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1989	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1990	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1991	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
1992	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1993	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1994	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1995	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1996	};
1997	static const unsigned int vin4_data18_mux[] = {
1998	VI4_DATA2_MARK, VI4_DATA3_MARK,
1999	VI4_DATA4_MARK, VI4_DATA5_MARK,
2000	VI4_DATA6_MARK, VI4_DATA7_MARK,
2001	VI4_DATA10_MARK, VI4_DATA11_MARK,
2002	VI4_DATA12_MARK, VI4_DATA13_MARK,
2003	VI4_DATA14_MARK, VI4_DATA15_MARK,
2004	VI4_DATA18_MARK, VI4_DATA19_MARK,
2005	VI4_DATA20_MARK, VI4_DATA21_MARK,
2006	VI4_DATA22_MARK, VI4_DATA23_MARK,
2007	};
2008	static const unsigned int vin4_data_pins[] = {
2009	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
2010	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
2011	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
2012	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2013	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
2014	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2015	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2016	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
2017	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
2018	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
2019	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2020	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
2021	};
2022	static const unsigned int vin4_data_mux[] = {
2023	VI4_DATA0_MARK, VI4_DATA1_MARK,
2024	VI4_DATA2_MARK, VI4_DATA3_MARK,
2025	VI4_DATA4_MARK, VI4_DATA5_MARK,
2026	VI4_DATA6_MARK, VI4_DATA7_MARK,
2027	VI4_DATA8_MARK, VI4_DATA9_MARK,
2028	VI4_DATA10_MARK, VI4_DATA11_MARK,
2029	VI4_DATA12_MARK, VI4_DATA13_MARK,
2030	VI4_DATA14_MARK, VI4_DATA15_MARK,
2031	VI4_DATA16_MARK, VI4_DATA17_MARK,
2032	VI4_DATA18_MARK, VI4_DATA19_MARK,
2033	VI4_DATA20_MARK, VI4_DATA21_MARK,
2034	VI4_DATA22_MARK, VI4_DATA23_MARK,
2035	};
2036	static const unsigned int vin4_sync_pins[] = {
2037	/* HSYNC#, VSYNC# */
2038	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
2039	};
2040	static const unsigned int vin4_sync_mux[] = {
2041	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
2042	};
2043	static const unsigned int vin4_field_pins[] = {
2044	/* FIELD */
2045	RCAR_GP_PIN(2, 27),
2046	};
2047	static const unsigned int vin4_field_mux[] = {
2048	VI4_FIELD_MARK,
2049	};
2050	static const unsigned int vin4_clkenb_pins[] = {
2051	/* CLKENB */
2052	RCAR_GP_PIN(2, 28),
2053	};
2054	static const unsigned int vin4_clkenb_mux[] = {
2055	VI4_CLKENB_MARK,
2056	};
2057	static const unsigned int vin4_clk_pins[] = {
2058	/* CLK */
2059	RCAR_GP_PIN(2, 0),
2060	};
2061	static const unsigned int vin4_clk_mux[] = {
2062	VI4_CLK_MARK,
2063	};
2064
2065	static const struct sh_pfc_pin_group pinmux_groups[] = {
2066	SH_PFC_PIN_GROUP(audio_clk_a),
2067	SH_PFC_PIN_GROUP(audio_clk_b),
2068	SH_PFC_PIN_GROUP(audio_clkout),
2069	SH_PFC_PIN_GROUP(audio_clkout1),
2070	SH_PFC_PIN_GROUP(avb0_link),
2071	SH_PFC_PIN_GROUP(avb0_magic),
2072	SH_PFC_PIN_GROUP(avb0_phy_int),
2073	SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */
2074	SH_PFC_PIN_GROUP(avb0_mdio),
2075	SH_PFC_PIN_GROUP(avb0_mii),
2076	SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
2077	SH_PFC_PIN_GROUP(avb0_avtp_match_a),
2078	SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
2079	SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
2080	SH_PFC_PIN_GROUP(avb0_avtp_match_b),
2081	SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
2082	SH_PFC_PIN_GROUP(can0_data_a),
2083	SH_PFC_PIN_GROUP(can0_data_b),
2084	SH_PFC_PIN_GROUP(can1_data_a),
2085	SH_PFC_PIN_GROUP(can1_data_b),
2086	SH_PFC_PIN_GROUP(can_clk),
2087	SH_PFC_PIN_GROUP(canfd0_data),
2088	SH_PFC_PIN_GROUP(canfd1_data),
2089	SH_PFC_PIN_GROUP(du_rgb666),
2090	SH_PFC_PIN_GROUP(du_rgb888),
2091	SH_PFC_PIN_GROUP(du_clk_in_1),
2092	SH_PFC_PIN_GROUP(du_clk_out_0),
2093	SH_PFC_PIN_GROUP(du_sync),
2094	SH_PFC_PIN_GROUP(du_disp_cde),
2095	SH_PFC_PIN_GROUP(du_cde),
2096	SH_PFC_PIN_GROUP(du_disp),
2097	SH_PFC_PIN_GROUP(i2c0),
2098	SH_PFC_PIN_GROUP(i2c1),
2099	SH_PFC_PIN_GROUP(i2c2_a),
2100	SH_PFC_PIN_GROUP(i2c2_b),
2101	SH_PFC_PIN_GROUP(i2c3_a),
2102	SH_PFC_PIN_GROUP(i2c3_b),
2103	SH_PFC_PIN_GROUP(mlb_3pin),
2104	BUS_DATA_PIN_GROUP(mmc_data, 1),
2105	BUS_DATA_PIN_GROUP(mmc_data, 4),
2106	BUS_DATA_PIN_GROUP(mmc_data, 8),
2107	SH_PFC_PIN_GROUP(mmc_ctrl),
2108	SH_PFC_PIN_GROUP(msiof0_clk),
2109	SH_PFC_PIN_GROUP(msiof0_sync),
2110	SH_PFC_PIN_GROUP(msiof0_ss1),
2111	SH_PFC_PIN_GROUP(msiof0_ss2),
2112	SH_PFC_PIN_GROUP(msiof0_txd),
2113	SH_PFC_PIN_GROUP(msiof0_rxd),
2114	SH_PFC_PIN_GROUP(msiof1_clk),
2115	SH_PFC_PIN_GROUP(msiof1_sync),
2116	SH_PFC_PIN_GROUP(msiof1_ss1),
2117	SH_PFC_PIN_GROUP(msiof1_ss2),
2118	SH_PFC_PIN_GROUP(msiof1_txd),
2119	SH_PFC_PIN_GROUP(msiof1_rxd),
2120	SH_PFC_PIN_GROUP(msiof2_clk),
2121	SH_PFC_PIN_GROUP(msiof2_sync_a),
2122	SH_PFC_PIN_GROUP(msiof2_sync_b),
2123	SH_PFC_PIN_GROUP(msiof2_ss1),
2124	SH_PFC_PIN_GROUP(msiof2_ss2),
2125	SH_PFC_PIN_GROUP(msiof2_txd),
2126	SH_PFC_PIN_GROUP(msiof2_rxd),
2127	SH_PFC_PIN_GROUP(msiof3_clk_a),
2128	SH_PFC_PIN_GROUP(msiof3_sync_a),
2129	SH_PFC_PIN_GROUP(msiof3_ss1_a),
2130	SH_PFC_PIN_GROUP(msiof3_ss2_a),
2131	SH_PFC_PIN_GROUP(msiof3_txd_a),
2132	SH_PFC_PIN_GROUP(msiof3_rxd_a),
2133	SH_PFC_PIN_GROUP(msiof3_clk_b),
2134	SH_PFC_PIN_GROUP(msiof3_sync_b),
2135	SH_PFC_PIN_GROUP(msiof3_ss1_b),
2136	SH_PFC_PIN_GROUP(msiof3_ss2_b),
2137	SH_PFC_PIN_GROUP(msiof3_txd_b),
2138	SH_PFC_PIN_GROUP(msiof3_rxd_b),
2139	SH_PFC_PIN_GROUP(pwm0_a),
2140	SH_PFC_PIN_GROUP(pwm0_b),
2141	SH_PFC_PIN_GROUP(pwm0_c),
2142	SH_PFC_PIN_GROUP(pwm1_a),
2143	SH_PFC_PIN_GROUP(pwm1_b),
2144	SH_PFC_PIN_GROUP(pwm1_c),
2145	SH_PFC_PIN_GROUP(pwm2_a),
2146	SH_PFC_PIN_GROUP(pwm2_b),
2147	SH_PFC_PIN_GROUP(pwm2_c),
2148	SH_PFC_PIN_GROUP(pwm3_a),
2149	SH_PFC_PIN_GROUP(pwm3_b),
2150	SH_PFC_PIN_GROUP(pwm3_c),
2151	SH_PFC_PIN_GROUP(qspi0_ctrl),
2152	SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
2153	SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
2154	SH_PFC_PIN_GROUP(qspi1_ctrl),
2155	SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
2156	SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
2157	BUS_DATA_PIN_GROUP(rpc_clk, 1),
2158	BUS_DATA_PIN_GROUP(rpc_clk, 2),
2159	SH_PFC_PIN_GROUP(rpc_ctrl),
2160	SH_PFC_PIN_GROUP(rpc_data),
2161	SH_PFC_PIN_GROUP(rpc_reset),
2162	SH_PFC_PIN_GROUP(rpc_int),
2163	SH_PFC_PIN_GROUP(scif0_data_a),
2164	SH_PFC_PIN_GROUP(scif0_clk_a),
2165	SH_PFC_PIN_GROUP(scif0_data_b),
2166	SH_PFC_PIN_GROUP(scif0_clk_b),
2167	SH_PFC_PIN_GROUP(scif0_ctrl),
2168	SH_PFC_PIN_GROUP(scif1_data_a),
2169	SH_PFC_PIN_GROUP(scif1_clk_a),
2170	SH_PFC_PIN_GROUP(scif1_data_b),
2171	SH_PFC_PIN_GROUP(scif1_clk_b),
2172	SH_PFC_PIN_GROUP(scif1_ctrl),
2173	SH_PFC_PIN_GROUP(scif2_data),
2174	SH_PFC_PIN_GROUP(scif2_clk),
2175	SH_PFC_PIN_GROUP(scif3_data_a),
2176	SH_PFC_PIN_GROUP(scif3_clk_a),
2177	SH_PFC_PIN_GROUP(scif3_data_b),
2178	SH_PFC_PIN_GROUP(scif3_clk_b),
2179	SH_PFC_PIN_GROUP(scif4_data_a),
2180	SH_PFC_PIN_GROUP(scif4_clk_a),
2181	SH_PFC_PIN_GROUP(scif4_data_b),
2182	SH_PFC_PIN_GROUP(scif4_clk_b),
2183	SH_PFC_PIN_GROUP(scif5_data_a),
2184	SH_PFC_PIN_GROUP(scif5_clk_a),
2185	SH_PFC_PIN_GROUP(scif5_data_b),
2186	SH_PFC_PIN_GROUP(scif5_clk_b),
2187	SH_PFC_PIN_GROUP(scif_clk),
2188	SH_PFC_PIN_GROUP(ssi3_data),
2189	SH_PFC_PIN_GROUP(ssi34_ctrl),
2190	SH_PFC_PIN_GROUP(ssi4_ctrl_a),
2191	SH_PFC_PIN_GROUP(ssi4_data_a),
2192	SH_PFC_PIN_GROUP(ssi4_ctrl_b),
2193	SH_PFC_PIN_GROUP(ssi4_data_b),
2194	SH_PFC_PIN_GROUP(usb0),
2195	BUS_DATA_PIN_GROUP(vin4_data, 8),
2196	BUS_DATA_PIN_GROUP(vin4_data, 10),
2197	BUS_DATA_PIN_GROUP(vin4_data, 12),
2198	BUS_DATA_PIN_GROUP(vin4_data, 16),
2199	SH_PFC_PIN_GROUP(vin4_data18),
2200	BUS_DATA_PIN_GROUP(vin4_data, 20),
2201	BUS_DATA_PIN_GROUP(vin4_data, 24),
2202	SH_PFC_PIN_GROUP(vin4_sync),
2203	SH_PFC_PIN_GROUP(vin4_field),
2204	SH_PFC_PIN_GROUP(vin4_clkenb),
2205	SH_PFC_PIN_GROUP(vin4_clk),
2206	};
2207
2208	static const char * const audio_clk_groups[] = {
2209	"audio_clk_a",
2210	"audio_clk_b",
2211	"audio_clkout",
2212	"audio_clkout1",
2213	};
2214
2215	static const char * const avb0_groups[] = {
2216	"avb0_link",
2217	"avb0_magic",
2218	"avb0_phy_int",
2219	"avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */
2220	"avb0_mdio",
2221	"avb0_mii",
2222	"avb0_avtp_pps_a",
2223	"avb0_avtp_match_a",
2224	"avb0_avtp_capture_a",
2225	"avb0_avtp_pps_b",
2226	"avb0_avtp_match_b",
2227	"avb0_avtp_capture_b",
2228	};
2229
2230	static const char * const can0_groups[] = {
2231	"can0_data_a",
2232	"can0_data_b",
2233	};
2234	static const char * const can1_groups[] = {
2235	"can1_data_a",
2236	"can1_data_b",
2237	};
2238	static const char * const can_clk_groups[] = {
2239	"can_clk",
2240	};
2241
2242	static const char * const canfd0_groups[] = {
2243	"canfd0_data",
2244	};
2245	static const char * const canfd1_groups[] = {
2246	"canfd1_data",
2247	};
2248
2249	static const char * const du_groups[] = {
2250	"du_rgb666",
2251	"du_rgb888",
2252	"du_clk_in_1",
2253	"du_clk_out_0",
2254	"du_sync",
2255	"du_disp_cde",
2256	"du_cde",
2257	"du_disp",
2258	};
2259
2260	static const char * const i2c0_groups[] = {
2261	"i2c0",
2262	};
2263	static const char * const i2c1_groups[] = {
2264	"i2c1",
2265	};
2266
2267	static const char * const i2c2_groups[] = {
2268	"i2c2_a",
2269	"i2c2_b",
2270	};
2271
2272	static const char * const i2c3_groups[] = {
2273	"i2c3_a",
2274	"i2c3_b",
2275	};
2276
2277	static const char * const mlb_3pin_groups[] = {
2278	"mlb_3pin",
2279	};
2280
2281	static const char * const mmc_groups[] = {
2282	"mmc_data1",
2283	"mmc_data4",
2284	"mmc_data8",
2285	"mmc_ctrl",
2286	};
2287
2288	static const char * const msiof0_groups[] = {
2289	"msiof0_clk",
2290	"msiof0_sync",
2291	"msiof0_ss1",
2292	"msiof0_ss2",
2293	"msiof0_txd",
2294	"msiof0_rxd",
2295	};
2296
2297	static const char * const msiof1_groups[] = {
2298	"msiof1_clk",
2299	"msiof1_sync",
2300	"msiof1_ss1",
2301	"msiof1_ss2",
2302	"msiof1_txd",
2303	"msiof1_rxd",
2304	};
2305
2306	static const char * const msiof2_groups[] = {
2307	"msiof2_clk",
2308	"msiof2_sync_a",
2309	"msiof2_sync_b",
2310	"msiof2_ss1",
2311	"msiof2_ss2",
2312	"msiof2_txd",
2313	"msiof2_rxd",
2314	};
2315
2316	static const char * const msiof3_groups[] = {
2317	"msiof3_clk_a",
2318	"msiof3_sync_a",
2319	"msiof3_ss1_a",
2320	"msiof3_ss2_a",
2321	"msiof3_txd_a",
2322	"msiof3_rxd_a",
2323	"msiof3_clk_b",
2324	"msiof3_sync_b",
2325	"msiof3_ss1_b",
2326	"msiof3_ss2_b",
2327	"msiof3_txd_b",
2328	"msiof3_rxd_b",
2329	};
2330
2331	static const char * const pwm0_groups[] = {
2332	"pwm0_a",
2333	"pwm0_b",
2334	"pwm0_c",
2335	};
2336
2337	static const char * const pwm1_groups[] = {
2338	"pwm1_a",
2339	"pwm1_b",
2340	"pwm1_c",
2341	};
2342
2343	static const char * const pwm2_groups[] = {
2344	"pwm2_a",
2345	"pwm2_b",
2346	"pwm2_c",
2347	};
2348
2349	static const char * const pwm3_groups[] = {
2350	"pwm3_a",
2351	"pwm3_b",
2352	"pwm3_c",
2353	};
2354
2355	static const char * const qspi0_groups[] = {
2356	"qspi0_ctrl",
2357	"qspi0_data2",
2358	"qspi0_data4",
2359	};
2360
2361	static const char * const qspi1_groups[] = {
2362	"qspi1_ctrl",
2363	"qspi1_data2",
2364	"qspi1_data4",
2365	};
2366
2367	static const char * const rpc_groups[] = {
2368	"rpc_clk1",
2369	"rpc_clk2",
2370	"rpc_ctrl",
2371	"rpc_data",
2372	"rpc_reset",
2373	"rpc_int",
2374	};
2375
2376	static const char * const scif0_groups[] = {
2377	"scif0_data_a",
2378	"scif0_clk_a",
2379	"scif0_data_b",
2380	"scif0_clk_b",
2381	"scif0_ctrl",
2382	};
2383
2384	static const char * const scif1_groups[] = {
2385	"scif1_data_a",
2386	"scif1_clk_a",
2387	"scif1_data_b",
2388	"scif1_clk_b",
2389	"scif1_ctrl",
2390	};
2391
2392	static const char * const scif2_groups[] = {
2393	"scif2_data",
2394	"scif2_clk",
2395	};
2396
2397	static const char * const scif3_groups[] = {
2398	"scif3_data_a",
2399	"scif3_clk_a",
2400	"scif3_data_b",
2401	"scif3_clk_b",
2402	};
2403
2404	static const char * const scif4_groups[] = {
2405	"scif4_data_a",
2406	"scif4_clk_a",
2407	"scif4_data_b",
2408	"scif4_clk_b",
2409	};
2410
2411	static const char * const scif5_groups[] = {
2412	"scif5_data_a",
2413	"scif5_clk_a",
2414	"scif5_data_b",
2415	"scif5_clk_b",
2416	};
2417
2418	static const char * const scif_clk_groups[] = {
2419	"scif_clk",
2420	};
2421
2422	static const char * const ssi_groups[] = {
2423	"ssi3_data",
2424	"ssi34_ctrl",
2425	"ssi4_ctrl_a",
2426	"ssi4_data_a",
2427	"ssi4_ctrl_b",
2428	"ssi4_data_b",
2429	};
2430
2431	static const char * const usb0_groups[] = {
2432	"usb0",
2433	};
2434
2435	static const char * const vin4_groups[] = {
2436	"vin4_data8",
2437	"vin4_data10",
2438	"vin4_data12",
2439	"vin4_data16",
2440	"vin4_data18",
2441	"vin4_data20",
2442	"vin4_data24",
2443	"vin4_sync",
2444	"vin4_field",
2445	"vin4_clkenb",
2446	"vin4_clk",
2447	};
2448
2449	static const struct sh_pfc_function pinmux_functions[] = {
2450	SH_PFC_FUNCTION(audio_clk),
2451	SH_PFC_FUNCTION(avb0),
2452	SH_PFC_FUNCTION(can0),
2453	SH_PFC_FUNCTION(can1),
2454	SH_PFC_FUNCTION(can_clk),
2455	SH_PFC_FUNCTION(canfd0),
2456	SH_PFC_FUNCTION(canfd1),
2457	SH_PFC_FUNCTION(du),
2458	SH_PFC_FUNCTION(i2c0),
2459	SH_PFC_FUNCTION(i2c1),
2460	SH_PFC_FUNCTION(i2c2),
2461	SH_PFC_FUNCTION(i2c3),
2462	SH_PFC_FUNCTION(mlb_3pin),
2463	SH_PFC_FUNCTION(mmc),
2464	SH_PFC_FUNCTION(msiof0),
2465	SH_PFC_FUNCTION(msiof1),
2466	SH_PFC_FUNCTION(msiof2),
2467	SH_PFC_FUNCTION(msiof3),
2468	SH_PFC_FUNCTION(pwm0),
2469	SH_PFC_FUNCTION(pwm1),
2470	SH_PFC_FUNCTION(pwm2),
2471	SH_PFC_FUNCTION(pwm3),
2472	SH_PFC_FUNCTION(qspi0),
2473	SH_PFC_FUNCTION(qspi1),
2474	SH_PFC_FUNCTION(rpc),
2475	SH_PFC_FUNCTION(scif0),
2476	SH_PFC_FUNCTION(scif1),
2477	SH_PFC_FUNCTION(scif2),
2478	SH_PFC_FUNCTION(scif3),
2479	SH_PFC_FUNCTION(scif4),
2480	SH_PFC_FUNCTION(scif5),
2481	SH_PFC_FUNCTION(scif_clk),
2482	SH_PFC_FUNCTION(ssi),
2483	SH_PFC_FUNCTION(usb0),
2484	SH_PFC_FUNCTION(vin4),
2485	};
2486
2487	static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2488	#define F_(x, y) FN_##y
2489	#define FM(x) FN_##x
2490	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2491	GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2492	GROUP(
2493	/* GP0_31_9 RESERVED */
2494	GP_0_8_FN, GPSR0_8,
2495	GP_0_7_FN, GPSR0_7,
2496	GP_0_6_FN, GPSR0_6,
2497	GP_0_5_FN, GPSR0_5,
2498	GP_0_4_FN, GPSR0_4,
2499	GP_0_3_FN, GPSR0_3,
2500	GP_0_2_FN, GPSR0_2,
2501	GP_0_1_FN, GPSR0_1,
2502	GP_0_0_FN, GPSR0_0, ))
2503	},
2504	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2505	GP_1_31_FN, GPSR1_31,
2506	GP_1_30_FN, GPSR1_30,
2507	GP_1_29_FN, GPSR1_29,
2508	GP_1_28_FN, GPSR1_28,
2509	GP_1_27_FN, GPSR1_27,
2510	GP_1_26_FN, GPSR1_26,
2511	GP_1_25_FN, GPSR1_25,
2512	GP_1_24_FN, GPSR1_24,
2513	GP_1_23_FN, GPSR1_23,
2514	GP_1_22_FN, GPSR1_22,
2515	GP_1_21_FN, GPSR1_21,
2516	GP_1_20_FN, GPSR1_20,
2517	GP_1_19_FN, GPSR1_19,
2518	GP_1_18_FN, GPSR1_18,
2519	GP_1_17_FN, GPSR1_17,
2520	GP_1_16_FN, GPSR1_16,
2521	GP_1_15_FN, GPSR1_15,
2522	GP_1_14_FN, GPSR1_14,
2523	GP_1_13_FN, GPSR1_13,
2524	GP_1_12_FN, GPSR1_12,
2525	GP_1_11_FN, GPSR1_11,
2526	GP_1_10_FN, GPSR1_10,
2527	GP_1_9_FN, GPSR1_9,
2528	GP_1_8_FN, GPSR1_8,
2529	GP_1_7_FN, GPSR1_7,
2530	GP_1_6_FN, GPSR1_6,
2531	GP_1_5_FN, GPSR1_5,
2532	GP_1_4_FN, GPSR1_4,
2533	GP_1_3_FN, GPSR1_3,
2534	GP_1_2_FN, GPSR1_2,
2535	GP_1_1_FN, GPSR1_1,
2536	GP_1_0_FN, GPSR1_0, ))
2537	},
2538	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2539	GP_2_31_FN, GPSR2_31,
2540	GP_2_30_FN, GPSR2_30,
2541	GP_2_29_FN, GPSR2_29,
2542	GP_2_28_FN, GPSR2_28,
2543	GP_2_27_FN, GPSR2_27,
2544	GP_2_26_FN, GPSR2_26,
2545	GP_2_25_FN, GPSR2_25,
2546	GP_2_24_FN, GPSR2_24,
2547	GP_2_23_FN, GPSR2_23,
2548	GP_2_22_FN, GPSR2_22,
2549	GP_2_21_FN, GPSR2_21,
2550	GP_2_20_FN, GPSR2_20,
2551	GP_2_19_FN, GPSR2_19,
2552	GP_2_18_FN, GPSR2_18,
2553	GP_2_17_FN, GPSR2_17,
2554	GP_2_16_FN, GPSR2_16,
2555	GP_2_15_FN, GPSR2_15,
2556	GP_2_14_FN, GPSR2_14,
2557	GP_2_13_FN, GPSR2_13,
2558	GP_2_12_FN, GPSR2_12,
2559	GP_2_11_FN, GPSR2_11,
2560	GP_2_10_FN, GPSR2_10,
2561	GP_2_9_FN, GPSR2_9,
2562	GP_2_8_FN, GPSR2_8,
2563	GP_2_7_FN, GPSR2_7,
2564	GP_2_6_FN, GPSR2_6,
2565	GP_2_5_FN, GPSR2_5,
2566	GP_2_4_FN, GPSR2_4,
2567	GP_2_3_FN, GPSR2_3,
2568	GP_2_2_FN, GPSR2_2,
2569	GP_2_1_FN, GPSR2_1,
2570	GP_2_0_FN, GPSR2_0, ))
2571	},
2572	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2573	GROUP(-22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2574	GROUP(
2575	/* GP3_31_10 RESERVED */
2576	GP_3_9_FN, GPSR3_9,
2577	GP_3_8_FN, GPSR3_8,
2578	GP_3_7_FN, GPSR3_7,
2579	GP_3_6_FN, GPSR3_6,
2580	GP_3_5_FN, GPSR3_5,
2581	GP_3_4_FN, GPSR3_4,
2582	GP_3_3_FN, GPSR3_3,
2583	GP_3_2_FN, GPSR3_2,
2584	GP_3_1_FN, GPSR3_1,
2585	GP_3_0_FN, GPSR3_0, ))
2586	},
2587	{ PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2588	GP_4_31_FN, GPSR4_31,
2589	GP_4_30_FN, GPSR4_30,
2590	GP_4_29_FN, GPSR4_29,
2591	GP_4_28_FN, GPSR4_28,
2592	GP_4_27_FN, GPSR4_27,
2593	GP_4_26_FN, GPSR4_26,
2594	GP_4_25_FN, GPSR4_25,
2595	GP_4_24_FN, GPSR4_24,
2596	GP_4_23_FN, GPSR4_23,
2597	GP_4_22_FN, GPSR4_22,
2598	GP_4_21_FN, GPSR4_21,
2599	GP_4_20_FN, GPSR4_20,
2600	GP_4_19_FN, GPSR4_19,
2601	GP_4_18_FN, GPSR4_18,
2602	GP_4_17_FN, GPSR4_17,
2603	GP_4_16_FN, GPSR4_16,
2604	GP_4_15_FN, GPSR4_15,
2605	GP_4_14_FN, GPSR4_14,
2606	GP_4_13_FN, GPSR4_13,
2607	GP_4_12_FN, GPSR4_12,
2608	GP_4_11_FN, GPSR4_11,
2609	GP_4_10_FN, GPSR4_10,
2610	GP_4_9_FN, GPSR4_9,
2611	GP_4_8_FN, GPSR4_8,
2612	GP_4_7_FN, GPSR4_7,
2613	GP_4_6_FN, GPSR4_6,
2614	GP_4_5_FN, GPSR4_5,
2615	GP_4_4_FN, GPSR4_4,
2616	GP_4_3_FN, GPSR4_3,
2617	GP_4_2_FN, GPSR4_2,
2618	GP_4_1_FN, GPSR4_1,
2619	GP_4_0_FN, GPSR4_0, ))
2620	},
2621	{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2622	GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2623	1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2624	GROUP(
2625	/* GP5_31_21 RESERVED */
2626	GP_5_20_FN, GPSR5_20,
2627	GP_5_19_FN, GPSR5_19,
2628	GP_5_18_FN, GPSR5_18,
2629	GP_5_17_FN, GPSR5_17,
2630	GP_5_16_FN, GPSR5_16,
2631	GP_5_15_FN, GPSR5_15,
2632	GP_5_14_FN, GPSR5_14,
2633	GP_5_13_FN, GPSR5_13,
2634	GP_5_12_FN, GPSR5_12,
2635	GP_5_11_FN, GPSR5_11,
2636	GP_5_10_FN, GPSR5_10,
2637	GP_5_9_FN, GPSR5_9,
2638	GP_5_8_FN, GPSR5_8,
2639	GP_5_7_FN, GPSR5_7,
2640	GP_5_6_FN, GPSR5_6,
2641	GP_5_5_FN, GPSR5_5,
2642	GP_5_4_FN, GPSR5_4,
2643	GP_5_3_FN, GPSR5_3,
2644	GP_5_2_FN, GPSR5_2,
2645	GP_5_1_FN, GPSR5_1,
2646	GP_5_0_FN, GPSR5_0, ))
2647	},
2648	{ PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
2649	GROUP(-18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2650	1, 1, 1),
2651	GROUP(
2652	/* GP6_31_14 RESERVED */
2653	GP_6_13_FN, GPSR6_13,
2654	GP_6_12_FN, GPSR6_12,
2655	GP_6_11_FN, GPSR6_11,
2656	GP_6_10_FN, GPSR6_10,
2657	GP_6_9_FN, GPSR6_9,
2658	GP_6_8_FN, GPSR6_8,
2659	GP_6_7_FN, GPSR6_7,
2660	GP_6_6_FN, GPSR6_6,
2661	GP_6_5_FN, GPSR6_5,
2662	GP_6_4_FN, GPSR6_4,
2663	GP_6_3_FN, GPSR6_3,
2664	GP_6_2_FN, GPSR6_2,
2665	GP_6_1_FN, GPSR6_1,
2666	GP_6_0_FN, GPSR6_0, ))
2667	},
2668	#undef F_
2669	#undef FM
2670
2671	#define F_(x, y) x,
2672	#define FM(x) FN_##x,
2673	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2674	IP0_31_28
2675	IP0_27_24
2676	IP0_23_20
2677	IP0_19_16
2678	IP0_15_12
2679	IP0_11_8
2680	IP0_7_4
2681	IP0_3_0 ))
2682	},
2683	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2684	IP1_31_28
2685	IP1_27_24
2686	IP1_23_20
2687	IP1_19_16
2688	IP1_15_12
2689	IP1_11_8
2690	IP1_7_4
2691	IP1_3_0 ))
2692	},
2693	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2694	IP2_31_28
2695	IP2_27_24
2696	IP2_23_20
2697	IP2_19_16
2698	IP2_15_12
2699	IP2_11_8
2700	IP2_7_4
2701	IP2_3_0 ))
2702	},
2703	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2704	IP3_31_28
2705	IP3_27_24
2706	IP3_23_20
2707	IP3_19_16
2708	IP3_15_12
2709	IP3_11_8
2710	IP3_7_4
2711	IP3_3_0 ))
2712	},
2713	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2714	IP4_31_28
2715	IP4_27_24
2716	IP4_23_20
2717	IP4_19_16
2718	IP4_15_12
2719	IP4_11_8
2720	IP4_7_4
2721	IP4_3_0 ))
2722	},
2723	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2724	IP5_31_28
2725	IP5_27_24
2726	IP5_23_20
2727	IP5_19_16
2728	IP5_15_12
2729	IP5_11_8
2730	IP5_7_4
2731	IP5_3_0 ))
2732	},
2733	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2734	IP6_31_28
2735	IP6_27_24
2736	IP6_23_20
2737	IP6_19_16
2738	IP6_15_12
2739	IP6_11_8
2740	IP6_7_4
2741	IP6_3_0 ))
2742	},
2743	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2744	IP7_31_28
2745	IP7_27_24
2746	IP7_23_20
2747	IP7_19_16
2748	IP7_15_12
2749	IP7_11_8
2750	IP7_7_4
2751	IP7_3_0 ))
2752	},
2753	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2754	IP8_31_28
2755	IP8_27_24
2756	IP8_23_20
2757	IP8_19_16
2758	IP8_15_12
2759	IP8_11_8
2760	IP8_7_4
2761	IP8_3_0 ))
2762	},
2763	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2764	IP9_31_28
2765	IP9_27_24
2766	IP9_23_20
2767	IP9_19_16
2768	IP9_15_12
2769	IP9_11_8
2770	IP9_7_4
2771	IP9_3_0 ))
2772	},
2773	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
2774	IP10_31_28
2775	IP10_27_24
2776	IP10_23_20
2777	IP10_19_16
2778	IP10_15_12
2779	IP10_11_8
2780	IP10_7_4
2781	IP10_3_0 ))
2782	},
2783	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
2784	IP11_31_28
2785	IP11_27_24
2786	IP11_23_20
2787	IP11_19_16
2788	IP11_15_12
2789	IP11_11_8
2790	IP11_7_4
2791	IP11_3_0 ))
2792	},
2793	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
2794	IP12_31_28
2795	IP12_27_24
2796	IP12_23_20
2797	IP12_19_16
2798	IP12_15_12
2799	IP12_11_8
2800	IP12_7_4
2801	IP12_3_0 ))
2802	},
2803	{ PINMUX_CFG_REG_VAR("IPSR13", 0xe6060234, 32,
2804	GROUP(-24, 4, 4),
2805	GROUP(
2806	/* IP13_31_8 RESERVED */
2807	IP13_7_4
2808	IP13_3_0 ))
2809	},
2810	#undef F_
2811	#undef FM
2812
2813	#define F_(x, y) x,
2814	#define FM(x) FN_##x,
2815	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2816	GROUP(-1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, -1,
2817	1, 1, 1, 1, 1, 1, -4, 1, 1, 1, 1, 1, 1),
2818	GROUP(
2819	/* RESERVED 31 */
2820	MOD_SEL0_30
2821	MOD_SEL0_29
2822	MOD_SEL0_28
2823	MOD_SEL0_27
2824	MOD_SEL0_26
2825	MOD_SEL0_25
2826	MOD_SEL0_24_23
2827	MOD_SEL0_22_21
2828	MOD_SEL0_20_19
2829	MOD_SEL0_18_17
2830	/* RESERVED 16 */
2831	MOD_SEL0_15
2832	MOD_SEL0_14
2833	MOD_SEL0_13
2834	MOD_SEL0_12
2835	MOD_SEL0_11
2836	MOD_SEL0_10
2837	/* RESERVED 9, 8, 7, 6 */
2838	MOD_SEL0_5
2839	MOD_SEL0_4
2840	MOD_SEL0_3
2841	MOD_SEL0_2
2842	MOD_SEL0_1
2843	MOD_SEL0_0 ))
2844	},
2845	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2846	GROUP(1, 1, 1, 1, 1, 1, -26),
2847	GROUP(
2848	MOD_SEL1_31
2849	MOD_SEL1_30
2850	MOD_SEL1_29
2851	MOD_SEL1_28
2852	MOD_SEL1_27
2853	MOD_SEL1_26
2854	/* RESERVED 25-0 */ ))
2855	},
2856	{ /* sentinel */ }
2857	};
2858
2859	enum ioctrl_regs {
2860	POCCTRL0,
2861	POCCTRL2,
2862	TDSELCTRL,
2863	};
2864
2865	static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2866	[POCCTRL0] = { 0xe6060380, },
2867	[POCCTRL2] = { .reg: 0xe6060388, },
2868	[TDSELCTRL] = { .reg: 0xe60603c0, },
2869	{ /* sentinel */ }
2870	};
2871
2872
2873	static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
2874	{
2875	switch (pin) {
2876	case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 9):
2877	*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2878	return 29 - (pin - RCAR_GP_PIN(3, 0));
2879
2880	case PIN_VDDQ_AVB0:
2881	*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
2882	return 0;
2883
2884	default:
2885	return -EINVAL;
2886	}
2887	}
2888
2889	static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2890	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2891	[ 0] = RCAR_GP_PIN(1, 9), /* DU_DG1 */
2892	[ 1] = RCAR_GP_PIN(1, 8), /* DU_DG0 */
2893	[ 2] = RCAR_GP_PIN(1, 7), /* DU_DB7 */
2894	[ 3] = RCAR_GP_PIN(1, 6), /* DU_DB6 */
2895	[ 4] = RCAR_GP_PIN(1, 5), /* DU_DB5 */
2896	[ 5] = RCAR_GP_PIN(1, 4), /* DU_DB4 */
2897	[ 6] = RCAR_GP_PIN(1, 3), /* DU_DB3 */
2898	[ 7] = RCAR_GP_PIN(1, 2), /* DU_DB2 */
2899	[ 8] = RCAR_GP_PIN(1, 1), /* DU_DB1 */
2900	[ 9] = RCAR_GP_PIN(1, 0), /* DU_DB0 */
2901	[10] = PIN_MLB_REF, /* MLB_REF */
2902	[11] = RCAR_GP_PIN(0, 8), /* MLB_SIG */
2903	[12] = RCAR_GP_PIN(0, 7), /* MLB_DAT */
2904	[13] = RCAR_GP_PIN(0, 6), /* MLB_CLK */
2905	[14] = RCAR_GP_PIN(0, 5), /* MSIOF2_RXD */
2906	[15] = RCAR_GP_PIN(0, 4), /* MSIOF2_TXD */
2907	[16] = RCAR_GP_PIN(0, 3), /* MSIOF2_SCK */
2908	[17] = RCAR_GP_PIN(0, 2), /* IRQ0_A */
2909	[18] = RCAR_GP_PIN(0, 1), /* USB0_OVC */
2910	[19] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */
2911	[20] = PIN_PRESETOUT_N, /* PRESETOUT# */
2912	[21] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
2913	[22] = PIN_FSCLKST_N, /* FSCLKST# */
2914	[23] = SH_PFC_PIN_NONE,
2915	[24] = SH_PFC_PIN_NONE,
2916	[25] = SH_PFC_PIN_NONE,
2917	[26] = SH_PFC_PIN_NONE,
2918	[27] = SH_PFC_PIN_NONE,
2919	[28] = PIN_TDI, /* TDI */
2920	[29] = PIN_TMS, /* TMS */
2921	[30] = PIN_TCK, /* TCK */
2922	[31] = PIN_TRST_N, /* TRST# */
2923	} },
2924	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2925	[ 0] = RCAR_GP_PIN(2, 9), /* VI4_DATA8 */
2926	[ 1] = RCAR_GP_PIN(2, 8), /* VI4_DATA7 */
2927	[ 2] = RCAR_GP_PIN(2, 7), /* VI4_DATA6 */
2928	[ 3] = RCAR_GP_PIN(2, 6), /* VI4_DATA5 */
2929	[ 4] = RCAR_GP_PIN(2, 5), /* VI4_DATA4 */
2930	[ 5] = RCAR_GP_PIN(2, 4), /* VI4_DATA3 */
2931	[ 6] = RCAR_GP_PIN(2, 3), /* VI4_DATA2 */
2932	[ 7] = RCAR_GP_PIN(2, 2), /* VI4_DATA1 */
2933	[ 8] = RCAR_GP_PIN(2, 1), /* VI4_DATA0 */
2934	[ 9] = RCAR_GP_PIN(2, 0), /* VI4_CLK */
2935	[10] = RCAR_GP_PIN(1, 31), /* QPOLB */
2936	[11] = RCAR_GP_PIN(1, 30), /* QPOLA */
2937	[12] = RCAR_GP_PIN(1, 29), /* DU_CDE */
2938	[13] = RCAR_GP_PIN(1, 28), /* DU_DISP/CDE */
2939	[14] = RCAR_GP_PIN(1, 27), /* DU_DISP */
2940	[15] = RCAR_GP_PIN(1, 26), /* DU_VSYNC */
2941	[16] = RCAR_GP_PIN(1, 25), /* DU_HSYNC */
2942	[17] = RCAR_GP_PIN(1, 24), /* DU_DOTCLKOUT0 */
2943	[18] = RCAR_GP_PIN(1, 23), /* DU_DR7 */
2944	[19] = RCAR_GP_PIN(1, 22), /* DU_DR6 */
2945	[20] = RCAR_GP_PIN(1, 21), /* DU_DR5 */
2946	[21] = RCAR_GP_PIN(1, 20), /* DU_DR4 */
2947	[22] = RCAR_GP_PIN(1, 19), /* DU_DR3 */
2948	[23] = RCAR_GP_PIN(1, 18), /* DU_DR2 */
2949	[24] = RCAR_GP_PIN(1, 17), /* DU_DR1 */
2950	[25] = RCAR_GP_PIN(1, 16), /* DU_DR0 */
2951	[26] = RCAR_GP_PIN(1, 15), /* DU_DG7 */
2952	[27] = RCAR_GP_PIN(1, 14), /* DU_DG6 */
2953	[28] = RCAR_GP_PIN(1, 13), /* DU_DG5 */
2954	[29] = RCAR_GP_PIN(1, 12), /* DU_DG4 */
2955	[30] = RCAR_GP_PIN(1, 11), /* DU_DG3 */
2956	[31] = RCAR_GP_PIN(1, 10), /* DU_DG2 */
2957	} },
2958	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2959	[ 0] = RCAR_GP_PIN(3, 8), /* NFDATA6 */
2960	[ 1] = RCAR_GP_PIN(3, 7), /* NFDATA5 */
2961	[ 2] = RCAR_GP_PIN(3, 6), /* NFDATA4 */
2962	[ 3] = RCAR_GP_PIN(3, 5), /* NFDATA3 */
2963	[ 4] = RCAR_GP_PIN(3, 4), /* NFDATA2 */
2964	[ 5] = RCAR_GP_PIN(3, 3), /* NFDATA1 */
2965	[ 6] = RCAR_GP_PIN(3, 2), /* NFDATA0 */
2966	[ 7] = RCAR_GP_PIN(3, 1), /* NFWE# (PUEN) / NFRE# (PUD) */
2967	[ 8] = RCAR_GP_PIN(3, 0), /* NFRE# (PUEN) / NFWE# (PUD) */
2968	[ 9] = RCAR_GP_PIN(4, 0), /* NFRB# */
2969	[10] = RCAR_GP_PIN(2, 31), /* NFCE# */
2970	[11] = RCAR_GP_PIN(2, 30), /* NFCLE */
2971	[12] = RCAR_GP_PIN(2, 29), /* NFALE */
2972	[13] = RCAR_GP_PIN(2, 28), /* VI4_CLKENB */
2973	[14] = RCAR_GP_PIN(2, 27), /* VI4_FIELD */
2974	[15] = RCAR_GP_PIN(2, 26), /* VI4_HSYNC# */
2975	[16] = RCAR_GP_PIN(2, 25), /* VI4_VSYNC# */
2976	[17] = RCAR_GP_PIN(2, 24), /* VI4_DATA23 */
2977	[18] = RCAR_GP_PIN(2, 23), /* VI4_DATA22 */
2978	[19] = RCAR_GP_PIN(2, 22), /* VI4_DATA21 */
2979	[20] = RCAR_GP_PIN(2, 21), /* VI4_DATA20 */
2980	[21] = RCAR_GP_PIN(2, 20), /* VI4_DATA19 */
2981	[22] = RCAR_GP_PIN(2, 19), /* VI4_DATA18 */
2982	[23] = RCAR_GP_PIN(2, 18), /* VI4_DATA17 */
2983	[24] = RCAR_GP_PIN(2, 17), /* VI4_DATA16 */
2984	[25] = RCAR_GP_PIN(2, 16), /* VI4_DATA15 */
2985	[26] = RCAR_GP_PIN(2, 15), /* VI4_DATA14 */
2986	[27] = RCAR_GP_PIN(2, 14), /* VI4_DATA13 */
2987	[28] = RCAR_GP_PIN(2, 13), /* VI4_DATA12 */
2988	[29] = RCAR_GP_PIN(2, 12), /* VI4_DATA11 */
2989	[30] = RCAR_GP_PIN(2, 11), /* VI4_DATA10 */
2990	[31] = RCAR_GP_PIN(2, 10), /* VI4_DATA9 */
2991	} },
2992	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2993	[ 0] = RCAR_GP_PIN(4, 31), /* CAN0_RX_A */
2994	[ 1] = RCAR_GP_PIN(5, 2), /* CAN_CLK */
2995	[ 2] = RCAR_GP_PIN(5, 1), /* TPU0TO1_A */
2996	[ 3] = RCAR_GP_PIN(5, 0), /* TPU0TO0_A */
2997	[ 4] = RCAR_GP_PIN(4, 27), /* TX2 */
2998	[ 5] = RCAR_GP_PIN(4, 26), /* RX2 */
2999	[ 6] = RCAR_GP_PIN(4, 25), /* SCK2 */
3000	[ 7] = RCAR_GP_PIN(4, 24), /* TX1_A */
3001	[ 8] = RCAR_GP_PIN(4, 23), /* RX1_A */
3002	[ 9] = RCAR_GP_PIN(4, 22), /* SCK1_A */
3003	[10] = RCAR_GP_PIN(4, 21), /* TX0_A */
3004	[11] = RCAR_GP_PIN(4, 20), /* RX0_A */
3005	[12] = RCAR_GP_PIN(4, 19), /* SCK0_A */
3006	[13] = RCAR_GP_PIN(4, 18), /* MSIOF1_RXD */
3007	[14] = RCAR_GP_PIN(4, 17), /* MSIOF1_TXD */
3008	[15] = RCAR_GP_PIN(4, 16), /* MSIOF1_SCK */
3009	[16] = RCAR_GP_PIN(4, 15), /* MSIOF0_RXD */
3010	[17] = RCAR_GP_PIN(4, 14), /* MSIOF0_TXD */
3011	[18] = RCAR_GP_PIN(4, 13), /* MSIOF0_SYNC */
3012	[19] = RCAR_GP_PIN(4, 12), /* MSIOF0_SCK */
3013	[20] = RCAR_GP_PIN(4, 11), /* SDA1 */
3014	[21] = RCAR_GP_PIN(4, 10), /* SCL1 */
3015	[22] = RCAR_GP_PIN(4, 9), /* SDA0 */
3016	[23] = RCAR_GP_PIN(4, 8), /* SCL0 */
3017	[24] = RCAR_GP_PIN(4, 7), /* SSI_WS4_A */
3018	[25] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4_A */
3019	[26] = RCAR_GP_PIN(4, 5), /* SSI_SCK4_A */
3020	[27] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */
3021	[28] = RCAR_GP_PIN(4, 3), /* SSI_SDATA3 */
3022	[29] = RCAR_GP_PIN(4, 2), /* SSI_SCK34 */
3023	[30] = RCAR_GP_PIN(4, 1), /* AUDIO_CLKA */
3024	[31] = RCAR_GP_PIN(3, 9), /* NFDATA7 */
3025	} },
3026	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
3027	[ 0] = RCAR_GP_PIN(6, 10), /* QSPI1_IO3 */
3028	[ 1] = RCAR_GP_PIN(6, 9), /* QSPI1_IO2 */
3029	[ 2] = RCAR_GP_PIN(6, 8), /* QSPI1_MISO_IO1 */
3030	[ 3] = RCAR_GP_PIN(6, 7), /* QSPI1_MOSI_IO0 */
3031	[ 4] = RCAR_GP_PIN(6, 6), /* QSPI1_SPCLK */
3032	[ 5] = RCAR_GP_PIN(6, 5), /* QSPI0_SSL */
3033	[ 6] = RCAR_GP_PIN(6, 4), /* QSPI0_IO3 */
3034	[ 7] = RCAR_GP_PIN(6, 3), /* QSPI0_IO2 */
3035	[ 8] = RCAR_GP_PIN(6, 2), /* QSPI0_MISO_IO1 */
3036	[ 9] = RCAR_GP_PIN(6, 1), /* QSPI0_MOSI_IO0 */
3037	[10] = RCAR_GP_PIN(6, 0), /* QSPI0_SPCLK */
3038	[11] = RCAR_GP_PIN(5, 20), /* AVB0_LINK */
3039	[12] = RCAR_GP_PIN(5, 19), /* AVB0_PHY_INT */
3040	[13] = RCAR_GP_PIN(5, 18), /* AVB0_MAGIC */
3041	[14] = RCAR_GP_PIN(5, 17), /* AVB0_MDC */
3042	[15] = RCAR_GP_PIN(5, 16), /* AVB0_MDIO */
3043	[16] = RCAR_GP_PIN(5, 15), /* AVB0_TXCREFCLK */
3044	[17] = RCAR_GP_PIN(5, 14), /* AVB0_TD3 */
3045	[18] = RCAR_GP_PIN(5, 13), /* AVB0_TD2 */
3046	[19] = RCAR_GP_PIN(5, 12), /* AVB0_TD1 */
3047	[20] = RCAR_GP_PIN(5, 11), /* AVB0_TD0 */
3048	[21] = RCAR_GP_PIN(5, 10), /* AVB0_TXC */
3049	[22] = RCAR_GP_PIN(5, 9), /* AVB0_TX_CTL */
3050	[23] = RCAR_GP_PIN(5, 8), /* AVB0_RD3 */
3051	[24] = RCAR_GP_PIN(5, 7), /* AVB0_RD2 */
3052	[25] = RCAR_GP_PIN(5, 6), /* AVB0_RD1 */
3053	[26] = RCAR_GP_PIN(5, 5), /* AVB0_RD0 */
3054	[27] = RCAR_GP_PIN(5, 4), /* AVB0_RXC */
3055	[28] = RCAR_GP_PIN(5, 3), /* AVB0_RX_CTL */
3056	[29] = RCAR_GP_PIN(4, 30), /* CAN1_TX_A */
3057	[30] = RCAR_GP_PIN(4, 29), /* CAN1_RX_A */
3058	[31] = RCAR_GP_PIN(4, 28), /* CAN0_TX_A */
3059	} },
3060	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) {
3061	[ 0] = SH_PFC_PIN_NONE,
3062	[ 1] = SH_PFC_PIN_NONE,
3063	[ 2] = SH_PFC_PIN_NONE,
3064	[ 3] = SH_PFC_PIN_NONE,
3065	[ 4] = SH_PFC_PIN_NONE,
3066	[ 5] = SH_PFC_PIN_NONE,
3067	[ 6] = SH_PFC_PIN_NONE,
3068	[ 7] = SH_PFC_PIN_NONE,
3069	[ 8] = SH_PFC_PIN_NONE,
3070	[ 9] = SH_PFC_PIN_NONE,
3071	[10] = SH_PFC_PIN_NONE,
3072	[11] = SH_PFC_PIN_NONE,
3073	[12] = SH_PFC_PIN_NONE,
3074	[13] = SH_PFC_PIN_NONE,
3075	[14] = SH_PFC_PIN_NONE,
3076	[15] = SH_PFC_PIN_NONE,
3077	[16] = SH_PFC_PIN_NONE,
3078	[17] = SH_PFC_PIN_NONE,
3079	[18] = SH_PFC_PIN_NONE,
3080	[19] = SH_PFC_PIN_NONE,
3081	[20] = SH_PFC_PIN_NONE,
3082	[21] = SH_PFC_PIN_NONE,
3083	[22] = SH_PFC_PIN_NONE,
3084	[23] = SH_PFC_PIN_NONE,
3085	[24] = SH_PFC_PIN_NONE,
3086	[25] = SH_PFC_PIN_NONE,
3087	[26] = SH_PFC_PIN_NONE,
3088	[27] = SH_PFC_PIN_NONE,
3089	[28] = SH_PFC_PIN_NONE,
3090	[29] = RCAR_GP_PIN(6, 13), /* RPC_INT# */
3091	[30] = RCAR_GP_PIN(6, 12), /* RPC_RESET# */
3092	[31] = RCAR_GP_PIN(6, 11), /* QSPI1_SSL */
3093	} },
3094	{ /* sentinel */ }
3095	};
3096
3097	static const struct pinmux_bias_reg *
3098	r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
3099	unsigned int *puen_bit, unsigned int *pud_bit)
3100	{
3101	const struct pinmux_bias_reg *reg;
3102	unsigned int bit;
3103
3104	reg = rcar_pin_to_bias_reg(info: pfc->info, pin, bit: &bit);
3105	if (!reg)
3106	return reg;
3107
3108	*puen_bit = bit;
3109
3110	/* NFWE# and NFRE# use different bit positions in PUD2 */
3111	switch (pin) {
3112	case RCAR_GP_PIN(3, 0): /* NFRE# */
3113	*pud_bit = 7;
3114	break;
3115
3116	case RCAR_GP_PIN(3, 1): /* NFWE# */
3117	*pud_bit = 8;
3118	break;
3119
3120	default:
3121	*pud_bit = bit;
3122	break;
3123	}
3124
3125	return reg;
3126	}
3127
3128	static unsigned int r8a77995_pinmux_get_bias(struct sh_pfc *pfc,
3129	unsigned int pin)
3130	{
3131	const struct pinmux_bias_reg *reg;
3132	unsigned int puen_bit, pud_bit;
3133
3134	reg = r8a77995_pin_to_bias_reg(pfc, pin, puen_bit: &puen_bit, pud_bit: &pud_bit);
3135	if (!reg)
3136	return PIN_CONFIG_BIAS_DISABLE;
3137
3138	if (!(sh_pfc_read(pfc, reg: reg->puen) & BIT(puen_bit)))
3139	return PIN_CONFIG_BIAS_DISABLE;
3140	else if (sh_pfc_read(pfc, reg: reg->pud) & BIT(pud_bit))
3141	return PIN_CONFIG_BIAS_PULL_UP;
3142	else
3143	return PIN_CONFIG_BIAS_PULL_DOWN;
3144	}
3145
3146	static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3147	unsigned int bias)
3148	{
3149	const struct pinmux_bias_reg *reg;
3150	unsigned int puen_bit, pud_bit;
3151	u32 enable, updown;
3152
3153	reg = r8a77995_pin_to_bias_reg(pfc, pin, puen_bit: &puen_bit, pud_bit: &pud_bit);
3154	if (!reg)
3155	return;
3156
3157	enable = sh_pfc_read(pfc, reg: reg->puen) & ~BIT(puen_bit);
3158	if (bias != PIN_CONFIG_BIAS_DISABLE) {
3159	enable |= BIT(puen_bit);
3160
3161	updown = sh_pfc_read(pfc, reg: reg->pud) & ~BIT(pud_bit);
3162	if (bias == PIN_CONFIG_BIAS_PULL_UP)
3163	updown |= BIT(pud_bit);
3164
3165	sh_pfc_write(pfc, reg: reg->pud, data: updown);
3166	}
3167	sh_pfc_write(pfc, reg: reg->puen, data: enable);
3168	}
3169
3170	static const struct sh_pfc_soc_operations r8a77995_pfc_ops = {
3171	.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
3172	.get_bias = r8a77995_pinmux_get_bias,
3173	.set_bias = r8a77995_pinmux_set_bias,
3174	};
3175
3176	const struct sh_pfc_soc_info r8a77995_pinmux_info = {
3177	.name = "r8a77995_pfc",
3178	.ops = &r8a77995_pfc_ops,
3179	.unlock_reg = 0xe6060000, /* PMMR */
3180
3181	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3182
3183	.pins = pinmux_pins,
3184	.nr_pins = ARRAY_SIZE(pinmux_pins),
3185	.groups = pinmux_groups,
3186	.nr_groups = ARRAY_SIZE(pinmux_groups),
3187	.functions = pinmux_functions,
3188	.nr_functions = ARRAY_SIZE(pinmux_functions),
3189
3190	.cfg_regs = pinmux_config_regs,
3191	.bias_regs = pinmux_bias_regs,
3192	.ioctrl_regs = pinmux_ioctrl_regs,
3193
3194	.pinmux_data = pinmux_data,
3195	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
3196	};
3197