1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * SH7786 Pinmux |
4 | * |
5 | * Copyright (C) 2008, 2009 Renesas Solutions Corp. |
6 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> |
7 | * |
8 | * Based on SH7785 pinmux |
9 | * |
10 | * Copyright (C) 2008 Magnus Damm |
11 | */ |
12 | |
13 | #include <linux/kernel.h> |
14 | #include <cpu/sh7786.h> |
15 | |
16 | #include "sh_pfc.h" |
17 | |
18 | enum { |
19 | PINMUX_RESERVED = 0, |
20 | |
21 | PINMUX_DATA_BEGIN, |
22 | PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, |
23 | PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, |
24 | PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, |
25 | PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, |
26 | PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, |
27 | PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, |
28 | PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, |
29 | PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, |
30 | PE7_DATA, PE6_DATA, |
31 | PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, |
32 | PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, |
33 | PG7_DATA, PG6_DATA, PG5_DATA, |
34 | PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, |
35 | PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, |
36 | PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, |
37 | PJ3_DATA, PJ2_DATA, PJ1_DATA, |
38 | PINMUX_DATA_END, |
39 | |
40 | PINMUX_INPUT_BEGIN, |
41 | PA7_IN, PA6_IN, PA5_IN, PA4_IN, |
42 | PA3_IN, PA2_IN, PA1_IN, PA0_IN, |
43 | PB7_IN, PB6_IN, PB5_IN, PB4_IN, |
44 | PB3_IN, PB2_IN, PB1_IN, PB0_IN, |
45 | PC7_IN, PC6_IN, PC5_IN, PC4_IN, |
46 | PC3_IN, PC2_IN, PC1_IN, PC0_IN, |
47 | PD7_IN, PD6_IN, PD5_IN, PD4_IN, |
48 | PD3_IN, PD2_IN, PD1_IN, PD0_IN, |
49 | PE7_IN, PE6_IN, |
50 | PF7_IN, PF6_IN, PF5_IN, PF4_IN, |
51 | PF3_IN, PF2_IN, PF1_IN, PF0_IN, |
52 | PG7_IN, PG6_IN, PG5_IN, |
53 | PH7_IN, PH6_IN, PH5_IN, PH4_IN, |
54 | PH3_IN, PH2_IN, PH1_IN, PH0_IN, |
55 | PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN, |
56 | PJ3_IN, PJ2_IN, PJ1_IN, |
57 | PINMUX_INPUT_END, |
58 | |
59 | PINMUX_OUTPUT_BEGIN, |
60 | PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, |
61 | PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, |
62 | PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT, |
63 | PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT, |
64 | PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, |
65 | PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, |
66 | PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, |
67 | PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, |
68 | PE7_OUT, PE6_OUT, |
69 | PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, |
70 | PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, |
71 | PG7_OUT, PG6_OUT, PG5_OUT, |
72 | PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT, |
73 | PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT, |
74 | PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT, |
75 | PJ3_OUT, PJ2_OUT, PJ1_OUT, |
76 | PINMUX_OUTPUT_END, |
77 | |
78 | PINMUX_FUNCTION_BEGIN, |
79 | PA7_FN, PA6_FN, PA5_FN, PA4_FN, |
80 | PA3_FN, PA2_FN, PA1_FN, PA0_FN, |
81 | PB7_FN, PB6_FN, PB5_FN, PB4_FN, |
82 | PB3_FN, PB2_FN, PB1_FN, PB0_FN, |
83 | PC7_FN, PC6_FN, PC5_FN, PC4_FN, |
84 | PC3_FN, PC2_FN, PC1_FN, PC0_FN, |
85 | PD7_FN, PD6_FN, PD5_FN, PD4_FN, |
86 | PD3_FN, PD2_FN, PD1_FN, PD0_FN, |
87 | PE7_FN, PE6_FN, |
88 | PF7_FN, PF6_FN, PF5_FN, PF4_FN, |
89 | PF3_FN, PF2_FN, PF1_FN, PF0_FN, |
90 | PG7_FN, PG6_FN, PG5_FN, |
91 | PH7_FN, PH6_FN, PH5_FN, PH4_FN, |
92 | PH3_FN, PH2_FN, PH1_FN, PH0_FN, |
93 | PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN, |
94 | PJ3_FN, PJ2_FN, PJ1_FN, |
95 | P1MSEL14_0, P1MSEL14_1, |
96 | P1MSEL13_0, P1MSEL13_1, |
97 | P1MSEL12_0, P1MSEL12_1, |
98 | P1MSEL11_0, P1MSEL11_1, |
99 | P1MSEL10_0, P1MSEL10_1, |
100 | P1MSEL9_0, P1MSEL9_1, |
101 | P1MSEL8_0, P1MSEL8_1, |
102 | P1MSEL7_0, P1MSEL7_1, |
103 | P1MSEL6_0, P1MSEL6_1, |
104 | P1MSEL5_0, P1MSEL5_1, |
105 | P1MSEL4_0, P1MSEL4_1, |
106 | P1MSEL3_0, P1MSEL3_1, |
107 | P1MSEL2_0, P1MSEL2_1, |
108 | P1MSEL1_0, P1MSEL1_1, |
109 | P1MSEL0_0, P1MSEL0_1, |
110 | |
111 | P2MSEL15_0, P2MSEL15_1, |
112 | P2MSEL14_0, P2MSEL14_1, |
113 | P2MSEL13_0, P2MSEL13_1, |
114 | P2MSEL12_0, P2MSEL12_1, |
115 | P2MSEL11_0, P2MSEL11_1, |
116 | P2MSEL10_0, P2MSEL10_1, |
117 | P2MSEL9_0, P2MSEL9_1, |
118 | P2MSEL8_0, P2MSEL8_1, |
119 | P2MSEL7_0, P2MSEL7_1, |
120 | P2MSEL6_0, P2MSEL6_1, |
121 | P2MSEL5_0, P2MSEL5_1, |
122 | P2MSEL4_0, P2MSEL4_1, |
123 | P2MSEL3_0, P2MSEL3_1, |
124 | P2MSEL2_0, P2MSEL2_1, |
125 | P2MSEL1_0, P2MSEL1_1, |
126 | P2MSEL0_0, P2MSEL0_1, |
127 | PINMUX_FUNCTION_END, |
128 | |
129 | PINMUX_MARK_BEGIN, |
130 | DCLKIN_MARK, DCLKOUT_MARK, ODDF_MARK, |
131 | VSYNC_MARK, HSYNC_MARK, CDE_MARK, DISP_MARK, |
132 | DR0_MARK, DR1_MARK, DR2_MARK, DR3_MARK, DR4_MARK, DR5_MARK, |
133 | DG0_MARK, DG1_MARK, DG2_MARK, DG3_MARK, DG4_MARK, DG5_MARK, |
134 | DB0_MARK, DB1_MARK, DB2_MARK, DB3_MARK, DB4_MARK, DB5_MARK, |
135 | ETH_MAGIC_MARK, ETH_LINK_MARK, ETH_TX_ER_MARK, ETH_TX_EN_MARK, |
136 | ETH_MDIO_MARK, ETH_RX_CLK_MARK, ETH_MDC_MARK, ETH_COL_MARK, |
137 | ETH_TX_CLK_MARK, ETH_CRS_MARK, ETH_RX_DV_MARK, ETH_RX_ER_MARK, |
138 | ETH_TXD3_MARK, ETH_TXD2_MARK, ETH_TXD1_MARK, ETH_TXD0_MARK, |
139 | ETH_RXD3_MARK, ETH_RXD2_MARK, ETH_RXD1_MARK, ETH_RXD0_MARK, |
140 | HSPI_CLK_MARK, HSPI_CS_MARK, HSPI_RX_MARK, HSPI_TX_MARK, |
141 | SCIF0_CTS_MARK, SCIF0_RTS_MARK, |
142 | SCIF0_SCK_MARK, SCIF0_RXD_MARK, SCIF0_TXD_MARK, |
143 | SCIF1_SCK_MARK, SCIF1_RXD_MARK, SCIF1_TXD_MARK, |
144 | SCIF3_SCK_MARK, SCIF3_RXD_MARK, SCIF3_TXD_MARK, |
145 | SCIF4_SCK_MARK, SCIF4_RXD_MARK, SCIF4_TXD_MARK, |
146 | SCIF5_SCK_MARK, SCIF5_RXD_MARK, SCIF5_TXD_MARK, |
147 | BREQ_MARK, IOIS16_MARK, CE2B_MARK, CE2A_MARK, BACK_MARK, |
148 | FALE_MARK, FRB_MARK, FSTATUS_MARK, |
149 | FSE_MARK, FCLE_MARK, |
150 | DACK0_MARK, DACK1_MARK, DACK2_MARK, DACK3_MARK, |
151 | DREQ0_MARK, DREQ1_MARK, DREQ2_MARK, DREQ3_MARK, |
152 | DRAK0_MARK, DRAK1_MARK, DRAK2_MARK, DRAK3_MARK, |
153 | USB_OVC1_MARK, USB_OVC0_MARK, |
154 | USB_PENC1_MARK, USB_PENC0_MARK, |
155 | HAC_RES_MARK, |
156 | HAC1_SDOUT_MARK, HAC1_SDIN_MARK, HAC1_SYNC_MARK, HAC1_BITCLK_MARK, |
157 | HAC0_SDOUT_MARK, HAC0_SDIN_MARK, HAC0_SYNC_MARK, HAC0_BITCLK_MARK, |
158 | SSI0_SDATA_MARK, SSI0_SCK_MARK, SSI0_WS_MARK, SSI0_CLK_MARK, |
159 | SSI1_SDATA_MARK, SSI1_SCK_MARK, SSI1_WS_MARK, SSI1_CLK_MARK, |
160 | SSI2_SDATA_MARK, SSI2_SCK_MARK, SSI2_WS_MARK, |
161 | SSI3_SDATA_MARK, SSI3_SCK_MARK, SSI3_WS_MARK, |
162 | SDIF1CMD_MARK, SDIF1CD_MARK, SDIF1WP_MARK, SDIF1CLK_MARK, |
163 | SDIF1D3_MARK, SDIF1D2_MARK, SDIF1D1_MARK, SDIF1D0_MARK, |
164 | SDIF0CMD_MARK, SDIF0CD_MARK, SDIF0WP_MARK, SDIF0CLK_MARK, |
165 | SDIF0D3_MARK, SDIF0D2_MARK, SDIF0D1_MARK, SDIF0D0_MARK, |
166 | TCLK_MARK, |
167 | IRL7_MARK, IRL6_MARK, IRL5_MARK, IRL4_MARK, |
168 | PINMUX_MARK_END, |
169 | }; |
170 | |
171 | static const u16 pinmux_data[] = { |
172 | /* PA GPIO */ |
173 | PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), |
174 | PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), |
175 | PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT), |
176 | PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT), |
177 | PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT), |
178 | PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT), |
179 | PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT), |
180 | PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT), |
181 | |
182 | /* PB GPIO */ |
183 | PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT), |
184 | PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT), |
185 | PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT), |
186 | PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT), |
187 | PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT), |
188 | PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT), |
189 | PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT), |
190 | PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT), |
191 | |
192 | /* PC GPIO */ |
193 | PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT), |
194 | PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT), |
195 | PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT), |
196 | PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT), |
197 | PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT), |
198 | PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT), |
199 | PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT), |
200 | PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT), |
201 | |
202 | /* PD GPIO */ |
203 | PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT), |
204 | PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT), |
205 | PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT), |
206 | PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT), |
207 | PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT), |
208 | PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT), |
209 | PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT), |
210 | PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT), |
211 | |
212 | /* PE GPIO */ |
213 | PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT), |
214 | PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT), |
215 | |
216 | /* PF GPIO */ |
217 | PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT), |
218 | PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT), |
219 | PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT), |
220 | PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT), |
221 | PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT), |
222 | PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT), |
223 | PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT), |
224 | PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT), |
225 | |
226 | /* PG GPIO */ |
227 | PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT), |
228 | PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT), |
229 | PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT), |
230 | |
231 | /* PH GPIO */ |
232 | PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT), |
233 | PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT), |
234 | PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT), |
235 | PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT), |
236 | PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT), |
237 | PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT), |
238 | PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT), |
239 | PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT), |
240 | |
241 | /* PJ GPIO */ |
242 | PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT), |
243 | PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT), |
244 | PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT), |
245 | PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT), |
246 | PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT), |
247 | PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT), |
248 | PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT), |
249 | |
250 | /* PA FN */ |
251 | PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN), |
252 | PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN), |
253 | PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN), |
254 | PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN), |
255 | PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN), |
256 | PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN), |
257 | PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN), |
258 | PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN), |
259 | PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN), |
260 | PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN), |
261 | PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN), |
262 | PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN), |
263 | PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN), |
264 | PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN), |
265 | PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN), |
266 | PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN), |
267 | |
268 | /* PB FN */ |
269 | PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN), |
270 | PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN), |
271 | PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN), |
272 | PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN), |
273 | PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN), |
274 | PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN), |
275 | PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN), |
276 | PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN), |
277 | PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN), |
278 | PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN), |
279 | PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN), |
280 | PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN), |
281 | PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN), |
282 | PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN), |
283 | PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN), |
284 | PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN), |
285 | |
286 | /* PC FN */ |
287 | PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN), |
288 | PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN), |
289 | PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN), |
290 | PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN), |
291 | PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN), |
292 | PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN), |
293 | PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN), |
294 | PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN), |
295 | |
296 | PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN), |
297 | PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN), |
298 | PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN), |
299 | PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN), |
300 | PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN), |
301 | PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN), |
302 | PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN), |
303 | PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN), |
304 | |
305 | /* PD FN */ |
306 | PINMUX_DATA(DCLKOUT_MARK, PD7_FN), |
307 | PINMUX_DATA(SCIF1_SCK_MARK, PD6_FN), |
308 | PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN), |
309 | PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN), |
310 | PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN), |
311 | PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN), |
312 | PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN), |
313 | PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN), |
314 | PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN), |
315 | PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN), |
316 | PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN), |
317 | PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN), |
318 | PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN), |
319 | PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN), |
320 | |
321 | /* PE FN */ |
322 | PINMUX_DATA(USB_PENC1_MARK, PE7_FN), |
323 | PINMUX_DATA(USB_PENC0_MARK, PE6_FN), |
324 | |
325 | /* PF FN */ |
326 | PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN), |
327 | PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN), |
328 | PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN), |
329 | PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN), |
330 | PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN), |
331 | PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN), |
332 | PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN), |
333 | PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN), |
334 | PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN), |
335 | PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN), |
336 | PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN), |
337 | PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN), |
338 | PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN), |
339 | PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN), |
340 | PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN), |
341 | PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN), |
342 | PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN), |
343 | PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN), |
344 | PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN), |
345 | PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN), |
346 | PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN), |
347 | PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN), |
348 | PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN), |
349 | PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN), |
350 | |
351 | /* PG FN */ |
352 | PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN), |
353 | PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN), |
354 | PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN), |
355 | PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN), |
356 | PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN), |
357 | PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN), |
358 | PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN), |
359 | PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN), |
360 | |
361 | /* PH FN */ |
362 | PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN), |
363 | PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN), |
364 | PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN), |
365 | PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN), |
366 | PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN), |
367 | PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN), |
368 | PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN), |
369 | PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN), |
370 | PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN), |
371 | PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN), |
372 | PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN), |
373 | PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN), |
374 | PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN), |
375 | PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN), |
376 | PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN), |
377 | PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN), |
378 | PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN), |
379 | PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN), |
380 | PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN), |
381 | PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN), |
382 | PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN), |
383 | |
384 | /* PJ FN */ |
385 | PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN), |
386 | PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN), |
387 | PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN), |
388 | PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN), |
389 | PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN), |
390 | PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN), |
391 | PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN), |
392 | PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN), |
393 | PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN), |
394 | PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN), |
395 | PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN), |
396 | PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN), |
397 | PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN), |
398 | PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN), |
399 | PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN), |
400 | PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN), |
401 | PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN), |
402 | PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN), |
403 | PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN), |
404 | }; |
405 | |
406 | static const struct sh_pfc_pin pinmux_pins[] = { |
407 | /* PA */ |
408 | PINMUX_GPIO(PA7), |
409 | PINMUX_GPIO(PA6), |
410 | PINMUX_GPIO(PA5), |
411 | PINMUX_GPIO(PA4), |
412 | PINMUX_GPIO(PA3), |
413 | PINMUX_GPIO(PA2), |
414 | PINMUX_GPIO(PA1), |
415 | PINMUX_GPIO(PA0), |
416 | |
417 | /* PB */ |
418 | PINMUX_GPIO(PB7), |
419 | PINMUX_GPIO(PB6), |
420 | PINMUX_GPIO(PB5), |
421 | PINMUX_GPIO(PB4), |
422 | PINMUX_GPIO(PB3), |
423 | PINMUX_GPIO(PB2), |
424 | PINMUX_GPIO(PB1), |
425 | PINMUX_GPIO(PB0), |
426 | |
427 | /* PC */ |
428 | PINMUX_GPIO(PC7), |
429 | PINMUX_GPIO(PC6), |
430 | PINMUX_GPIO(PC5), |
431 | PINMUX_GPIO(PC4), |
432 | PINMUX_GPIO(PC3), |
433 | PINMUX_GPIO(PC2), |
434 | PINMUX_GPIO(PC1), |
435 | PINMUX_GPIO(PC0), |
436 | |
437 | /* PD */ |
438 | PINMUX_GPIO(PD7), |
439 | PINMUX_GPIO(PD6), |
440 | PINMUX_GPIO(PD5), |
441 | PINMUX_GPIO(PD4), |
442 | PINMUX_GPIO(PD3), |
443 | PINMUX_GPIO(PD2), |
444 | PINMUX_GPIO(PD1), |
445 | PINMUX_GPIO(PD0), |
446 | |
447 | /* PE */ |
448 | PINMUX_GPIO(PE7), |
449 | PINMUX_GPIO(PE6), |
450 | |
451 | /* PF */ |
452 | PINMUX_GPIO(PF7), |
453 | PINMUX_GPIO(PF6), |
454 | PINMUX_GPIO(PF5), |
455 | PINMUX_GPIO(PF4), |
456 | PINMUX_GPIO(PF3), |
457 | PINMUX_GPIO(PF2), |
458 | PINMUX_GPIO(PF1), |
459 | PINMUX_GPIO(PF0), |
460 | |
461 | /* PG */ |
462 | PINMUX_GPIO(PG7), |
463 | PINMUX_GPIO(PG6), |
464 | PINMUX_GPIO(PG5), |
465 | |
466 | /* PH */ |
467 | PINMUX_GPIO(PH7), |
468 | PINMUX_GPIO(PH6), |
469 | PINMUX_GPIO(PH5), |
470 | PINMUX_GPIO(PH4), |
471 | PINMUX_GPIO(PH3), |
472 | PINMUX_GPIO(PH2), |
473 | PINMUX_GPIO(PH1), |
474 | PINMUX_GPIO(PH0), |
475 | |
476 | /* PJ */ |
477 | PINMUX_GPIO(PJ7), |
478 | PINMUX_GPIO(PJ6), |
479 | PINMUX_GPIO(PJ5), |
480 | PINMUX_GPIO(PJ4), |
481 | PINMUX_GPIO(PJ3), |
482 | PINMUX_GPIO(PJ2), |
483 | PINMUX_GPIO(PJ1), |
484 | }; |
485 | |
486 | #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) |
487 | |
488 | static const struct pinmux_func pinmux_func_gpios[] = { |
489 | /* FN */ |
490 | GPIO_FN(CDE), |
491 | GPIO_FN(ETH_MAGIC), |
492 | GPIO_FN(DISP), |
493 | GPIO_FN(ETH_LINK), |
494 | GPIO_FN(DR5), |
495 | GPIO_FN(ETH_TX_ER), |
496 | GPIO_FN(DR4), |
497 | GPIO_FN(ETH_TX_EN), |
498 | GPIO_FN(DR3), |
499 | GPIO_FN(ETH_TXD3), |
500 | GPIO_FN(DR2), |
501 | GPIO_FN(ETH_TXD2), |
502 | GPIO_FN(DR1), |
503 | GPIO_FN(ETH_TXD1), |
504 | GPIO_FN(DR0), |
505 | GPIO_FN(ETH_TXD0), |
506 | GPIO_FN(VSYNC), |
507 | GPIO_FN(HSPI_CLK), |
508 | GPIO_FN(ODDF), |
509 | GPIO_FN(HSPI_CS), |
510 | GPIO_FN(DG5), |
511 | GPIO_FN(ETH_MDIO), |
512 | GPIO_FN(DG4), |
513 | GPIO_FN(ETH_RX_CLK), |
514 | GPIO_FN(DG3), |
515 | GPIO_FN(ETH_MDC), |
516 | GPIO_FN(DG2), |
517 | GPIO_FN(ETH_COL), |
518 | GPIO_FN(DG1), |
519 | GPIO_FN(ETH_TX_CLK), |
520 | GPIO_FN(DG0), |
521 | GPIO_FN(ETH_CRS), |
522 | GPIO_FN(DCLKIN), |
523 | GPIO_FN(HSPI_RX), |
524 | GPIO_FN(HSYNC), |
525 | GPIO_FN(HSPI_TX), |
526 | GPIO_FN(DB5), |
527 | GPIO_FN(ETH_RXD3), |
528 | GPIO_FN(DB4), |
529 | GPIO_FN(ETH_RXD2), |
530 | GPIO_FN(DB3), |
531 | GPIO_FN(ETH_RXD1), |
532 | GPIO_FN(DB2), |
533 | GPIO_FN(ETH_RXD0), |
534 | GPIO_FN(DB1), |
535 | GPIO_FN(ETH_RX_DV), |
536 | GPIO_FN(DB0), |
537 | GPIO_FN(ETH_RX_ER), |
538 | GPIO_FN(DCLKOUT), |
539 | GPIO_FN(SCIF1_SCK), |
540 | GPIO_FN(SCIF1_RXD), |
541 | GPIO_FN(SCIF1_TXD), |
542 | GPIO_FN(DACK1), |
543 | GPIO_FN(BACK), |
544 | GPIO_FN(FALE), |
545 | GPIO_FN(DACK0), |
546 | GPIO_FN(FCLE), |
547 | GPIO_FN(DREQ1), |
548 | GPIO_FN(BREQ), |
549 | GPIO_FN(USB_OVC1), |
550 | GPIO_FN(DREQ0), |
551 | GPIO_FN(USB_OVC0), |
552 | GPIO_FN(USB_PENC1), |
553 | GPIO_FN(USB_PENC0), |
554 | GPIO_FN(HAC1_SDOUT), |
555 | GPIO_FN(SSI1_SDATA), |
556 | GPIO_FN(SDIF1CMD), |
557 | GPIO_FN(HAC1_SDIN), |
558 | GPIO_FN(SSI1_SCK), |
559 | GPIO_FN(SDIF1CD), |
560 | GPIO_FN(HAC1_SYNC), |
561 | GPIO_FN(SSI1_WS), |
562 | GPIO_FN(SDIF1WP), |
563 | GPIO_FN(HAC1_BITCLK), |
564 | GPIO_FN(SSI1_CLK), |
565 | GPIO_FN(SDIF1CLK), |
566 | GPIO_FN(HAC0_SDOUT), |
567 | GPIO_FN(SSI0_SDATA), |
568 | GPIO_FN(SDIF1D3), |
569 | GPIO_FN(HAC0_SDIN), |
570 | GPIO_FN(SSI0_SCK), |
571 | GPIO_FN(SDIF1D2), |
572 | GPIO_FN(HAC0_SYNC), |
573 | GPIO_FN(SSI0_WS), |
574 | GPIO_FN(SDIF1D1), |
575 | GPIO_FN(HAC0_BITCLK), |
576 | GPIO_FN(SSI0_CLK), |
577 | GPIO_FN(SDIF1D0), |
578 | GPIO_FN(SCIF3_SCK), |
579 | GPIO_FN(SSI2_SDATA), |
580 | GPIO_FN(SCIF3_RXD), |
581 | GPIO_FN(TCLK), |
582 | GPIO_FN(SSI2_SCK), |
583 | GPIO_FN(SCIF3_TXD), |
584 | GPIO_FN(HAC_RES), |
585 | GPIO_FN(SSI2_WS), |
586 | GPIO_FN(DACK3), |
587 | GPIO_FN(SDIF0CMD), |
588 | GPIO_FN(DACK2), |
589 | GPIO_FN(SDIF0CD), |
590 | GPIO_FN(DREQ3), |
591 | GPIO_FN(SDIF0WP), |
592 | GPIO_FN(SCIF0_CTS), |
593 | GPIO_FN(DREQ2), |
594 | GPIO_FN(SDIF0CLK), |
595 | GPIO_FN(SCIF0_RTS), |
596 | GPIO_FN(IRL7), |
597 | GPIO_FN(SDIF0D3), |
598 | GPIO_FN(SCIF0_SCK), |
599 | GPIO_FN(IRL6), |
600 | GPIO_FN(SDIF0D2), |
601 | GPIO_FN(SCIF0_RXD), |
602 | GPIO_FN(IRL5), |
603 | GPIO_FN(SDIF0D1), |
604 | GPIO_FN(SCIF0_TXD), |
605 | GPIO_FN(IRL4), |
606 | GPIO_FN(SDIF0D0), |
607 | GPIO_FN(SCIF5_SCK), |
608 | GPIO_FN(FRB), |
609 | GPIO_FN(SCIF5_RXD), |
610 | GPIO_FN(IOIS16), |
611 | GPIO_FN(SCIF5_TXD), |
612 | GPIO_FN(CE2B), |
613 | GPIO_FN(DRAK3), |
614 | GPIO_FN(CE2A), |
615 | GPIO_FN(SCIF4_SCK), |
616 | GPIO_FN(DRAK2), |
617 | GPIO_FN(SSI3_WS), |
618 | GPIO_FN(SCIF4_RXD), |
619 | GPIO_FN(DRAK1), |
620 | GPIO_FN(SSI3_SDATA), |
621 | GPIO_FN(FSTATUS), |
622 | GPIO_FN(SCIF4_TXD), |
623 | GPIO_FN(DRAK0), |
624 | GPIO_FN(SSI3_SCK), |
625 | GPIO_FN(FSE), |
626 | }; |
627 | |
628 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |
629 | { PINMUX_CFG_REG("PACR" , 0xffcc0000, 16, 2, GROUP( |
630 | PA7_FN, PA7_OUT, PA7_IN, 0, |
631 | PA6_FN, PA6_OUT, PA6_IN, 0, |
632 | PA5_FN, PA5_OUT, PA5_IN, 0, |
633 | PA4_FN, PA4_OUT, PA4_IN, 0, |
634 | PA3_FN, PA3_OUT, PA3_IN, 0, |
635 | PA2_FN, PA2_OUT, PA2_IN, 0, |
636 | PA1_FN, PA1_OUT, PA1_IN, 0, |
637 | PA0_FN, PA0_OUT, PA0_IN, 0 )) |
638 | }, |
639 | { PINMUX_CFG_REG("PBCR" , 0xffcc0002, 16, 2, GROUP( |
640 | PB7_FN, PB7_OUT, PB7_IN, 0, |
641 | PB6_FN, PB6_OUT, PB6_IN, 0, |
642 | PB5_FN, PB5_OUT, PB5_IN, 0, |
643 | PB4_FN, PB4_OUT, PB4_IN, 0, |
644 | PB3_FN, PB3_OUT, PB3_IN, 0, |
645 | PB2_FN, PB2_OUT, PB2_IN, 0, |
646 | PB1_FN, PB1_OUT, PB1_IN, 0, |
647 | PB0_FN, PB0_OUT, PB0_IN, 0 )) |
648 | }, |
649 | { PINMUX_CFG_REG("PCCR" , 0xffcc0004, 16, 2, GROUP( |
650 | PC7_FN, PC7_OUT, PC7_IN, 0, |
651 | PC6_FN, PC6_OUT, PC6_IN, 0, |
652 | PC5_FN, PC5_OUT, PC5_IN, 0, |
653 | PC4_FN, PC4_OUT, PC4_IN, 0, |
654 | PC3_FN, PC3_OUT, PC3_IN, 0, |
655 | PC2_FN, PC2_OUT, PC2_IN, 0, |
656 | PC1_FN, PC1_OUT, PC1_IN, 0, |
657 | PC0_FN, PC0_OUT, PC0_IN, 0 )) |
658 | }, |
659 | { PINMUX_CFG_REG("PDCR" , 0xffcc0006, 16, 2, GROUP( |
660 | PD7_FN, PD7_OUT, PD7_IN, 0, |
661 | PD6_FN, PD6_OUT, PD6_IN, 0, |
662 | PD5_FN, PD5_OUT, PD5_IN, 0, |
663 | PD4_FN, PD4_OUT, PD4_IN, 0, |
664 | PD3_FN, PD3_OUT, PD3_IN, 0, |
665 | PD2_FN, PD2_OUT, PD2_IN, 0, |
666 | PD1_FN, PD1_OUT, PD1_IN, 0, |
667 | PD0_FN, PD0_OUT, PD0_IN, 0 )) |
668 | }, |
669 | { PINMUX_CFG_REG_VAR("PECR" , 0xffcc0008, 16, |
670 | GROUP(2, 2, -12), |
671 | GROUP( |
672 | PE7_FN, PE7_OUT, PE7_IN, 0, |
673 | PE6_FN, PE6_OUT, PE6_IN, 0, |
674 | /* RESERVED [12] */ )) |
675 | }, |
676 | { PINMUX_CFG_REG("PFCR" , 0xffcc000a, 16, 2, GROUP( |
677 | PF7_FN, PF7_OUT, PF7_IN, 0, |
678 | PF6_FN, PF6_OUT, PF6_IN, 0, |
679 | PF5_FN, PF5_OUT, PF5_IN, 0, |
680 | PF4_FN, PF4_OUT, PF4_IN, 0, |
681 | PF3_FN, PF3_OUT, PF3_IN, 0, |
682 | PF2_FN, PF2_OUT, PF2_IN, 0, |
683 | PF1_FN, PF1_OUT, PF1_IN, 0, |
684 | PF0_FN, PF0_OUT, PF0_IN, 0 )) |
685 | }, |
686 | { PINMUX_CFG_REG_VAR("PGCR" , 0xffcc000c, 16, |
687 | GROUP(2, 2, 2, -10), |
688 | GROUP( |
689 | PG7_FN, PG7_OUT, PG7_IN, 0, |
690 | PG6_FN, PG6_OUT, PG6_IN, 0, |
691 | PG5_FN, PG5_OUT, PG5_IN, 0, |
692 | /* RESERVED [10] */ )) |
693 | }, |
694 | { PINMUX_CFG_REG("PHCR" , 0xffcc000e, 16, 2, GROUP( |
695 | PH7_FN, PH7_OUT, PH7_IN, 0, |
696 | PH6_FN, PH6_OUT, PH6_IN, 0, |
697 | PH5_FN, PH5_OUT, PH5_IN, 0, |
698 | PH4_FN, PH4_OUT, PH4_IN, 0, |
699 | PH3_FN, PH3_OUT, PH3_IN, 0, |
700 | PH2_FN, PH2_OUT, PH2_IN, 0, |
701 | PH1_FN, PH1_OUT, PH1_IN, 0, |
702 | PH0_FN, PH0_OUT, PH0_IN, 0 )) |
703 | }, |
704 | { PINMUX_CFG_REG("PJCR" , 0xffcc0010, 16, 2, GROUP( |
705 | PJ7_FN, PJ7_OUT, PJ7_IN, 0, |
706 | PJ6_FN, PJ6_OUT, PJ6_IN, 0, |
707 | PJ5_FN, PJ5_OUT, PJ5_IN, 0, |
708 | PJ4_FN, PJ4_OUT, PJ4_IN, 0, |
709 | PJ3_FN, PJ3_OUT, PJ3_IN, 0, |
710 | PJ2_FN, PJ2_OUT, PJ2_IN, 0, |
711 | PJ1_FN, PJ1_OUT, PJ1_IN, 0, |
712 | 0, 0, 0, 0, )) |
713 | }, |
714 | { PINMUX_CFG_REG("P1MSELR" , 0xffcc0080, 16, 1, GROUP( |
715 | 0, 0, |
716 | P1MSEL14_0, P1MSEL14_1, |
717 | P1MSEL13_0, P1MSEL13_1, |
718 | P1MSEL12_0, P1MSEL12_1, |
719 | P1MSEL11_0, P1MSEL11_1, |
720 | P1MSEL10_0, P1MSEL10_1, |
721 | P1MSEL9_0, P1MSEL9_1, |
722 | P1MSEL8_0, P1MSEL8_1, |
723 | P1MSEL7_0, P1MSEL7_1, |
724 | P1MSEL6_0, P1MSEL6_1, |
725 | P1MSEL5_0, P1MSEL5_1, |
726 | P1MSEL4_0, P1MSEL4_1, |
727 | P1MSEL3_0, P1MSEL3_1, |
728 | P1MSEL2_0, P1MSEL2_1, |
729 | P1MSEL1_0, P1MSEL1_1, |
730 | P1MSEL0_0, P1MSEL0_1 )) |
731 | }, |
732 | { PINMUX_CFG_REG("P2MSELR" , 0xffcc0082, 16, 1, GROUP( |
733 | P2MSEL15_0, P2MSEL15_1, |
734 | P2MSEL14_0, P2MSEL14_1, |
735 | P2MSEL13_0, P2MSEL13_1, |
736 | P2MSEL12_0, P2MSEL12_1, |
737 | P2MSEL11_0, P2MSEL11_1, |
738 | P2MSEL10_0, P2MSEL10_1, |
739 | P2MSEL9_0, P2MSEL9_1, |
740 | P2MSEL8_0, P2MSEL8_1, |
741 | P2MSEL7_0, P2MSEL7_1, |
742 | P2MSEL6_0, P2MSEL6_1, |
743 | P2MSEL5_0, P2MSEL5_1, |
744 | P2MSEL4_0, P2MSEL4_1, |
745 | P2MSEL3_0, P2MSEL3_1, |
746 | P2MSEL2_0, P2MSEL2_1, |
747 | P2MSEL1_0, P2MSEL1_1, |
748 | P2MSEL0_0, P2MSEL0_1 )) |
749 | }, |
750 | { /* sentinel */ } |
751 | }; |
752 | |
753 | static const struct pinmux_data_reg pinmux_data_regs[] = { |
754 | { PINMUX_DATA_REG("PADR" , 0xffcc0020, 8, GROUP( |
755 | PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, |
756 | PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA )) |
757 | }, |
758 | { PINMUX_DATA_REG("PBDR" , 0xffcc0022, 8, GROUP( |
759 | PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, |
760 | PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA )) |
761 | }, |
762 | { PINMUX_DATA_REG("PCDR" , 0xffcc0024, 8, GROUP( |
763 | PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, |
764 | PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA )) |
765 | }, |
766 | { PINMUX_DATA_REG("PDDR" , 0xffcc0026, 8, GROUP( |
767 | PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, |
768 | PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA )) |
769 | }, |
770 | { PINMUX_DATA_REG("PEDR" , 0xffcc0028, 8, GROUP( |
771 | PE7_DATA, PE6_DATA, |
772 | 0, 0, 0, 0, 0, 0 )) |
773 | }, |
774 | { PINMUX_DATA_REG("PFDR" , 0xffcc002a, 8, GROUP( |
775 | PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, |
776 | PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA )) |
777 | }, |
778 | { PINMUX_DATA_REG("PGDR" , 0xffcc002c, 8, GROUP( |
779 | PG7_DATA, PG6_DATA, PG5_DATA, 0, |
780 | 0, 0, 0, 0 )) |
781 | }, |
782 | { PINMUX_DATA_REG("PHDR" , 0xffcc002e, 8, GROUP( |
783 | PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, |
784 | PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA )) |
785 | }, |
786 | { PINMUX_DATA_REG("PJDR" , 0xffcc0030, 8, GROUP( |
787 | PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, |
788 | PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 )) |
789 | }, |
790 | { /* sentinel */ } |
791 | }; |
792 | |
793 | const struct sh_pfc_soc_info sh7786_pinmux_info = { |
794 | .name = "sh7786_pfc" , |
795 | .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, |
796 | .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, |
797 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, |
798 | |
799 | .pins = pinmux_pins, |
800 | .nr_pins = ARRAY_SIZE(pinmux_pins), |
801 | .func_gpios = pinmux_func_gpios, |
802 | .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), |
803 | |
804 | .cfg_regs = pinmux_config_regs, |
805 | .data_regs = pinmux_data_regs, |
806 | |
807 | .pinmux_data = pinmux_data, |
808 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), |
809 | }; |
810 | |