1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* |
3 | * da9211-regulator.h - Regulator definitions for DA9211/DA9212 |
4 | * /DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 |
5 | * Copyright (C) 2015 Dialog Semiconductor Ltd. |
6 | */ |
7 | |
8 | #ifndef __DA9211_REGISTERS_H__ |
9 | #define __DA9211_REGISTERS_H__ |
10 | |
11 | /* Page selection */ |
12 | #define DA9211_REG_PAGE_CON 0x00 |
13 | |
14 | /* System Control and Event Registers */ |
15 | #define DA9211_REG_STATUS_A 0x50 |
16 | #define DA9211_REG_STATUS_B 0x51 |
17 | #define DA9211_REG_EVENT_A 0x52 |
18 | #define DA9211_REG_EVENT_B 0x53 |
19 | #define DA9211_REG_MASK_A 0x54 |
20 | #define DA9211_REG_MASK_B 0x55 |
21 | #define DA9211_REG_CONTROL_A 0x56 |
22 | |
23 | /* GPIO Control Registers */ |
24 | #define DA9211_REG_GPIO_0_1 0x58 |
25 | #define DA9211_REG_GPIO_2_3 0x59 |
26 | #define DA9211_REG_GPIO_4 0x5A |
27 | |
28 | /* Regulator Registers */ |
29 | #define DA9211_REG_BUCKA_CONT 0x5D |
30 | #define DA9211_REG_BUCKB_CONT 0x5E |
31 | #define DA9211_REG_BUCK_ILIM 0xD0 |
32 | #define DA9211_REG_BUCKA_CONF 0xD1 |
33 | #define DA9211_REG_BUCKB_CONF 0xD2 |
34 | #define DA9211_REG_BUCK_CONF 0xD3 |
35 | #define DA9211_REG_VBACKA_MAX 0xD5 |
36 | #define DA9211_REG_VBACKB_MAX 0xD6 |
37 | #define DA9211_REG_VBUCKA_A 0xD7 |
38 | #define DA9211_REG_VBUCKA_B 0xD8 |
39 | #define DA9211_REG_VBUCKB_A 0xD9 |
40 | #define DA9211_REG_VBUCKB_B 0xDA |
41 | |
42 | /* I2C Interface Settings */ |
43 | #define DA9211_REG_INTERFACE 0x105 |
44 | |
45 | /* BUCK Phase Selection*/ |
46 | #define DA9211_REG_CONFIG_E 0x147 |
47 | |
48 | /* Device ID */ |
49 | #define DA9211_REG_DEVICE_ID 0x201 |
50 | |
51 | /* |
52 | * Registers bits |
53 | */ |
54 | /* DA9211_REG_PAGE_CON (addr=0x00) */ |
55 | #define DA9211_REG_PAGE_SHIFT 1 |
56 | #define DA9211_REG_PAGE_MASK 0x06 |
57 | /* On I2C registers 0x00 - 0xFF */ |
58 | #define DA9211_REG_PAGE0 0 |
59 | /* On I2C registers 0x100 - 0x1FF */ |
60 | #define DA9211_REG_PAGE2 2 |
61 | #define DA9211_PAGE_WRITE_MODE 0x00 |
62 | #define DA9211_REPEAT_WRITE_MODE 0x40 |
63 | #define DA9211_PAGE_REVERT 0x80 |
64 | |
65 | /* DA9211_REG_STATUS_A (addr=0x50) */ |
66 | #define DA9211_GPI0 0x01 |
67 | #define DA9211_GPI1 0x02 |
68 | #define DA9211_GPI2 0x04 |
69 | #define DA9211_GPI3 0x08 |
70 | #define DA9211_GPI4 0x10 |
71 | |
72 | /* DA9211_REG_EVENT_A (addr=0x52) */ |
73 | #define DA9211_E_GPI0 0x01 |
74 | #define DA9211_E_GPI1 0x02 |
75 | #define DA9211_E_GPI2 0x04 |
76 | #define DA9211_E_GPI3 0x08 |
77 | #define DA9211_E_GPI4 0x10 |
78 | #define DA9211_E_UVLO_IO 0x40 |
79 | |
80 | /* DA9211_REG_EVENT_B (addr=0x53) */ |
81 | #define DA9211_E_PWRGOOD_A 0x01 |
82 | #define DA9211_E_PWRGOOD_B 0x02 |
83 | #define DA9211_E_TEMP_WARN 0x04 |
84 | #define DA9211_E_TEMP_CRIT 0x08 |
85 | #define DA9211_E_OV_CURR_A 0x10 |
86 | #define DA9211_E_OV_CURR_B 0x20 |
87 | |
88 | /* DA9211_REG_MASK_A (addr=0x54) */ |
89 | #define DA9211_M_GPI0 0x01 |
90 | #define DA9211_M_GPI1 0x02 |
91 | #define DA9211_M_GPI2 0x04 |
92 | #define DA9211_M_GPI3 0x08 |
93 | #define DA9211_M_GPI4 0x10 |
94 | #define DA9211_M_UVLO_IO 0x40 |
95 | |
96 | /* DA9211_REG_MASK_B (addr=0x55) */ |
97 | #define DA9211_M_PWRGOOD_A 0x01 |
98 | #define DA9211_M_PWRGOOD_B 0x02 |
99 | #define DA9211_M_TEMP_WARN 0x04 |
100 | #define DA9211_M_TEMP_CRIT 0x08 |
101 | #define DA9211_M_OV_CURR_A 0x10 |
102 | #define DA9211_M_OV_CURR_B 0x20 |
103 | |
104 | /* DA9211_REG_CONTROL_A (addr=0x56) */ |
105 | #define DA9211_DEBOUNCING_SHIFT 0 |
106 | #define DA9211_DEBOUNCING_MASK 0x07 |
107 | #define DA9211_SLEW_RATE_SHIFT 3 |
108 | #define DA9211_SLEW_RATE_A_MASK 0x18 |
109 | #define DA9211_SLEW_RATE_B_SHIFT 5 |
110 | #define DA9211_SLEW_RATE_B_MASK 0x60 |
111 | #define DA9211_V_LOCK 0x80 |
112 | |
113 | /* DA9211_REG_GPIO_0_1 (addr=0x58) */ |
114 | #define DA9211_GPIO0_PIN_SHIFT 0 |
115 | #define DA9211_GPIO0_PIN_MASK 0x03 |
116 | #define DA9211_GPIO0_PIN_GPI 0x00 |
117 | #define DA9211_GPIO0_PIN_GPO_OD 0x02 |
118 | #define DA9211_GPIO0_PIN_GPO 0x03 |
119 | #define DA9211_GPIO0_TYPE 0x04 |
120 | #define DA9211_GPIO0_TYPE_GPI 0x00 |
121 | #define DA9211_GPIO0_TYPE_GPO 0x04 |
122 | #define DA9211_GPIO0_MODE 0x08 |
123 | #define DA9211_GPIO1_PIN_SHIFT 4 |
124 | #define DA9211_GPIO1_PIN_MASK 0x30 |
125 | #define DA9211_GPIO1_PIN_GPI 0x00 |
126 | #define DA9211_GPIO1_PIN_VERROR 0x10 |
127 | #define DA9211_GPIO1_PIN_GPO_OD 0x20 |
128 | #define DA9211_GPIO1_PIN_GPO 0x30 |
129 | #define DA9211_GPIO1_TYPE_SHIFT 0x40 |
130 | #define DA9211_GPIO1_TYPE_GPI 0x00 |
131 | #define DA9211_GPIO1_TYPE_GPO 0x40 |
132 | #define DA9211_GPIO1_MODE 0x80 |
133 | |
134 | /* DA9211_REG_GPIO_2_3 (addr=0x59) */ |
135 | #define DA9211_GPIO2_PIN_SHIFT 0 |
136 | #define DA9211_GPIO2_PIN_MASK 0x03 |
137 | #define DA9211_GPIO2_PIN_GPI 0x00 |
138 | #define DA9211_GPIO5_PIN_BUCK_CLK 0x10 |
139 | #define DA9211_GPIO2_PIN_GPO_OD 0x02 |
140 | #define DA9211_GPIO2_PIN_GPO 0x03 |
141 | #define DA9211_GPIO2_TYPE 0x04 |
142 | #define DA9211_GPIO2_TYPE_GPI 0x00 |
143 | #define DA9211_GPIO2_TYPE_GPO 0x04 |
144 | #define DA9211_GPIO2_MODE 0x08 |
145 | #define DA9211_GPIO3_PIN_SHIFT 4 |
146 | #define DA9211_GPIO3_PIN_MASK 0x30 |
147 | #define DA9211_GPIO3_PIN_GPI 0x00 |
148 | #define DA9211_GPIO3_PIN_IERROR 0x10 |
149 | #define DA9211_GPIO3_PIN_GPO_OD 0x20 |
150 | #define DA9211_GPIO3_PIN_GPO 0x30 |
151 | #define DA9211_GPIO3_TYPE_SHIFT 0x40 |
152 | #define DA9211_GPIO3_TYPE_GPI 0x00 |
153 | #define DA9211_GPIO3_TYPE_GPO 0x40 |
154 | #define DA9211_GPIO3_MODE 0x80 |
155 | |
156 | /* DA9211_REG_GPIO_4 (addr=0x5A) */ |
157 | #define DA9211_GPIO4_PIN_SHIFT 0 |
158 | #define DA9211_GPIO4_PIN_MASK 0x03 |
159 | #define DA9211_GPIO4_PIN_GPI 0x00 |
160 | #define DA9211_GPIO4_PIN_GPO_OD 0x02 |
161 | #define DA9211_GPIO4_PIN_GPO 0x03 |
162 | #define DA9211_GPIO4_TYPE 0x04 |
163 | #define DA9211_GPIO4_TYPE_GPI 0x00 |
164 | #define DA9211_GPIO4_TYPE_GPO 0x04 |
165 | #define DA9211_GPIO4_MODE 0x08 |
166 | |
167 | /* DA9211_REG_BUCKA_CONT (addr=0x5D) */ |
168 | #define DA9211_BUCKA_EN 0x01 |
169 | #define DA9211_BUCKA_GPI_SHIFT 1 |
170 | #define DA9211_BUCKA_GPI_MASK 0x06 |
171 | #define DA9211_BUCKA_GPI_OFF 0x00 |
172 | #define DA9211_BUCKA_GPI_GPIO0 0x02 |
173 | #define DA9211_BUCKA_GPI_GPIO1 0x04 |
174 | #define DA9211_BUCKA_GPI_GPIO3 0x06 |
175 | #define DA9211_BUCKA_PD_DIS 0x08 |
176 | #define DA9211_VBUCKA_SEL 0x10 |
177 | #define DA9211_VBUCKA_SEL_A 0x00 |
178 | #define DA9211_VBUCKA_SEL_B 0x10 |
179 | #define DA9211_VBUCKA_GPI_SHIFT 5 |
180 | #define DA9211_VBUCKA_GPI_MASK 0x60 |
181 | #define DA9211_VBUCKA_GPI_OFF 0x00 |
182 | #define DA9211_VBUCKA_GPI_GPIO1 0x20 |
183 | #define DA9211_VBUCKA_GPI_GPIO2 0x40 |
184 | #define DA9211_VBUCKA_GPI_GPIO4 0x60 |
185 | |
186 | /* DA9211_REG_BUCKB_CONT (addr=0x5E) */ |
187 | #define DA9211_BUCKB_EN 0x01 |
188 | #define DA9211_BUCKB_GPI_SHIFT 1 |
189 | #define DA9211_BUCKB_GPI_MASK 0x06 |
190 | #define DA9211_BUCKB_GPI_OFF 0x00 |
191 | #define DA9211_BUCKB_GPI_GPIO0 0x02 |
192 | #define DA9211_BUCKB_GPI_GPIO1 0x04 |
193 | #define DA9211_BUCKB_GPI_GPIO3 0x06 |
194 | #define DA9211_BUCKB_PD_DIS 0x08 |
195 | #define DA9211_VBUCKB_SEL 0x10 |
196 | #define DA9211_VBUCKB_SEL_A 0x00 |
197 | #define DA9211_VBUCKB_SEL_B 0x10 |
198 | #define DA9211_VBUCKB_GPI_SHIFT 5 |
199 | #define DA9211_VBUCKB_GPI_MASK 0x60 |
200 | #define DA9211_VBUCKB_GPI_OFF 0x00 |
201 | #define DA9211_VBUCKB_GPI_GPIO1 0x20 |
202 | #define DA9211_VBUCKB_GPI_GPIO2 0x40 |
203 | #define DA9211_VBUCKB_GPI_GPIO4 0x60 |
204 | |
205 | /* DA9211_REG_BUCK_ILIM (addr=0xD0) */ |
206 | #define DA9211_BUCKA_ILIM_SHIFT 0 |
207 | #define DA9211_BUCKA_ILIM_MASK 0x0F |
208 | #define DA9211_BUCKB_ILIM_SHIFT 4 |
209 | #define DA9211_BUCKB_ILIM_MASK 0xF0 |
210 | |
211 | /* DA9211_REG_BUCKA_CONF (addr=0xD1) */ |
212 | #define DA9211_BUCKA_MODE_SHIFT 0 |
213 | #define DA9211_BUCKA_MODE_MASK 0x03 |
214 | #define DA9211_BUCKA_MODE_MANUAL 0x00 |
215 | #define DA9211_BUCKA_MODE_SLEEP 0x01 |
216 | #define DA9211_BUCKA_MODE_SYNC 0x02 |
217 | #define DA9211_BUCKA_MODE_AUTO 0x03 |
218 | #define DA9211_BUCKA_UP_CTRL_SHIFT 2 |
219 | #define DA9211_BUCKA_UP_CTRL_MASK 0x1C |
220 | #define DA9211_BUCKA_DOWN_CTRL_SHIFT 5 |
221 | #define DA9211_BUCKA_DOWN_CTRL_MASK 0xE0 |
222 | |
223 | /* DA9211_REG_BUCKB_CONF (addr=0xD2) */ |
224 | #define DA9211_BUCKB_MODE_SHIFT 0 |
225 | #define DA9211_BUCKB_MODE_MASK 0x03 |
226 | #define DA9211_BUCKB_MODE_MANUAL 0x00 |
227 | #define DA9211_BUCKB_MODE_SLEEP 0x01 |
228 | #define DA9211_BUCKB_MODE_SYNC 0x02 |
229 | #define DA9211_BUCKB_MODE_AUTO 0x03 |
230 | #define DA9211_BUCKB_UP_CTRL_SHIFT 2 |
231 | #define DA9211_BUCKB_UP_CTRL_MASK 0x1C |
232 | #define DA9211_BUCKB_DOWN_CTRL_SHIFT 5 |
233 | #define DA9211_BUCKB_DOWN_CTRL_MASK 0xE0 |
234 | |
235 | /* DA9211_REG_BUCK_CONF (addr=0xD3) */ |
236 | #define DA9211_PHASE_SEL_A_SHIFT 0 |
237 | #define DA9211_PHASE_SEL_A_MASK 0x03 |
238 | #define DA9211_PHASE_SEL_B_SHIFT 2 |
239 | #define DA9211_PHASE_SEL_B_MASK 0x04 |
240 | #define DA9211_PH_SH_EN_A_SHIFT 3 |
241 | #define DA9211_PH_SH_EN_A_MASK 0x08 |
242 | #define DA9211_PH_SH_EN_B_SHIFT 4 |
243 | #define DA9211_PH_SH_EN_B_MASK 0x10 |
244 | |
245 | /* DA9211_REG_VBUCKA_MAX (addr=0xD5) */ |
246 | #define DA9211_VBUCKA_BASE_SHIFT 0 |
247 | #define DA9211_VBUCKA_BASE_MASK 0x7F |
248 | |
249 | /* DA9211_REG_VBUCKB_MAX (addr=0xD6) */ |
250 | #define DA9211_VBUCKB_BASE_SHIFT 0 |
251 | #define DA9211_VBUCKB_BASE_MASK 0x7F |
252 | |
253 | /* DA9211_REG_VBUCKA/B_A/B (addr=0xD7/0xD8/0xD9/0xDA) */ |
254 | #define DA9211_VBUCK_SHIFT 0 |
255 | #define DA9211_VBUCK_MASK 0x7F |
256 | #define DA9211_VBUCK_BIAS 0 |
257 | #define DA9211_BUCK_SL 0x80 |
258 | |
259 | /* DA9211_REG_INTERFACE (addr=0x105) */ |
260 | #define DA9211_IF_BASE_ADDR_SHIFT 4 |
261 | #define DA9211_IF_BASE_ADDR_MASK 0xF0 |
262 | |
263 | /* DA9211_REG_CONFIG_E (addr=0x147) */ |
264 | #define DA9211_SLAVE_SEL 0x40 |
265 | |
266 | #endif /* __DA9211_REGISTERS_H__ */ |
267 | |