1// SPDX-License-Identifier: GPL-2.0
2/*
3 * An I2C driver for the PCF85063 RTC
4 * Copyright 2014 Rose Technology
5 *
6 * Author: Søren Andersen <san@rosetechnology.dk>
7 * Maintainers: http://www.nslu2-linux.org/
8 *
9 * Copyright (C) 2019 Micro Crystal AG
10 * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
11 */
12#include <linux/clk-provider.h>
13#include <linux/i2c.h>
14#include <linux/bcd.h>
15#include <linux/rtc.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/pm_wakeirq.h>
19#include <linux/regmap.h>
20
21/*
22 * Information for this driver was pulled from the following datasheets.
23 *
24 * https://www.nxp.com/docs/en/data-sheet/PCF85063A.pdf
25 * https://www.nxp.com/docs/en/data-sheet/PCF85063TP.pdf
26 *
27 * PCF85063A -- Rev. 7 — 30 March 2018
28 * PCF85063TP -- Rev. 4 — 6 May 2015
29 *
30 * https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
31 * RV8263 -- Rev. 1.0 — January 2019
32 */
33
34#define PCF85063_REG_CTRL1 0x00 /* status */
35#define PCF85063_REG_CTRL1_CAP_SEL BIT(0)
36#define PCF85063_REG_CTRL1_STOP BIT(5)
37#define PCF85063_REG_CTRL1_EXT_TEST BIT(7)
38#define PCF85063_REG_CTRL1_SWR 0x58
39
40#define PCF85063_REG_CTRL2 0x01
41#define PCF85063_CTRL2_AF BIT(6)
42#define PCF85063_CTRL2_AIE BIT(7)
43
44#define PCF85063_REG_OFFSET 0x02
45#define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
46#define PCF85063_OFFSET_MODE BIT(7)
47#define PCF85063_OFFSET_STEP0 4340
48#define PCF85063_OFFSET_STEP1 4069
49
50#define PCF85063_REG_CLKO_F_MASK 0x07 /* frequency mask */
51#define PCF85063_REG_CLKO_F_32768HZ 0x00
52#define PCF85063_REG_CLKO_F_OFF 0x07
53
54#define PCF85063_REG_RAM 0x03
55
56#define PCF85063_REG_SC 0x04 /* datetime */
57#define PCF85063_REG_SC_OS 0x80
58
59#define PCF85063_REG_ALM_S 0x0b
60#define PCF85063_AEN BIT(7)
61
62struct pcf85063_config {
63 struct regmap_config regmap;
64 unsigned has_alarms:1;
65 unsigned force_cap_7000:1;
66};
67
68struct pcf85063 {
69 struct rtc_device *rtc;
70 struct regmap *regmap;
71#ifdef CONFIG_COMMON_CLK
72 struct clk_hw clkout_hw;
73#endif
74};
75
76static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
77{
78 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
79 int rc;
80 u8 regs[7];
81
82 /*
83 * while reading, the time/date registers are blocked and not updated
84 * anymore until the access is finished. To not lose a second
85 * event, the access must be finished within one second. So, read all
86 * time/date registers in one turn.
87 */
88 rc = regmap_bulk_read(map: pcf85063->regmap, PCF85063_REG_SC, val: regs,
89 val_count: sizeof(regs));
90 if (rc)
91 return rc;
92
93 /* if the clock has lost its power it makes no sense to use its time */
94 if (regs[0] & PCF85063_REG_SC_OS) {
95 dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
96 return -EINVAL;
97 }
98
99 tm->tm_sec = bcd2bin(regs[0] & 0x7F);
100 tm->tm_min = bcd2bin(regs[1] & 0x7F);
101 tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
102 tm->tm_mday = bcd2bin(regs[3] & 0x3F);
103 tm->tm_wday = regs[4] & 0x07;
104 tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
105 tm->tm_year = bcd2bin(regs[6]);
106 tm->tm_year += 100;
107
108 return 0;
109}
110
111static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
112{
113 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
114 int rc;
115 u8 regs[7];
116
117 /*
118 * to accurately set the time, reset the divider chain and keep it in
119 * reset state until all time/date registers are written
120 */
121 rc = regmap_update_bits(map: pcf85063->regmap, PCF85063_REG_CTRL1,
122 PCF85063_REG_CTRL1_EXT_TEST |
123 PCF85063_REG_CTRL1_STOP,
124 PCF85063_REG_CTRL1_STOP);
125 if (rc)
126 return rc;
127
128 /* hours, minutes and seconds */
129 regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
130
131 regs[1] = bin2bcd(tm->tm_min);
132 regs[2] = bin2bcd(tm->tm_hour);
133
134 /* Day of month, 1 - 31 */
135 regs[3] = bin2bcd(tm->tm_mday);
136
137 /* Day, 0 - 6 */
138 regs[4] = tm->tm_wday & 0x07;
139
140 /* month, 1 - 12 */
141 regs[5] = bin2bcd(tm->tm_mon + 1);
142
143 /* year and century */
144 regs[6] = bin2bcd(tm->tm_year - 100);
145
146 /* write all registers at once */
147 rc = regmap_bulk_write(map: pcf85063->regmap, PCF85063_REG_SC,
148 val: regs, val_count: sizeof(regs));
149 if (rc)
150 return rc;
151
152 /*
153 * Write the control register as a separate action since the size of
154 * the register space is different between the PCF85063TP and
155 * PCF85063A devices. The rollover point can not be used.
156 */
157 return regmap_update_bits(map: pcf85063->regmap, PCF85063_REG_CTRL1,
158 PCF85063_REG_CTRL1_STOP, val: 0);
159}
160
161static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
162{
163 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
164 u8 buf[4];
165 unsigned int val;
166 int ret;
167
168 ret = regmap_bulk_read(map: pcf85063->regmap, PCF85063_REG_ALM_S,
169 val: buf, val_count: sizeof(buf));
170 if (ret)
171 return ret;
172
173 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7f);
174 alrm->time.tm_min = bcd2bin(buf[1] & 0x7f);
175 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3f);
176 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3f);
177
178 ret = regmap_read(map: pcf85063->regmap, PCF85063_REG_CTRL2, val: &val);
179 if (ret)
180 return ret;
181
182 alrm->enabled = !!(val & PCF85063_CTRL2_AIE);
183
184 return 0;
185}
186
187static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
188{
189 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
190 u8 buf[5];
191 int ret;
192
193 buf[0] = bin2bcd(alrm->time.tm_sec);
194 buf[1] = bin2bcd(alrm->time.tm_min);
195 buf[2] = bin2bcd(alrm->time.tm_hour);
196 buf[3] = bin2bcd(alrm->time.tm_mday);
197 buf[4] = PCF85063_AEN; /* Do not match on week day */
198
199 ret = regmap_update_bits(map: pcf85063->regmap, PCF85063_REG_CTRL2,
200 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, val: 0);
201 if (ret)
202 return ret;
203
204 ret = regmap_bulk_write(map: pcf85063->regmap, PCF85063_REG_ALM_S,
205 val: buf, val_count: sizeof(buf));
206 if (ret)
207 return ret;
208
209 return regmap_update_bits(map: pcf85063->regmap, PCF85063_REG_CTRL2,
210 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
211 val: alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
212}
213
214static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
215 unsigned int enabled)
216{
217 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
218
219 return regmap_update_bits(map: pcf85063->regmap, PCF85063_REG_CTRL2,
220 PCF85063_CTRL2_AIE,
221 val: enabled ? PCF85063_CTRL2_AIE : 0);
222}
223
224static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
225{
226 struct pcf85063 *pcf85063 = dev_id;
227 unsigned int val;
228 int err;
229
230 err = regmap_read(map: pcf85063->regmap, PCF85063_REG_CTRL2, val: &val);
231 if (err)
232 return IRQ_NONE;
233
234 if (val & PCF85063_CTRL2_AF) {
235 rtc_update_irq(rtc: pcf85063->rtc, num: 1, RTC_IRQF | RTC_AF);
236 regmap_update_bits(map: pcf85063->regmap, PCF85063_REG_CTRL2,
237 PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
238 val: 0);
239 return IRQ_HANDLED;
240 }
241
242 return IRQ_NONE;
243}
244
245static int pcf85063_read_offset(struct device *dev, long *offset)
246{
247 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
248 long val;
249 u32 reg;
250 int ret;
251
252 ret = regmap_read(map: pcf85063->regmap, PCF85063_REG_OFFSET, val: &reg);
253 if (ret < 0)
254 return ret;
255
256 val = sign_extend32(value: reg & ~PCF85063_OFFSET_MODE,
257 PCF85063_OFFSET_SIGN_BIT);
258
259 if (reg & PCF85063_OFFSET_MODE)
260 *offset = val * PCF85063_OFFSET_STEP1;
261 else
262 *offset = val * PCF85063_OFFSET_STEP0;
263
264 return 0;
265}
266
267static int pcf85063_set_offset(struct device *dev, long offset)
268{
269 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
270 s8 mode0, mode1, reg;
271 unsigned int error0, error1;
272
273 if (offset > PCF85063_OFFSET_STEP0 * 63)
274 return -ERANGE;
275 if (offset < PCF85063_OFFSET_STEP0 * -64)
276 return -ERANGE;
277
278 mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
279 mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
280
281 error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
282 error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
283 if (mode1 > 63 || mode1 < -64 || error0 < error1)
284 reg = mode0 & ~PCF85063_OFFSET_MODE;
285 else
286 reg = mode1 | PCF85063_OFFSET_MODE;
287
288 return regmap_write(map: pcf85063->regmap, PCF85063_REG_OFFSET, val: reg);
289}
290
291static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
292 unsigned long arg)
293{
294 struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
295 int status, ret = 0;
296
297 switch (cmd) {
298 case RTC_VL_READ:
299 ret = regmap_read(map: pcf85063->regmap, PCF85063_REG_SC, val: &status);
300 if (ret < 0)
301 return ret;
302
303 status = (status & PCF85063_REG_SC_OS) ? RTC_VL_DATA_INVALID : 0;
304
305 return put_user(status, (unsigned int __user *)arg);
306
307 default:
308 return -ENOIOCTLCMD;
309 }
310}
311
312static const struct rtc_class_ops pcf85063_rtc_ops = {
313 .read_time = pcf85063_rtc_read_time,
314 .set_time = pcf85063_rtc_set_time,
315 .read_offset = pcf85063_read_offset,
316 .set_offset = pcf85063_set_offset,
317 .read_alarm = pcf85063_rtc_read_alarm,
318 .set_alarm = pcf85063_rtc_set_alarm,
319 .alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
320 .ioctl = pcf85063_ioctl,
321};
322
323static int pcf85063_nvmem_read(void *priv, unsigned int offset,
324 void *val, size_t bytes)
325{
326 unsigned int tmp;
327 int ret;
328
329 ret = regmap_read(map: priv, PCF85063_REG_RAM, val: &tmp);
330 if (ret < 0)
331 return ret;
332
333 *(u8 *)val = tmp;
334
335 return 0;
336}
337
338static int pcf85063_nvmem_write(void *priv, unsigned int offset,
339 void *val, size_t bytes)
340{
341 return regmap_write(map: priv, PCF85063_REG_RAM, val: *(u8 *)val);
342}
343
344static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
345 const struct device_node *np,
346 unsigned int force_cap)
347{
348 u32 load = 7000;
349 u8 reg = 0;
350
351 if (force_cap)
352 load = force_cap;
353 else
354 of_property_read_u32(np, propname: "quartz-load-femtofarads", out_value: &load);
355
356 switch (load) {
357 default:
358 dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
359 load);
360 fallthrough;
361 case 7000:
362 break;
363 case 12500:
364 reg = PCF85063_REG_CTRL1_CAP_SEL;
365 break;
366 }
367
368 return regmap_update_bits(map: pcf85063->regmap, PCF85063_REG_CTRL1,
369 PCF85063_REG_CTRL1_CAP_SEL, val: reg);
370}
371
372#ifdef CONFIG_COMMON_CLK
373/*
374 * Handling of the clkout
375 */
376
377#define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
378
379static int clkout_rates[] = {
380 32768,
381 16384,
382 8192,
383 4096,
384 2048,
385 1024,
386 1,
387 0
388};
389
390static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
391 unsigned long parent_rate)
392{
393 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
394 unsigned int buf;
395 int ret = regmap_read(map: pcf85063->regmap, PCF85063_REG_CTRL2, val: &buf);
396
397 if (ret < 0)
398 return 0;
399
400 buf &= PCF85063_REG_CLKO_F_MASK;
401 return clkout_rates[buf];
402}
403
404static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
405 unsigned long *prate)
406{
407 int i;
408
409 for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
410 if (clkout_rates[i] <= rate)
411 return clkout_rates[i];
412
413 return 0;
414}
415
416static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
417 unsigned long parent_rate)
418{
419 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
420 int i;
421
422 for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
423 if (clkout_rates[i] == rate)
424 return regmap_update_bits(map: pcf85063->regmap,
425 PCF85063_REG_CTRL2,
426 PCF85063_REG_CLKO_F_MASK, val: i);
427
428 return -EINVAL;
429}
430
431static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
432{
433 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
434 unsigned int buf;
435 int ret;
436
437 ret = regmap_read(map: pcf85063->regmap, PCF85063_REG_CTRL2, val: &buf);
438 if (ret < 0)
439 return ret;
440 buf &= PCF85063_REG_CLKO_F_MASK;
441
442 if (enable) {
443 if (buf == PCF85063_REG_CLKO_F_OFF)
444 buf = PCF85063_REG_CLKO_F_32768HZ;
445 else
446 return 0;
447 } else {
448 if (buf != PCF85063_REG_CLKO_F_OFF)
449 buf = PCF85063_REG_CLKO_F_OFF;
450 else
451 return 0;
452 }
453
454 return regmap_update_bits(map: pcf85063->regmap, PCF85063_REG_CTRL2,
455 PCF85063_REG_CLKO_F_MASK, val: buf);
456}
457
458static int pcf85063_clkout_prepare(struct clk_hw *hw)
459{
460 return pcf85063_clkout_control(hw, enable: 1);
461}
462
463static void pcf85063_clkout_unprepare(struct clk_hw *hw)
464{
465 pcf85063_clkout_control(hw, enable: 0);
466}
467
468static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
469{
470 struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
471 unsigned int buf;
472 int ret = regmap_read(map: pcf85063->regmap, PCF85063_REG_CTRL2, val: &buf);
473
474 if (ret < 0)
475 return 0;
476
477 return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
478}
479
480static const struct clk_ops pcf85063_clkout_ops = {
481 .prepare = pcf85063_clkout_prepare,
482 .unprepare = pcf85063_clkout_unprepare,
483 .is_prepared = pcf85063_clkout_is_prepared,
484 .recalc_rate = pcf85063_clkout_recalc_rate,
485 .round_rate = pcf85063_clkout_round_rate,
486 .set_rate = pcf85063_clkout_set_rate,
487};
488
489static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
490{
491 struct clk *clk;
492 struct clk_init_data init;
493 struct device_node *node = pcf85063->rtc->dev.parent->of_node;
494 struct device_node *fixed_clock;
495
496 fixed_clock = of_get_child_by_name(node, name: "clock");
497 if (fixed_clock) {
498 /*
499 * skip registering square wave clock when a fixed
500 * clock has been registered. The fixed clock is
501 * registered automatically when being referenced.
502 */
503 of_node_put(node: fixed_clock);
504 return NULL;
505 }
506
507 init.name = "pcf85063-clkout";
508 init.ops = &pcf85063_clkout_ops;
509 init.flags = 0;
510 init.parent_names = NULL;
511 init.num_parents = 0;
512 pcf85063->clkout_hw.init = &init;
513
514 /* optional override of the clockname */
515 of_property_read_string(np: node, propname: "clock-output-names", out_string: &init.name);
516
517 /* register the clock */
518 clk = devm_clk_register(dev: &pcf85063->rtc->dev, hw: &pcf85063->clkout_hw);
519
520 if (!IS_ERR(ptr: clk))
521 of_clk_add_provider(np: node, clk_src_get: of_clk_src_simple_get, data: clk);
522
523 return clk;
524}
525#endif
526
527static const struct pcf85063_config config_pcf85063 = {
528 .regmap = {
529 .reg_bits = 8,
530 .val_bits = 8,
531 .max_register = 0x0a,
532 },
533};
534
535static const struct pcf85063_config config_pcf85063tp = {
536 .regmap = {
537 .reg_bits = 8,
538 .val_bits = 8,
539 .max_register = 0x0a,
540 },
541};
542
543static const struct pcf85063_config config_pcf85063a = {
544 .regmap = {
545 .reg_bits = 8,
546 .val_bits = 8,
547 .max_register = 0x11,
548 },
549 .has_alarms = 1,
550};
551
552static const struct pcf85063_config config_rv8263 = {
553 .regmap = {
554 .reg_bits = 8,
555 .val_bits = 8,
556 .max_register = 0x11,
557 },
558 .has_alarms = 1,
559 .force_cap_7000 = 1,
560};
561
562static int pcf85063_probe(struct i2c_client *client)
563{
564 struct pcf85063 *pcf85063;
565 unsigned int tmp;
566 int err;
567 const struct pcf85063_config *config;
568 struct nvmem_config nvmem_cfg = {
569 .name = "pcf85063_nvram",
570 .reg_read = pcf85063_nvmem_read,
571 .reg_write = pcf85063_nvmem_write,
572 .type = NVMEM_TYPE_BATTERY_BACKED,
573 .size = 1,
574 };
575
576 dev_dbg(&client->dev, "%s\n", __func__);
577
578 pcf85063 = devm_kzalloc(dev: &client->dev, size: sizeof(struct pcf85063),
579 GFP_KERNEL);
580 if (!pcf85063)
581 return -ENOMEM;
582
583 config = i2c_get_match_data(client);
584 if (!config)
585 return -ENODEV;
586
587 pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
588 if (IS_ERR(ptr: pcf85063->regmap))
589 return PTR_ERR(ptr: pcf85063->regmap);
590
591 i2c_set_clientdata(client, data: pcf85063);
592
593 err = regmap_read(map: pcf85063->regmap, PCF85063_REG_SC, val: &tmp);
594 if (err)
595 return dev_err_probe(dev: &client->dev, err, fmt: "RTC chip is not present\n");
596
597 pcf85063->rtc = devm_rtc_allocate_device(dev: &client->dev);
598 if (IS_ERR(ptr: pcf85063->rtc))
599 return PTR_ERR(ptr: pcf85063->rtc);
600
601 /*
602 * If a Power loss is detected, SW reset the device.
603 * From PCF85063A datasheet:
604 * There is a low probability that some devices will have corruption
605 * of the registers after the automatic power-on reset...
606 */
607 if (tmp & PCF85063_REG_SC_OS) {
608 dev_warn(&client->dev,
609 "POR issue detected, sending a SW reset\n");
610 err = regmap_write(map: pcf85063->regmap, PCF85063_REG_CTRL1,
611 PCF85063_REG_CTRL1_SWR);
612 if (err < 0)
613 dev_warn(&client->dev,
614 "SW reset failed, trying to continue\n");
615 }
616
617 err = pcf85063_load_capacitance(pcf85063, np: client->dev.of_node,
618 force_cap: config->force_cap_7000 ? 7000 : 0);
619 if (err < 0)
620 dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
621 err);
622
623 pcf85063->rtc->ops = &pcf85063_rtc_ops;
624 pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
625 pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
626 set_bit(RTC_FEATURE_ALARM_RES_2S, addr: pcf85063->rtc->features);
627 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, addr: pcf85063->rtc->features);
628 clear_bit(RTC_FEATURE_ALARM, addr: pcf85063->rtc->features);
629
630 if (config->has_alarms && client->irq > 0) {
631 unsigned long irqflags = IRQF_TRIGGER_LOW;
632
633 if (dev_fwnode(&client->dev))
634 irqflags = 0;
635
636 err = devm_request_threaded_irq(dev: &client->dev, irq: client->irq,
637 NULL, thread_fn: pcf85063_rtc_handle_irq,
638 irqflags: irqflags | IRQF_ONESHOT,
639 devname: "pcf85063", dev_id: pcf85063);
640 if (err) {
641 dev_warn(&pcf85063->rtc->dev,
642 "unable to request IRQ, alarms disabled\n");
643 } else {
644 set_bit(RTC_FEATURE_ALARM, addr: pcf85063->rtc->features);
645 device_init_wakeup(dev: &client->dev, enable: true);
646 err = dev_pm_set_wake_irq(dev: &client->dev, irq: client->irq);
647 if (err)
648 dev_err(&pcf85063->rtc->dev,
649 "failed to enable irq wake\n");
650 }
651 }
652
653 nvmem_cfg.priv = pcf85063->regmap;
654 devm_rtc_nvmem_register(rtc: pcf85063->rtc, nvmem_config: &nvmem_cfg);
655
656#ifdef CONFIG_COMMON_CLK
657 /* register clk in common clk framework */
658 pcf85063_clkout_register_clk(pcf85063);
659#endif
660
661 return devm_rtc_register_device(pcf85063->rtc);
662}
663
664static const struct i2c_device_id pcf85063_ids[] = {
665 { "pca85073a", .driver_data = (kernel_ulong_t)&config_pcf85063a },
666 { "pcf85063", .driver_data = (kernel_ulong_t)&config_pcf85063 },
667 { "pcf85063tp", .driver_data = (kernel_ulong_t)&config_pcf85063tp },
668 { "pcf85063a", .driver_data = (kernel_ulong_t)&config_pcf85063a },
669 { "rv8263", .driver_data = (kernel_ulong_t)&config_rv8263 },
670 {}
671};
672MODULE_DEVICE_TABLE(i2c, pcf85063_ids);
673
674#ifdef CONFIG_OF
675static const struct of_device_id pcf85063_of_match[] = {
676 { .compatible = "nxp,pca85073a", .data = &config_pcf85063a },
677 { .compatible = "nxp,pcf85063", .data = &config_pcf85063 },
678 { .compatible = "nxp,pcf85063tp", .data = &config_pcf85063tp },
679 { .compatible = "nxp,pcf85063a", .data = &config_pcf85063a },
680 { .compatible = "microcrystal,rv8263", .data = &config_rv8263 },
681 {}
682};
683MODULE_DEVICE_TABLE(of, pcf85063_of_match);
684#endif
685
686static struct i2c_driver pcf85063_driver = {
687 .driver = {
688 .name = "rtc-pcf85063",
689 .of_match_table = of_match_ptr(pcf85063_of_match),
690 },
691 .probe = pcf85063_probe,
692 .id_table = pcf85063_ids,
693};
694
695module_i2c_driver(pcf85063_driver);
696
697MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
698MODULE_DESCRIPTION("PCF85063 RTC driver");
699MODULE_LICENSE("GPL");
700

source code of linux/drivers/rtc/rtc-pcf85063.c