1 | /* 57xx_hsi_bnx2fc.h: QLogic Linux FCoE offload driver. |
2 | * Handles operations such as session offload/upload etc, and manages |
3 | * session resources such as connection id and qp resources. |
4 | * |
5 | * Copyright (c) 2008-2013 Broadcom Corporation |
6 | * Copyright (c) 2014-2016 QLogic Corporation |
7 | * Copyright (c) 2016-2017 Cavium Inc. |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by |
11 | * the Free Software Foundation. |
12 | * |
13 | */ |
14 | |
15 | #ifndef __57XX_FCOE_HSI_LINUX_LE__ |
16 | #define __57XX_FCOE_HSI_LINUX_LE__ |
17 | |
18 | /* |
19 | * common data for all protocols |
20 | */ |
21 | struct b577xx_doorbell_hdr { |
22 | u8 ; |
23 | #define B577XX_DOORBELL_HDR_RX (0x1<<0) |
24 | #define B577XX_DOORBELL_HDR_RX_SHIFT 0 |
25 | #define B577XX_DOORBELL_HDR_DB_TYPE (0x1<<1) |
26 | #define B577XX_DOORBELL_HDR_DB_TYPE_SHIFT 1 |
27 | #define B577XX_DOORBELL_HDR_DPM_SIZE (0x3<<2) |
28 | #define B577XX_DOORBELL_HDR_DPM_SIZE_SHIFT 2 |
29 | #define B577XX_DOORBELL_HDR_CONN_TYPE (0xF<<4) |
30 | #define B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT 4 |
31 | }; |
32 | |
33 | /* |
34 | * doorbell message sent to the chip |
35 | */ |
36 | struct b577xx_doorbell { |
37 | #if defined(__BIG_ENDIAN) |
38 | u16 zero_fill2; |
39 | u8 zero_fill1; |
40 | struct b577xx_doorbell_hdr header; |
41 | #elif defined(__LITTLE_ENDIAN) |
42 | struct b577xx_doorbell_hdr ; |
43 | u8 zero_fill1; |
44 | u16 zero_fill2; |
45 | #endif |
46 | }; |
47 | |
48 | |
49 | |
50 | /* |
51 | * doorbell message sent to the chip |
52 | */ |
53 | struct b577xx_doorbell_set_prod { |
54 | #if defined(__BIG_ENDIAN) |
55 | u16 prod; |
56 | u8 zero_fill1; |
57 | struct b577xx_doorbell_hdr header; |
58 | #elif defined(__LITTLE_ENDIAN) |
59 | struct b577xx_doorbell_hdr ; |
60 | u8 zero_fill1; |
61 | u16 prod; |
62 | #endif |
63 | }; |
64 | |
65 | |
66 | struct regpair { |
67 | __le32 lo; |
68 | __le32 hi; |
69 | }; |
70 | |
71 | |
72 | /* |
73 | * ABTS info $$KEEP_ENDIANNESS$$ |
74 | */ |
75 | struct fcoe_abts_info { |
76 | __le16 aborted_task_id; |
77 | __le16 reserved0; |
78 | __le32 reserved1; |
79 | }; |
80 | |
81 | |
82 | /* |
83 | * Fixed size structure in order to plant it in Union structure |
84 | * $$KEEP_ENDIANNESS$$ |
85 | */ |
86 | struct fcoe_abts_rsp_union { |
87 | u8 r_ctl; |
88 | u8 rsrv[3]; |
89 | __le32 abts_rsp_payload[7]; |
90 | }; |
91 | |
92 | |
93 | /* |
94 | * 4 regs size $$KEEP_ENDIANNESS$$ |
95 | */ |
96 | struct fcoe_bd_ctx { |
97 | __le32 buf_addr_hi; |
98 | __le32 buf_addr_lo; |
99 | __le16 buf_len; |
100 | __le16 rsrv0; |
101 | __le16 flags; |
102 | __le16 rsrv1; |
103 | }; |
104 | |
105 | |
106 | /* |
107 | * FCoE cached sges context $$KEEP_ENDIANNESS$$ |
108 | */ |
109 | struct fcoe_cached_sge_ctx { |
110 | struct regpair cur_buf_addr; |
111 | __le16 cur_buf_rem; |
112 | __le16 second_buf_rem; |
113 | struct regpair second_buf_addr; |
114 | }; |
115 | |
116 | |
117 | /* |
118 | * Cleanup info $$KEEP_ENDIANNESS$$ |
119 | */ |
120 | struct fcoe_cleanup_info { |
121 | __le16 cleaned_task_id; |
122 | __le16 rolled_tx_seq_cnt; |
123 | __le32 rolled_tx_data_offset; |
124 | }; |
125 | |
126 | |
127 | /* |
128 | * Fcp RSP flags $$KEEP_ENDIANNESS$$ |
129 | */ |
130 | struct fcoe_fcp_rsp_flags { |
131 | u8 flags; |
132 | #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0) |
133 | #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0 |
134 | #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1) |
135 | #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1 |
136 | #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2) |
137 | #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2 |
138 | #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3) |
139 | #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3 |
140 | #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4) |
141 | #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4 |
142 | #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5) |
143 | #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5 |
144 | }; |
145 | |
146 | /* |
147 | * Fcp RSP payload $$KEEP_ENDIANNESS$$ |
148 | */ |
149 | struct fcoe_fcp_rsp_payload { |
150 | struct regpair reserved0; |
151 | __le32 fcp_resid; |
152 | u8 scsi_status_code; |
153 | struct fcoe_fcp_rsp_flags fcp_flags; |
154 | __le16 retry_delay_timer; |
155 | __le32 fcp_rsp_len; |
156 | __le32 fcp_sns_len; |
157 | }; |
158 | |
159 | /* |
160 | * Fixed size structure in order to plant it in Union structure |
161 | * $$KEEP_ENDIANNESS$$ |
162 | */ |
163 | struct fcoe_fcp_rsp_union { |
164 | struct fcoe_fcp_rsp_payload payload; |
165 | struct regpair reserved0; |
166 | }; |
167 | |
168 | /* |
169 | * FC header $$KEEP_ENDIANNESS$$ |
170 | */ |
171 | struct fcoe_fc_hdr { |
172 | u8 s_id[3]; |
173 | u8 cs_ctl; |
174 | u8 d_id[3]; |
175 | u8 r_ctl; |
176 | __le16 seq_cnt; |
177 | u8 df_ctl; |
178 | u8 seq_id; |
179 | u8 f_ctl[3]; |
180 | u8 type; |
181 | __le32 parameters; |
182 | __le16 rx_id; |
183 | __le16 ox_id; |
184 | }; |
185 | |
186 | /* |
187 | * FC header union $$KEEP_ENDIANNESS$$ |
188 | */ |
189 | struct fcoe_mp_rsp_union { |
190 | struct fcoe_fc_hdr fc_hdr; |
191 | __le32 mp_payload_len; |
192 | __le32 rsrv; |
193 | }; |
194 | |
195 | /* |
196 | * Completion information $$KEEP_ENDIANNESS$$ |
197 | */ |
198 | union fcoe_comp_flow_info { |
199 | struct fcoe_fcp_rsp_union fcp_rsp; |
200 | struct fcoe_abts_rsp_union abts_rsp; |
201 | struct fcoe_mp_rsp_union mp_rsp; |
202 | __le32 opaque[8]; |
203 | }; |
204 | |
205 | |
206 | /* |
207 | * External ABTS info $$KEEP_ENDIANNESS$$ |
208 | */ |
209 | struct fcoe_ext_abts_info { |
210 | __le32 rsrv0[6]; |
211 | struct fcoe_abts_info ctx; |
212 | }; |
213 | |
214 | |
215 | /* |
216 | * External cleanup info $$KEEP_ENDIANNESS$$ |
217 | */ |
218 | struct fcoe_ext_cleanup_info { |
219 | __le32 rsrv0[6]; |
220 | struct fcoe_cleanup_info ctx; |
221 | }; |
222 | |
223 | |
224 | /* |
225 | * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$ |
226 | */ |
227 | struct fcoe_fw_tx_seq_ctx { |
228 | __le32 data_offset; |
229 | __le16 seq_cnt; |
230 | __le16 rsrv0; |
231 | }; |
232 | |
233 | /* |
234 | * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$ |
235 | */ |
236 | struct fcoe_ext_fw_tx_seq_ctx { |
237 | __le32 rsrv0[6]; |
238 | struct fcoe_fw_tx_seq_ctx ctx; |
239 | }; |
240 | |
241 | |
242 | /* |
243 | * FCoE multiple sges context $$KEEP_ENDIANNESS$$ |
244 | */ |
245 | struct fcoe_mul_sges_ctx { |
246 | struct regpair cur_sge_addr; |
247 | __le16 cur_sge_off; |
248 | u8 cur_sge_idx; |
249 | u8 sgl_size; |
250 | }; |
251 | |
252 | /* |
253 | * FCoE external multiple sges context $$KEEP_ENDIANNESS$$ |
254 | */ |
255 | struct fcoe_ext_mul_sges_ctx { |
256 | struct fcoe_mul_sges_ctx mul_sgl; |
257 | struct regpair rsrv0; |
258 | }; |
259 | |
260 | |
261 | /* |
262 | * FCP CMD payload $$KEEP_ENDIANNESS$$ |
263 | */ |
264 | struct fcoe_fcp_cmd_payload { |
265 | __le32 opaque[8]; |
266 | }; |
267 | |
268 | |
269 | |
270 | |
271 | |
272 | /* |
273 | * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$ |
274 | */ |
275 | struct fcoe_fcp_xfr_rdy_payload { |
276 | __le32 burst_len; |
277 | __le32 data_ro; |
278 | }; |
279 | |
280 | |
281 | /* |
282 | * FC frame $$KEEP_ENDIANNESS$$ |
283 | */ |
284 | struct fcoe_fc_frame { |
285 | struct fcoe_fc_hdr fc_hdr; |
286 | __le32 reserved0[2]; |
287 | }; |
288 | |
289 | |
290 | |
291 | |
292 | /* |
293 | * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$ |
294 | */ |
295 | union fcoe_kcqe_params { |
296 | __le32 reserved0[4]; |
297 | }; |
298 | |
299 | /* |
300 | * FCoE KCQ CQE $$KEEP_ENDIANNESS$$ |
301 | */ |
302 | struct fcoe_kcqe { |
303 | __le32 fcoe_conn_id; |
304 | __le32 completion_status; |
305 | __le32 fcoe_conn_context_id; |
306 | union fcoe_kcqe_params params; |
307 | __le16 qe_self_seq; |
308 | u8 op_code; |
309 | u8 flags; |
310 | #define FCOE_KCQE_RESERVED0 (0x7<<0) |
311 | #define FCOE_KCQE_RESERVED0_SHIFT 0 |
312 | #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3) |
313 | #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3 |
314 | #define FCOE_KCQE_LAYER_CODE (0x7<<4) |
315 | #define FCOE_KCQE_LAYER_CODE_SHIFT 4 |
316 | #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) |
317 | #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7 |
318 | }; |
319 | |
320 | |
321 | |
322 | /* |
323 | * FCoE KWQE header $$KEEP_ENDIANNESS$$ |
324 | */ |
325 | struct { |
326 | u8 ; |
327 | u8 ; |
328 | #define (0xF<<0) |
329 | #define 0 |
330 | #define (0x7<<4) |
331 | #define 4 |
332 | #define (0x1<<7) |
333 | #define 7 |
334 | }; |
335 | |
336 | /* |
337 | * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$ |
338 | */ |
339 | struct fcoe_kwqe_init1 { |
340 | __le16 num_tasks; |
341 | struct fcoe_kwqe_header hdr; |
342 | __le32 task_list_pbl_addr_lo; |
343 | __le32 task_list_pbl_addr_hi; |
344 | __le32 dummy_buffer_addr_lo; |
345 | __le32 dummy_buffer_addr_hi; |
346 | __le16 sq_num_wqes; |
347 | __le16 rq_num_wqes; |
348 | __le16 rq_buffer_log_size; |
349 | __le16 cq_num_wqes; |
350 | __le16 mtu; |
351 | u8 num_sessions_log; |
352 | u8 flags; |
353 | #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) |
354 | #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0 |
355 | #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4) |
356 | #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4 |
357 | #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7) |
358 | #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7 |
359 | }; |
360 | |
361 | /* |
362 | * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$ |
363 | */ |
364 | struct fcoe_kwqe_init2 { |
365 | u8 hsi_major_version; |
366 | u8 hsi_minor_version; |
367 | struct fcoe_kwqe_header hdr; |
368 | __le32 hash_tbl_pbl_addr_lo; |
369 | __le32 hash_tbl_pbl_addr_hi; |
370 | __le32 t2_hash_tbl_addr_lo; |
371 | __le32 t2_hash_tbl_addr_hi; |
372 | __le32 t2_ptr_hash_tbl_addr_lo; |
373 | __le32 t2_ptr_hash_tbl_addr_hi; |
374 | __le32 free_list_count; |
375 | }; |
376 | |
377 | /* |
378 | * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$ |
379 | */ |
380 | struct fcoe_kwqe_init3 { |
381 | __le16 reserved0; |
382 | struct fcoe_kwqe_header hdr; |
383 | __le32 error_bit_map_lo; |
384 | __le32 error_bit_map_hi; |
385 | u8 perf_config; |
386 | u8 reserved21[3]; |
387 | __le32 reserved2[4]; |
388 | }; |
389 | |
390 | /* |
391 | * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$ |
392 | */ |
393 | struct fcoe_kwqe_conn_offload1 { |
394 | __le16 fcoe_conn_id; |
395 | struct fcoe_kwqe_header hdr; |
396 | __le32 sq_addr_lo; |
397 | __le32 sq_addr_hi; |
398 | __le32 rq_pbl_addr_lo; |
399 | __le32 rq_pbl_addr_hi; |
400 | __le32 rq_first_pbe_addr_lo; |
401 | __le32 rq_first_pbe_addr_hi; |
402 | __le16 rq_prod; |
403 | __le16 reserved0; |
404 | }; |
405 | |
406 | /* |
407 | * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$ |
408 | */ |
409 | struct fcoe_kwqe_conn_offload2 { |
410 | __le16 tx_max_fc_pay_len; |
411 | struct fcoe_kwqe_header hdr; |
412 | __le32 cq_addr_lo; |
413 | __le32 cq_addr_hi; |
414 | __le32 xferq_addr_lo; |
415 | __le32 xferq_addr_hi; |
416 | __le32 conn_db_addr_lo; |
417 | __le32 conn_db_addr_hi; |
418 | __le32 reserved1; |
419 | }; |
420 | |
421 | /* |
422 | * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$ |
423 | */ |
424 | struct fcoe_kwqe_conn_offload3 { |
425 | __le16 vlan_tag; |
426 | #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) |
427 | #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0 |
428 | #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) |
429 | #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12 |
430 | #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) |
431 | #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13 |
432 | struct fcoe_kwqe_header hdr; |
433 | u8 s_id[3]; |
434 | u8 tx_max_conc_seqs_c3; |
435 | u8 d_id[3]; |
436 | u8 flags; |
437 | #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) |
438 | #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0 |
439 | #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1) |
440 | #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1 |
441 | #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2) |
442 | #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2 |
443 | #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3) |
444 | #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3 |
445 | #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4) |
446 | #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4 |
447 | #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5) |
448 | #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5 |
449 | #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6) |
450 | #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6 |
451 | #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) |
452 | #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7 |
453 | __le32 reserved; |
454 | __le32 confq_first_pbe_addr_lo; |
455 | __le32 confq_first_pbe_addr_hi; |
456 | __le16 tx_total_conc_seqs; |
457 | __le16 rx_max_fc_pay_len; |
458 | __le16 rx_total_conc_seqs; |
459 | u8 rx_max_conc_seqs_c3; |
460 | u8 rx_open_seqs_exch_c3; |
461 | }; |
462 | |
463 | /* |
464 | * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$ |
465 | */ |
466 | struct fcoe_kwqe_conn_offload4 { |
467 | u8 e_d_tov_timer_val; |
468 | u8 reserved2; |
469 | struct fcoe_kwqe_header hdr; |
470 | u8 src_mac_addr_lo[2]; |
471 | u8 src_mac_addr_mid[2]; |
472 | u8 src_mac_addr_hi[2]; |
473 | u8 dst_mac_addr_hi[2]; |
474 | u8 dst_mac_addr_lo[2]; |
475 | u8 dst_mac_addr_mid[2]; |
476 | __le32 lcq_addr_lo; |
477 | __le32 lcq_addr_hi; |
478 | __le32 confq_pbl_base_addr_lo; |
479 | __le32 confq_pbl_base_addr_hi; |
480 | }; |
481 | |
482 | /* |
483 | * FCoE connection enable request $$KEEP_ENDIANNESS$$ |
484 | */ |
485 | struct fcoe_kwqe_conn_enable_disable { |
486 | __le16 reserved0; |
487 | struct fcoe_kwqe_header hdr; |
488 | u8 src_mac_addr_lo[2]; |
489 | u8 src_mac_addr_mid[2]; |
490 | u8 src_mac_addr_hi[2]; |
491 | u16 vlan_tag; |
492 | #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) |
493 | #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0 |
494 | #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12) |
495 | #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12 |
496 | #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) |
497 | #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13 |
498 | u8 dst_mac_addr_lo[2]; |
499 | u8 dst_mac_addr_mid[2]; |
500 | u8 dst_mac_addr_hi[2]; |
501 | __le16 reserved1; |
502 | u8 s_id[3]; |
503 | u8 vlan_flag; |
504 | u8 d_id[3]; |
505 | u8 reserved3; |
506 | __le32 context_id; |
507 | __le32 conn_id; |
508 | __le32 reserved4; |
509 | }; |
510 | |
511 | /* |
512 | * FCoE connection destroy request $$KEEP_ENDIANNESS$$ |
513 | */ |
514 | struct fcoe_kwqe_conn_destroy { |
515 | __le16 reserved0; |
516 | struct fcoe_kwqe_header hdr; |
517 | __le32 context_id; |
518 | __le32 conn_id; |
519 | __le32 reserved1[5]; |
520 | }; |
521 | |
522 | /* |
523 | * FCoe destroy request $$KEEP_ENDIANNESS$$ |
524 | */ |
525 | struct fcoe_kwqe_destroy { |
526 | __le16 reserved0; |
527 | struct fcoe_kwqe_header hdr; |
528 | __le32 reserved1[7]; |
529 | }; |
530 | |
531 | /* |
532 | * FCoe statistics request $$KEEP_ENDIANNESS$$ |
533 | */ |
534 | struct fcoe_kwqe_stat { |
535 | __le16 reserved0; |
536 | struct fcoe_kwqe_header hdr; |
537 | __le32 stat_params_addr_lo; |
538 | __le32 stat_params_addr_hi; |
539 | __le32 reserved1[5]; |
540 | }; |
541 | |
542 | /* |
543 | * FCoE KWQ WQE $$KEEP_ENDIANNESS$$ |
544 | */ |
545 | union fcoe_kwqe { |
546 | struct fcoe_kwqe_init1 init1; |
547 | struct fcoe_kwqe_init2 init2; |
548 | struct fcoe_kwqe_init3 init3; |
549 | struct fcoe_kwqe_conn_offload1 conn_offload1; |
550 | struct fcoe_kwqe_conn_offload2 conn_offload2; |
551 | struct fcoe_kwqe_conn_offload3 conn_offload3; |
552 | struct fcoe_kwqe_conn_offload4 conn_offload4; |
553 | struct fcoe_kwqe_conn_enable_disable conn_enable_disable; |
554 | struct fcoe_kwqe_conn_destroy conn_destroy; |
555 | struct fcoe_kwqe_destroy destroy; |
556 | struct fcoe_kwqe_stat statistics; |
557 | }; |
558 | |
559 | |
560 | |
561 | |
562 | |
563 | |
564 | |
565 | |
566 | |
567 | |
568 | |
569 | |
570 | |
571 | |
572 | |
573 | |
574 | /* |
575 | * TX SGL context $$KEEP_ENDIANNESS$$ |
576 | */ |
577 | union fcoe_sgl_union_ctx { |
578 | struct fcoe_cached_sge_ctx cached_sge; |
579 | struct fcoe_ext_mul_sges_ctx sgl; |
580 | __le32 opaque[5]; |
581 | }; |
582 | |
583 | /* |
584 | * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$ |
585 | */ |
586 | struct fcoe_read_flow_info { |
587 | union fcoe_sgl_union_ctx sgl_ctx; |
588 | __le32 rsrv0[3]; |
589 | }; |
590 | |
591 | |
592 | /* |
593 | * Fcoe stat context $$KEEP_ENDIANNESS$$ |
594 | */ |
595 | struct fcoe_s_stat_ctx { |
596 | u8 flags; |
597 | #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0) |
598 | #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0 |
599 | #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1) |
600 | #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1 |
601 | #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2) |
602 | #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2 |
603 | #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3) |
604 | #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3 |
605 | #define FCOE_S_STAT_CTX_P_RJT (0x1<<4) |
606 | #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4 |
607 | #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5) |
608 | #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5 |
609 | #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6) |
610 | #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6 |
611 | }; |
612 | |
613 | /* |
614 | * Fcoe rx seq context $$KEEP_ENDIANNESS$$ |
615 | */ |
616 | struct fcoe_rx_seq_ctx { |
617 | u8 seq_id; |
618 | struct fcoe_s_stat_ctx s_stat; |
619 | __le16 seq_cnt; |
620 | __le32 low_exp_ro; |
621 | __le32 high_exp_ro; |
622 | }; |
623 | |
624 | |
625 | /* |
626 | * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$ |
627 | */ |
628 | union fcoe_rx_wr_union_ctx { |
629 | struct fcoe_read_flow_info read_info; |
630 | union fcoe_comp_flow_info comp_info; |
631 | __le32 opaque[8]; |
632 | }; |
633 | |
634 | |
635 | |
636 | /* |
637 | * FCoE SQ element $$KEEP_ENDIANNESS$$ |
638 | */ |
639 | struct fcoe_sqe { |
640 | __le16 wqe; |
641 | #define FCOE_SQE_TASK_ID (0x7FFF<<0) |
642 | #define FCOE_SQE_TASK_ID_SHIFT 0 |
643 | #define FCOE_SQE_TOGGLE_BIT (0x1<<15) |
644 | #define FCOE_SQE_TOGGLE_BIT_SHIFT 15 |
645 | }; |
646 | |
647 | |
648 | |
649 | /* |
650 | * 14 regs $$KEEP_ENDIANNESS$$ |
651 | */ |
652 | struct fcoe_tce_tx_only { |
653 | union fcoe_sgl_union_ctx sgl_ctx; |
654 | __le32 rsrv0; |
655 | }; |
656 | |
657 | /* |
658 | * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$ |
659 | */ |
660 | union fcoe_tx_wr_rx_rd_union_ctx { |
661 | struct fcoe_fc_frame tx_frame; |
662 | struct fcoe_fcp_cmd_payload fcp_cmd; |
663 | struct fcoe_ext_cleanup_info cleanup; |
664 | struct fcoe_ext_abts_info abts; |
665 | struct fcoe_ext_fw_tx_seq_ctx tx_seq; |
666 | __le32 opaque[8]; |
667 | }; |
668 | |
669 | /* |
670 | * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$ |
671 | */ |
672 | struct fcoe_tce_tx_wr_rx_rd_const { |
673 | u8 init_flags; |
674 | #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0) |
675 | #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0 |
676 | #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3) |
677 | #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3 |
678 | #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4) |
679 | #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4 |
680 | #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5) |
681 | #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5 |
682 | #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7) |
683 | #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7 |
684 | u8 tx_flags; |
685 | #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0) |
686 | #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0 |
687 | #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1) |
688 | #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1 |
689 | #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5) |
690 | #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5 |
691 | #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6) |
692 | #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6 |
693 | #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2 (0x1<<7) |
694 | #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2_SHIFT 7 |
695 | __le16 rsrv3; |
696 | __le32 verify_tx_seq; |
697 | }; |
698 | |
699 | /* |
700 | * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$ |
701 | */ |
702 | struct fcoe_tce_tx_wr_rx_rd { |
703 | union fcoe_tx_wr_rx_rd_union_ctx union_ctx; |
704 | struct fcoe_tce_tx_wr_rx_rd_const const_ctx; |
705 | }; |
706 | |
707 | /* |
708 | * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$ |
709 | */ |
710 | struct fcoe_tce_rx_wr_tx_rd_const { |
711 | __le32 data_2_trns; |
712 | __le32 init_flags; |
713 | #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0) |
714 | #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0 |
715 | #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24) |
716 | #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24 |
717 | }; |
718 | |
719 | /* |
720 | * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$ |
721 | */ |
722 | struct fcoe_tce_rx_wr_tx_rd_var { |
723 | __le16 rx_flags; |
724 | #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0) |
725 | #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0 |
726 | #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4) |
727 | #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4 |
728 | #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7) |
729 | #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7 |
730 | #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8) |
731 | #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8 |
732 | #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12) |
733 | #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12 |
734 | #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13) |
735 | #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13 |
736 | #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14) |
737 | #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14 |
738 | #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15) |
739 | #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15 |
740 | __le16 rx_id; |
741 | struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy; |
742 | }; |
743 | |
744 | /* |
745 | * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$ |
746 | */ |
747 | struct fcoe_tce_rx_wr_tx_rd { |
748 | struct fcoe_tce_rx_wr_tx_rd_const const_ctx; |
749 | struct fcoe_tce_rx_wr_tx_rd_var var_ctx; |
750 | }; |
751 | |
752 | /* |
753 | * tce_rx_only $$KEEP_ENDIANNESS$$ |
754 | */ |
755 | struct fcoe_tce_rx_only { |
756 | struct fcoe_rx_seq_ctx rx_seq_ctx; |
757 | union fcoe_rx_wr_union_ctx union_ctx; |
758 | }; |
759 | |
760 | /* |
761 | * task_ctx_entry $$KEEP_ENDIANNESS$$ |
762 | */ |
763 | struct fcoe_task_ctx_entry { |
764 | struct fcoe_tce_tx_only txwr_only; |
765 | struct fcoe_tce_tx_wr_rx_rd txwr_rxrd; |
766 | struct fcoe_tce_rx_wr_tx_rd rxwr_txrd; |
767 | struct fcoe_tce_rx_only rxwr_only; |
768 | }; |
769 | |
770 | |
771 | |
772 | |
773 | |
774 | |
775 | |
776 | |
777 | |
778 | |
779 | /* |
780 | * FCoE XFRQ element $$KEEP_ENDIANNESS$$ |
781 | */ |
782 | struct fcoe_xfrqe { |
783 | __le16 wqe; |
784 | #define FCOE_XFRQE_TASK_ID (0x7FFF<<0) |
785 | #define FCOE_XFRQE_TASK_ID_SHIFT 0 |
786 | #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15) |
787 | #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15 |
788 | }; |
789 | |
790 | |
791 | /* |
792 | * fcoe rx doorbell message sent to the chip $$KEEP_ENDIANNESS$$ |
793 | */ |
794 | struct b577xx_fcoe_rx_doorbell { |
795 | struct b577xx_doorbell_hdr hdr; |
796 | u8 params; |
797 | #define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM (0x1F<<0) |
798 | #define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM_SHIFT 0 |
799 | #define B577XX_FCOE_RX_DOORBELL_OPCODE (0x7<<5) |
800 | #define B577XX_FCOE_RX_DOORBELL_OPCODE_SHIFT 5 |
801 | __le16 doorbell_cq_cons; |
802 | }; |
803 | |
804 | |
805 | /* |
806 | * FCoE CONFQ element $$KEEP_ENDIANNESS$$ |
807 | */ |
808 | struct fcoe_confqe { |
809 | __le16 ox_id; |
810 | __le16 rx_id; |
811 | __le32 param; |
812 | }; |
813 | |
814 | |
815 | /* |
816 | * FCoE connection data base |
817 | */ |
818 | struct fcoe_conn_db { |
819 | #if defined(__BIG_ENDIAN) |
820 | u16 rsrv0; |
821 | u16 rq_prod; |
822 | #elif defined(__LITTLE_ENDIAN) |
823 | u16 rq_prod; |
824 | u16 rsrv0; |
825 | #endif |
826 | u32 rsrv1; |
827 | struct regpair cq_arm; |
828 | }; |
829 | |
830 | |
831 | /* |
832 | * FCoE CQ element $$KEEP_ENDIANNESS$$ |
833 | */ |
834 | struct fcoe_cqe { |
835 | __le16 wqe; |
836 | #define FCOE_CQE_CQE_INFO (0x3FFF<<0) |
837 | #define FCOE_CQE_CQE_INFO_SHIFT 0 |
838 | #define FCOE_CQE_CQE_TYPE (0x1<<14) |
839 | #define FCOE_CQE_CQE_TYPE_SHIFT 14 |
840 | #define FCOE_CQE_TOGGLE_BIT (0x1<<15) |
841 | #define FCOE_CQE_TOGGLE_BIT_SHIFT 15 |
842 | }; |
843 | |
844 | |
845 | /* |
846 | * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$ |
847 | */ |
848 | struct fcoe_partial_err_report_entry { |
849 | __le32 err_warn_bitmap_lo; |
850 | __le32 err_warn_bitmap_hi; |
851 | __le32 tx_buf_off; |
852 | __le32 rx_buf_off; |
853 | }; |
854 | |
855 | /* |
856 | * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$ |
857 | */ |
858 | struct fcoe_err_report_entry { |
859 | struct fcoe_partial_err_report_entry data; |
860 | struct fcoe_fc_hdr fc_hdr; |
861 | }; |
862 | |
863 | |
864 | /* |
865 | * FCoE hash table entry (32 bytes) $$KEEP_ENDIANNESS$$ |
866 | */ |
867 | struct fcoe_hash_table_entry { |
868 | u8 s_id_0; |
869 | u8 s_id_1; |
870 | u8 s_id_2; |
871 | u8 d_id_0; |
872 | u8 d_id_1; |
873 | u8 d_id_2; |
874 | __le16 dst_mac_addr_hi; |
875 | __le16 dst_mac_addr_mid; |
876 | __le16 dst_mac_addr_lo; |
877 | __le16 src_mac_addr_hi; |
878 | __le16 vlan_id; |
879 | __le16 src_mac_addr_lo; |
880 | __le16 src_mac_addr_mid; |
881 | u8 vlan_flag; |
882 | u8 reserved0; |
883 | __le16 reserved1; |
884 | __le32 reserved2; |
885 | __le32 field_id; |
886 | #define FCOE_HASH_TABLE_ENTRY_CID (0xFFFFFF<<0) |
887 | #define FCOE_HASH_TABLE_ENTRY_CID_SHIFT 0 |
888 | #define FCOE_HASH_TABLE_ENTRY_RESERVED3 (0x7F<<24) |
889 | #define FCOE_HASH_TABLE_ENTRY_RESERVED3_SHIFT 24 |
890 | #define FCOE_HASH_TABLE_ENTRY_VALID (0x1<<31) |
891 | #define FCOE_HASH_TABLE_ENTRY_VALID_SHIFT 31 |
892 | }; |
893 | |
894 | |
895 | /* |
896 | * FCoE LCQ element $$KEEP_ENDIANNESS$$ |
897 | */ |
898 | struct fcoe_lcqe { |
899 | __le32 wqe; |
900 | #define FCOE_LCQE_TASK_ID (0xFFFF<<0) |
901 | #define FCOE_LCQE_TASK_ID_SHIFT 0 |
902 | #define FCOE_LCQE_LCQE_TYPE (0xFF<<16) |
903 | #define FCOE_LCQE_LCQE_TYPE_SHIFT 16 |
904 | #define FCOE_LCQE_RESERVED (0xFF<<24) |
905 | #define FCOE_LCQE_RESERVED_SHIFT 24 |
906 | }; |
907 | |
908 | |
909 | |
910 | /* |
911 | * FCoE pending work request CQE $$KEEP_ENDIANNESS$$ |
912 | */ |
913 | struct fcoe_pend_wq_cqe { |
914 | __le16 wqe; |
915 | #define FCOE_PEND_WQ_CQE_TASK_ID (0x3FFF<<0) |
916 | #define FCOE_PEND_WQ_CQE_TASK_ID_SHIFT 0 |
917 | #define FCOE_PEND_WQ_CQE_CQE_TYPE (0x1<<14) |
918 | #define FCOE_PEND_WQ_CQE_CQE_TYPE_SHIFT 14 |
919 | #define FCOE_PEND_WQ_CQE_TOGGLE_BIT (0x1<<15) |
920 | #define FCOE_PEND_WQ_CQE_TOGGLE_BIT_SHIFT 15 |
921 | }; |
922 | |
923 | |
924 | /* |
925 | * FCoE RX statistics parameters section#0 $$KEEP_ENDIANNESS$$ |
926 | */ |
927 | struct fcoe_rx_stat_params_section0 { |
928 | __le32 fcoe_rx_pkt_cnt; |
929 | __le32 fcoe_rx_byte_cnt; |
930 | }; |
931 | |
932 | |
933 | /* |
934 | * FCoE RX statistics parameters section#1 $$KEEP_ENDIANNESS$$ |
935 | */ |
936 | struct fcoe_rx_stat_params_section1 { |
937 | __le32 fcoe_ver_cnt; |
938 | __le32 fcoe_rx_drop_pkt_cnt; |
939 | }; |
940 | |
941 | |
942 | /* |
943 | * FCoE RX statistics parameters section#2 $$KEEP_ENDIANNESS$$ |
944 | */ |
945 | struct fcoe_rx_stat_params_section2 { |
946 | __le32 fc_crc_cnt; |
947 | __le32 eofa_del_cnt; |
948 | __le32 miss_frame_cnt; |
949 | __le32 seq_timeout_cnt; |
950 | __le32 drop_seq_cnt; |
951 | __le32 fcoe_rx_drop_pkt_cnt; |
952 | __le32 fcp_rx_pkt_cnt; |
953 | __le32 reserved0; |
954 | }; |
955 | |
956 | |
957 | /* |
958 | * FCoE TX statistics parameters $$KEEP_ENDIANNESS$$ |
959 | */ |
960 | struct fcoe_tx_stat_params { |
961 | __le32 fcoe_tx_pkt_cnt; |
962 | __le32 fcoe_tx_byte_cnt; |
963 | __le32 fcp_tx_pkt_cnt; |
964 | __le32 reserved0; |
965 | }; |
966 | |
967 | /* |
968 | * FCoE statistics parameters $$KEEP_ENDIANNESS$$ |
969 | */ |
970 | struct fcoe_statistics_params { |
971 | struct fcoe_tx_stat_params tx_stat; |
972 | struct fcoe_rx_stat_params_section0 rx_stat0; |
973 | struct fcoe_rx_stat_params_section1 rx_stat1; |
974 | struct fcoe_rx_stat_params_section2 rx_stat2; |
975 | }; |
976 | |
977 | |
978 | /* |
979 | * FCoE t2 hash table entry (64 bytes) $$KEEP_ENDIANNESS$$ |
980 | */ |
981 | struct fcoe_t2_hash_table_entry { |
982 | struct fcoe_hash_table_entry data; |
983 | struct regpair next; |
984 | struct regpair reserved0[3]; |
985 | }; |
986 | |
987 | |
988 | |
989 | /* |
990 | * FCoE unsolicited CQE $$KEEP_ENDIANNESS$$ |
991 | */ |
992 | struct fcoe_unsolicited_cqe { |
993 | __le16 wqe; |
994 | #define FCOE_UNSOLICITED_CQE_SUBTYPE (0x3<<0) |
995 | #define FCOE_UNSOLICITED_CQE_SUBTYPE_SHIFT 0 |
996 | #define FCOE_UNSOLICITED_CQE_PKT_LEN (0xFFF<<2) |
997 | #define FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT 2 |
998 | #define FCOE_UNSOLICITED_CQE_CQE_TYPE (0x1<<14) |
999 | #define FCOE_UNSOLICITED_CQE_CQE_TYPE_SHIFT 14 |
1000 | #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT (0x1<<15) |
1001 | #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT_SHIFT 15 |
1002 | }; |
1003 | |
1004 | #endif /* __57XX_FCOE_HSI_LINUX_LE__ */ |
1005 | |