1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * pmcraid.h -- PMC Sierra MaxRAID controller driver header file |
4 | * |
5 | * Written By: Anil Ravindranath<anil_ravindranath@pmc-sierra.com> |
6 | * PMC-Sierra Inc |
7 | * |
8 | * Copyright (C) 2008, 2009 PMC Sierra Inc. |
9 | */ |
10 | |
11 | #ifndef _PMCRAID_H |
12 | #define _PMCRAID_H |
13 | |
14 | #include <linux/types.h> |
15 | #include <linux/completion.h> |
16 | #include <linux/list.h> |
17 | #include <scsi/scsi.h> |
18 | #include <scsi/scsi_cmnd.h> |
19 | #include <linux/cdev.h> |
20 | #include <net/netlink.h> |
21 | #include <net/genetlink.h> |
22 | #include <linux/connector.h> |
23 | /* |
24 | * Driver name : string representing the driver name |
25 | * Device file : /dev file to be used for management interfaces |
26 | * Driver version: version string in major_version.minor_version.patch format |
27 | * Driver date : date information in "Mon dd yyyy" format |
28 | */ |
29 | #define PMCRAID_DRIVER_NAME "PMC MaxRAID" |
30 | #define PMCRAID_DEVFILE "pmcsas" |
31 | #define PMCRAID_DRIVER_VERSION "1.0.3" |
32 | |
33 | #define PMCRAID_FW_VERSION_1 0x002 |
34 | |
35 | /* Maximum number of adapters supported by current version of the driver */ |
36 | #define PMCRAID_MAX_ADAPTERS 1024 |
37 | |
38 | /* Bit definitions as per firmware, bit position [0][1][2].....[31] */ |
39 | #define PMC_BIT8(n) (1 << (7-n)) |
40 | #define PMC_BIT16(n) (1 << (15-n)) |
41 | #define PMC_BIT32(n) (1 << (31-n)) |
42 | |
43 | /* PMC PCI vendor ID and device ID values */ |
44 | #define PCI_VENDOR_ID_PMC 0x11F8 |
45 | #define PCI_DEVICE_ID_PMC_MAXRAID 0x5220 |
46 | |
47 | /* |
48 | * MAX_CMD : maximum commands that can be outstanding with IOA |
49 | * MAX_IO_CMD : command blocks available for IO commands |
50 | * MAX_HCAM_CMD : command blocks available for HCAMS |
51 | * MAX_INTERNAL_CMD : command blocks available for internal commands like reset |
52 | */ |
53 | #define PMCRAID_MAX_CMD 1024 |
54 | #define PMCRAID_MAX_IO_CMD 1020 |
55 | #define PMCRAID_MAX_HCAM_CMD 2 |
56 | #define PMCRAID_MAX_INTERNAL_CMD 2 |
57 | |
58 | /* MAX_IOADLS : max number of scatter-gather lists supported by IOA |
59 | * IOADLS_INTERNAL : number of ioadls included as part of IOARCB. |
60 | * IOADLS_EXTERNAL : number of ioadls allocated external to IOARCB |
61 | */ |
62 | #define PMCRAID_IOADLS_INTERNAL 27 |
63 | #define PMCRAID_IOADLS_EXTERNAL 37 |
64 | #define PMCRAID_MAX_IOADLS PMCRAID_IOADLS_INTERNAL |
65 | |
66 | /* HRRQ_ENTRY_SIZE : size of hrrq buffer |
67 | * IOARCB_ALIGNMENT : alignment required for IOARCB |
68 | * IOADL_ALIGNMENT : alignment requirement for IOADLs |
69 | * MSIX_VECTORS : number of MSIX vectors supported |
70 | */ |
71 | #define HRRQ_ENTRY_SIZE sizeof(__le32) |
72 | #define PMCRAID_IOARCB_ALIGNMENT 32 |
73 | #define PMCRAID_IOADL_ALIGNMENT 16 |
74 | #define PMCRAID_IOASA_ALIGNMENT 4 |
75 | #define PMCRAID_NUM_MSIX_VECTORS 16 |
76 | |
77 | /* various other limits */ |
78 | #define PMCRAID_VENDOR_ID_LEN 8 |
79 | #define PMCRAID_PRODUCT_ID_LEN 16 |
80 | #define PMCRAID_SERIAL_NUM_LEN 8 |
81 | #define PMCRAID_LUN_LEN 8 |
82 | #define PMCRAID_MAX_CDB_LEN 16 |
83 | #define PMCRAID_DEVICE_ID_LEN 8 |
84 | #define PMCRAID_SENSE_DATA_LEN 256 |
85 | #define PMCRAID_ADD_CMD_PARAM_LEN 48 |
86 | |
87 | #define PMCRAID_MAX_BUS_TO_SCAN 1 |
88 | #define PMCRAID_MAX_NUM_TARGETS_PER_BUS 256 |
89 | #define PMCRAID_MAX_NUM_LUNS_PER_TARGET 8 |
90 | |
91 | /* IOA bus/target/lun number of IOA resources */ |
92 | #define PMCRAID_IOA_BUS_ID 0xfe |
93 | #define PMCRAID_IOA_TARGET_ID 0xff |
94 | #define PMCRAID_IOA_LUN_ID 0xff |
95 | #define PMCRAID_VSET_BUS_ID 0x1 |
96 | #define PMCRAID_VSET_LUN_ID 0x0 |
97 | #define PMCRAID_PHYS_BUS_ID 0x0 |
98 | #define PMCRAID_VIRTUAL_ENCL_BUS_ID 0x8 |
99 | #define PMCRAID_MAX_VSET_TARGETS 0x7F |
100 | #define PMCRAID_MAX_VSET_LUNS_PER_TARGET 8 |
101 | |
102 | #define PMCRAID_IOA_MAX_SECTORS 32767 |
103 | #define PMCRAID_VSET_MAX_SECTORS 512 |
104 | #define PMCRAID_MAX_CMD_PER_LUN 254 |
105 | |
106 | /* Number of configuration table entries (resources), includes 1 FP, |
107 | * 1 Enclosure device |
108 | */ |
109 | #define PMCRAID_MAX_RESOURCES 256 |
110 | |
111 | /* Adapter Commands used by driver */ |
112 | #define PMCRAID_QUERY_RESOURCE_STATE 0xC2 |
113 | #define PMCRAID_RESET_DEVICE 0xC3 |
114 | /* options to select reset target */ |
115 | #define ENABLE_RESET_MODIFIER 0x80 |
116 | #define RESET_DEVICE_LUN 0x40 |
117 | #define RESET_DEVICE_TARGET 0x20 |
118 | #define RESET_DEVICE_BUS 0x10 |
119 | |
120 | #define PMCRAID_IDENTIFY_HRRQ 0xC4 |
121 | #define PMCRAID_QUERY_IOA_CONFIG 0xC5 |
122 | #define PMCRAID_QUERY_CMD_STATUS 0xCB |
123 | #define PMCRAID_ABORT_CMD 0xC7 |
124 | |
125 | /* CANCEL ALL command, provides option for setting SYNC_COMPLETE |
126 | * on the target resources for which commands got cancelled |
127 | */ |
128 | #define PMCRAID_CANCEL_ALL_REQUESTS 0xCE |
129 | #define PMCRAID_SYNC_COMPLETE_AFTER_CANCEL PMC_BIT8(0) |
130 | |
131 | /* HCAM command and types of HCAM supported by IOA */ |
132 | #define PMCRAID_HOST_CONTROLLED_ASYNC 0xCF |
133 | #define PMCRAID_HCAM_CODE_CONFIG_CHANGE 0x01 |
134 | #define PMCRAID_HCAM_CODE_LOG_DATA 0x02 |
135 | |
136 | /* IOA shutdown command and various shutdown types */ |
137 | #define PMCRAID_IOA_SHUTDOWN 0xF7 |
138 | #define PMCRAID_SHUTDOWN_NORMAL 0x00 |
139 | #define PMCRAID_SHUTDOWN_PREPARE_FOR_NORMAL 0x40 |
140 | #define PMCRAID_SHUTDOWN_NONE 0x100 |
141 | #define PMCRAID_SHUTDOWN_ABBREV 0x80 |
142 | |
143 | /* SET SUPPORTED DEVICES command and the option to select all the |
144 | * devices to be supported |
145 | */ |
146 | #define PMCRAID_SET_SUPPORTED_DEVICES 0xFB |
147 | #define ALL_DEVICES_SUPPORTED PMC_BIT8(0) |
148 | |
149 | /* This option is used with SCSI WRITE_BUFFER command */ |
150 | #define PMCRAID_WR_BUF_DOWNLOAD_AND_SAVE 0x05 |
151 | |
152 | /* IOASC Codes used by driver */ |
153 | #define PMCRAID_IOASC_SENSE_MASK 0xFFFFFF00 |
154 | #define PMCRAID_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) |
155 | #define PMCRAID_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) |
156 | #define PMCRAID_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) |
157 | #define PMCRAID_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) |
158 | |
159 | #define PMCRAID_IOASC_GOOD_COMPLETION 0x00000000 |
160 | #define PMCRAID_IOASC_GC_IOARCB_NOTFOUND 0x005A0000 |
161 | #define PMCRAID_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 |
162 | #define PMCRAID_IOASC_NR_IOA_RESET_REQUIRED 0x02048000 |
163 | #define PMCRAID_IOASC_NR_SYNC_REQUIRED 0x023F0000 |
164 | #define PMCRAID_IOASC_ME_READ_ERROR_NO_REALLOC 0x03110C00 |
165 | #define PMCRAID_IOASC_HW_CANNOT_COMMUNICATE 0x04050000 |
166 | #define PMCRAID_IOASC_HW_DEVICE_TIMEOUT 0x04080100 |
167 | #define PMCRAID_IOASC_HW_DEVICE_BUS_STATUS_ERROR 0x04448500 |
168 | #define PMCRAID_IOASC_HW_IOA_RESET_REQUIRED 0x04448600 |
169 | #define PMCRAID_IOASC_IR_INVALID_RESOURCE_HANDLE 0x05250000 |
170 | #define PMCRAID_IOASC_AC_TERMINATED_BY_HOST 0x0B5A0000 |
171 | #define PMCRAID_IOASC_UA_BUS_WAS_RESET 0x06290000 |
172 | #define PMCRAID_IOASC_TIME_STAMP_OUT_OF_SYNC 0x06908B00 |
173 | #define PMCRAID_IOASC_UA_BUS_WAS_RESET_BY_OTHER 0x06298000 |
174 | |
175 | /* Driver defined IOASCs */ |
176 | #define PMCRAID_IOASC_IOA_WAS_RESET 0x10000001 |
177 | #define PMCRAID_IOASC_PCI_ACCESS_ERROR 0x10000002 |
178 | |
179 | /* Various timeout values (in milliseconds) used. If any of these are chip |
180 | * specific, move them to pmcraid_chip_details structure. |
181 | */ |
182 | #define PMCRAID_PCI_DEASSERT_TIMEOUT 2000 |
183 | #define PMCRAID_BIST_TIMEOUT 2000 |
184 | #define PMCRAID_AENWAIT_TIMEOUT 5000 |
185 | #define PMCRAID_TRANSOP_TIMEOUT 60000 |
186 | |
187 | #define PMCRAID_RESET_TIMEOUT (2 * HZ) |
188 | #define PMCRAID_CHECK_FOR_RESET_TIMEOUT ((HZ / 10)) |
189 | #define PMCRAID_VSET_IO_TIMEOUT (60 * HZ) |
190 | #define PMCRAID_INTERNAL_TIMEOUT (60 * HZ) |
191 | #define PMCRAID_SHUTDOWN_TIMEOUT (150 * HZ) |
192 | #define PMCRAID_RESET_BUS_TIMEOUT (60 * HZ) |
193 | #define PMCRAID_RESET_HOST_TIMEOUT (150 * HZ) |
194 | #define PMCRAID_REQUEST_SENSE_TIMEOUT (30 * HZ) |
195 | #define PMCRAID_SET_SUP_DEV_TIMEOUT (2 * 60 * HZ) |
196 | |
197 | /* structure to represent a scatter-gather element (IOADL descriptor) */ |
198 | struct pmcraid_ioadl_desc { |
199 | __le64 address; |
200 | __le32 data_len; |
201 | __u8 reserved[3]; |
202 | __u8 flags; |
203 | } __attribute__((packed, aligned(PMCRAID_IOADL_ALIGNMENT))); |
204 | |
205 | /* pmcraid_ioadl_desc.flags values */ |
206 | #define IOADL_FLAGS_CHAINED PMC_BIT8(0) |
207 | #define IOADL_FLAGS_LAST_DESC PMC_BIT8(1) |
208 | #define IOADL_FLAGS_READ_LAST PMC_BIT8(1) |
209 | #define IOADL_FLAGS_WRITE_LAST PMC_BIT8(1) |
210 | |
211 | |
212 | /* additional IOARCB data which can be CDB or additional request parameters |
213 | * or list of IOADLs. Firmware supports max of 512 bytes for IOARCB, hence then |
214 | * number of IOADLs are limted to 27. In case they are more than 27, they will |
215 | * be used in chained form |
216 | */ |
217 | struct pmcraid_ioarcb_add_data { |
218 | union { |
219 | struct pmcraid_ioadl_desc ioadl[PMCRAID_IOADLS_INTERNAL]; |
220 | __u8 add_cmd_params[PMCRAID_ADD_CMD_PARAM_LEN]; |
221 | } u; |
222 | }; |
223 | |
224 | /* |
225 | * IOA Request Control Block |
226 | */ |
227 | struct pmcraid_ioarcb { |
228 | __le64 ioarcb_bus_addr; |
229 | __le32 resource_handle; |
230 | __le32 response_handle; |
231 | __le64 ioadl_bus_addr; |
232 | __le32 ioadl_length; |
233 | __le32 data_transfer_length; |
234 | __le64 ioasa_bus_addr; |
235 | __le16 ioasa_len; |
236 | __le16 cmd_timeout; |
237 | __le16 add_cmd_param_offset; |
238 | __le16 add_cmd_param_length; |
239 | __le32 reserved1[2]; |
240 | __le32 reserved2; |
241 | __u8 request_type; |
242 | __u8 request_flags0; |
243 | __u8 request_flags1; |
244 | __u8 hrrq_id; |
245 | __u8 cdb[PMCRAID_MAX_CDB_LEN]; |
246 | struct pmcraid_ioarcb_add_data add_data; |
247 | }; |
248 | |
249 | /* well known resource handle values */ |
250 | #define PMCRAID_IOA_RES_HANDLE 0xffffffff |
251 | #define PMCRAID_INVALID_RES_HANDLE 0 |
252 | |
253 | /* pmcraid_ioarcb.request_type values */ |
254 | #define REQ_TYPE_SCSI 0x00 |
255 | #define REQ_TYPE_IOACMD 0x01 |
256 | #define REQ_TYPE_HCAM 0x02 |
257 | |
258 | /* pmcraid_ioarcb.flags0 values */ |
259 | #define TRANSFER_DIR_WRITE PMC_BIT8(0) |
260 | #define INHIBIT_UL_CHECK PMC_BIT8(2) |
261 | #define SYNC_OVERRIDE PMC_BIT8(3) |
262 | #define SYNC_COMPLETE PMC_BIT8(4) |
263 | #define NO_LINK_DESCS PMC_BIT8(5) |
264 | |
265 | /* pmcraid_ioarcb.flags1 values */ |
266 | #define DELAY_AFTER_RESET PMC_BIT8(0) |
267 | #define TASK_TAG_SIMPLE 0x10 |
268 | #define TASK_TAG_ORDERED 0x20 |
269 | #define TASK_TAG_QUEUE_HEAD 0x30 |
270 | |
271 | /* toggle bit offset in response handle */ |
272 | #define HRRQ_TOGGLE_BIT 0x01 |
273 | #define HRRQ_RESPONSE_BIT 0x02 |
274 | |
275 | /* IOA Status Area */ |
276 | struct pmcraid_ioasa_vset { |
277 | __le32 failing_lba_hi; |
278 | __le32 failing_lba_lo; |
279 | __le32 reserved; |
280 | } __attribute__((packed, aligned(4))); |
281 | |
282 | struct pmcraid_ioasa { |
283 | __le32 ioasc; |
284 | __le16 returned_status_length; |
285 | __le16 available_status_length; |
286 | __le32 residual_data_length; |
287 | __le32 ilid; |
288 | __le32 fd_ioasc; |
289 | __le32 fd_res_address; |
290 | __le32 fd_res_handle; |
291 | __le32 reserved; |
292 | |
293 | /* resource specific sense information */ |
294 | union { |
295 | struct pmcraid_ioasa_vset vset; |
296 | } u; |
297 | |
298 | /* IOA autosense data */ |
299 | __le16 auto_sense_length; |
300 | __le16 error_data_length; |
301 | __u8 sense_data[PMCRAID_SENSE_DATA_LEN]; |
302 | } __attribute__((packed, aligned(4))); |
303 | |
304 | #define PMCRAID_DRIVER_ILID 0xffffffff |
305 | |
306 | /* Config Table Entry per Resource */ |
307 | struct pmcraid_config_table_entry { |
308 | __u8 resource_type; |
309 | __u8 bus_protocol; |
310 | __le16 array_id; |
311 | __u8 common_flags0; |
312 | __u8 common_flags1; |
313 | __u8 unique_flags0; |
314 | __u8 unique_flags1; /*also used as vset target_id */ |
315 | __le32 resource_handle; |
316 | __le32 resource_address; |
317 | __u8 device_id[PMCRAID_DEVICE_ID_LEN]; |
318 | __u8 lun[PMCRAID_LUN_LEN]; |
319 | } __attribute__((packed, aligned(4))); |
320 | |
321 | /* extended configuration table sizes are also of 32 bytes in size */ |
322 | struct pmcraid_config_table_entry_ext { |
323 | struct pmcraid_config_table_entry cfgte; |
324 | }; |
325 | |
326 | /* resource types (config_table_entry.resource_type values) */ |
327 | #define RES_TYPE_AF_DASD 0x00 |
328 | #define RES_TYPE_GSCSI 0x01 |
329 | #define RES_TYPE_VSET 0x02 |
330 | #define RES_TYPE_IOA_FP 0xFF |
331 | |
332 | #define RES_IS_IOA(res) ((res).resource_type == RES_TYPE_IOA_FP) |
333 | #define RES_IS_GSCSI(res) ((res).resource_type == RES_TYPE_GSCSI) |
334 | #define RES_IS_VSET(res) ((res).resource_type == RES_TYPE_VSET) |
335 | #define RES_IS_AFDASD(res) ((res).resource_type == RES_TYPE_AF_DASD) |
336 | |
337 | /* bus_protocol values used by driver */ |
338 | #define RES_TYPE_VENCLOSURE 0x8 |
339 | |
340 | /* config_table_entry.common_flags0 */ |
341 | #define MULTIPATH_RESOURCE PMC_BIT32(0) |
342 | |
343 | /* unique_flags1 */ |
344 | #define IMPORT_MODE_MANUAL PMC_BIT8(0) |
345 | |
346 | /* well known resource handle values */ |
347 | #define RES_HANDLE_IOA 0xFFFFFFFF |
348 | #define RES_HANDLE_NONE 0x00000000 |
349 | |
350 | /* well known resource address values */ |
351 | #define RES_ADDRESS_IOAFP 0xFEFFFFFF |
352 | #define RES_ADDRESS_INVALID 0xFFFFFFFF |
353 | |
354 | /* BUS/TARGET/LUN values from resource_addrr */ |
355 | #define RES_BUS(res_addr) (le32_to_cpu(res_addr) & 0xFF) |
356 | #define RES_TARGET(res_addr) ((le32_to_cpu(res_addr) >> 16) & 0xFF) |
357 | #define RES_LUN(res_addr) 0x0 |
358 | |
359 | /* configuration table structure */ |
360 | struct pmcraid_config_table { |
361 | __le16 num_entries; |
362 | __u8 table_format; |
363 | __u8 reserved1; |
364 | __u8 flags; |
365 | __u8 reserved2[11]; |
366 | union { |
367 | struct pmcraid_config_table_entry |
368 | entries[PMCRAID_MAX_RESOURCES]; |
369 | struct pmcraid_config_table_entry_ext |
370 | entries_ext[PMCRAID_MAX_RESOURCES]; |
371 | }; |
372 | } __attribute__((packed, aligned(4))); |
373 | |
374 | /* config_table.flags value */ |
375 | #define MICROCODE_UPDATE_REQUIRED PMC_BIT32(0) |
376 | |
377 | /* |
378 | * HCAM format |
379 | */ |
380 | #define PMCRAID_HOSTRCB_LDNSIZE 4056 |
381 | |
382 | /* Error log notification format */ |
383 | struct pmcraid_hostrcb_error { |
384 | __le32 fd_ioasc; |
385 | __le32 fd_ra; |
386 | __le32 fd_rh; |
387 | __le32 prc; |
388 | union { |
389 | __u8 data[PMCRAID_HOSTRCB_LDNSIZE]; |
390 | } u; |
391 | } __attribute__ ((packed, aligned(4))); |
392 | |
393 | struct pmcraid_hcam_hdr { |
394 | __u8 op_code; |
395 | __u8 notification_type; |
396 | __u8 notification_lost; |
397 | __u8 flags; |
398 | __u8 overlay_id; |
399 | __u8 reserved1[3]; |
400 | __le32 ilid; |
401 | __le32 timestamp1; |
402 | __le32 timestamp2; |
403 | __le32 data_len; |
404 | } __attribute__((packed, aligned(4))); |
405 | |
406 | #define PMCRAID_AEN_GROUP 0x3 |
407 | |
408 | struct pmcraid_hcam_ccn { |
409 | struct pmcraid_hcam_hdr ; |
410 | struct pmcraid_config_table_entry cfg_entry; |
411 | struct pmcraid_config_table_entry cfg_entry_old; |
412 | } __attribute__((packed, aligned(4))); |
413 | |
414 | #define PMCRAID_CCN_EXT_SIZE 3944 |
415 | struct pmcraid_hcam_ccn_ext { |
416 | struct pmcraid_hcam_hdr ; |
417 | struct pmcraid_config_table_entry_ext cfg_entry; |
418 | struct pmcraid_config_table_entry_ext cfg_entry_old; |
419 | __u8 reserved[PMCRAID_CCN_EXT_SIZE]; |
420 | } __attribute__((packed, aligned(4))); |
421 | |
422 | struct pmcraid_hcam_ldn { |
423 | struct pmcraid_hcam_hdr ; |
424 | struct pmcraid_hostrcb_error error_log; |
425 | } __attribute__((packed, aligned(4))); |
426 | |
427 | /* pmcraid_hcam.op_code values */ |
428 | #define HOSTRCB_TYPE_CCN 0xE1 |
429 | #define HOSTRCB_TYPE_LDN 0xE2 |
430 | |
431 | /* pmcraid_hcam.notification_type values */ |
432 | #define NOTIFICATION_TYPE_ENTRY_CHANGED 0x0 |
433 | #define NOTIFICATION_TYPE_ENTRY_NEW 0x1 |
434 | #define NOTIFICATION_TYPE_ENTRY_DELETED 0x2 |
435 | #define NOTIFICATION_TYPE_STATE_CHANGE 0x3 |
436 | #define NOTIFICATION_TYPE_ENTRY_STATECHANGED 0x4 |
437 | #define NOTIFICATION_TYPE_ERROR_LOG 0x10 |
438 | #define NOTIFICATION_TYPE_INFORMATION_LOG 0x11 |
439 | |
440 | #define HOSTRCB_NOTIFICATIONS_LOST PMC_BIT8(0) |
441 | |
442 | /* pmcraid_hcam.flags values */ |
443 | #define HOSTRCB_INTERNAL_OP_ERROR PMC_BIT8(0) |
444 | #define HOSTRCB_ERROR_RESPONSE_SENT PMC_BIT8(1) |
445 | |
446 | /* pmcraid_hcam.overlay_id values */ |
447 | #define HOSTRCB_OVERLAY_ID_08 0x08 |
448 | #define HOSTRCB_OVERLAY_ID_09 0x09 |
449 | #define HOSTRCB_OVERLAY_ID_11 0x11 |
450 | #define HOSTRCB_OVERLAY_ID_12 0x12 |
451 | #define HOSTRCB_OVERLAY_ID_13 0x13 |
452 | #define HOSTRCB_OVERLAY_ID_14 0x14 |
453 | #define HOSTRCB_OVERLAY_ID_16 0x16 |
454 | #define HOSTRCB_OVERLAY_ID_17 0x17 |
455 | #define HOSTRCB_OVERLAY_ID_20 0x20 |
456 | #define HOSTRCB_OVERLAY_ID_FF 0xFF |
457 | |
458 | /* Implementation specific card details */ |
459 | struct pmcraid_chip_details { |
460 | /* hardware register offsets */ |
461 | unsigned long ioastatus; |
462 | unsigned long ioarrin; |
463 | unsigned long mailbox; |
464 | unsigned long global_intr_mask; |
465 | unsigned long ioa_host_intr; |
466 | unsigned long ioa_host_msix_intr; |
467 | unsigned long ioa_host_intr_clr; |
468 | unsigned long ioa_host_mask; |
469 | unsigned long ioa_host_mask_clr; |
470 | unsigned long host_ioa_intr; |
471 | unsigned long host_ioa_intr_clr; |
472 | |
473 | /* timeout used during transitional to operational state */ |
474 | unsigned long transop_timeout; |
475 | }; |
476 | |
477 | /* IOA to HOST doorbells (interrupts) */ |
478 | #define INTRS_TRANSITION_TO_OPERATIONAL PMC_BIT32(0) |
479 | #define INTRS_IOARCB_TRANSFER_FAILED PMC_BIT32(3) |
480 | #define INTRS_IOA_UNIT_CHECK PMC_BIT32(4) |
481 | #define INTRS_NO_HRRQ_FOR_CMD_RESPONSE PMC_BIT32(5) |
482 | #define INTRS_CRITICAL_OP_IN_PROGRESS PMC_BIT32(6) |
483 | #define INTRS_IO_DEBUG_ACK PMC_BIT32(7) |
484 | #define INTRS_IOARRIN_LOST PMC_BIT32(27) |
485 | #define INTRS_SYSTEM_BUS_MMIO_ERROR PMC_BIT32(28) |
486 | #define INTRS_IOA_PROCESSOR_ERROR PMC_BIT32(29) |
487 | #define INTRS_HRRQ_VALID PMC_BIT32(30) |
488 | #define INTRS_OPERATIONAL_STATUS PMC_BIT32(0) |
489 | #define INTRS_ALLOW_MSIX_VECTOR0 PMC_BIT32(31) |
490 | |
491 | /* Host to IOA Doorbells */ |
492 | #define DOORBELL_RUNTIME_RESET PMC_BIT32(1) |
493 | #define DOORBELL_IOA_RESET_ALERT PMC_BIT32(7) |
494 | #define DOORBELL_IOA_DEBUG_ALERT PMC_BIT32(9) |
495 | #define DOORBELL_ENABLE_DESTRUCTIVE_DIAGS PMC_BIT32(8) |
496 | #define DOORBELL_IOA_START_BIST PMC_BIT32(23) |
497 | #define DOORBELL_INTR_MODE_MSIX PMC_BIT32(25) |
498 | #define DOORBELL_INTR_MSIX_CLR PMC_BIT32(26) |
499 | #define DOORBELL_RESET_IOA PMC_BIT32(31) |
500 | |
501 | /* Global interrupt mask register value */ |
502 | #define GLOBAL_INTERRUPT_MASK 0x5ULL |
503 | |
504 | #define PMCRAID_ERROR_INTERRUPTS (INTRS_IOARCB_TRANSFER_FAILED | \ |
505 | INTRS_IOA_UNIT_CHECK | \ |
506 | INTRS_NO_HRRQ_FOR_CMD_RESPONSE | \ |
507 | INTRS_IOARRIN_LOST | \ |
508 | INTRS_SYSTEM_BUS_MMIO_ERROR | \ |
509 | INTRS_IOA_PROCESSOR_ERROR) |
510 | |
511 | #define PMCRAID_PCI_INTERRUPTS (PMCRAID_ERROR_INTERRUPTS | \ |
512 | INTRS_HRRQ_VALID | \ |
513 | INTRS_TRANSITION_TO_OPERATIONAL |\ |
514 | INTRS_ALLOW_MSIX_VECTOR0) |
515 | |
516 | /* control_block, associated with each of the commands contains IOARCB, IOADLs |
517 | * memory for IOASA. Additional 3 * 16 bytes are allocated in order to support |
518 | * additional request parameters (of max size 48) any command. |
519 | */ |
520 | struct pmcraid_control_block { |
521 | struct pmcraid_ioarcb ioarcb; |
522 | struct pmcraid_ioadl_desc ioadl[PMCRAID_IOADLS_EXTERNAL + 3]; |
523 | struct pmcraid_ioasa ioasa; |
524 | } __attribute__ ((packed, aligned(PMCRAID_IOARCB_ALIGNMENT))); |
525 | |
526 | /* pmcraid_sglist - Scatter-gather list allocated for passthrough ioctls |
527 | */ |
528 | struct pmcraid_sglist { |
529 | u32 order; |
530 | u32 num_sg; |
531 | u32 num_dma_sg; |
532 | struct scatterlist *scatterlist; |
533 | }; |
534 | |
535 | /* page D0 inquiry data of focal point resource */ |
536 | struct pmcraid_inquiry_data { |
537 | __u8 ph_dev_type; |
538 | __u8 page_code; |
539 | __u8 reserved1; |
540 | __u8 add_page_len; |
541 | __u8 length; |
542 | __u8 reserved2; |
543 | __be16 fw_version; |
544 | __u8 reserved3[16]; |
545 | }; |
546 | |
547 | #define PMCRAID_TIMESTAMP_LEN 12 |
548 | #define PMCRAID_REQ_TM_STR_LEN 6 |
549 | #define PMCRAID_SCSI_SET_TIMESTAMP 0xA4 |
550 | #define PMCRAID_SCSI_SERVICE_ACTION 0x0F |
551 | |
552 | struct pmcraid_timestamp_data { |
553 | __u8 reserved1[4]; |
554 | __u8 timestamp[PMCRAID_REQ_TM_STR_LEN]; /* current time value */ |
555 | __u8 reserved2[2]; |
556 | }; |
557 | |
558 | /* pmcraid_cmd - LLD representation of SCSI command */ |
559 | struct pmcraid_cmd { |
560 | |
561 | /* Ptr and bus address of DMA.able control block for this command */ |
562 | struct pmcraid_control_block *ioa_cb; |
563 | dma_addr_t ioa_cb_bus_addr; |
564 | dma_addr_t dma_handle; |
565 | |
566 | /* pointer to mid layer structure of SCSI commands */ |
567 | struct scsi_cmnd *scsi_cmd; |
568 | |
569 | struct list_head free_list; |
570 | struct completion wait_for_completion; |
571 | struct timer_list timer; /* needed for internal commands */ |
572 | u32 timeout; /* current timeout value */ |
573 | u32 index; /* index into the command list */ |
574 | u8 completion_req; /* for handling internal commands */ |
575 | u8 release; /* for handling completions */ |
576 | |
577 | void (*cmd_done) (struct pmcraid_cmd *); |
578 | struct pmcraid_instance *drv_inst; |
579 | |
580 | struct pmcraid_sglist *sglist; /* used for passthrough IOCTLs */ |
581 | |
582 | /* scratch used */ |
583 | union { |
584 | /* during reset sequence */ |
585 | unsigned long time_left; |
586 | struct pmcraid_resource_entry *res; |
587 | int hrrq_index; |
588 | |
589 | /* used during IO command error handling. Sense buffer |
590 | * for REQUEST SENSE command if firmware is not sending |
591 | * auto sense data |
592 | */ |
593 | struct { |
594 | u8 *sense_buffer; |
595 | dma_addr_t sense_buffer_dma; |
596 | }; |
597 | }; |
598 | }; |
599 | |
600 | /* |
601 | * Interrupt registers of IOA |
602 | */ |
603 | struct pmcraid_interrupts { |
604 | void __iomem *ioa_host_interrupt_reg; |
605 | void __iomem *ioa_host_msix_interrupt_reg; |
606 | void __iomem *ioa_host_interrupt_clr_reg; |
607 | void __iomem *ioa_host_interrupt_mask_reg; |
608 | void __iomem *ioa_host_interrupt_mask_clr_reg; |
609 | void __iomem *global_interrupt_mask_reg; |
610 | void __iomem *host_ioa_interrupt_reg; |
611 | void __iomem *host_ioa_interrupt_clr_reg; |
612 | }; |
613 | |
614 | /* ISR parameters LLD allocates (one for each MSI-X if enabled) vectors */ |
615 | struct pmcraid_isr_param { |
616 | struct pmcraid_instance *drv_inst; |
617 | u8 hrrq_id; /* hrrq entry index */ |
618 | }; |
619 | |
620 | |
621 | /* AEN message header sent as part of event data to applications */ |
622 | struct pmcraid_aen_msg { |
623 | u32 hostno; |
624 | u32 length; |
625 | u8 reserved[8]; |
626 | u8 data[]; |
627 | }; |
628 | |
629 | /* Controller state event message type */ |
630 | struct pmcraid_state_msg { |
631 | struct pmcraid_aen_msg msg; |
632 | u32 ioa_state; |
633 | }; |
634 | |
635 | #define PMC_DEVICE_EVENT_RESET_START 0x11000000 |
636 | #define PMC_DEVICE_EVENT_RESET_SUCCESS 0x11000001 |
637 | #define PMC_DEVICE_EVENT_RESET_FAILED 0x11000002 |
638 | #define PMC_DEVICE_EVENT_SHUTDOWN_START 0x11000003 |
639 | #define PMC_DEVICE_EVENT_SHUTDOWN_SUCCESS 0x11000004 |
640 | #define PMC_DEVICE_EVENT_SHUTDOWN_FAILED 0x11000005 |
641 | |
642 | struct pmcraid_hostrcb { |
643 | struct pmcraid_instance *drv_inst; |
644 | struct pmcraid_aen_msg *msg; |
645 | struct pmcraid_hcam_hdr *hcam; /* pointer to hcam buffer */ |
646 | struct pmcraid_cmd *cmd; /* pointer to command block used */ |
647 | dma_addr_t baddr; /* system address of hcam buffer */ |
648 | atomic_t ignore; /* process HCAM response ? */ |
649 | }; |
650 | |
651 | #define PMCRAID_AEN_HDR_SIZE sizeof(struct pmcraid_aen_msg) |
652 | |
653 | |
654 | |
655 | /* |
656 | * Per adapter structure maintained by LLD |
657 | */ |
658 | struct pmcraid_instance { |
659 | /* Array of allowed-to-be-exposed resources, initialized from |
660 | * Configutation Table, later updated with CCNs |
661 | */ |
662 | struct pmcraid_resource_entry *res_entries; |
663 | |
664 | struct list_head free_res_q; /* res_entries lists for easy lookup */ |
665 | struct list_head used_res_q; /* List of to be exposed resources */ |
666 | spinlock_t resource_lock; /* spinlock to protect resource list */ |
667 | |
668 | void __iomem *mapped_dma_addr; |
669 | void __iomem *ioa_status; /* Iomapped IOA status register */ |
670 | void __iomem *mailbox; /* Iomapped mailbox register */ |
671 | void __iomem *ioarrin; /* IOmapped IOARR IN register */ |
672 | |
673 | struct pmcraid_interrupts int_regs; |
674 | struct pmcraid_chip_details *chip_cfg; |
675 | |
676 | /* HostRCBs needed for HCAM */ |
677 | struct pmcraid_hostrcb ldn; |
678 | struct pmcraid_hostrcb ccn; |
679 | struct pmcraid_state_msg scn; /* controller state change msg */ |
680 | |
681 | |
682 | /* Bus address of start of HRRQ */ |
683 | dma_addr_t hrrq_start_bus_addr[PMCRAID_NUM_MSIX_VECTORS]; |
684 | |
685 | /* Pointer to 1st entry of HRRQ */ |
686 | __le32 *hrrq_start[PMCRAID_NUM_MSIX_VECTORS]; |
687 | |
688 | /* Pointer to last entry of HRRQ */ |
689 | __le32 *hrrq_end[PMCRAID_NUM_MSIX_VECTORS]; |
690 | |
691 | /* Pointer to current pointer of hrrq */ |
692 | __le32 *hrrq_curr[PMCRAID_NUM_MSIX_VECTORS]; |
693 | |
694 | /* Lock for HRRQ access */ |
695 | spinlock_t hrrq_lock[PMCRAID_NUM_MSIX_VECTORS]; |
696 | |
697 | struct pmcraid_inquiry_data *inq_data; |
698 | dma_addr_t inq_data_baddr; |
699 | |
700 | struct pmcraid_timestamp_data *timestamp_data; |
701 | dma_addr_t timestamp_data_baddr; |
702 | |
703 | /* size of configuration table entry, varies based on the firmware */ |
704 | u32 config_table_entry_size; |
705 | |
706 | /* Expected toggle bit at host */ |
707 | u8 host_toggle_bit[PMCRAID_NUM_MSIX_VECTORS]; |
708 | |
709 | |
710 | /* Wait Q for threads to wait for Reset IOA completion */ |
711 | wait_queue_head_t reset_wait_q; |
712 | struct pmcraid_cmd *reset_cmd; |
713 | |
714 | /* structures for supporting SIGIO based AEN. */ |
715 | struct fasync_struct *aen_queue; |
716 | struct mutex aen_queue_lock; /* lock for aen subscribers list */ |
717 | struct cdev cdev; |
718 | |
719 | struct Scsi_Host *host; /* mid layer interface structure handle */ |
720 | struct pci_dev *pdev; /* PCI device structure handle */ |
721 | |
722 | /* No of Reset IOA retries . IOA marked dead if threshold exceeds */ |
723 | u8 ioa_reset_attempts; |
724 | #define PMCRAID_RESET_ATTEMPTS 3 |
725 | |
726 | u8 current_log_level; /* default level for logging IOASC errors */ |
727 | |
728 | u8 num_hrrq; /* Number of interrupt vectors allocated */ |
729 | u8 interrupt_mode; /* current interrupt mode legacy or msix */ |
730 | dev_t dev; /* Major-Minor numbers for Char device */ |
731 | |
732 | /* Used as ISR handler argument */ |
733 | struct pmcraid_isr_param hrrq_vector[PMCRAID_NUM_MSIX_VECTORS]; |
734 | |
735 | /* Message id as filled in last fired IOARCB, used to identify HRRQ */ |
736 | atomic_t last_message_id; |
737 | |
738 | /* configuration table */ |
739 | struct pmcraid_config_table *cfg_table; |
740 | dma_addr_t cfg_table_bus_addr; |
741 | |
742 | /* structures related to command blocks */ |
743 | struct kmem_cache *cmd_cachep; /* cache for cmd blocks */ |
744 | struct dma_pool *control_pool; /* pool for control blocks */ |
745 | char cmd_pool_name[64]; /* name of cmd cache */ |
746 | char ctl_pool_name[64]; /* name of control cache */ |
747 | |
748 | struct pmcraid_cmd *cmd_list[PMCRAID_MAX_CMD]; |
749 | |
750 | struct list_head free_cmd_pool; |
751 | struct list_head pending_cmd_pool; |
752 | spinlock_t free_pool_lock; /* free pool lock */ |
753 | spinlock_t pending_pool_lock; /* pending pool lock */ |
754 | |
755 | /* Tasklet to handle deferred processing */ |
756 | struct tasklet_struct isr_tasklet[PMCRAID_NUM_MSIX_VECTORS]; |
757 | |
758 | /* Work-queue (Shared) for deferred reset processing */ |
759 | struct work_struct worker_q; |
760 | |
761 | /* No of IO commands pending with FW */ |
762 | atomic_t outstanding_cmds; |
763 | |
764 | /* should add/delete resources to mid-layer now ?*/ |
765 | atomic_t expose_resources; |
766 | |
767 | |
768 | |
769 | u32 ioa_state:4; /* For IOA Reset sequence FSM */ |
770 | #define IOA_STATE_OPERATIONAL 0x0 |
771 | #define IOA_STATE_UNKNOWN 0x1 |
772 | #define IOA_STATE_DEAD 0x2 |
773 | #define IOA_STATE_IN_SOFT_RESET 0x3 |
774 | #define IOA_STATE_IN_HARD_RESET 0x4 |
775 | #define IOA_STATE_IN_RESET_ALERT 0x5 |
776 | #define IOA_STATE_IN_BRINGDOWN 0x6 |
777 | #define IOA_STATE_IN_BRINGUP 0x7 |
778 | |
779 | u32 ioa_reset_in_progress:1; /* true if IOA reset is in progress */ |
780 | u32 ioa_hard_reset:1; /* TRUE if Hard Reset is needed */ |
781 | u32 ioa_unit_check:1; /* Indicates Unit Check condition */ |
782 | u32 ioa_bringdown:1; /* whether IOA needs to be brought down */ |
783 | u32 force_ioa_reset:1; /* force adapter reset ? */ |
784 | u32 reinit_cfg_table:1; /* reinit config table due to lost CCN */ |
785 | u32 ioa_shutdown_type:2;/* shutdown type used during reset */ |
786 | #define SHUTDOWN_NONE 0x0 |
787 | #define SHUTDOWN_NORMAL 0x1 |
788 | #define SHUTDOWN_ABBREV 0x2 |
789 | u32 timestamp_error:1; /* indicate set timestamp for out of sync */ |
790 | |
791 | }; |
792 | |
793 | /* LLD maintained resource entry structure */ |
794 | struct pmcraid_resource_entry { |
795 | struct list_head queue; /* link to "to be exposed" resources */ |
796 | union { |
797 | struct pmcraid_config_table_entry cfg_entry; |
798 | struct pmcraid_config_table_entry_ext cfg_entry_ext; |
799 | }; |
800 | struct scsi_device *scsi_dev; /* Link scsi_device structure */ |
801 | atomic_t read_failures; /* count of failed READ commands */ |
802 | atomic_t write_failures; /* count of failed WRITE commands */ |
803 | |
804 | /* To indicate add/delete/modify during CCN */ |
805 | u8 change_detected; |
806 | #define RES_CHANGE_ADD 0x1 /* add this to mid-layer */ |
807 | #define RES_CHANGE_DEL 0x2 /* remove this from mid-layer */ |
808 | |
809 | u8 reset_progress; /* Device is resetting */ |
810 | |
811 | /* |
812 | * When IOA asks for sync (i.e. IOASC = Not Ready, Sync Required), this |
813 | * flag will be set, mid layer will be asked to retry. In the next |
814 | * attempt, this flag will be checked in queuecommand() to set |
815 | * SYNC_COMPLETE flag in IOARCB (flag_0). |
816 | */ |
817 | u8 sync_reqd; |
818 | |
819 | /* target indicates the mapped target_id assigned to this resource if |
820 | * this is VSET resource. For non-VSET resources this will be un-used |
821 | * or zero |
822 | */ |
823 | u8 target; |
824 | }; |
825 | |
826 | /* Data structures used in IOASC error code logging */ |
827 | struct pmcraid_ioasc_error { |
828 | u32 ioasc_code; /* IOASC code */ |
829 | u8 log_level; /* default log level assignment. */ |
830 | char *error_string; |
831 | }; |
832 | |
833 | /* Initial log_level assignments for various IOASCs */ |
834 | #define IOASC_LOG_LEVEL_NONE 0x0 /* no logging */ |
835 | #define IOASC_LOG_LEVEL_MUST 0x1 /* must log: all high-severity errors */ |
836 | #define IOASC_LOG_LEVEL_HARD 0x2 /* optional – low severity errors */ |
837 | |
838 | /* Error information maintained by LLD. LLD initializes the pmcraid_error_table |
839 | * statically. |
840 | */ |
841 | static struct pmcraid_ioasc_error pmcraid_ioasc_error_table[] = { |
842 | {0x01180600, IOASC_LOG_LEVEL_HARD, |
843 | "Recovered Error, soft media error, sector reassignment suggested" }, |
844 | {0x015D0000, IOASC_LOG_LEVEL_HARD, |
845 | "Recovered Error, failure prediction threshold exceeded" }, |
846 | {0x015D9200, IOASC_LOG_LEVEL_HARD, |
847 | "Recovered Error, soft Cache Card Battery error threshold" }, |
848 | {0x015D9200, IOASC_LOG_LEVEL_HARD, |
849 | "Recovered Error, soft Cache Card Battery error threshold" }, |
850 | {0x02048000, IOASC_LOG_LEVEL_HARD, |
851 | "Not Ready, IOA Reset Required" }, |
852 | {0x02408500, IOASC_LOG_LEVEL_HARD, |
853 | "Not Ready, IOA microcode download required" }, |
854 | {0x03110B00, IOASC_LOG_LEVEL_HARD, |
855 | "Medium Error, data unreadable, reassignment suggested" }, |
856 | {0x03110C00, IOASC_LOG_LEVEL_MUST, |
857 | "Medium Error, data unreadable do not reassign" }, |
858 | {0x03310000, IOASC_LOG_LEVEL_HARD, |
859 | "Medium Error, media corrupted" }, |
860 | {0x04050000, IOASC_LOG_LEVEL_HARD, |
861 | "Hardware Error, IOA can't communicate with device" }, |
862 | {0x04080000, IOASC_LOG_LEVEL_MUST, |
863 | "Hardware Error, device bus error" }, |
864 | {0x04088000, IOASC_LOG_LEVEL_MUST, |
865 | "Hardware Error, device bus is not functioning" }, |
866 | {0x04118000, IOASC_LOG_LEVEL_HARD, |
867 | "Hardware Error, IOA reserved area data check" }, |
868 | {0x04118100, IOASC_LOG_LEVEL_HARD, |
869 | "Hardware Error, IOA reserved area invalid data pattern" }, |
870 | {0x04118200, IOASC_LOG_LEVEL_HARD, |
871 | "Hardware Error, IOA reserved area LRC error" }, |
872 | {0x04320000, IOASC_LOG_LEVEL_HARD, |
873 | "Hardware Error, reassignment space exhausted" }, |
874 | {0x04330000, IOASC_LOG_LEVEL_HARD, |
875 | "Hardware Error, data transfer underlength error" }, |
876 | {0x04330000, IOASC_LOG_LEVEL_HARD, |
877 | "Hardware Error, data transfer overlength error" }, |
878 | {0x04418000, IOASC_LOG_LEVEL_MUST, |
879 | "Hardware Error, PCI bus error" }, |
880 | {0x04440000, IOASC_LOG_LEVEL_HARD, |
881 | "Hardware Error, device error" }, |
882 | {0x04448200, IOASC_LOG_LEVEL_MUST, |
883 | "Hardware Error, IOA error" }, |
884 | {0x04448300, IOASC_LOG_LEVEL_HARD, |
885 | "Hardware Error, undefined device response" }, |
886 | {0x04448400, IOASC_LOG_LEVEL_HARD, |
887 | "Hardware Error, IOA microcode error" }, |
888 | {0x04448600, IOASC_LOG_LEVEL_HARD, |
889 | "Hardware Error, IOA reset required" }, |
890 | {0x04449200, IOASC_LOG_LEVEL_HARD, |
891 | "Hardware Error, hard Cache Fearuee Card Battery error" }, |
892 | {0x0444A000, IOASC_LOG_LEVEL_HARD, |
893 | "Hardware Error, failed device altered" }, |
894 | {0x0444A200, IOASC_LOG_LEVEL_HARD, |
895 | "Hardware Error, data check after reassignment" }, |
896 | {0x0444A300, IOASC_LOG_LEVEL_HARD, |
897 | "Hardware Error, LRC error after reassignment" }, |
898 | {0x044A0000, IOASC_LOG_LEVEL_HARD, |
899 | "Hardware Error, device bus error (msg/cmd phase)" }, |
900 | {0x04670400, IOASC_LOG_LEVEL_HARD, |
901 | "Hardware Error, new device can't be used" }, |
902 | {0x04678000, IOASC_LOG_LEVEL_HARD, |
903 | "Hardware Error, invalid multiadapter configuration" }, |
904 | {0x04678100, IOASC_LOG_LEVEL_HARD, |
905 | "Hardware Error, incorrect connection between enclosures" }, |
906 | {0x04678200, IOASC_LOG_LEVEL_HARD, |
907 | "Hardware Error, connections exceed IOA design limits" }, |
908 | {0x04678300, IOASC_LOG_LEVEL_HARD, |
909 | "Hardware Error, incorrect multipath connection" }, |
910 | {0x04679000, IOASC_LOG_LEVEL_HARD, |
911 | "Hardware Error, command to LUN failed" }, |
912 | {0x064C8000, IOASC_LOG_LEVEL_HARD, |
913 | "Unit Attention, cache exists for missing/failed device" }, |
914 | {0x06670100, IOASC_LOG_LEVEL_HARD, |
915 | "Unit Attention, incompatible exposed mode device" }, |
916 | {0x06670600, IOASC_LOG_LEVEL_HARD, |
917 | "Unit Attention, attachment of logical unit failed" }, |
918 | {0x06678000, IOASC_LOG_LEVEL_HARD, |
919 | "Unit Attention, cables exceed connective design limit" }, |
920 | {0x06678300, IOASC_LOG_LEVEL_HARD, |
921 | "Unit Attention, incomplete multipath connection between" \ |
922 | "IOA and enclosure" }, |
923 | {0x06678400, IOASC_LOG_LEVEL_HARD, |
924 | "Unit Attention, incomplete multipath connection between" \ |
925 | "device and enclosure" }, |
926 | {0x06678500, IOASC_LOG_LEVEL_HARD, |
927 | "Unit Attention, incomplete multipath connection between" \ |
928 | "IOA and remote IOA" }, |
929 | {0x06678600, IOASC_LOG_LEVEL_HARD, |
930 | "Unit Attention, missing remote IOA" }, |
931 | {0x06679100, IOASC_LOG_LEVEL_HARD, |
932 | "Unit Attention, enclosure doesn't support required multipath" \ |
933 | "function" }, |
934 | {0x06698200, IOASC_LOG_LEVEL_HARD, |
935 | "Unit Attention, corrupt array parity detected on device" }, |
936 | {0x066B0200, IOASC_LOG_LEVEL_HARD, |
937 | "Unit Attention, array exposed" }, |
938 | {0x066B8200, IOASC_LOG_LEVEL_HARD, |
939 | "Unit Attention, exposed array is still protected" }, |
940 | {0x066B9200, IOASC_LOG_LEVEL_HARD, |
941 | "Unit Attention, Multipath redundancy level got worse" }, |
942 | {0x07270000, IOASC_LOG_LEVEL_HARD, |
943 | "Data Protect, device is read/write protected by IOA" }, |
944 | {0x07278000, IOASC_LOG_LEVEL_HARD, |
945 | "Data Protect, IOA doesn't support device attribute" }, |
946 | {0x07278100, IOASC_LOG_LEVEL_HARD, |
947 | "Data Protect, NVRAM mirroring prohibited" }, |
948 | {0x07278400, IOASC_LOG_LEVEL_HARD, |
949 | "Data Protect, array is short 2 or more devices" }, |
950 | {0x07278600, IOASC_LOG_LEVEL_HARD, |
951 | "Data Protect, exposed array is short a required device" }, |
952 | {0x07278700, IOASC_LOG_LEVEL_HARD, |
953 | "Data Protect, array members not at required addresses" }, |
954 | {0x07278800, IOASC_LOG_LEVEL_HARD, |
955 | "Data Protect, exposed mode device resource address conflict" }, |
956 | {0x07278900, IOASC_LOG_LEVEL_HARD, |
957 | "Data Protect, incorrect resource address of exposed mode device" }, |
958 | {0x07278A00, IOASC_LOG_LEVEL_HARD, |
959 | "Data Protect, Array is missing a device and parity is out of sync" }, |
960 | {0x07278B00, IOASC_LOG_LEVEL_HARD, |
961 | "Data Protect, maximum number of arrays already exist" }, |
962 | {0x07278C00, IOASC_LOG_LEVEL_HARD, |
963 | "Data Protect, cannot locate cache data for device" }, |
964 | {0x07278D00, IOASC_LOG_LEVEL_HARD, |
965 | "Data Protect, cache data exits for a changed device" }, |
966 | {0x07279100, IOASC_LOG_LEVEL_HARD, |
967 | "Data Protect, detection of a device requiring format" }, |
968 | {0x07279200, IOASC_LOG_LEVEL_HARD, |
969 | "Data Protect, IOA exceeds maximum number of devices" }, |
970 | {0x07279600, IOASC_LOG_LEVEL_HARD, |
971 | "Data Protect, missing array, volume set is not functional" }, |
972 | {0x07279700, IOASC_LOG_LEVEL_HARD, |
973 | "Data Protect, single device for a volume set" }, |
974 | {0x07279800, IOASC_LOG_LEVEL_HARD, |
975 | "Data Protect, missing multiple devices for a volume set" }, |
976 | {0x07279900, IOASC_LOG_LEVEL_HARD, |
977 | "Data Protect, maximum number of volument sets already exists" }, |
978 | {0x07279A00, IOASC_LOG_LEVEL_HARD, |
979 | "Data Protect, other volume set problem" }, |
980 | }; |
981 | |
982 | /* macros to help in debugging */ |
983 | #define pmcraid_err(...) \ |
984 | printk(KERN_ERR "MaxRAID: "__VA_ARGS__) |
985 | |
986 | #define pmcraid_info(...) \ |
987 | if (pmcraid_debug_log) \ |
988 | printk(KERN_INFO "MaxRAID: "__VA_ARGS__) |
989 | |
990 | /* check if given command is a SCSI READ or SCSI WRITE command */ |
991 | #define SCSI_READ_CMD 0x1 /* any of SCSI READ commands */ |
992 | #define SCSI_WRITE_CMD 0x2 /* any of SCSI WRITE commands */ |
993 | #define SCSI_CMD_TYPE(opcode) \ |
994 | ({ u8 op = opcode; u8 __type = 0;\ |
995 | if (op == READ_6 || op == READ_10 || op == READ_12 || op == READ_16)\ |
996 | __type = SCSI_READ_CMD;\ |
997 | else if (op == WRITE_6 || op == WRITE_10 || op == WRITE_12 || \ |
998 | op == WRITE_16)\ |
999 | __type = SCSI_WRITE_CMD;\ |
1000 | __type;\ |
1001 | }) |
1002 | |
1003 | #define IS_SCSI_READ_WRITE(opcode) \ |
1004 | ({ u8 __type = SCSI_CMD_TYPE(opcode); \ |
1005 | (__type == SCSI_READ_CMD || __type == SCSI_WRITE_CMD) ? 1 : 0;\ |
1006 | }) |
1007 | |
1008 | |
1009 | /* |
1010 | * pmcraid_ioctl_header - definition of header structure that precedes all the |
1011 | * buffers given as ioctl arguments. |
1012 | * |
1013 | * .signature : always ASCII string, "PMCRAID" |
1014 | * .reserved : not used |
1015 | * .buffer_length : length of the buffer following the header |
1016 | */ |
1017 | struct { |
1018 | u8 [8]; |
1019 | u32 ; |
1020 | u32 ; |
1021 | }; |
1022 | |
1023 | #define PMCRAID_IOCTL_SIGNATURE "PMCRAID" |
1024 | |
1025 | /* |
1026 | * keys to differentiate between driver handled IOCTLs and passthrough |
1027 | * IOCTLs passed to IOA. driver determines the ioctl type using macro |
1028 | * _IOC_TYPE |
1029 | */ |
1030 | #define PMCRAID_DRIVER_IOCTL 'D' |
1031 | |
1032 | #define DRV_IOCTL(n, size) \ |
1033 | _IOC(_IOC_READ|_IOC_WRITE, PMCRAID_DRIVER_IOCTL, (n), (size)) |
1034 | |
1035 | /* |
1036 | * _ARGSIZE: macro that gives size of the argument type passed to an IOCTL cmd. |
1037 | * This is to facilitate applications avoiding un-necessary memory allocations. |
1038 | * For example, most of driver handled ioctls do not require ioarcb, ioasa. |
1039 | */ |
1040 | #define _ARGSIZE(arg) (sizeof(struct pmcraid_ioctl_header) + sizeof(arg)) |
1041 | |
1042 | /* Driver handled IOCTL command definitions */ |
1043 | |
1044 | #define PMCRAID_IOCTL_RESET_ADAPTER \ |
1045 | DRV_IOCTL(5, sizeof(struct pmcraid_ioctl_header)) |
1046 | |
1047 | #endif /* _PMCRAID_H */ |
1048 | |