1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | |
3 | #ifndef __SOC_MEDIATEK_MT8188_MMSYS_H |
4 | #define __SOC_MEDIATEK_MT8188_MMSYS_H |
5 | |
6 | #include <linux/soc/mediatek/mtk-mmsys.h> |
7 | #include <dt-bindings/reset/mt8188-resets.h> |
8 | |
9 | #define MT8188_VDO0_SW0_RST_B 0x190 |
10 | #define MT8188_VDO0_OVL_MOUT_EN 0xf14 |
11 | #define MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) |
12 | #define MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) |
13 | #define MT8188_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) |
14 | #define MT8188_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) |
15 | #define MT8188_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) |
16 | #define MT8188_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) |
17 | |
18 | #define MT8188_VDO0_SEL_IN 0xf34 |
19 | #define MT8188_VDO0_SEL_OUT 0xf38 |
20 | |
21 | #define MT8188_VDO0_DISP_RDMA_SEL 0xf40 |
22 | #define MT8188_SOUT_DISP_RDMA0_TO_MASK GENMASK(2, 0) |
23 | #define MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 (0 << 0) |
24 | #define MT8188_SOUT_DISP_RDMA0_TO_DISP_DSI0 (1 << 0) |
25 | #define MT8188_SOUT_DISP_RDMA0_TO_DISP_DP_INTF0 (5 << 0) |
26 | #define MT8188_SEL_IN_DISP_RDMA0_FROM_MASK GENMASK(8, 8) |
27 | #define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 (0 << 8) |
28 | #define MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_RSZ0 (1 << 8) |
29 | |
30 | |
31 | #define MT8188_VDO0_DSI0_SEL_IN 0xf44 |
32 | #define MT8188_SEL_IN_DSI0_FROM_MASK BIT(0) |
33 | #define MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 0) |
34 | #define MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 0) |
35 | |
36 | #define MT8188_VDO0_DP_INTF0_SEL_IN 0xf4C |
37 | #define MT8188_SEL_IN_DP_INTF0_FROM_MASK GENMASK(2, 0) |
38 | #define MT8188_SEL_IN_DP_INTF0_FROM_DSC_WRAP0C1_OUT (0 << 0) |
39 | #define MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 0) |
40 | #define MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 (3 << 0) |
41 | |
42 | #define MT8188_VDO0_DISP_DITHER0_SEL_OUT 0xf58 |
43 | #define MT8188_SOUT_DISP_DITHER0_TO_MASK GENMASK(2, 0) |
44 | #define MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) |
45 | #define MT8188_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) |
46 | #define MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0 (6 << 0) |
47 | #define MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 (7 << 0) |
48 | |
49 | #define MT8188_VDO0_VPP_MERGE_SEL 0xf60 |
50 | #define MT8188_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0) |
51 | #define MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) |
52 | #define MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT (3 << 0) |
53 | |
54 | #define MT8188_SOUT_VPP_MERGE_TO_MASK GENMASK(6, 4) |
55 | #define MT8188_SOUT_VPP_MERGE_TO_DSI1 (0 << 4) |
56 | #define MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 4) |
57 | #define MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 4) |
58 | #define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 4) |
59 | #define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 4) |
60 | #define MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 (5 << 4) |
61 | #define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11) |
62 | #define MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) |
63 | |
64 | #define MT8188_VDO0_DSC_WARP_SEL 0xf64 |
65 | #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK GENMASK(0, 0) |
66 | #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 (0 << 0) |
67 | #define MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_VPP_MERGE (1 << 0) |
68 | #define MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(19, 16) |
69 | #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 BIT(16) |
70 | #define MT8188_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 BIT(17) |
71 | #define MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE BIT(18) |
72 | #define MT8188_SOUT_DSC_WRAP0_OUT_TO_DISP_WDMA0 BIT(19) |
73 | |
74 | #define MT8188_VDO1_SW0_RST_B 0x1d0 |
75 | #define MT8188_VDO1_HDR_TOP_CFG 0xd00 |
76 | #define MT8188_VDO1_MIXER_IN1_ALPHA 0xd30 |
77 | #define MT8188_VDO1_MIXER_IN1_PAD 0xd40 |
78 | #define MT8188_VDO1_MIXER_VSYNC_LEN 0xd5c |
79 | #define MT8188_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 |
80 | #define MT8188_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 |
81 | #define MT8188_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 |
82 | #define MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 |
83 | #define MT8188_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 |
84 | #define MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 1 |
85 | #define MT8188_VDO1_DISP_DPI1_SEL_IN 0xf10 |
86 | #define MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT 0 |
87 | #define MT8188_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 |
88 | #define MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT 0 |
89 | #define MT8188_VDO1_MERGE4_SOUT_SEL 0xf18 |
90 | #define MT8188_MERGE4_SOUT_TO_DPI1_SEL BIT(2) |
91 | #define MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL BIT(3) |
92 | #define MT8188_VDO1_MIXER_IN1_SEL_IN 0xf24 |
93 | #define MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT 1 |
94 | #define MT8188_VDO1_MIXER_IN2_SEL_IN 0xf28 |
95 | #define MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT 1 |
96 | #define MT8188_VDO1_MIXER_IN3_SEL_IN 0xf2c |
97 | #define MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT 1 |
98 | #define MT8188_VDO1_MIXER_IN4_SEL_IN 0xf30 |
99 | #define MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT 1 |
100 | #define MT8188_VDO1_MIXER_OUT_SOUT_SEL 0xf34 |
101 | #define MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL 1 |
102 | #define MT8188_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c |
103 | #define MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 1 |
104 | #define MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 |
105 | #define MT8188_SOUT_TO_MIXER_IN1_SEL 1 |
106 | #define MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 |
107 | #define MT8188_SOUT_TO_MIXER_IN2_SEL 1 |
108 | #define MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 |
109 | #define MT8188_SOUT_TO_MIXER_IN3_SEL 1 |
110 | #define MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c |
111 | #define MT8188_SOUT_TO_MIXER_IN4_SEL 1 |
112 | #define MT8188_VDO1_MERGE4_ASYNC_SEL_IN 0xf50 |
113 | #define MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT 1 |
114 | #define MT8188_VDO1_MIXER_IN1_SOUT_SEL 0xf58 |
115 | #define MT8188_MIXER_IN1_SOUT_TO_DISP_MIXER 0 |
116 | #define MT8188_VDO1_MIXER_IN2_SOUT_SEL 0xf5c |
117 | #define MT8188_MIXER_IN2_SOUT_TO_DISP_MIXER 0 |
118 | #define MT8188_VDO1_MIXER_IN3_SOUT_SEL 0xf60 |
119 | #define MT8188_MIXER_IN3_SOUT_TO_DISP_MIXER 0 |
120 | #define MT8188_VDO1_MIXER_IN4_SOUT_SEL 0xf64 |
121 | #define MT8188_MIXER_IN4_SOUT_TO_DISP_MIXER 0 |
122 | #define MT8188_VDO1_MIXER_SOUT_SEL_IN 0xf68 |
123 | #define MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 |
124 | |
125 | static const u8 mmsys_mt8188_vdo0_rst_tb[] = { |
126 | [MT8188_VDO0_RST_DISP_OVL0] = MMSYS_RST_NR(0, 0), |
127 | [MT8188_VDO0_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 2), |
128 | [MT8188_VDO0_RST_DISP_CCORR0] = MMSYS_RST_NR(0, 4), |
129 | [MT8188_VDO0_RST_DISP_MUTEX0] = MMSYS_RST_NR(0, 6), |
130 | [MT8188_VDO0_RST_DISP_GAMMA0] = MMSYS_RST_NR(0, 8), |
131 | [MT8188_VDO0_RST_DISP_DITHER0] = MMSYS_RST_NR(0, 10), |
132 | [MT8188_VDO0_RST_DISP_WDMA0] = MMSYS_RST_NR(0, 17), |
133 | [MT8188_VDO0_RST_DISP_RDMA0] = MMSYS_RST_NR(0, 19), |
134 | [MT8188_VDO0_RST_DSI0] = MMSYS_RST_NR(0, 21), |
135 | [MT8188_VDO0_RST_DSI1] = MMSYS_RST_NR(0, 22), |
136 | [MT8188_VDO0_RST_DSC_WRAP0] = MMSYS_RST_NR(0, 23), |
137 | [MT8188_VDO0_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 24), |
138 | [MT8188_VDO0_RST_DP_INTF0] = MMSYS_RST_NR(0, 25), |
139 | [MT8188_VDO0_RST_DISP_AAL0] = MMSYS_RST_NR(0, 26), |
140 | [MT8188_VDO0_RST_INLINEROT0] = MMSYS_RST_NR(0, 27), |
141 | [MT8188_VDO0_RST_APB_BUS] = MMSYS_RST_NR(0, 28), |
142 | [MT8188_VDO0_RST_DISP_COLOR0] = MMSYS_RST_NR(0, 29), |
143 | [MT8188_VDO0_RST_MDP_WROT0] = MMSYS_RST_NR(0, 30), |
144 | [MT8188_VDO0_RST_DISP_RSZ0] = MMSYS_RST_NR(0, 31), |
145 | }; |
146 | |
147 | static const u8 mmsys_mt8188_vdo1_rst_tb[] = { |
148 | [MT8188_VDO1_RST_SMI_LARB2] = MMSYS_RST_NR(0, 0), |
149 | [MT8188_VDO1_RST_SMI_LARB3] = MMSYS_RST_NR(0, 1), |
150 | [MT8188_VDO1_RST_GALS] = MMSYS_RST_NR(0, 2), |
151 | [MT8188_VDO1_RST_FAKE_ENG0] = MMSYS_RST_NR(0, 3), |
152 | [MT8188_VDO1_RST_FAKE_ENG1] = MMSYS_RST_NR(0, 4), |
153 | [MT8188_VDO1_RST_MDP_RDMA0] = MMSYS_RST_NR(0, 5), |
154 | [MT8188_VDO1_RST_MDP_RDMA1] = MMSYS_RST_NR(0, 6), |
155 | [MT8188_VDO1_RST_MDP_RDMA2] = MMSYS_RST_NR(0, 7), |
156 | [MT8188_VDO1_RST_MDP_RDMA3] = MMSYS_RST_NR(0, 8), |
157 | [MT8188_VDO1_RST_VPP_MERGE0] = MMSYS_RST_NR(0, 9), |
158 | [MT8188_VDO1_RST_VPP_MERGE1] = MMSYS_RST_NR(0, 10), |
159 | [MT8188_VDO1_RST_VPP_MERGE2] = MMSYS_RST_NR(0, 11), |
160 | [MT8188_VDO1_RST_VPP_MERGE3] = MMSYS_RST_NR(1, 0), |
161 | [MT8188_VDO1_RST_VPP_MERGE4] = MMSYS_RST_NR(1, 1), |
162 | [MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 2), |
163 | [MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 3), |
164 | [MT8188_VDO1_RST_DISP_MUTEX] = MMSYS_RST_NR(1, 4), |
165 | [MT8188_VDO1_RST_MDP_RDMA4] = MMSYS_RST_NR(1, 5), |
166 | [MT8188_VDO1_RST_MDP_RDMA5] = MMSYS_RST_NR(1, 6), |
167 | [MT8188_VDO1_RST_MDP_RDMA6] = MMSYS_RST_NR(1, 7), |
168 | [MT8188_VDO1_RST_MDP_RDMA7] = MMSYS_RST_NR(1, 8), |
169 | [MT8188_VDO1_RST_DP_INTF1_MMCK] = MMSYS_RST_NR(1, 9), |
170 | [MT8188_VDO1_RST_DPI0_MM_CK] = MMSYS_RST_NR(1, 10), |
171 | [MT8188_VDO1_RST_DPI1_MM_CK] = MMSYS_RST_NR(1, 11), |
172 | [MT8188_VDO1_RST_MERGE0_DL_ASYNC] = MMSYS_RST_NR(1, 13), |
173 | [MT8188_VDO1_RST_MERGE1_DL_ASYNC] = MMSYS_RST_NR(1, 14), |
174 | [MT8188_VDO1_RST_MERGE2_DL_ASYNC] = MMSYS_RST_NR(1, 15), |
175 | [MT8188_VDO1_RST_MERGE3_DL_ASYNC] = MMSYS_RST_NR(1, 16), |
176 | [MT8188_VDO1_RST_MERGE4_DL_ASYNC] = MMSYS_RST_NR(1, 17), |
177 | [MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 18), |
178 | [MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC] = MMSYS_RST_NR(1, 19), |
179 | [MT8188_VDO1_RST_PADDING0] = MMSYS_RST_NR(1, 20), |
180 | [MT8188_VDO1_RST_PADDING1] = MMSYS_RST_NR(1, 21), |
181 | [MT8188_VDO1_RST_PADDING2] = MMSYS_RST_NR(1, 22), |
182 | [MT8188_VDO1_RST_PADDING3] = MMSYS_RST_NR(1, 23), |
183 | [MT8188_VDO1_RST_PADDING4] = MMSYS_RST_NR(1, 24), |
184 | [MT8188_VDO1_RST_PADDING5] = MMSYS_RST_NR(1, 25), |
185 | [MT8188_VDO1_RST_PADDING6] = MMSYS_RST_NR(1, 26), |
186 | [MT8188_VDO1_RST_PADDING7] = MMSYS_RST_NR(1, 27), |
187 | [MT8188_VDO1_RST_DISP_RSZ0] = MMSYS_RST_NR(1, 28), |
188 | [MT8188_VDO1_RST_DISP_RSZ1] = MMSYS_RST_NR(1, 29), |
189 | [MT8188_VDO1_RST_DISP_RSZ2] = MMSYS_RST_NR(1, 30), |
190 | [MT8188_VDO1_RST_DISP_RSZ3] = MMSYS_RST_NR(1, 31), |
191 | [MT8188_VDO1_RST_HDR_VDO_FE0] = MMSYS_RST_NR(2, 0), |
192 | [MT8188_VDO1_RST_HDR_GFX_FE0] = MMSYS_RST_NR(2, 1), |
193 | [MT8188_VDO1_RST_HDR_VDO_BE] = MMSYS_RST_NR(2, 2), |
194 | [MT8188_VDO1_RST_HDR_VDO_FE1] = MMSYS_RST_NR(2, 16), |
195 | [MT8188_VDO1_RST_HDR_GFX_FE1] = MMSYS_RST_NR(2, 17), |
196 | [MT8188_VDO1_RST_DISP_MIXER] = MMSYS_RST_NR(2, 18), |
197 | [MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 19), |
198 | [MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 20), |
199 | [MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC] = MMSYS_RST_NR(2, 21), |
200 | [MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC] = MMSYS_RST_NR(2, 22), |
201 | [MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC] = MMSYS_RST_NR(2, 23), |
202 | }; |
203 | |
204 | static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = { |
205 | { |
206 | DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, |
207 | MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0, |
208 | MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0 |
209 | }, { |
210 | DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0, |
211 | MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0, |
212 | MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0 |
213 | }, { |
214 | DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, |
215 | MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK, |
216 | MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0 |
217 | }, { |
218 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, |
219 | MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, |
220 | MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0 |
221 | }, { |
222 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_MERGE0, |
223 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, |
224 | MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT |
225 | }, { |
226 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0, |
227 | MT8188_VDO0_DSC_WARP_SEL, |
228 | MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK, |
229 | MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0 |
230 | }, { |
231 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, |
232 | MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK, |
233 | MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0 |
234 | }, { |
235 | DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, |
236 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK, |
237 | MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT |
238 | }, { |
239 | DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, |
240 | MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK, |
241 | MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT |
242 | }, { |
243 | DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, |
244 | MT8188_VDO0_DISP_RDMA_SEL, MT8188_SOUT_DISP_RDMA0_TO_MASK, |
245 | MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0 |
246 | }, { |
247 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, |
248 | MT8188_VDO0_DISP_DITHER0_SEL_OUT, |
249 | MT8188_SOUT_DISP_DITHER0_TO_MASK, |
250 | MT8188_SOUT_DISP_DITHER0_TO_DSI0 |
251 | }, { |
252 | DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0, |
253 | MT8188_VDO0_DISP_DITHER0_SEL_OUT, |
254 | MT8188_SOUT_DISP_DITHER0_TO_MASK, |
255 | MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0 |
256 | }, { |
257 | DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, |
258 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, |
259 | MT8188_SOUT_VPP_MERGE_TO_DP_INTF0 |
260 | }, { |
261 | DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0, |
262 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, |
263 | MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 |
264 | }, { |
265 | DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA0, |
266 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, |
267 | MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0 |
268 | }, { |
269 | DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0, |
270 | MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK, |
271 | MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN |
272 | }, { |
273 | DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, |
274 | MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, |
275 | MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0 |
276 | }, { |
277 | DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, |
278 | MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK, |
279 | MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE |
280 | }, |
281 | }; |
282 | |
283 | static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = { |
284 | { |
285 | DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1, |
286 | MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), |
287 | MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 |
288 | }, { |
289 | DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1, |
290 | MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), |
291 | MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 |
292 | }, { |
293 | DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2, |
294 | MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), |
295 | MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 |
296 | }, { |
297 | DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, |
298 | MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), |
299 | MT8188_SOUT_TO_MIXER_IN1_SEL |
300 | }, { |
301 | DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, |
302 | MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), |
303 | MT8188_SOUT_TO_MIXER_IN2_SEL |
304 | }, { |
305 | DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, |
306 | MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), |
307 | MT8188_SOUT_TO_MIXER_IN3_SEL |
308 | }, { |
309 | DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, |
310 | MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), |
311 | MT8188_SOUT_TO_MIXER_IN4_SEL |
312 | }, { |
313 | DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, |
314 | MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), |
315 | MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL |
316 | }, { |
317 | DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER, |
318 | MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), |
319 | MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT |
320 | }, { |
321 | DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER, |
322 | MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), |
323 | MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT |
324 | }, { |
325 | DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER, |
326 | MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), |
327 | MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT |
328 | }, { |
329 | DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER, |
330 | MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), |
331 | MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT |
332 | }, { |
333 | DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, |
334 | MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), |
335 | MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER |
336 | }, { |
337 | DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5, |
338 | MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), |
339 | MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT |
340 | }, { |
341 | DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, |
342 | MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), |
343 | MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT |
344 | }, { |
345 | DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, |
346 | MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), |
347 | MT8188_MERGE4_SOUT_TO_DPI1_SEL |
348 | }, { |
349 | DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, |
350 | MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), |
351 | MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT |
352 | }, { |
353 | DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, |
354 | MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0), |
355 | MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL |
356 | } |
357 | }; |
358 | |
359 | #endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */ |
360 | |