| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /****************************************************************************** |
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| 3 | * |
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| 4 | * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved. |
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| 5 | * |
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| 6 | * Modifications for inclusion into the Linux staging tree are |
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| 7 | * Copyright(c) 2010 Larry Finger. All rights reserved. |
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| 8 | * |
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| 9 | * Contact information: |
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| 10 | * WLAN FAE <wlanfae@realtek.com> |
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| 11 | * Larry Finger <Larry.Finger@lwfinger.net> |
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| 12 | * |
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| 13 | ******************************************************************************/ |
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| 14 | #ifndef __RTL8712_GP_BITDEF_H__ |
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| 15 | #define __RTL8712_GP_BITDEF_H__ |
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| 16 | |
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| 17 | /*GPIO_CTRL*/ |
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| 18 | #define _GPIO_MOD_MSK 0xFF000000 |
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| 19 | #define _GPIO_MOD_SHT 24 |
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| 20 | #define _GPIO_IO_SEL_MSK 0x00FF0000 |
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| 21 | #define _GPIO_IO_SEL_SHT 16 |
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| 22 | #define _GPIO_OUT_MSK 0x0000FF00 |
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| 23 | #define _GPIO_OUT_SHT 8 |
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| 24 | #define _GPIO_IN_MSK 0x000000FF |
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| 25 | #define _GPIO_IN_SHT 0 |
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| 26 | |
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| 27 | /*SYS_PINMUX_CFG*/ |
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| 28 | #define _GPIOSEL_MSK 0x0003 |
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| 29 | #define _GPIOSEL_SHT 0 |
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| 30 | |
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| 31 | /*LED_CFG*/ |
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| 32 | #define _LED1SV BIT(7) |
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| 33 | #define _LED1CM_MSK 0x0070 |
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| 34 | #define _LED1CM_SHT 4 |
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| 35 | #define _LED0SV BIT(3) |
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| 36 | #define _LED0CM_MSK 0x0007 |
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| 37 | #define _LED0CM_SHT 0 |
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| 38 | |
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| 39 | /*PHY_REG*/ |
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| 40 | #define _HST_RDRDY_SHT 0 |
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| 41 | #define _HST_RDRDY_MSK 0xFF |
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| 42 | #define _HST_RDRDY BIT(_HST_RDRDY_SHT) |
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| 43 | #define _CPU_WTBUSY_SHT 1 |
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| 44 | #define _CPU_WTBUSY_MSK 0xFF |
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| 45 | #define _CPU_WTBUSY BIT(_CPU_WTBUSY_SHT) |
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| 46 | |
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| 47 | /* 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF)*/ |
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| 48 | |
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| 49 | /* 8192S GPIO Config Setting (offset 0x2F1, 1 byte)*/ |
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| 50 | |
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| 51 | /*----------------------------------------------------------------------------*/ |
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| 52 | |
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| 53 | #define GPIOMUX_EN BIT(3) /* When this bit is set to "1", |
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| 54 | * GPIO PINs will switch to MAC |
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| 55 | * GPIO Function |
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| 56 | */ |
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| 57 | #define GPIOSEL_GPIO 0 /* UART or JTAG or pure GPIO*/ |
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| 58 | #define GPIOSEL_PHYDBG 1 /* PHYDBG*/ |
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| 59 | #define GPIOSEL_BT 2 /* BT_coex*/ |
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| 60 | #define GPIOSEL_WLANDBG 3 /* WLANDBG*/ |
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| 61 | #define GPIOSEL_GPIO_MASK (~(BIT(0) | BIT(1))) |
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| 62 | /* HW Radio OFF switch (GPIO BIT) */ |
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| 63 | #define HAL_8192S_HW_GPIO_OFF_BIT BIT(3) |
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| 64 | #define HAL_8192S_HW_GPIO_OFF_MASK 0xF7 |
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| 65 | #define HAL_8192S_HW_GPIO_WPS_BIT BIT(4) |
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| 66 | |
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| 67 | #endif /*__RTL8712_GP_BITDEF_H__*/ |
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| 68 | |
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| 69 | |
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