| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. |
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| 4 | * All rights reserved. |
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| 5 | * |
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| 6 | * Purpose: MAC routines |
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| 7 | * |
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| 8 | * Author: Tevin Chen |
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| 9 | * |
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| 10 | * Date: May 21, 1996 |
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| 11 | * |
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| 12 | * Revision History: |
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| 13 | * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. |
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| 14 | * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53. |
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| 15 | * 09-03-2003 Bryan YC Fan: Add vt6655_mac_dis_protect_md & vt6655_mac_en_protect_md |
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| 16 | */ |
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| 17 | |
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| 18 | #ifndef __MAC_H__ |
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| 19 | #define __MAC_H__ |
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| 20 | |
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| 21 | #include "device.h" |
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| 22 | |
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| 23 | /*--------------------- Export Definitions -------------------------*/ |
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| 24 | /* Registers in the MAC */ |
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| 25 | #define MAC_MAX_CONTEXT_SIZE_PAGE0 256 |
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| 26 | #define MAC_MAX_CONTEXT_SIZE_PAGE1 128 |
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| 27 | |
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| 28 | /* Registers not related to 802.11b */ |
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| 29 | #define MAC_REG_BCFG0 0x00 |
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| 30 | #define MAC_REG_BCFG1 0x01 |
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| 31 | #define MAC_REG_FCR0 0x02 |
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| 32 | #define MAC_REG_FCR1 0x03 |
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| 33 | #define MAC_REG_BISTCMD 0x04 |
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| 34 | #define MAC_REG_BISTSR0 0x05 |
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| 35 | #define MAC_REG_BISTSR1 0x06 |
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| 36 | #define MAC_REG_BISTSR2 0x07 |
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| 37 | #define MAC_REG_I2MCSR 0x08 |
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| 38 | #define MAC_REG_I2MTGID 0x09 |
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| 39 | #define MAC_REG_I2MTGAD 0x0A |
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| 40 | #define MAC_REG_I2MCFG 0x0B |
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| 41 | #define MAC_REG_I2MDIPT 0x0C |
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| 42 | #define MAC_REG_I2MDOPT 0x0E |
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| 43 | #define MAC_REG_PMC0 0x10 |
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| 44 | #define MAC_REG_PMC1 0x11 |
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| 45 | #define MAC_REG_STICKHW 0x12 |
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| 46 | #define MAC_REG_LOCALID 0x14 |
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| 47 | #define MAC_REG_TESTCFG 0x15 |
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| 48 | #define MAC_REG_JUMPER0 0x16 |
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| 49 | #define MAC_REG_JUMPER1 0x17 |
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| 50 | #define MAC_REG_TMCTL0 0x18 |
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| 51 | #define MAC_REG_TMCTL1 0x19 |
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| 52 | #define MAC_REG_TMDATA0 0x1C |
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| 53 | |
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| 54 | /* MAC Parameter related */ |
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| 55 | #define MAC_REG_LRT 0x20 |
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| 56 | #define MAC_REG_SRT 0x21 |
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| 57 | #define MAC_REG_SIFS 0x22 |
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| 58 | #define MAC_REG_DIFS 0x23 |
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| 59 | #define MAC_REG_EIFS 0x24 |
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| 60 | #define MAC_REG_SLOT 0x25 |
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| 61 | #define MAC_REG_BI 0x26 |
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| 62 | #define MAC_REG_CWMAXMIN0 0x28 |
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| 63 | #define MAC_REG_LINKOFFTOTM 0x2A |
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| 64 | #define MAC_REG_SWTMOT 0x2B |
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| 65 | #define MAC_REG_MIBCNTR 0x2C |
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| 66 | #define MAC_REG_RTSOKCNT 0x2C |
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| 67 | #define MAC_REG_RTSFAILCNT 0x2D |
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| 68 | #define MAC_REG_ACKFAILCNT 0x2E |
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| 69 | #define MAC_REG_FCSERRCNT 0x2F |
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| 70 | |
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| 71 | /* TSF Related */ |
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| 72 | #define MAC_REG_TSFCNTR 0x30 |
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| 73 | #define MAC_REG_NEXTTBTT 0x38 |
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| 74 | #define MAC_REG_TSFOFST 0x40 |
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| 75 | #define MAC_REG_TFTCTL 0x48 |
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| 76 | |
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| 77 | /* WMAC Control/Status Related */ |
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| 78 | #define MAC_REG_ENCFG 0x4C |
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| 79 | #define MAC_REG_PAGE1SEL 0x4F |
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| 80 | #define MAC_REG_CFG 0x50 |
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| 81 | #define MAC_REG_TEST 0x52 |
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| 82 | #define MAC_REG_HOSTCR 0x54 |
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| 83 | #define MAC_REG_MACCR 0x55 |
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| 84 | #define MAC_REG_RCR 0x56 |
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| 85 | #define MAC_REG_TCR 0x57 |
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| 86 | #define MAC_REG_IMR 0x58 |
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| 87 | #define MAC_REG_ISR 0x5C |
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| 88 | |
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| 89 | /* Power Saving Related */ |
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| 90 | #define MAC_REG_PSCFG 0x60 |
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| 91 | #define MAC_REG_PSCTL 0x61 |
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| 92 | #define MAC_REG_PSPWRSIG 0x62 |
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| 93 | #define MAC_REG_BBCR13 0x63 |
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| 94 | #define MAC_REG_AIDATIM 0x64 |
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| 95 | #define MAC_REG_PWBT 0x66 |
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| 96 | #define MAC_REG_WAKEOKTMR 0x68 |
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| 97 | #define MAC_REG_CALTMR 0x69 |
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| 98 | #define MAC_REG_SYNSPACCNT 0x6A |
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| 99 | #define MAC_REG_WAKSYNOPT 0x6B |
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| 100 | |
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| 101 | /* Baseband/IF Control Group */ |
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| 102 | #define MAC_REG_BBREGCTL 0x6C |
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| 103 | #define MAC_REG_CHANNEL 0x6D |
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| 104 | #define MAC_REG_BBREGADR 0x6E |
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| 105 | #define MAC_REG_BBREGDATA 0x6F |
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| 106 | #define MAC_REG_IFREGCTL 0x70 |
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| 107 | #define MAC_REG_IFDATA 0x71 |
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| 108 | #define MAC_REG_ITRTMSET 0x74 |
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| 109 | #define MAC_REG_PAPEDELAY 0x77 |
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| 110 | #define MAC_REG_SOFTPWRCTL 0x78 |
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| 111 | #define MAC_REG_GPIOCTL0 0x7A |
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| 112 | #define MAC_REG_GPIOCTL1 0x7B |
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| 113 | |
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| 114 | /* MAC DMA Related Group */ |
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| 115 | #define MAC_REG_TXDMACTL0 0x7C |
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| 116 | #define MAC_REG_TXDMAPTR0 0x80 |
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| 117 | #define MAC_REG_AC0DMACTL 0x84 |
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| 118 | #define MAC_REG_AC0DMAPTR 0x88 |
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| 119 | #define MAC_REG_BCNDMACTL 0x8C |
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| 120 | #define MAC_REG_BCNDMAPTR 0x90 |
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| 121 | #define MAC_REG_RXDMACTL0 0x94 |
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| 122 | #define MAC_REG_RXDMAPTR0 0x98 |
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| 123 | #define MAC_REG_RXDMACTL1 0x9C |
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| 124 | #define MAC_REG_RXDMAPTR1 0xA0 |
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| 125 | #define MAC_REG_SYNCDMACTL 0xA4 |
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| 126 | #define MAC_REG_SYNCDMAPTR 0xA8 |
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| 127 | #define MAC_REG_ATIMDMACTL 0xAC |
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| 128 | #define MAC_REG_ATIMDMAPTR 0xB0 |
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| 129 | |
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| 130 | /* MiscFF PIO related */ |
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| 131 | #define MAC_REG_MISCFFNDEX 0xB4 |
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| 132 | #define MAC_REG_MISCFFCTL 0xB6 |
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| 133 | #define MAC_REG_MISCFFDATA 0xB8 |
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| 134 | |
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| 135 | /* Extend SW Timer */ |
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| 136 | #define MAC_REG_TMDATA1 0xBC |
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| 137 | |
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| 138 | /* WOW Related Group */ |
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| 139 | #define MAC_REG_WAKEUPEN0 0xC0 |
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| 140 | #define MAC_REG_WAKEUPEN1 0xC1 |
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| 141 | #define MAC_REG_WAKEUPSR0 0xC2 |
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| 142 | #define MAC_REG_WAKEUPSR1 0xC3 |
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| 143 | #define MAC_REG_WAKE128_0 0xC4 |
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| 144 | #define MAC_REG_WAKE128_1 0xD4 |
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| 145 | #define MAC_REG_WAKE128_2 0xE4 |
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| 146 | #define MAC_REG_WAKE128_3 0xF4 |
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| 147 | |
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| 148 | /************** Page 1 ******************/ |
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| 149 | #define MAC_REG_CRC_128_0 0x04 |
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| 150 | #define MAC_REG_CRC_128_1 0x06 |
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| 151 | #define MAC_REG_CRC_128_2 0x08 |
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| 152 | #define MAC_REG_CRC_128_3 0x0A |
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| 153 | |
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| 154 | /* MAC Configuration Group */ |
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| 155 | #define MAC_REG_PAR0 0x0C |
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| 156 | #define MAC_REG_PAR4 0x10 |
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| 157 | #define MAC_REG_BSSID0 0x14 |
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| 158 | #define MAC_REG_BSSID4 0x18 |
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| 159 | #define MAC_REG_MAR0 0x1C |
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| 160 | #define MAC_REG_MAR4 0x20 |
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| 161 | |
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| 162 | /* MAC RSPPKT INFO Group */ |
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| 163 | #define MAC_REG_RSPINF_B_1 0x24 |
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| 164 | #define MAC_REG_RSPINF_B_2 0x28 |
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| 165 | #define MAC_REG_RSPINF_B_5 0x2C |
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| 166 | #define MAC_REG_RSPINF_B_11 0x30 |
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| 167 | #define MAC_REG_RSPINF_A_6 0x34 |
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| 168 | #define MAC_REG_RSPINF_A_9 0x36 |
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| 169 | #define MAC_REG_RSPINF_A_12 0x38 |
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| 170 | #define MAC_REG_RSPINF_A_18 0x3A |
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| 171 | #define MAC_REG_RSPINF_A_24 0x3C |
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| 172 | #define MAC_REG_RSPINF_A_36 0x3E |
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| 173 | #define MAC_REG_RSPINF_A_48 0x40 |
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| 174 | #define MAC_REG_RSPINF_A_54 0x42 |
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| 175 | #define MAC_REG_RSPINF_A_72 0x44 |
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| 176 | |
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| 177 | /* 802.11h relative */ |
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| 178 | #define MAC_REG_QUIETINIT 0x60 |
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| 179 | #define MAC_REG_QUIETGAP 0x62 |
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| 180 | #define MAC_REG_QUIETDUR 0x64 |
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| 181 | #define MAC_REG_MSRCTL 0x66 |
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| 182 | #define MAC_REG_MSRBBSTS 0x67 |
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| 183 | #define MAC_REG_MSRSTART 0x68 |
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| 184 | #define MAC_REG_MSRDURATION 0x70 |
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| 185 | #define MAC_REG_CCAFRACTION 0x72 |
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| 186 | #define MAC_REG_PWRCCK 0x73 |
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| 187 | #define MAC_REG_PWROFDM 0x7C |
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| 188 | |
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| 189 | /* Bits in the BCFG0 register */ |
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| 190 | #define BCFG0_PERROFF 0x40 |
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| 191 | #define BCFG0_MRDMDIS 0x20 |
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| 192 | #define BCFG0_MRDLDIS 0x10 |
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| 193 | #define BCFG0_MWMEN 0x08 |
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| 194 | #define BCFG0_VSERREN 0x02 |
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| 195 | #define BCFG0_LATMEN 0x01 |
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| 196 | |
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| 197 | /* Bits in the BCFG1 register */ |
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| 198 | #define BCFG1_CFUNOPT 0x80 |
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| 199 | #define BCFG1_CREQOPT 0x40 |
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| 200 | #define BCFG1_DMA8 0x10 |
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| 201 | #define BCFG1_ARBITOPT 0x08 |
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| 202 | #define BCFG1_PCIMEN 0x04 |
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| 203 | #define BCFG1_MIOEN 0x02 |
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| 204 | #define BCFG1_CISDLYEN 0x01 |
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| 205 | |
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| 206 | /* Bits in RAMBIST registers */ |
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| 207 | #define BISTCMD_TSTPAT5 0x00 |
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| 208 | #define BISTCMD_TSTPATA 0x80 |
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| 209 | #define BISTCMD_TSTERR 0x20 |
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| 210 | #define BISTCMD_TSTPATF 0x18 |
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| 211 | #define BISTCMD_TSTPAT0 0x10 |
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| 212 | #define BISTCMD_TSTMODE 0x04 |
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| 213 | #define BISTCMD_TSTITTX 0x03 |
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| 214 | #define BISTCMD_TSTATRX 0x02 |
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| 215 | #define BISTCMD_TSTATTX 0x01 |
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| 216 | #define BISTCMD_TSTRX 0x00 |
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| 217 | #define BISTSR0_BISTGO 0x01 |
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| 218 | #define BISTSR1_TSTSR 0x01 |
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| 219 | #define BISTSR2_CMDPRTEN 0x02 |
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| 220 | #define BISTSR2_RAMTSTEN 0x01 |
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| 221 | |
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| 222 | /* Bits in the I2MCFG EEPROM register */ |
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| 223 | #define I2MCFG_BOUNDCTL 0x80 |
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| 224 | #define I2MCFG_WAITCTL 0x20 |
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| 225 | #define I2MCFG_SCLOECTL 0x10 |
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| 226 | #define I2MCFG_WBUSYCTL 0x08 |
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| 227 | #define I2MCFG_NORETRY 0x04 |
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| 228 | #define I2MCFG_I2MLDSEQ 0x02 |
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| 229 | #define I2MCFG_I2CMFAST 0x01 |
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| 230 | |
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| 231 | /* Bits in the I2MCSR EEPROM register */ |
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| 232 | #define I2MCSR_EEMW 0x80 |
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| 233 | #define I2MCSR_EEMR 0x40 |
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| 234 | #define I2MCSR_AUTOLD 0x08 |
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| 235 | #define I2MCSR_NACK 0x02 |
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| 236 | #define I2MCSR_DONE 0x01 |
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| 237 | |
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| 238 | /* Bits in the PMC1 register */ |
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| 239 | #define SPS_RST 0x80 |
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| 240 | #define PCISTIKY 0x40 |
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| 241 | #define PME_OVR 0x02 |
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| 242 | |
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| 243 | /* Bits in the STICKYHW register */ |
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| 244 | #define STICKHW_DS1_SHADOW 0x02 |
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| 245 | #define STICKHW_DS0_SHADOW 0x01 |
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| 246 | |
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| 247 | /* Bits in the TMCTL register */ |
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| 248 | #define TMCTL_TSUSP 0x04 |
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| 249 | #define TMCTL_TMD 0x02 |
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| 250 | #define TMCTL_TE 0x01 |
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| 251 | |
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| 252 | /* Bits in the TFTCTL register */ |
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| 253 | #define TFTCTL_HWUTSF 0x80 |
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| 254 | #define TFTCTL_TBTTSYNC 0x40 |
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| 255 | #define TFTCTL_HWUTSFEN 0x20 |
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| 256 | #define TFTCTL_TSFCNTRRD 0x10 |
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| 257 | #define TFTCTL_TBTTSYNCEN 0x08 |
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| 258 | #define TFTCTL_TSFSYNCEN 0x04 |
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| 259 | #define TFTCTL_TSFCNTRST 0x02 |
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| 260 | #define TFTCTL_TSFCNTREN 0x01 |
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| 261 | |
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| 262 | /* Bits in the EnhanceCFG register */ |
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| 263 | #define ENCFG_BARKERPREAM 0x00020000 |
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| 264 | #define ENCFG_NXTBTTCFPSTR 0x00010000 |
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| 265 | #define ENCFG_BCNSUSCLR 0x00000200 |
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| 266 | #define ENCFG_BCNSUSIND 0x00000100 |
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| 267 | #define ENCFG_CFP_PROTECTEN 0x00000040 |
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| 268 | #define ENCFG_PROTECTMD 0x00000020 |
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| 269 | #define ENCFG_HWPARCFP 0x00000010 |
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| 270 | #define ENCFG_CFNULRSP 0x00000004 |
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| 271 | #define ENCFG_BBTYPE_MASK 0x00000003 |
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| 272 | #define ENCFG_BBTYPE_G 0x00000002 |
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| 273 | #define ENCFG_BBTYPE_B 0x00000001 |
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| 274 | #define ENCFG_BBTYPE_A 0x00000000 |
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| 275 | |
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| 276 | /* Bits in the Page1Sel register */ |
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| 277 | #define PAGE1_SEL 0x01 |
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| 278 | |
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| 279 | /* Bits in the CFG register */ |
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| 280 | #define CFG_TKIPOPT 0x80 |
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| 281 | #define CFG_RXDMAOPT 0x40 |
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| 282 | #define CFG_TMOT_SW 0x20 |
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| 283 | #define CFG_TMOT_HWLONG 0x10 |
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| 284 | #define CFG_TMOT_HW 0x00 |
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| 285 | #define CFG_CFPENDOPT 0x08 |
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| 286 | #define CFG_BCNSUSEN 0x04 |
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| 287 | #define CFG_NOTXTIMEOUT 0x02 |
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| 288 | #define CFG_NOBUFOPT 0x01 |
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| 289 | |
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| 290 | /* Bits in the TEST register */ |
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| 291 | #define TEST_LBEXT 0x80 |
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| 292 | #define TEST_LBINT 0x40 |
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| 293 | #define TEST_LBNONE 0x00 |
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| 294 | #define TEST_SOFTINT 0x20 |
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| 295 | #define TEST_CONTTX 0x10 |
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| 296 | #define TEST_TXPE 0x08 |
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| 297 | #define TEST_NAVDIS 0x04 |
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| 298 | #define TEST_NOCTS 0x02 |
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| 299 | #define TEST_NOACK 0x01 |
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| 300 | |
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| 301 | /* Bits in the HOSTCR register */ |
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| 302 | #define HOSTCR_TXONST 0x80 |
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| 303 | #define HOSTCR_RXONST 0x40 |
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| 304 | #define HOSTCR_ADHOC 0x20 /* Network Type 1 = Ad-hoc */ |
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| 305 | #define HOSTCR_AP 0x10 /* Port Type 1 = AP */ |
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| 306 | #define HOSTCR_TXON 0x08 /* 0000 1000 */ |
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| 307 | #define HOSTCR_RXON 0x04 /* 0000 0100 */ |
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| 308 | #define HOSTCR_MACEN 0x02 /* 0000 0010 */ |
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| 309 | #define HOSTCR_SOFTRST 0x01 /* 0000 0001 */ |
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| 310 | |
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| 311 | /* Bits in the MACCR register */ |
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| 312 | #define MACCR_SYNCFLUSHOK 0x04 |
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| 313 | #define MACCR_SYNCFLUSH 0x02 |
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| 314 | #define MACCR_CLRNAV 0x01 |
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| 315 | |
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| 316 | /* Bits in the MAC_REG_GPIOCTL0 register */ |
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| 317 | #define LED_ACTSET 0x01 |
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| 318 | #define LED_RFOFF 0x02 |
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| 319 | #define LED_NOCONNECT 0x04 |
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| 320 | |
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| 321 | /* Bits in the RCR register */ |
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| 322 | #define RCR_SSID 0x80 |
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| 323 | #define RCR_RXALLTYPE 0x40 |
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| 324 | #define RCR_UNICAST 0x20 |
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| 325 | #define RCR_BROADCAST 0x10 |
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| 326 | #define RCR_MULTICAST 0x08 |
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| 327 | #define RCR_WPAERR 0x04 |
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| 328 | #define RCR_ERRCRC 0x02 |
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| 329 | #define RCR_BSSID 0x01 |
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| 330 | |
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| 331 | /* Bits in the TCR register */ |
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| 332 | #define TCR_SYNCDCFOPT 0x02 |
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| 333 | #define TCR_AUTOBCNTX 0x01 /* Beacon automatically transmit enable */ |
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| 334 | |
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| 335 | /* Bits in the IMR register */ |
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| 336 | #define IMR_MEASURESTART 0x80000000 |
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| 337 | #define IMR_QUIETSTART 0x20000000 |
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| 338 | #define IMR_RADARDETECT 0x10000000 |
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| 339 | #define IMR_MEASUREEND 0x08000000 |
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| 340 | #define IMR_SOFTTIMER1 0x00200000 |
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| 341 | #define IMR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */ |
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| 342 | #define IMR_RXNOBUF 0x00000800 |
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| 343 | #define IMR_MIBNEARFULL 0x00000400 |
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| 344 | #define IMR_SOFTINT 0x00000200 |
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| 345 | #define IMR_FETALERR 0x00000100 |
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| 346 | #define IMR_WATCHDOG 0x00000080 |
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| 347 | #define IMR_SOFTTIMER 0x00000040 |
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| 348 | #define IMR_GPIO 0x00000020 |
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| 349 | #define IMR_TBTT 0x00000010 |
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| 350 | #define IMR_RXDMA0 0x00000008 |
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| 351 | #define IMR_BNTX 0x00000004 |
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| 352 | #define IMR_AC0DMA 0x00000002 |
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| 353 | #define IMR_TXDMA0 0x00000001 |
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| 354 | |
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| 355 | /* Bits in the ISR register */ |
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| 356 | #define ISR_MEASURESTART 0x80000000 |
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| 357 | #define ISR_QUIETSTART 0x20000000 |
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| 358 | #define ISR_RADARDETECT 0x10000000 |
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| 359 | #define ISR_MEASUREEND 0x08000000 |
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| 360 | #define ISR_SOFTTIMER1 0x00200000 |
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| 361 | #define ISR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */ |
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| 362 | #define ISR_RXNOBUF 0x00000800 /* 0000 0000 0000 1000 0000 0000 */ |
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| 363 | #define ISR_MIBNEARFULL 0x00000400 /* 0000 0000 0000 0100 0000 0000 */ |
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| 364 | #define ISR_SOFTINT 0x00000200 |
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| 365 | #define ISR_FETALERR 0x00000100 |
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| 366 | #define ISR_WATCHDOG 0x00000080 |
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| 367 | #define ISR_SOFTTIMER 0x00000040 |
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| 368 | #define ISR_GPIO 0x00000020 |
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| 369 | #define ISR_TBTT 0x00000010 |
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| 370 | #define ISR_RXDMA0 0x00000008 |
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| 371 | #define ISR_BNTX 0x00000004 |
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| 372 | #define ISR_AC0DMA 0x00000002 |
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| 373 | #define ISR_TXDMA0 0x00000001 |
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| 374 | |
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| 375 | /* Bits in the PSCFG register */ |
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| 376 | #define PSCFG_PHILIPMD 0x40 |
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| 377 | #define PSCFG_WAKECALEN 0x20 |
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| 378 | #define PSCFG_WAKETMREN 0x10 |
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| 379 | #define PSCFG_BBPSPROG 0x08 |
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| 380 | #define PSCFG_WAKESYN 0x04 |
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| 381 | #define PSCFG_SLEEPSYN 0x02 |
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| 382 | #define PSCFG_AUTOSLEEP 0x01 |
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| 383 | |
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| 384 | /* Bits in the PSCTL register */ |
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| 385 | #define PSCTL_WAKEDONE 0x20 |
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| 386 | #define PSCTL_PS 0x10 |
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| 387 | #define PSCTL_GO2DOZE 0x08 |
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| 388 | #define PSCTL_LNBCN 0x04 |
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| 389 | #define PSCTL_ALBCN 0x02 |
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| 390 | #define PSCTL_PSEN 0x01 |
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| 391 | |
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| 392 | /* Bits in the PSPWSIG register */ |
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| 393 | #define PSSIG_WPE3 0x80 |
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| 394 | #define PSSIG_WPE2 0x40 |
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| 395 | #define PSSIG_WPE1 0x20 |
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| 396 | #define PSSIG_WRADIOPE 0x10 |
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| 397 | #define PSSIG_SPE3 0x08 |
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| 398 | #define PSSIG_SPE2 0x04 |
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| 399 | #define PSSIG_SPE1 0x02 |
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| 400 | #define PSSIG_SRADIOPE 0x01 |
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| 401 | |
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| 402 | /* Bits in the BBREGCTL register */ |
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| 403 | #define BBREGCTL_DONE 0x04 |
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| 404 | #define BBREGCTL_REGR 0x02 |
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| 405 | #define BBREGCTL_REGW 0x01 |
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| 406 | |
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| 407 | /* Bits in the IFREGCTL register */ |
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| 408 | #define IFREGCTL_DONE 0x04 |
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| 409 | #define IFREGCTL_IFRF 0x02 |
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| 410 | #define IFREGCTL_REGW 0x01 |
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| 411 | |
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| 412 | /* Bits in the SOFTPWRCTL register */ |
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| 413 | #define SOFTPWRCTL_RFLEOPT 0x0800 |
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| 414 | #define SOFTPWRCTL_TXPEINV 0x0200 |
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| 415 | #define SOFTPWRCTL_SWPECTI 0x0100 |
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| 416 | #define SOFTPWRCTL_SWPAPE 0x0020 |
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| 417 | #define SOFTPWRCTL_SWCALEN 0x0010 |
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| 418 | #define SOFTPWRCTL_SWRADIO_PE 0x0008 |
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| 419 | #define SOFTPWRCTL_SWPE2 0x0004 |
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| 420 | #define SOFTPWRCTL_SWPE1 0x0002 |
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| 421 | #define SOFTPWRCTL_SWPE3 0x0001 |
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| 422 | |
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| 423 | /* Bits in the GPIOCTL1 register */ |
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| 424 | #define GPIO1_DATA1 0x20 |
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| 425 | #define GPIO1_MD1 0x10 |
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| 426 | #define GPIO1_DATA0 0x02 |
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| 427 | #define GPIO1_MD0 0x01 |
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| 428 | |
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| 429 | /* Bits in the DMACTL register */ |
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| 430 | #define DMACTL_CLRRUN 0x00080000 |
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| 431 | #define DMACTL_RUN 0x00000008 |
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| 432 | #define DMACTL_WAKE 0x00000004 |
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| 433 | #define DMACTL_DEAD 0x00000002 |
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| 434 | #define DMACTL_ACTIVE 0x00000001 |
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| 435 | |
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| 436 | /* Bits in the RXDMACTL0 register */ |
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| 437 | #define RX_PERPKT 0x00000100 |
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| 438 | #define RX_PERPKTCLR 0x01000000 |
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| 439 | |
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| 440 | /* Bits in the BCNDMACTL register */ |
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| 441 | #define BEACON_READY 0x01 |
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| 442 | |
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| 443 | /* Bits in the MISCFFCTL register */ |
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| 444 | #define MISCFFCTL_WRITE 0x0001 |
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| 445 | |
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| 446 | /* Bits in WAKEUPEN0 */ |
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| 447 | #define WAKEUPEN0_DIRPKT 0x10 |
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| 448 | #define WAKEUPEN0_LINKOFF 0x08 |
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| 449 | #define WAKEUPEN0_ATIMEN 0x04 |
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| 450 | #define WAKEUPEN0_TIMEN 0x02 |
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| 451 | #define WAKEUPEN0_MAGICEN 0x01 |
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| 452 | |
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| 453 | /* Bits in WAKEUPEN1 */ |
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| 454 | #define WAKEUPEN1_128_3 0x08 |
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| 455 | #define WAKEUPEN1_128_2 0x04 |
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| 456 | #define WAKEUPEN1_128_1 0x02 |
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| 457 | #define WAKEUPEN1_128_0 0x01 |
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| 458 | |
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| 459 | /* Bits in WAKEUPSR0 */ |
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| 460 | #define WAKEUPSR0_DIRPKT 0x10 |
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| 461 | #define WAKEUPSR0_LINKOFF 0x08 |
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| 462 | #define WAKEUPSR0_ATIMEN 0x04 |
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| 463 | #define WAKEUPSR0_TIMEN 0x02 |
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| 464 | #define WAKEUPSR0_MAGICEN 0x01 |
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| 465 | |
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| 466 | /* Bits in WAKEUPSR1 */ |
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| 467 | #define WAKEUPSR1_128_3 0x08 |
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| 468 | #define WAKEUPSR1_128_2 0x04 |
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| 469 | #define WAKEUPSR1_128_1 0x02 |
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| 470 | #define WAKEUPSR1_128_0 0x01 |
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| 471 | |
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| 472 | /* Bits in the MAC_REG_GPIOCTL register */ |
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| 473 | #define GPIO0_MD 0x01 |
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| 474 | #define GPIO0_DATA 0x02 |
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| 475 | #define GPIO0_INTMD 0x04 |
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| 476 | #define GPIO1_MD 0x10 |
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| 477 | #define GPIO1_DATA 0x20 |
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| 478 | |
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| 479 | /* Bits in the MSRCTL register */ |
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| 480 | #define MSRCTL_FINISH 0x80 |
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| 481 | #define MSRCTL_READY 0x40 |
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| 482 | #define MSRCTL_RADARDETECT 0x20 |
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| 483 | #define MSRCTL_EN 0x10 |
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| 484 | #define MSRCTL_QUIETTXCHK 0x08 |
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| 485 | #define MSRCTL_QUIETRPT 0x04 |
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| 486 | #define MSRCTL_QUIETINT 0x02 |
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| 487 | #define MSRCTL_QUIETEN 0x01 |
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| 488 | |
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| 489 | /* Bits in the MSRCTL1 register */ |
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| 490 | #define MSRCTL1_TXPWR 0x08 |
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| 491 | #define MSRCTL1_CSAPAREN 0x04 |
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| 492 | #define MSRCTL1_TXPAUSE 0x01 |
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| 493 | |
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| 494 | /* Loopback mode */ |
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| 495 | #define MAC_LB_EXT 0x02 |
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| 496 | #define MAC_LB_INTERNAL 0x01 |
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| 497 | #define MAC_LB_NONE 0x00 |
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| 498 | |
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| 499 | #define DEFAULT_BI 0x200 |
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| 500 | |
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| 501 | /* MiscFIFO Offset */ |
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| 502 | #define MISCFIFO_KEYETRY0 32 |
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| 503 | #define MISCFIFO_KEYENTRYSIZE 22 |
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| 504 | #define MISCFIFO_SYNINFO_IDX 10 |
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| 505 | #define MISCFIFO_SYNDATA_IDX 11 |
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| 506 | #define MISCFIFO_SYNDATASIZE 21 |
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| 507 | |
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| 508 | /* enabled mask value of irq */ |
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| 509 | #define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \ |
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| 510 | IMR_RXDMA1 | \ |
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| 511 | IMR_RXNOBUF | \ |
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| 512 | IMR_MIBNEARFULL | \ |
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| 513 | IMR_SOFTINT | \ |
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| 514 | IMR_FETALERR | \ |
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| 515 | IMR_WATCHDOG | \ |
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| 516 | IMR_SOFTTIMER | \ |
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| 517 | IMR_GPIO | \ |
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| 518 | IMR_TBTT | \ |
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| 519 | IMR_RXDMA0 | \ |
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| 520 | IMR_BNTX | \ |
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| 521 | IMR_AC0DMA | \ |
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| 522 | IMR_TXDMA0) |
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| 523 | |
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| 524 | /* max time out delay time */ |
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| 525 | #define W_MAX_TIMEOUT 0xFFF0U |
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| 526 | |
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| 527 | /* wait time within loop */ |
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| 528 | #define CB_DELAY_LOOP_WAIT 10 /* 10ms */ |
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| 529 | |
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| 530 | /* revision id */ |
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| 531 | #define REV_ID_VT3253_A0 0x00 |
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| 532 | #define REV_ID_VT3253_A1 0x01 |
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| 533 | #define REV_ID_VT3253_B0 0x08 |
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| 534 | #define REV_ID_VT3253_B1 0x09 |
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| 535 | |
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| 536 | /*--------------------- Export Types ------------------------------*/ |
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| 537 | |
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| 538 | /*--------------------- Export Macros ------------------------------*/ |
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| 539 | |
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| 540 | #define VT6655_MAC_SELECT_PAGE0(iobase) iowrite8(0, iobase + MAC_REG_PAGE1SEL) |
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| 541 | |
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| 542 | #define VT6655_MAC_SELECT_PAGE1(iobase) iowrite8(1, iobase + MAC_REG_PAGE1SEL) |
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| 543 | |
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| 544 | #define MAKEWORD(lb, hb) \ |
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| 545 | ((unsigned short)(((unsigned char)(lb)) | (((unsigned short)((unsigned char)(hb))) << 8))) |
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| 546 | |
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| 547 | void vt6655_mac_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask); |
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| 548 | void vt6655_mac_word_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask); |
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| 549 | void vt6655_mac_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask); |
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| 550 | void vt6655_mac_word_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask); |
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| 551 | |
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| 552 | void vt6655_mac_set_short_retry_limit(struct vnt_private *priv, unsigned char retry_limit); |
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| 553 | |
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| 554 | void MACvSetLongRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit); |
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| 555 | |
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| 556 | bool MACbSoftwareReset(struct vnt_private *priv); |
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| 557 | bool MACbShutdown(struct vnt_private *priv); |
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| 558 | void MACvInitialize(struct vnt_private *priv); |
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| 559 | void vt6655_mac_set_curr_rx_0_desc_addr(struct vnt_private *priv, u32 curr_desc_addr); |
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| 560 | void vt6655_mac_set_curr_rx_1_desc_addr(struct vnt_private *priv, u32 curr_desc_addr); |
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| 561 | void vt6655_mac_set_curr_tx_desc_addr(int tx_type, struct vnt_private *priv, u32 curr_desc_addr); |
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| 562 | void MACvSetCurrSyncDescAddrEx(struct vnt_private *priv, |
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| 563 | u32 curr_desc_addr); |
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| 564 | void MACvSetCurrATIMDescAddrEx(struct vnt_private *priv, |
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| 565 | u32 curr_desc_addr); |
|---|
| 566 | void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay); |
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| 567 | void MACvOneShotTimer1MicroSec(struct vnt_private *priv, unsigned int uDelayTime); |
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| 568 | |
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| 569 | void MACvSetMISCFifo(struct vnt_private *priv, unsigned short wOffset, |
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| 570 | u32 dwData); |
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| 571 | |
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| 572 | bool MACbPSWakeup(struct vnt_private *priv); |
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| 573 | |
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| 574 | void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl, |
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| 575 | unsigned int uEntryIdx, unsigned int uKeyIdx, |
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| 576 | unsigned char *pbyAddr, u32 *pdwKey, |
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| 577 | unsigned char local_id); |
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| 578 | void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx); |
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| 579 | |
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| 580 | #endif /* __MAC_H__ */ |
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| 581 | |
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