1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* USB4 specific functionality
4	*
5	* Copyright (C) 2019, Intel Corporation
6	* Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7	* Rajmohan Mani <rajmohan.mani@intel.com>
8	*/
9
10	#include <linux/delay.h>
11	#include <linux/ktime.h>
12	#include <linux/units.h>
13
14	#include "sb_regs.h"
15	#include "tb.h"
16
17	#define USB4_DATA_RETRIES 3
18	#define USB4_DATA_DWORDS 16
19
20	enum usb4_sb_target {
21	USB4_SB_TARGET_ROUTER,
22	USB4_SB_TARGET_PARTNER,
23	USB4_SB_TARGET_RETIMER,
24	};
25
26	#define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)
27	#define USB4_NVM_READ_OFFSET_SHIFT 2
28	#define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)
29	#define USB4_NVM_READ_LENGTH_SHIFT 24
30
31	#define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK
32	#define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT
33
34	#define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)
35	#define USB4_DROM_ADDRESS_SHIFT 2
36	#define USB4_DROM_SIZE_MASK GENMASK(19, 15)
37	#define USB4_DROM_SIZE_SHIFT 15
38
39	#define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)
40
41	#define USB4_BA_LENGTH_MASK GENMASK(7, 0)
42	#define USB4_BA_INDEX_MASK GENMASK(15, 0)
43
44	enum usb4_ba_index {
45	USB4_BA_MAX_USB3 = 0x1,
46	USB4_BA_MIN_DP_AUX = 0x2,
47	USB4_BA_MIN_DP_MAIN = 0x3,
48	USB4_BA_MAX_PCIE = 0x4,
49	USB4_BA_MAX_HI = 0x5,
50	};
51
52	#define USB4_BA_VALUE_MASK GENMASK(31, 16)
53	#define USB4_BA_VALUE_SHIFT 16
54
55	static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode,
56	u32 *metadata, u8 *status,
57	const void *tx_data, size_t tx_dwords,
58	void *rx_data, size_t rx_dwords)
59	{
60	u32 val;
61	int ret;
62
63	if (metadata) {
64	ret = tb_sw_write(sw, buffer: metadata, space: TB_CFG_SWITCH, ROUTER_CS_25, length: 1);
65	if (ret)
66	return ret;
67	}
68	if (tx_dwords) {
69	ret = tb_sw_write(sw, buffer: tx_data, space: TB_CFG_SWITCH, ROUTER_CS_9,
70	length: tx_dwords);
71	if (ret)
72	return ret;
73	}
74
75	val = opcode | ROUTER_CS_26_OV;
76	ret = tb_sw_write(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_26, length: 1);
77	if (ret)
78	return ret;
79
80	ret = tb_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, value: 0, timeout_msec: 500);
81	if (ret)
82	return ret;
83
84	ret = tb_sw_read(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_26, length: 1);
85	if (ret)
86	return ret;
87
88	if (val & ROUTER_CS_26_ONS)
89	return -EOPNOTSUPP;
90
91	if (status)
92	*status = (val & ROUTER_CS_26_STATUS_MASK) >>
93	ROUTER_CS_26_STATUS_SHIFT;
94
95	if (metadata) {
96	ret = tb_sw_read(sw, buffer: metadata, space: TB_CFG_SWITCH, ROUTER_CS_25, length: 1);
97	if (ret)
98	return ret;
99	}
100	if (rx_dwords) {
101	ret = tb_sw_read(sw, buffer: rx_data, space: TB_CFG_SWITCH, ROUTER_CS_9,
102	length: rx_dwords);
103	if (ret)
104	return ret;
105	}
106
107	return 0;
108	}
109
110	static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata,
111	u8 *status, const void *tx_data, size_t tx_dwords,
112	void *rx_data, size_t rx_dwords)
113	{
114	const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
115
116	if (tx_dwords > USB4_DATA_DWORDS || rx_dwords > USB4_DATA_DWORDS)
117	return -EINVAL;
118
119	/*
120	* If the connection manager implementation provides USB4 router
121	* operation proxy callback, call it here instead of running the
122	* operation natively.
123	*/
124	if (cm_ops->usb4_switch_op) {
125	int ret;
126
127	ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status,
128	tx_data, tx_dwords, rx_data,
129	rx_dwords);
130	if (ret != -EOPNOTSUPP)
131	return ret;
132
133	/*
134	* If the proxy was not supported then run the native
135	* router operation instead.
136	*/
137	}
138
139	return usb4_native_switch_op(sw, opcode, metadata, status, tx_data,
140	tx_dwords, rx_data, rx_dwords);
141	}
142
143	static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode,
144	u32 *metadata, u8 *status)
145	{
146	return __usb4_switch_op(sw, opcode, metadata, status, NULL, tx_dwords: 0, NULL, rx_dwords: 0);
147	}
148
149	static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode,
150	u32 *metadata, u8 *status,
151	const void *tx_data, size_t tx_dwords,
152	void *rx_data, size_t rx_dwords)
153	{
154	return __usb4_switch_op(sw, opcode, metadata, status, tx_data,
155	tx_dwords, rx_data, rx_dwords);
156	}
157
158	/**
159	* usb4_switch_check_wakes() - Check for wakes and notify PM core about them
160	* @sw: Router whose wakes to check
161	*
162	* Checks wakes occurred during suspend and notify the PM core about them.
163	*/
164	void usb4_switch_check_wakes(struct tb_switch *sw)
165	{
166	bool wakeup_usb4 = false;
167	struct usb4_port *usb4;
168	struct tb_port *port;
169	bool wakeup = false;
170	u32 val;
171
172	if (tb_route(sw)) {
173	if (tb_sw_read(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_6, length: 1))
174	return;
175
176	tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n",
177	(val & ROUTER_CS_6_WOPS) ? "yes" : "no",
178	(val & ROUTER_CS_6_WOUS) ? "yes" : "no");
179
180	wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS);
181	}
182
183	/*
184	* Check for any downstream ports for USB4 wake,
185	* connection wake and disconnection wake.
186	*/
187	tb_switch_for_each_port(sw, port) {
188	if (!port->cap_usb4)
189	continue;
190
191	if (tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
192	offset: port->cap_usb4 + PORT_CS_18, length: 1))
193	break;
194
195	tb_port_dbg(port, "USB4 wake: %s, connection wake: %s, disconnection wake: %s\n",
196	(val & PORT_CS_18_WOU4S) ? "yes" : "no",
197	(val & PORT_CS_18_WOCS) ? "yes" : "no",
198	(val & PORT_CS_18_WODS) ? "yes" : "no");
199
200	wakeup_usb4 = val & (PORT_CS_18_WOU4S | PORT_CS_18_WOCS |
201	PORT_CS_18_WODS);
202
203	usb4 = port->usb4;
204	if (device_may_wakeup(dev: &usb4->dev) && wakeup_usb4)
205	pm_wakeup_event(dev: &usb4->dev, msec: 0);
206
207	wakeup |= wakeup_usb4;
208	}
209
210	if (wakeup)
211	pm_wakeup_event(dev: &sw->dev, msec: 0);
212	}
213
214	static bool link_is_usb4(struct tb_port *port)
215	{
216	u32 val;
217
218	if (!port->cap_usb4)
219	return false;
220
221	if (tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
222	offset: port->cap_usb4 + PORT_CS_18, length: 1))
223	return false;
224
225	return !(val & PORT_CS_18_TCM);
226	}
227
228	/**
229	* usb4_switch_setup() - Additional setup for USB4 device
230	* @sw: USB4 router to setup
231	*
232	* USB4 routers need additional settings in order to enable all the
233	* tunneling. This function enables USB and PCIe tunneling if it can be
234	* enabled (e.g the parent switch also supports them). If USB tunneling
235	* is not available for some reason (like that there is Thunderbolt 3
236	* switch upstream) then the internal xHCI controller is enabled
237	* instead.
238	*
239	* This does not set the configuration valid bit of the router. To do
240	* that call usb4_switch_configuration_valid().
241	*/
242	int usb4_switch_setup(struct tb_switch *sw)
243	{
244	struct tb_switch *parent = tb_switch_parent(sw);
245	struct tb_port *down;
246	bool tbt3, xhci;
247	u32 val = 0;
248	int ret;
249
250	if (!tb_route(sw))
251	return 0;
252
253	ret = tb_sw_read(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_6, length: 1);
254	if (ret)
255	return ret;
256
257	down = tb_switch_downstream_port(sw);
258	sw->link_usb4 = link_is_usb4(port: down);
259	tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT");
260
261	xhci = val & ROUTER_CS_6_HCI;
262	tbt3 = !(val & ROUTER_CS_6_TNS);
263
264	tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
265	tbt3 ? "yes" : "no", xhci ? "yes" : "no");
266
267	ret = tb_sw_read(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_5, length: 1);
268	if (ret)
269	return ret;
270
271	if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 &&
272	tb_switch_find_port(sw: parent, type: TB_TYPE_USB3_DOWN)) {
273	val |= ROUTER_CS_5_UTO;
274	xhci = false;
275	}
276
277	/*
278	* Only enable PCIe tunneling if the parent router supports it
279	* and it is not disabled.
280	*/
281	if (tb_acpi_may_tunnel_pcie() &&
282	tb_switch_find_port(sw: parent, type: TB_TYPE_PCIE_DOWN)) {
283	val |= ROUTER_CS_5_PTO;
284	/*
285	* xHCI can be enabled if PCIe tunneling is supported
286	* and the parent does not have any USB3 dowstream
287	* adapters (so we cannot do USB 3.x tunneling).
288	*/
289	if (xhci)
290	val |= ROUTER_CS_5_HCO;
291	}
292
293	/* TBT3 supported by the CM */
294	val &= ~ROUTER_CS_5_CNS;
295
296	return tb_sw_write(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_5, length: 1);
297	}
298
299	/**
300	* usb4_switch_configuration_valid() - Set tunneling configuration to be valid
301	* @sw: USB4 router
302	*
303	* Sets configuration valid bit for the router. Must be called before
304	* any tunnels can be set through the router and after
305	* usb4_switch_setup() has been called. Can be called to host and device
306	* routers (does nothing for the latter).
307	*
308	* Returns %0 in success and negative errno otherwise.
309	*/
310	int usb4_switch_configuration_valid(struct tb_switch *sw)
311	{
312	u32 val;
313	int ret;
314
315	if (!tb_route(sw))
316	return 0;
317
318	ret = tb_sw_read(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_5, length: 1);
319	if (ret)
320	return ret;
321
322	val |= ROUTER_CS_5_CV;
323
324	ret = tb_sw_write(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_5, length: 1);
325	if (ret)
326	return ret;
327
328	return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
329	ROUTER_CS_6_CR, timeout_msec: 50);
330	}
331
332	/**
333	* usb4_switch_read_uid() - Read UID from USB4 router
334	* @sw: USB4 router
335	* @uid: UID is stored here
336	*
337	* Reads 64-bit UID from USB4 router config space.
338	*/
339	int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
340	{
341	return tb_sw_read(sw, buffer: uid, space: TB_CFG_SWITCH, ROUTER_CS_7, length: 2);
342	}
343
344	static int usb4_switch_drom_read_block(void *data,
345	unsigned int dwaddress, void *buf,
346	size_t dwords)
347	{
348	struct tb_switch *sw = data;
349	u8 status = 0;
350	u32 metadata;
351	int ret;
352
353	metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
354	metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
355	USB4_DROM_ADDRESS_MASK;
356
357	ret = usb4_switch_op_data(sw, opcode: USB4_SWITCH_OP_DROM_READ, metadata: &metadata,
358	status: &status, NULL, tx_dwords: 0, rx_data: buf, rx_dwords: dwords);
359	if (ret)
360	return ret;
361
362	return status ? -EIO : 0;
363	}
364
365	/**
366	* usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
367	* @sw: USB4 router
368	* @address: Byte address inside DROM to start reading
369	* @buf: Buffer where the DROM content is stored
370	* @size: Number of bytes to read from DROM
371	*
372	* Uses USB4 router operations to read router DROM. For devices this
373	* should always work but for hosts it may return %-EOPNOTSUPP in which
374	* case the host router does not have DROM.
375	*/
376	int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
377	size_t size)
378	{
379	return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
380	read_block: usb4_switch_drom_read_block, read_block_data: sw);
381	}
382
383	/**
384	* usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
385	* @sw: USB4 router
386	*
387	* Checks whether conditions are met so that lane bonding can be
388	* established with the upstream router. Call only for device routers.
389	*/
390	bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
391	{
392	struct tb_port *up;
393	int ret;
394	u32 val;
395
396	up = tb_upstream_port(sw);
397	ret = tb_port_read(port: up, buffer: &val, space: TB_CFG_PORT, offset: up->cap_usb4 + PORT_CS_18, length: 1);
398	if (ret)
399	return false;
400
401	return !!(val & PORT_CS_18_BE);
402	}
403
404	/**
405	* usb4_switch_set_wake() - Enabled/disable wake
406	* @sw: USB4 router
407	* @flags: Wakeup flags (%0 to disable)
408	*
409	* Enables/disables router to wake up from sleep.
410	*/
411	int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags)
412	{
413	struct usb4_port *usb4;
414	struct tb_port *port;
415	u64 route = tb_route(sw);
416	u32 val;
417	int ret;
418
419	/*
420	* Enable wakes coming from all USB4 downstream ports (from
421	* child routers). For device routers do this also for the
422	* upstream USB4 port.
423	*/
424	tb_switch_for_each_port(sw, port) {
425	if (!tb_port_is_null(port))
426	continue;
427	if (!route && tb_is_upstream_port(port))
428	continue;
429	if (!port->cap_usb4)
430	continue;
431
432	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
433	offset: port->cap_usb4 + PORT_CS_19, length: 1);
434	if (ret)
435	return ret;
436
437	val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4);
438
439	if (tb_is_upstream_port(port)) {
440	val |= PORT_CS_19_WOU4;
441	} else {
442	bool configured = val & PORT_CS_19_PC;
443	usb4 = port->usb4;
444
445	if (((flags & TB_WAKE_ON_CONNECT) |
446	device_may_wakeup(dev: &usb4->dev)) && !configured)
447	val |= PORT_CS_19_WOC;
448	if (((flags & TB_WAKE_ON_DISCONNECT) |
449	device_may_wakeup(dev: &usb4->dev)) && configured)
450	val |= PORT_CS_19_WOD;
451	if ((flags & TB_WAKE_ON_USB4) && configured)
452	val |= PORT_CS_19_WOU4;
453	}
454
455	ret = tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
456	offset: port->cap_usb4 + PORT_CS_19, length: 1);
457	if (ret)
458	return ret;
459	}
460
461	/*
462	* Enable wakes from PCIe, USB 3.x and DP on this router. Only
463	* needed for device routers.
464	*/
465	if (route) {
466	ret = tb_sw_read(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_5, length: 1);
467	if (ret)
468	return ret;
469
470	val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU | ROUTER_CS_5_WOD);
471	if (flags & TB_WAKE_ON_USB3)
472	val |= ROUTER_CS_5_WOU;
473	if (flags & TB_WAKE_ON_PCIE)
474	val |= ROUTER_CS_5_WOP;
475	if (flags & TB_WAKE_ON_DP)
476	val |= ROUTER_CS_5_WOD;
477
478	ret = tb_sw_write(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_5, length: 1);
479	if (ret)
480	return ret;
481	}
482
483	return 0;
484	}
485
486	/**
487	* usb4_switch_set_sleep() - Prepare the router to enter sleep
488	* @sw: USB4 router
489	*
490	* Sets sleep bit for the router. Returns when the router sleep ready
491	* bit has been asserted.
492	*/
493	int usb4_switch_set_sleep(struct tb_switch *sw)
494	{
495	int ret;
496	u32 val;
497
498	/* Set sleep bit and wait for sleep ready to be asserted */
499	ret = tb_sw_read(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_5, length: 1);
500	if (ret)
501	return ret;
502
503	val |= ROUTER_CS_5_SLP;
504
505	ret = tb_sw_write(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_5, length: 1);
506	if (ret)
507	return ret;
508
509	return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
510	ROUTER_CS_6_SLPR, timeout_msec: 500);
511	}
512
513	/**
514	* usb4_switch_nvm_sector_size() - Return router NVM sector size
515	* @sw: USB4 router
516	*
517	* If the router supports NVM operations this function returns the NVM
518	* sector size in bytes. If NVM operations are not supported returns
519	* %-EOPNOTSUPP.
520	*/
521	int usb4_switch_nvm_sector_size(struct tb_switch *sw)
522	{
523	u32 metadata;
524	u8 status;
525	int ret;
526
527	ret = usb4_switch_op(sw, opcode: USB4_SWITCH_OP_NVM_SECTOR_SIZE, metadata: &metadata,
528	status: &status);
529	if (ret)
530	return ret;
531
532	if (status)
533	return status == 0x2 ? -EOPNOTSUPP : -EIO;
534
535	return metadata & USB4_NVM_SECTOR_SIZE_MASK;
536	}
537
538	static int usb4_switch_nvm_read_block(void *data,
539	unsigned int dwaddress, void *buf, size_t dwords)
540	{
541	struct tb_switch *sw = data;
542	u8 status = 0;
543	u32 metadata;
544	int ret;
545
546	metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
547	USB4_NVM_READ_LENGTH_MASK;
548	metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
549	USB4_NVM_READ_OFFSET_MASK;
550
551	ret = usb4_switch_op_data(sw, opcode: USB4_SWITCH_OP_NVM_READ, metadata: &metadata,
552	status: &status, NULL, tx_dwords: 0, rx_data: buf, rx_dwords: dwords);
553	if (ret)
554	return ret;
555
556	return status ? -EIO : 0;
557	}
558
559	/**
560	* usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
561	* @sw: USB4 router
562	* @address: Starting address in bytes
563	* @buf: Read data is placed here
564	* @size: How many bytes to read
565	*
566	* Reads NVM contents of the router. If NVM is not supported returns
567	* %-EOPNOTSUPP.
568	*/
569	int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
570	size_t size)
571	{
572	return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
573	read_block: usb4_switch_nvm_read_block, read_block_data: sw);
574	}
575
576	/**
577	* usb4_switch_nvm_set_offset() - Set NVM write offset
578	* @sw: USB4 router
579	* @address: Start offset
580	*
581	* Explicitly sets NVM write offset. Normally when writing to NVM this
582	* is done automatically by usb4_switch_nvm_write().
583	*
584	* Returns %0 in success and negative errno if there was a failure.
585	*/
586	int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address)
587	{
588	u32 metadata, dwaddress;
589	u8 status = 0;
590	int ret;
591
592	dwaddress = address / 4;
593	metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
594	USB4_NVM_SET_OFFSET_MASK;
595
596	ret = usb4_switch_op(sw, opcode: USB4_SWITCH_OP_NVM_SET_OFFSET, metadata: &metadata,
597	status: &status);
598	if (ret)
599	return ret;
600
601	return status ? -EIO : 0;
602	}
603
604	static int usb4_switch_nvm_write_next_block(void *data, unsigned int dwaddress,
605	const void *buf, size_t dwords)
606	{
607	struct tb_switch *sw = data;
608	u8 status;
609	int ret;
610
611	ret = usb4_switch_op_data(sw, opcode: USB4_SWITCH_OP_NVM_WRITE, NULL, status: &status,
612	tx_data: buf, tx_dwords: dwords, NULL, rx_dwords: 0);
613	if (ret)
614	return ret;
615
616	return status ? -EIO : 0;
617	}
618
619	/**
620	* usb4_switch_nvm_write() - Write to the router NVM
621	* @sw: USB4 router
622	* @address: Start address where to write in bytes
623	* @buf: Pointer to the data to write
624	* @size: Size of @buf in bytes
625	*
626	* Writes @buf to the router NVM using USB4 router operations. If NVM
627	* write is not supported returns %-EOPNOTSUPP.
628	*/
629	int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
630	const void *buf, size_t size)
631	{
632	int ret;
633
634	ret = usb4_switch_nvm_set_offset(sw, address);
635	if (ret)
636	return ret;
637
638	return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
639	write_next_block: usb4_switch_nvm_write_next_block, write_block_data: sw);
640	}
641
642	/**
643	* usb4_switch_nvm_authenticate() - Authenticate new NVM
644	* @sw: USB4 router
645	*
646	* After the new NVM has been written via usb4_switch_nvm_write(), this
647	* function triggers NVM authentication process. The router gets power
648	* cycled and if the authentication is successful the new NVM starts
649	* running. In case of failure returns negative errno.
650	*
651	* The caller should call usb4_switch_nvm_authenticate_status() to read
652	* the status of the authentication after power cycle. It should be the
653	* first router operation to avoid the status being lost.
654	*/
655	int usb4_switch_nvm_authenticate(struct tb_switch *sw)
656	{
657	int ret;
658
659	ret = usb4_switch_op(sw, opcode: USB4_SWITCH_OP_NVM_AUTH, NULL, NULL);
660	switch (ret) {
661	/*
662	* The router is power cycled once NVM_AUTH is started so it is
663	* expected to get any of the following errors back.
664	*/
665	case -EACCES:
666	case -ENOTCONN:
667	case -ETIMEDOUT:
668	return 0;
669
670	default:
671	return ret;
672	}
673	}
674
675	/**
676	* usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate
677	* @sw: USB4 router
678	* @status: Status code of the operation
679	*
680	* The function checks if there is status available from the last NVM
681	* authenticate router operation. If there is status then %0 is returned
682	* and the status code is placed in @status. Returns negative errno in case
683	* of failure.
684	*
685	* Must be called before any other router operation.
686	*/
687	int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status)
688	{
689	const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
690	u16 opcode;
691	u32 val;
692	int ret;
693
694	if (cm_ops->usb4_switch_nvm_authenticate_status) {
695	ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status);
696	if (ret != -EOPNOTSUPP)
697	return ret;
698	}
699
700	ret = tb_sw_read(sw, buffer: &val, space: TB_CFG_SWITCH, ROUTER_CS_26, length: 1);
701	if (ret)
702	return ret;
703
704	/* Check that the opcode is correct */
705	opcode = val & ROUTER_CS_26_OPCODE_MASK;
706	if (opcode == USB4_SWITCH_OP_NVM_AUTH) {
707	if (val & ROUTER_CS_26_OV)
708	return -EBUSY;
709	if (val & ROUTER_CS_26_ONS)
710	return -EOPNOTSUPP;
711
712	*status = (val & ROUTER_CS_26_STATUS_MASK) >>
713	ROUTER_CS_26_STATUS_SHIFT;
714	} else {
715	*status = 0;
716	}
717
718	return 0;
719	}
720
721	/**
722	* usb4_switch_credits_init() - Read buffer allocation parameters
723	* @sw: USB4 router
724	*
725	* Reads @sw buffer allocation parameters and initializes @sw buffer
726	* allocation fields accordingly. Specifically @sw->credits_allocation
727	* is set to %true if these parameters can be used in tunneling.
728	*
729	* Returns %0 on success and negative errno otherwise.
730	*/
731	int usb4_switch_credits_init(struct tb_switch *sw)
732	{
733	int max_usb3, min_dp_aux, min_dp_main, max_pcie, max_dma;
734	int ret, length, i, nports;
735	const struct tb_port *port;
736	u32 data[USB4_DATA_DWORDS];
737	u32 metadata = 0;
738	u8 status = 0;
739
740	memset(data, 0, sizeof(data));
741	ret = usb4_switch_op_data(sw, opcode: USB4_SWITCH_OP_BUFFER_ALLOC, metadata: &metadata,
742	status: &status, NULL, tx_dwords: 0, rx_data: data, ARRAY_SIZE(data));
743	if (ret)
744	return ret;
745	if (status)
746	return -EIO;
747
748	length = metadata & USB4_BA_LENGTH_MASK;
749	if (WARN_ON(length > ARRAY_SIZE(data)))
750	return -EMSGSIZE;
751
752	max_usb3 = -1;
753	min_dp_aux = -1;
754	min_dp_main = -1;
755	max_pcie = -1;
756	max_dma = -1;
757
758	tb_sw_dbg(sw, "credit allocation parameters:\n");
759
760	for (i = 0; i < length; i++) {
761	u16 index, value;
762
763	index = data[i] & USB4_BA_INDEX_MASK;
764	value = (data[i] & USB4_BA_VALUE_MASK) >> USB4_BA_VALUE_SHIFT;
765
766	switch (index) {
767	case USB4_BA_MAX_USB3:
768	tb_sw_dbg(sw, " USB3: %u\n", value);
769	max_usb3 = value;
770	break;
771	case USB4_BA_MIN_DP_AUX:
772	tb_sw_dbg(sw, " DP AUX: %u\n", value);
773	min_dp_aux = value;
774	break;
775	case USB4_BA_MIN_DP_MAIN:
776	tb_sw_dbg(sw, " DP main: %u\n", value);
777	min_dp_main = value;
778	break;
779	case USB4_BA_MAX_PCIE:
780	tb_sw_dbg(sw, " PCIe: %u\n", value);
781	max_pcie = value;
782	break;
783	case USB4_BA_MAX_HI:
784	tb_sw_dbg(sw, " DMA: %u\n", value);
785	max_dma = value;
786	break;
787	default:
788	tb_sw_dbg(sw, " unknown credit allocation index %#x, skipping\n",
789	index);
790	break;
791	}
792	}
793
794	/*
795	* Validate the buffer allocation preferences. If we find
796	* issues, log a warning and fall back using the hard-coded
797	* values.
798	*/
799
800	/* Host router must report baMaxHI */
801	if (!tb_route(sw) && max_dma < 0) {
802	tb_sw_warn(sw, "host router is missing baMaxHI\n");
803	goto err_invalid;
804	}
805
806	nports = 0;
807	tb_switch_for_each_port(sw, port) {
808	if (tb_port_is_null(port))
809	nports++;
810	}
811
812	/* Must have DP buffer allocation (multiple USB4 ports) */
813	if (nports > 2 && (min_dp_aux < 0 || min_dp_main < 0)) {
814	tb_sw_warn(sw, "multiple USB4 ports require baMinDPaux/baMinDPmain\n");
815	goto err_invalid;
816	}
817
818	tb_switch_for_each_port(sw, port) {
819	if (tb_port_is_dpout(port) && min_dp_main < 0) {
820	tb_sw_warn(sw, "missing baMinDPmain");
821	goto err_invalid;
822	}
823	if ((tb_port_is_dpin(port) || tb_port_is_dpout(port)) &&
824	min_dp_aux < 0) {
825	tb_sw_warn(sw, "missing baMinDPaux");
826	goto err_invalid;
827	}
828	if ((tb_port_is_usb3_down(port) || tb_port_is_usb3_up(port)) &&
829	max_usb3 < 0) {
830	tb_sw_warn(sw, "missing baMaxUSB3");
831	goto err_invalid;
832	}
833	if ((tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) &&
834	max_pcie < 0) {
835	tb_sw_warn(sw, "missing baMaxPCIe");
836	goto err_invalid;
837	}
838	}
839
840	/*
841	* Buffer allocation passed the validation so we can use it in
842	* path creation.
843	*/
844	sw->credit_allocation = true;
845	if (max_usb3 > 0)
846	sw->max_usb3_credits = max_usb3;
847	if (min_dp_aux > 0)
848	sw->min_dp_aux_credits = min_dp_aux;
849	if (min_dp_main > 0)
850	sw->min_dp_main_credits = min_dp_main;
851	if (max_pcie > 0)
852	sw->max_pcie_credits = max_pcie;
853	if (max_dma > 0)
854	sw->max_dma_credits = max_dma;
855
856	return 0;
857
858	err_invalid:
859	return -EINVAL;
860	}
861
862	/**
863	* usb4_switch_query_dp_resource() - Query availability of DP IN resource
864	* @sw: USB4 router
865	* @in: DP IN adapter
866	*
867	* For DP tunneling this function can be used to query availability of
868	* DP IN resource. Returns true if the resource is available for DP
869	* tunneling, false otherwise.
870	*/
871	bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
872	{
873	u32 metadata = in->port;
874	u8 status;
875	int ret;
876
877	ret = usb4_switch_op(sw, opcode: USB4_SWITCH_OP_QUERY_DP_RESOURCE, metadata: &metadata,
878	status: &status);
879	/*
880	* If DP resource allocation is not supported assume it is
881	* always available.
882	*/
883	if (ret == -EOPNOTSUPP)
884	return true;
885	if (ret)
886	return false;
887
888	return !status;
889	}
890
891	/**
892	* usb4_switch_alloc_dp_resource() - Allocate DP IN resource
893	* @sw: USB4 router
894	* @in: DP IN adapter
895	*
896	* Allocates DP IN resource for DP tunneling using USB4 router
897	* operations. If the resource was allocated returns %0. Otherwise
898	* returns negative errno, in particular %-EBUSY if the resource is
899	* already allocated.
900	*/
901	int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
902	{
903	u32 metadata = in->port;
904	u8 status;
905	int ret;
906
907	ret = usb4_switch_op(sw, opcode: USB4_SWITCH_OP_ALLOC_DP_RESOURCE, metadata: &metadata,
908	status: &status);
909	if (ret == -EOPNOTSUPP)
910	return 0;
911	if (ret)
912	return ret;
913
914	return status ? -EBUSY : 0;
915	}
916
917	/**
918	* usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
919	* @sw: USB4 router
920	* @in: DP IN adapter
921	*
922	* Releases the previously allocated DP IN resource.
923	*/
924	int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
925	{
926	u32 metadata = in->port;
927	u8 status;
928	int ret;
929
930	ret = usb4_switch_op(sw, opcode: USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, metadata: &metadata,
931	status: &status);
932	if (ret == -EOPNOTSUPP)
933	return 0;
934	if (ret)
935	return ret;
936
937	return status ? -EIO : 0;
938	}
939
940	static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port)
941	{
942	struct tb_port *p;
943	int usb4_idx = 0;
944
945	/* Assume port is primary */
946	tb_switch_for_each_port(sw, p) {
947	if (!tb_port_is_null(port: p))
948	continue;
949	if (tb_is_upstream_port(port: p))
950	continue;
951	if (!p->link_nr) {
952	if (p == port)
953	break;
954	usb4_idx++;
955	}
956	}
957
958	return usb4_idx;
959	}
960
961	/**
962	* usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
963	* @sw: USB4 router
964	* @port: USB4 port
965	*
966	* USB4 routers have direct mapping between USB4 ports and PCIe
967	* downstream adapters where the PCIe topology is extended. This
968	* function returns the corresponding downstream PCIe adapter or %NULL
969	* if no such mapping was possible.
970	*/
971	struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
972	const struct tb_port *port)
973	{
974	int usb4_idx = usb4_port_idx(sw, port);
975	struct tb_port *p;
976	int pcie_idx = 0;
977
978	/* Find PCIe down port matching usb4_port */
979	tb_switch_for_each_port(sw, p) {
980	if (!tb_port_is_pcie_down(port: p))
981	continue;
982
983	if (pcie_idx == usb4_idx)
984	return p;
985
986	pcie_idx++;
987	}
988
989	return NULL;
990	}
991
992	/**
993	* usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
994	* @sw: USB4 router
995	* @port: USB4 port
996	*
997	* USB4 routers have direct mapping between USB4 ports and USB 3.x
998	* downstream adapters where the USB 3.x topology is extended. This
999	* function returns the corresponding downstream USB 3.x adapter or
1000	* %NULL if no such mapping was possible.
1001	*/
1002	struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
1003	const struct tb_port *port)
1004	{
1005	int usb4_idx = usb4_port_idx(sw, port);
1006	struct tb_port *p;
1007	int usb_idx = 0;
1008
1009	/* Find USB3 down port matching usb4_port */
1010	tb_switch_for_each_port(sw, p) {
1011	if (!tb_port_is_usb3_down(port: p))
1012	continue;
1013
1014	if (usb_idx == usb4_idx)
1015	return p;
1016
1017	usb_idx++;
1018	}
1019
1020	return NULL;
1021	}
1022
1023	/**
1024	* usb4_switch_add_ports() - Add USB4 ports for this router
1025	* @sw: USB4 router
1026	*
1027	* For USB4 router finds all USB4 ports and registers devices for each.
1028	* Can be called to any router.
1029	*
1030	* Return %0 in case of success and negative errno in case of failure.
1031	*/
1032	int usb4_switch_add_ports(struct tb_switch *sw)
1033	{
1034	struct tb_port *port;
1035
1036	if (tb_switch_is_icm(sw) || !tb_switch_is_usb4(sw))
1037	return 0;
1038
1039	tb_switch_for_each_port(sw, port) {
1040	struct usb4_port *usb4;
1041
1042	if (!tb_port_is_null(port))
1043	continue;
1044	if (!port->cap_usb4)
1045	continue;
1046
1047	usb4 = usb4_port_device_add(port);
1048	if (IS_ERR(ptr: usb4)) {
1049	usb4_switch_remove_ports(sw);
1050	return PTR_ERR(ptr: usb4);
1051	}
1052
1053	port->usb4 = usb4;
1054	}
1055
1056	return 0;
1057	}
1058
1059	/**
1060	* usb4_switch_remove_ports() - Removes USB4 ports from this router
1061	* @sw: USB4 router
1062	*
1063	* Unregisters previously registered USB4 ports.
1064	*/
1065	void usb4_switch_remove_ports(struct tb_switch *sw)
1066	{
1067	struct tb_port *port;
1068
1069	tb_switch_for_each_port(sw, port) {
1070	if (port->usb4) {
1071	usb4_port_device_remove(usb4: port->usb4);
1072	port->usb4 = NULL;
1073	}
1074	}
1075	}
1076
1077	/**
1078	* usb4_port_unlock() - Unlock USB4 downstream port
1079	* @port: USB4 port to unlock
1080	*
1081	* Unlocks USB4 downstream port so that the connection manager can
1082	* access the router below this port.
1083	*/
1084	int usb4_port_unlock(struct tb_port *port)
1085	{
1086	int ret;
1087	u32 val;
1088
1089	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT, ADP_CS_4, length: 1);
1090	if (ret)
1091	return ret;
1092
1093	val &= ~ADP_CS_4_LCK;
1094	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT, ADP_CS_4, length: 1);
1095	}
1096
1097	/**
1098	* usb4_port_hotplug_enable() - Enables hotplug for a port
1099	* @port: USB4 port to operate on
1100	*
1101	* Enables hot plug events on a given port. This is only intended
1102	* to be used on lane, DP-IN, and DP-OUT adapters.
1103	*/
1104	int usb4_port_hotplug_enable(struct tb_port *port)
1105	{
1106	int ret;
1107	u32 val;
1108
1109	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT, ADP_CS_5, length: 1);
1110	if (ret)
1111	return ret;
1112
1113	val &= ~ADP_CS_5_DHP;
1114	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT, ADP_CS_5, length: 1);
1115	}
1116
1117	/**
1118	* usb4_port_reset() - Issue downstream port reset
1119	* @port: USB4 port to reset
1120	*
1121	* Issues downstream port reset to @port.
1122	*/
1123	int usb4_port_reset(struct tb_port *port)
1124	{
1125	int ret;
1126	u32 val;
1127
1128	if (!port->cap_usb4)
1129	return -EINVAL;
1130
1131	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
1132	offset: port->cap_usb4 + PORT_CS_19, length: 1);
1133	if (ret)
1134	return ret;
1135
1136	val |= PORT_CS_19_DPR;
1137
1138	ret = tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
1139	offset: port->cap_usb4 + PORT_CS_19, length: 1);
1140	if (ret)
1141	return ret;
1142
1143	fsleep(usecs: 10000);
1144
1145	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
1146	offset: port->cap_usb4 + PORT_CS_19, length: 1);
1147	if (ret)
1148	return ret;
1149
1150	val &= ~PORT_CS_19_DPR;
1151
1152	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
1153	offset: port->cap_usb4 + PORT_CS_19, length: 1);
1154	}
1155
1156	static int usb4_port_set_configured(struct tb_port *port, bool configured)
1157	{
1158	int ret;
1159	u32 val;
1160
1161	if (!port->cap_usb4)
1162	return -EINVAL;
1163
1164	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
1165	offset: port->cap_usb4 + PORT_CS_19, length: 1);
1166	if (ret)
1167	return ret;
1168
1169	if (configured)
1170	val |= PORT_CS_19_PC;
1171	else
1172	val &= ~PORT_CS_19_PC;
1173
1174	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
1175	offset: port->cap_usb4 + PORT_CS_19, length: 1);
1176	}
1177
1178	/**
1179	* usb4_port_configure() - Set USB4 port configured
1180	* @port: USB4 router
1181	*
1182	* Sets the USB4 link to be configured for power management purposes.
1183	*/
1184	int usb4_port_configure(struct tb_port *port)
1185	{
1186	return usb4_port_set_configured(port, configured: true);
1187	}
1188
1189	/**
1190	* usb4_port_unconfigure() - Set USB4 port unconfigured
1191	* @port: USB4 router
1192	*
1193	* Sets the USB4 link to be unconfigured for power management purposes.
1194	*/
1195	void usb4_port_unconfigure(struct tb_port *port)
1196	{
1197	usb4_port_set_configured(port, configured: false);
1198	}
1199
1200	static int usb4_set_xdomain_configured(struct tb_port *port, bool configured)
1201	{
1202	int ret;
1203	u32 val;
1204
1205	if (!port->cap_usb4)
1206	return -EINVAL;
1207
1208	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
1209	offset: port->cap_usb4 + PORT_CS_19, length: 1);
1210	if (ret)
1211	return ret;
1212
1213	if (configured)
1214	val |= PORT_CS_19_PID;
1215	else
1216	val &= ~PORT_CS_19_PID;
1217
1218	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
1219	offset: port->cap_usb4 + PORT_CS_19, length: 1);
1220	}
1221
1222	/**
1223	* usb4_port_configure_xdomain() - Configure port for XDomain
1224	* @port: USB4 port connected to another host
1225	* @xd: XDomain that is connected to the port
1226	*
1227	* Marks the USB4 port as being connected to another host and updates
1228	* the link type. Returns %0 in success and negative errno in failure.
1229	*/
1230	int usb4_port_configure_xdomain(struct tb_port *port, struct tb_xdomain *xd)
1231	{
1232	xd->link_usb4 = link_is_usb4(port);
1233	return usb4_set_xdomain_configured(port, configured: true);
1234	}
1235
1236	/**
1237	* usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain
1238	* @port: USB4 port that was connected to another host
1239	*
1240	* Clears USB4 port from being marked as XDomain.
1241	*/
1242	void usb4_port_unconfigure_xdomain(struct tb_port *port)
1243	{
1244	usb4_set_xdomain_configured(port, configured: false);
1245	}
1246
1247	static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit,
1248	u32 value, int timeout_msec)
1249	{
1250	ktime_t timeout = ktime_add_ms(kt: ktime_get(), msec: timeout_msec);
1251
1252	do {
1253	u32 val;
1254	int ret;
1255
1256	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT, offset, length: 1);
1257	if (ret)
1258	return ret;
1259
1260	if ((val & bit) == value)
1261	return 0;
1262
1263	usleep_range(min: 50, max: 100);
1264	} while (ktime_before(cmp1: ktime_get(), cmp2: timeout));
1265
1266	return -ETIMEDOUT;
1267	}
1268
1269	static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords)
1270	{
1271	if (dwords > USB4_DATA_DWORDS)
1272	return -EINVAL;
1273
1274	return tb_port_read(port, buffer: data, space: TB_CFG_PORT, offset: port->cap_usb4 + PORT_CS_2,
1275	length: dwords);
1276	}
1277
1278	static int usb4_port_write_data(struct tb_port *port, const void *data,
1279	size_t dwords)
1280	{
1281	if (dwords > USB4_DATA_DWORDS)
1282	return -EINVAL;
1283
1284	return tb_port_write(port, buffer: data, space: TB_CFG_PORT, offset: port->cap_usb4 + PORT_CS_2,
1285	length: dwords);
1286	}
1287
1288	static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target,
1289	u8 index, u8 reg, void *buf, u8 size)
1290	{
1291	size_t dwords = DIV_ROUND_UP(size, 4);
1292	int ret;
1293	u32 val;
1294
1295	if (!port->cap_usb4)
1296	return -EINVAL;
1297
1298	val = reg;
1299	val |= size << PORT_CS_1_LENGTH_SHIFT;
1300	val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1301	if (target == USB4_SB_TARGET_RETIMER)
1302	val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1303	val |= PORT_CS_1_PND;
1304
1305	ret = tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
1306	offset: port->cap_usb4 + PORT_CS_1, length: 1);
1307	if (ret)
1308	return ret;
1309
1310	ret = usb4_port_wait_for_bit(port, offset: port->cap_usb4 + PORT_CS_1,
1311	PORT_CS_1_PND, value: 0, timeout_msec: 500);
1312	if (ret)
1313	return ret;
1314
1315	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
1316	offset: port->cap_usb4 + PORT_CS_1, length: 1);
1317	if (ret)
1318	return ret;
1319
1320	if (val & PORT_CS_1_NR)
1321	return -ENODEV;
1322	if (val & PORT_CS_1_RC)
1323	return -EIO;
1324
1325	return buf ? usb4_port_read_data(port, data: buf, dwords) : 0;
1326	}
1327
1328	static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
1329	u8 index, u8 reg, const void *buf, u8 size)
1330	{
1331	size_t dwords = DIV_ROUND_UP(size, 4);
1332	int ret;
1333	u32 val;
1334
1335	if (!port->cap_usb4)
1336	return -EINVAL;
1337
1338	if (buf) {
1339	ret = usb4_port_write_data(port, data: buf, dwords);
1340	if (ret)
1341	return ret;
1342	}
1343
1344	val = reg;
1345	val |= size << PORT_CS_1_LENGTH_SHIFT;
1346	val |= PORT_CS_1_WNR_WRITE;
1347	val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1348	if (target == USB4_SB_TARGET_RETIMER)
1349	val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1350	val |= PORT_CS_1_PND;
1351
1352	ret = tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
1353	offset: port->cap_usb4 + PORT_CS_1, length: 1);
1354	if (ret)
1355	return ret;
1356
1357	ret = usb4_port_wait_for_bit(port, offset: port->cap_usb4 + PORT_CS_1,
1358	PORT_CS_1_PND, value: 0, timeout_msec: 500);
1359	if (ret)
1360	return ret;
1361
1362	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
1363	offset: port->cap_usb4 + PORT_CS_1, length: 1);
1364	if (ret)
1365	return ret;
1366
1367	if (val & PORT_CS_1_NR)
1368	return -ENODEV;
1369	if (val & PORT_CS_1_RC)
1370	return -EIO;
1371
1372	return 0;
1373	}
1374
1375	static int usb4_port_sb_opcode_err_to_errno(u32 val)
1376	{
1377	switch (val) {
1378	case 0:
1379	return 0;
1380	case USB4_SB_OPCODE_ERR:
1381	return -EAGAIN;
1382	case USB4_SB_OPCODE_ONS:
1383	return -EOPNOTSUPP;
1384	default:
1385	return -EIO;
1386	}
1387	}
1388
1389	static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target,
1390	u8 index, enum usb4_sb_opcode opcode, int timeout_msec)
1391	{
1392	ktime_t timeout;
1393	u32 val;
1394	int ret;
1395
1396	val = opcode;
1397	ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, buf: &val,
1398	size: sizeof(val));
1399	if (ret)
1400	return ret;
1401
1402	timeout = ktime_add_ms(kt: ktime_get(), msec: timeout_msec);
1403
1404	do {
1405	/* Check results */
1406	ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE,
1407	buf: &val, size: sizeof(val));
1408	if (ret)
1409	return ret;
1410
1411	if (val != opcode)
1412	return usb4_port_sb_opcode_err_to_errno(val);
1413	} while (ktime_before(cmp1: ktime_get(), cmp2: timeout));
1414
1415	return -ETIMEDOUT;
1416	}
1417
1418	static int usb4_port_set_router_offline(struct tb_port *port, bool offline)
1419	{
1420	u32 val = !offline;
1421	int ret;
1422
1423	ret = usb4_port_sb_write(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1424	USB4_SB_METADATA, buf: &val, size: sizeof(val));
1425	if (ret)
1426	return ret;
1427
1428	val = USB4_SB_OPCODE_ROUTER_OFFLINE;
1429	return usb4_port_sb_write(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1430	USB4_SB_OPCODE, buf: &val, size: sizeof(val));
1431	}
1432
1433	/**
1434	* usb4_port_router_offline() - Put the USB4 port to offline mode
1435	* @port: USB4 port
1436	*
1437	* This function puts the USB4 port into offline mode. In this mode the
1438	* port does not react on hotplug events anymore. This needs to be
1439	* called before retimer access is done when the USB4 links is not up.
1440	*
1441	* Returns %0 in case of success and negative errno if there was an
1442	* error.
1443	*/
1444	int usb4_port_router_offline(struct tb_port *port)
1445	{
1446	return usb4_port_set_router_offline(port, offline: true);
1447	}
1448
1449	/**
1450	* usb4_port_router_online() - Put the USB4 port back to online
1451	* @port: USB4 port
1452	*
1453	* Makes the USB4 port functional again.
1454	*/
1455	int usb4_port_router_online(struct tb_port *port)
1456	{
1457	return usb4_port_set_router_offline(port, offline: false);
1458	}
1459
1460	/**
1461	* usb4_port_enumerate_retimers() - Send RT broadcast transaction
1462	* @port: USB4 port
1463	*
1464	* This forces the USB4 port to send broadcast RT transaction which
1465	* makes the retimers on the link to assign index to themselves. Returns
1466	* %0 in case of success and negative errno if there was an error.
1467	*/
1468	int usb4_port_enumerate_retimers(struct tb_port *port)
1469	{
1470	u32 val;
1471
1472	val = USB4_SB_OPCODE_ENUMERATE_RETIMERS;
1473	return usb4_port_sb_write(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1474	USB4_SB_OPCODE, buf: &val, size: sizeof(val));
1475	}
1476
1477	/**
1478	* usb4_port_clx_supported() - Check if CLx is supported by the link
1479	* @port: Port to check for CLx support for
1480	*
1481	* PORT_CS_18_CPS bit reflects if the link supports CLx including
1482	* active cables (if connected on the link).
1483	*/
1484	bool usb4_port_clx_supported(struct tb_port *port)
1485	{
1486	int ret;
1487	u32 val;
1488
1489	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
1490	offset: port->cap_usb4 + PORT_CS_18, length: 1);
1491	if (ret)
1492	return false;
1493
1494	return !!(val & PORT_CS_18_CPS);
1495	}
1496
1497	/**
1498	* usb4_port_asym_supported() - If the port supports asymmetric link
1499	* @port: USB4 port
1500	*
1501	* Checks if the port and the cable supports asymmetric link and returns
1502	* %true in that case.
1503	*/
1504	bool usb4_port_asym_supported(struct tb_port *port)
1505	{
1506	u32 val;
1507
1508	if (!port->cap_usb4)
1509	return false;
1510
1511	if (tb_port_read(port, buffer: &val, space: TB_CFG_PORT, offset: port->cap_usb4 + PORT_CS_18, length: 1))
1512	return false;
1513
1514	return !!(val & PORT_CS_18_CSA);
1515	}
1516
1517	/**
1518	* usb4_port_asym_set_link_width() - Set link width to asymmetric or symmetric
1519	* @port: USB4 port
1520	* @width: Asymmetric width to configure
1521	*
1522	* Sets USB4 port link width to @width. Can be called for widths where
1523	* usb4_port_asym_width_supported() returned @true.
1524	*/
1525	int usb4_port_asym_set_link_width(struct tb_port *port, enum tb_link_width width)
1526	{
1527	u32 val;
1528	int ret;
1529
1530	if (!port->cap_phy)
1531	return -EINVAL;
1532
1533	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
1534	offset: port->cap_phy + LANE_ADP_CS_1, length: 1);
1535	if (ret)
1536	return ret;
1537
1538	val &= ~LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK;
1539	switch (width) {
1540	case TB_LINK_WIDTH_DUAL:
1541	val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1542	LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL);
1543	break;
1544	case TB_LINK_WIDTH_ASYM_TX:
1545	val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1546	LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX);
1547	break;
1548	case TB_LINK_WIDTH_ASYM_RX:
1549	val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1550	LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX);
1551	break;
1552	default:
1553	return -EINVAL;
1554	}
1555
1556	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
1557	offset: port->cap_phy + LANE_ADP_CS_1, length: 1);
1558	}
1559
1560	/**
1561	* usb4_port_asym_start() - Start symmetry change and wait for completion
1562	* @port: USB4 port
1563	*
1564	* Start symmetry change of the link to asymmetric or symmetric
1565	* (according to what was previously set in tb_port_set_link_width().
1566	* Wait for completion of the change.
1567	*
1568	* Returns %0 in case of success, %-ETIMEDOUT if case of timeout or
1569	* a negative errno in case of a failure.
1570	*/
1571	int usb4_port_asym_start(struct tb_port *port)
1572	{
1573	int ret;
1574	u32 val;
1575
1576	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
1577	offset: port->cap_usb4 + PORT_CS_19, length: 1);
1578	if (ret)
1579	return ret;
1580
1581	val &= ~PORT_CS_19_START_ASYM;
1582	val |= FIELD_PREP(PORT_CS_19_START_ASYM, 1);
1583
1584	ret = tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
1585	offset: port->cap_usb4 + PORT_CS_19, length: 1);
1586	if (ret)
1587	return ret;
1588
1589	/*
1590	* Wait for PORT_CS_19_START_ASYM to be 0. This means the USB4
1591	* port started the symmetry transition.
1592	*/
1593	ret = usb4_port_wait_for_bit(port, offset: port->cap_usb4 + PORT_CS_19,
1594	PORT_CS_19_START_ASYM, value: 0, timeout_msec: 1000);
1595	if (ret)
1596	return ret;
1597
1598	/* Then wait for the transtion to be completed */
1599	return usb4_port_wait_for_bit(port, offset: port->cap_usb4 + PORT_CS_18,
1600	PORT_CS_18_TIP, value: 0, timeout_msec: 5000);
1601	}
1602
1603	/**
1604	* usb4_port_margining_caps() - Read USB4 port marginig capabilities
1605	* @port: USB4 port
1606	* @caps: Array with at least two elements to hold the results
1607	*
1608	* Reads the USB4 port lane margining capabilities into @caps.
1609	*/
1610	int usb4_port_margining_caps(struct tb_port *port, u32 *caps)
1611	{
1612	int ret;
1613
1614	ret = usb4_port_sb_op(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1615	opcode: USB4_SB_OPCODE_READ_LANE_MARGINING_CAP, timeout_msec: 500);
1616	if (ret)
1617	return ret;
1618
1619	return usb4_port_sb_read(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1620	USB4_SB_DATA, buf: caps, size: sizeof(*caps) * 2);
1621	}
1622
1623	/**
1624	* usb4_port_hw_margin() - Run hardware lane margining on port
1625	* @port: USB4 port
1626	* @lanes: Which lanes to run (must match the port capabilities). Can be
1627	* %0, %1 or %7.
1628	* @ber_level: BER level contour value
1629	* @timing: Perform timing margining instead of voltage
1630	* @right_high: Use Right/high margin instead of left/low
1631	* @results: Array with at least two elements to hold the results
1632	*
1633	* Runs hardware lane margining on USB4 port and returns the result in
1634	* @results.
1635	*/
1636	int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes,
1637	unsigned int ber_level, bool timing, bool right_high,
1638	u32 *results)
1639	{
1640	u32 val;
1641	int ret;
1642
1643	val = lanes;
1644	if (timing)
1645	val |= USB4_MARGIN_HW_TIME;
1646	if (right_high)
1647	val |= USB4_MARGIN_HW_RH;
1648	if (ber_level)
1649	val |= (ber_level << USB4_MARGIN_HW_BER_SHIFT) &
1650	USB4_MARGIN_HW_BER_MASK;
1651
1652	ret = usb4_port_sb_write(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1653	USB4_SB_METADATA, buf: &val, size: sizeof(val));
1654	if (ret)
1655	return ret;
1656
1657	ret = usb4_port_sb_op(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1658	opcode: USB4_SB_OPCODE_RUN_HW_LANE_MARGINING, timeout_msec: 2500);
1659	if (ret)
1660	return ret;
1661
1662	return usb4_port_sb_read(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1663	USB4_SB_DATA, buf: results, size: sizeof(*results) * 2);
1664	}
1665
1666	/**
1667	* usb4_port_sw_margin() - Run software lane margining on port
1668	* @port: USB4 port
1669	* @lanes: Which lanes to run (must match the port capabilities). Can be
1670	* %0, %1 or %7.
1671	* @timing: Perform timing margining instead of voltage
1672	* @right_high: Use Right/high margin instead of left/low
1673	* @counter: What to do with the error counter
1674	*
1675	* Runs software lane margining on USB4 port. Read back the error
1676	* counters by calling usb4_port_sw_margin_errors(). Returns %0 in
1677	* success and negative errno otherwise.
1678	*/
1679	int usb4_port_sw_margin(struct tb_port *port, unsigned int lanes, bool timing,
1680	bool right_high, u32 counter)
1681	{
1682	u32 val;
1683	int ret;
1684
1685	val = lanes;
1686	if (timing)
1687	val |= USB4_MARGIN_SW_TIME;
1688	if (right_high)
1689	val |= USB4_MARGIN_SW_RH;
1690	val |= (counter << USB4_MARGIN_SW_COUNTER_SHIFT) &
1691	USB4_MARGIN_SW_COUNTER_MASK;
1692
1693	ret = usb4_port_sb_write(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1694	USB4_SB_METADATA, buf: &val, size: sizeof(val));
1695	if (ret)
1696	return ret;
1697
1698	return usb4_port_sb_op(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1699	opcode: USB4_SB_OPCODE_RUN_SW_LANE_MARGINING, timeout_msec: 2500);
1700	}
1701
1702	/**
1703	* usb4_port_sw_margin_errors() - Read the software margining error counters
1704	* @port: USB4 port
1705	* @errors: Error metadata is copied here.
1706	*
1707	* This reads back the software margining error counters from the port.
1708	* Returns %0 in success and negative errno otherwise.
1709	*/
1710	int usb4_port_sw_margin_errors(struct tb_port *port, u32 *errors)
1711	{
1712	int ret;
1713
1714	ret = usb4_port_sb_op(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1715	opcode: USB4_SB_OPCODE_READ_SW_MARGIN_ERR, timeout_msec: 150);
1716	if (ret)
1717	return ret;
1718
1719	return usb4_port_sb_read(port, target: USB4_SB_TARGET_ROUTER, index: 0,
1720	USB4_SB_METADATA, buf: errors, size: sizeof(*errors));
1721	}
1722
1723	static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
1724	enum usb4_sb_opcode opcode,
1725	int timeout_msec)
1726	{
1727	return usb4_port_sb_op(port, target: USB4_SB_TARGET_RETIMER, index, opcode,
1728	timeout_msec);
1729	}
1730
1731	/**
1732	* usb4_port_retimer_set_inbound_sbtx() - Enable sideband channel transactions
1733	* @port: USB4 port
1734	* @index: Retimer index
1735	*
1736	* Enables sideband channel transations on SBTX. Can be used when USB4
1737	* link does not go up, for example if there is no device connected.
1738	*/
1739	int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index)
1740	{
1741	int ret;
1742
1743	ret = usb4_port_retimer_op(port, index, opcode: USB4_SB_OPCODE_SET_INBOUND_SBTX,
1744	timeout_msec: 500);
1745
1746	if (ret != -ENODEV)
1747	return ret;
1748
1749	/*
1750	* Per the USB4 retimer spec, the retimer is not required to
1751	* send an RT (Retimer Transaction) response for the first
1752	* SET_INBOUND_SBTX command
1753	*/
1754	return usb4_port_retimer_op(port, index, opcode: USB4_SB_OPCODE_SET_INBOUND_SBTX,
1755	timeout_msec: 500);
1756	}
1757
1758	/**
1759	* usb4_port_retimer_unset_inbound_sbtx() - Disable sideband channel transactions
1760	* @port: USB4 port
1761	* @index: Retimer index
1762	*
1763	* Disables sideband channel transations on SBTX. The reverse of
1764	* usb4_port_retimer_set_inbound_sbtx().
1765	*/
1766	int usb4_port_retimer_unset_inbound_sbtx(struct tb_port *port, u8 index)
1767	{
1768	return usb4_port_retimer_op(port, index,
1769	opcode: USB4_SB_OPCODE_UNSET_INBOUND_SBTX, timeout_msec: 500);
1770	}
1771
1772	/**
1773	* usb4_port_retimer_read() - Read from retimer sideband registers
1774	* @port: USB4 port
1775	* @index: Retimer index
1776	* @reg: Sideband register to read
1777	* @buf: Data from @reg is stored here
1778	* @size: Number of bytes to read
1779	*
1780	* Function reads retimer sideband registers starting from @reg. The
1781	* retimer is connected to @port at @index. Returns %0 in case of
1782	* success, and read data is copied to @buf. If there is no retimer
1783	* present at given @index returns %-ENODEV. In any other failure
1784	* returns negative errno.
1785	*/
1786	int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf,
1787	u8 size)
1788	{
1789	return usb4_port_sb_read(port, target: USB4_SB_TARGET_RETIMER, index, reg, buf,
1790	size);
1791	}
1792
1793	/**
1794	* usb4_port_retimer_write() - Write to retimer sideband registers
1795	* @port: USB4 port
1796	* @index: Retimer index
1797	* @reg: Sideband register to write
1798	* @buf: Data that is written starting from @reg
1799	* @size: Number of bytes to write
1800	*
1801	* Writes retimer sideband registers starting from @reg. The retimer is
1802	* connected to @port at @index. Returns %0 in case of success. If there
1803	* is no retimer present at given @index returns %-ENODEV. In any other
1804	* failure returns negative errno.
1805	*/
1806	int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg,
1807	const void *buf, u8 size)
1808	{
1809	return usb4_port_sb_write(port, target: USB4_SB_TARGET_RETIMER, index, reg, buf,
1810	size);
1811	}
1812
1813	/**
1814	* usb4_port_retimer_is_last() - Is the retimer last on-board retimer
1815	* @port: USB4 port
1816	* @index: Retimer index
1817	*
1818	* If the retimer at @index is last one (connected directly to the
1819	* Type-C port) this function returns %1. If it is not returns %0. If
1820	* the retimer is not present returns %-ENODEV. Otherwise returns
1821	* negative errno.
1822	*/
1823	int usb4_port_retimer_is_last(struct tb_port *port, u8 index)
1824	{
1825	u32 metadata;
1826	int ret;
1827
1828	ret = usb4_port_retimer_op(port, index, opcode: USB4_SB_OPCODE_QUERY_LAST_RETIMER,
1829	timeout_msec: 500);
1830	if (ret)
1831	return ret;
1832
1833	ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, buf: &metadata,
1834	size: sizeof(metadata));
1835	return ret ? ret : metadata & 1;
1836	}
1837
1838	/**
1839	* usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size
1840	* @port: USB4 port
1841	* @index: Retimer index
1842	*
1843	* Reads NVM sector size (in bytes) of a retimer at @index. This
1844	* operation can be used to determine whether the retimer supports NVM
1845	* upgrade for example. Returns sector size in bytes or negative errno
1846	* in case of error. Specifically returns %-ENODEV if there is no
1847	* retimer at @index.
1848	*/
1849	int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index)
1850	{
1851	u32 metadata;
1852	int ret;
1853
1854	ret = usb4_port_retimer_op(port, index, opcode: USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE,
1855	timeout_msec: 500);
1856	if (ret)
1857	return ret;
1858
1859	ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, buf: &metadata,
1860	size: sizeof(metadata));
1861	return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK;
1862	}
1863
1864	/**
1865	* usb4_port_retimer_nvm_set_offset() - Set NVM write offset
1866	* @port: USB4 port
1867	* @index: Retimer index
1868	* @address: Start offset
1869	*
1870	* Exlicitly sets NVM write offset. Normally when writing to NVM this is
1871	* done automatically by usb4_port_retimer_nvm_write().
1872	*
1873	* Returns %0 in success and negative errno if there was a failure.
1874	*/
1875	int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index,
1876	unsigned int address)
1877	{
1878	u32 metadata, dwaddress;
1879	int ret;
1880
1881	dwaddress = address / 4;
1882	metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
1883	USB4_NVM_SET_OFFSET_MASK;
1884
1885	ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, buf: &metadata,
1886	size: sizeof(metadata));
1887	if (ret)
1888	return ret;
1889
1890	return usb4_port_retimer_op(port, index, opcode: USB4_SB_OPCODE_NVM_SET_OFFSET,
1891	timeout_msec: 500);
1892	}
1893
1894	struct retimer_info {
1895	struct tb_port *port;
1896	u8 index;
1897	};
1898
1899	static int usb4_port_retimer_nvm_write_next_block(void *data,
1900	unsigned int dwaddress, const void *buf, size_t dwords)
1901
1902	{
1903	const struct retimer_info *info = data;
1904	struct tb_port *port = info->port;
1905	u8 index = info->index;
1906	int ret;
1907
1908	ret = usb4_port_retimer_write(port, index, USB4_SB_DATA,
1909	buf, size: dwords * 4);
1910	if (ret)
1911	return ret;
1912
1913	return usb4_port_retimer_op(port, index,
1914	opcode: USB4_SB_OPCODE_NVM_BLOCK_WRITE, timeout_msec: 1000);
1915	}
1916
1917	/**
1918	* usb4_port_retimer_nvm_write() - Write to retimer NVM
1919	* @port: USB4 port
1920	* @index: Retimer index
1921	* @address: Byte address where to start the write
1922	* @buf: Data to write
1923	* @size: Size in bytes how much to write
1924	*
1925	* Writes @size bytes from @buf to the retimer NVM. Used for NVM
1926	* upgrade. Returns %0 if the data was written successfully and negative
1927	* errno in case of failure. Specifically returns %-ENODEV if there is
1928	* no retimer at @index.
1929	*/
1930	int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address,
1931	const void *buf, size_t size)
1932	{
1933	struct retimer_info info = { .port = port, .index = index };
1934	int ret;
1935
1936	ret = usb4_port_retimer_nvm_set_offset(port, index, address);
1937	if (ret)
1938	return ret;
1939
1940	return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
1941	write_next_block: usb4_port_retimer_nvm_write_next_block, write_block_data: &info);
1942	}
1943
1944	/**
1945	* usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade
1946	* @port: USB4 port
1947	* @index: Retimer index
1948	*
1949	* After the new NVM image has been written via usb4_port_retimer_nvm_write()
1950	* this function can be used to trigger the NVM upgrade process. If
1951	* successful the retimer restarts with the new NVM and may not have the
1952	* index set so one needs to call usb4_port_enumerate_retimers() to
1953	* force index to be assigned.
1954	*/
1955	int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index)
1956	{
1957	u32 val;
1958
1959	/*
1960	* We need to use the raw operation here because once the
1961	* authentication completes the retimer index is not set anymore
1962	* so we do not get back the status now.
1963	*/
1964	val = USB4_SB_OPCODE_NVM_AUTH_WRITE;
1965	return usb4_port_sb_write(port, target: USB4_SB_TARGET_RETIMER, index,
1966	USB4_SB_OPCODE, buf: &val, size: sizeof(val));
1967	}
1968
1969	/**
1970	* usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade
1971	* @port: USB4 port
1972	* @index: Retimer index
1973	* @status: Raw status code read from metadata
1974	*
1975	* This can be called after usb4_port_retimer_nvm_authenticate() and
1976	* usb4_port_enumerate_retimers() to fetch status of the NVM upgrade.
1977	*
1978	* Returns %0 if the authentication status was successfully read. The
1979	* completion metadata (the result) is then stored into @status. If
1980	* reading the status fails, returns negative errno.
1981	*/
1982	int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
1983	u32 *status)
1984	{
1985	u32 metadata, val;
1986	int ret;
1987
1988	ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, buf: &val,
1989	size: sizeof(val));
1990	if (ret)
1991	return ret;
1992
1993	ret = usb4_port_sb_opcode_err_to_errno(val);
1994	switch (ret) {
1995	case 0:
1996	*status = 0;
1997	return 0;
1998
1999	case -EAGAIN:
2000	ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA,
2001	buf: &metadata, size: sizeof(metadata));
2002	if (ret)
2003	return ret;
2004
2005	*status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK;
2006	return 0;
2007
2008	default:
2009	return ret;
2010	}
2011	}
2012
2013	static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress,
2014	void *buf, size_t dwords)
2015	{
2016	const struct retimer_info *info = data;
2017	struct tb_port *port = info->port;
2018	u8 index = info->index;
2019	u32 metadata;
2020	int ret;
2021
2022	metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT;
2023	if (dwords < USB4_DATA_DWORDS)
2024	metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT;
2025
2026	ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, buf: &metadata,
2027	size: sizeof(metadata));
2028	if (ret)
2029	return ret;
2030
2031	ret = usb4_port_retimer_op(port, index, opcode: USB4_SB_OPCODE_NVM_READ, timeout_msec: 500);
2032	if (ret)
2033	return ret;
2034
2035	return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf,
2036	size: dwords * 4);
2037	}
2038
2039	/**
2040	* usb4_port_retimer_nvm_read() - Read contents of retimer NVM
2041	* @port: USB4 port
2042	* @index: Retimer index
2043	* @address: NVM address (in bytes) to start reading
2044	* @buf: Data read from NVM is stored here
2045	* @size: Number of bytes to read
2046	*
2047	* Reads retimer NVM and copies the contents to @buf. Returns %0 if the
2048	* read was successful and negative errno in case of failure.
2049	* Specifically returns %-ENODEV if there is no retimer at @index.
2050	*/
2051	int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
2052	unsigned int address, void *buf, size_t size)
2053	{
2054	struct retimer_info info = { .port = port, .index = index };
2055
2056	return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
2057	read_block: usb4_port_retimer_nvm_read_block, read_block_data: &info);
2058	}
2059
2060	static inline unsigned int
2061	usb4_usb3_port_max_bandwidth(const struct tb_port *port, unsigned int bw)
2062	{
2063	/* Take the possible bandwidth limitation into account */
2064	if (port->max_bw)
2065	return min(bw, port->max_bw);
2066	return bw;
2067	}
2068
2069	/**
2070	* usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate
2071	* @port: USB3 adapter port
2072	*
2073	* Return maximum supported link rate of a USB3 adapter in Mb/s.
2074	* Negative errno in case of error.
2075	*/
2076	int usb4_usb3_port_max_link_rate(struct tb_port *port)
2077	{
2078	int ret, lr;
2079	u32 val;
2080
2081	if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
2082	return -EINVAL;
2083
2084	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2085	offset: port->cap_adap + ADP_USB3_CS_4, length: 1);
2086	if (ret)
2087	return ret;
2088
2089	lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT;
2090	ret = lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000;
2091
2092	return usb4_usb3_port_max_bandwidth(port, bw: ret);
2093	}
2094
2095	static int usb4_usb3_port_cm_request(struct tb_port *port, bool request)
2096	{
2097	int ret;
2098	u32 val;
2099
2100	if (!tb_port_is_usb3_down(port))
2101	return -EINVAL;
2102	if (tb_route(sw: port->sw))
2103	return -EINVAL;
2104
2105	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2106	offset: port->cap_adap + ADP_USB3_CS_2, length: 1);
2107	if (ret)
2108	return ret;
2109
2110	if (request)
2111	val |= ADP_USB3_CS_2_CMR;
2112	else
2113	val &= ~ADP_USB3_CS_2_CMR;
2114
2115	ret = tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2116	offset: port->cap_adap + ADP_USB3_CS_2, length: 1);
2117	if (ret)
2118	return ret;
2119
2120	/*
2121	* We can use val here directly as the CMR bit is in the same place
2122	* as HCA. Just mask out others.
2123	*/
2124	val &= ADP_USB3_CS_2_CMR;
2125	return usb4_port_wait_for_bit(port, offset: port->cap_adap + ADP_USB3_CS_1,
2126	ADP_USB3_CS_1_HCA, value: val, timeout_msec: 1500);
2127	}
2128
2129	static inline int usb4_usb3_port_set_cm_request(struct tb_port *port)
2130	{
2131	return usb4_usb3_port_cm_request(port, request: true);
2132	}
2133
2134	static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port)
2135	{
2136	return usb4_usb3_port_cm_request(port, request: false);
2137	}
2138
2139	static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale)
2140	{
2141	unsigned long uframes;
2142
2143	uframes = bw * 512UL << scale;
2144	return DIV_ROUND_CLOSEST(uframes * 8000, MEGA);
2145	}
2146
2147	static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale)
2148	{
2149	unsigned long uframes;
2150
2151	/* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */
2152	uframes = ((unsigned long)mbps * MEGA) / 8000;
2153	return DIV_ROUND_UP(uframes, 512UL << scale);
2154	}
2155
2156	static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port,
2157	int *upstream_bw,
2158	int *downstream_bw)
2159	{
2160	u32 val, bw, scale;
2161	int ret;
2162
2163	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2164	offset: port->cap_adap + ADP_USB3_CS_2, length: 1);
2165	if (ret)
2166	return ret;
2167
2168	ret = tb_port_read(port, buffer: &scale, space: TB_CFG_PORT,
2169	offset: port->cap_adap + ADP_USB3_CS_3, length: 1);
2170	if (ret)
2171	return ret;
2172
2173	scale &= ADP_USB3_CS_3_SCALE_MASK;
2174
2175	bw = val & ADP_USB3_CS_2_AUBW_MASK;
2176	*upstream_bw = usb3_bw_to_mbps(bw, scale);
2177
2178	bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT;
2179	*downstream_bw = usb3_bw_to_mbps(bw, scale);
2180
2181	return 0;
2182	}
2183
2184	/**
2185	* usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3
2186	* @port: USB3 adapter port
2187	* @upstream_bw: Allocated upstream bandwidth is stored here
2188	* @downstream_bw: Allocated downstream bandwidth is stored here
2189	*
2190	* Stores currently allocated USB3 bandwidth into @upstream_bw and
2191	* @downstream_bw in Mb/s. Returns %0 in case of success and negative
2192	* errno in failure.
2193	*/
2194	int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
2195	int *downstream_bw)
2196	{
2197	int ret;
2198
2199	ret = usb4_usb3_port_set_cm_request(port);
2200	if (ret)
2201	return ret;
2202
2203	ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw,
2204	downstream_bw);
2205	usb4_usb3_port_clear_cm_request(port);
2206
2207	return ret;
2208	}
2209
2210	static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port,
2211	int *upstream_bw,
2212	int *downstream_bw)
2213	{
2214	u32 val, bw, scale;
2215	int ret;
2216
2217	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2218	offset: port->cap_adap + ADP_USB3_CS_1, length: 1);
2219	if (ret)
2220	return ret;
2221
2222	ret = tb_port_read(port, buffer: &scale, space: TB_CFG_PORT,
2223	offset: port->cap_adap + ADP_USB3_CS_3, length: 1);
2224	if (ret)
2225	return ret;
2226
2227	scale &= ADP_USB3_CS_3_SCALE_MASK;
2228
2229	bw = val & ADP_USB3_CS_1_CUBW_MASK;
2230	*upstream_bw = usb3_bw_to_mbps(bw, scale);
2231
2232	bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT;
2233	*downstream_bw = usb3_bw_to_mbps(bw, scale);
2234
2235	return 0;
2236	}
2237
2238	static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port,
2239	int upstream_bw,
2240	int downstream_bw)
2241	{
2242	u32 val, ubw, dbw, scale;
2243	int ret, max_bw;
2244
2245	/* Figure out suitable scale */
2246	scale = 0;
2247	max_bw = max(upstream_bw, downstream_bw);
2248	while (scale < 64) {
2249	if (mbps_to_usb3_bw(mbps: max_bw, scale) < 4096)
2250	break;
2251	scale++;
2252	}
2253
2254	if (WARN_ON(scale >= 64))
2255	return -EINVAL;
2256
2257	ret = tb_port_write(port, buffer: &scale, space: TB_CFG_PORT,
2258	offset: port->cap_adap + ADP_USB3_CS_3, length: 1);
2259	if (ret)
2260	return ret;
2261
2262	ubw = mbps_to_usb3_bw(mbps: upstream_bw, scale);
2263	dbw = mbps_to_usb3_bw(mbps: downstream_bw, scale);
2264
2265	tb_port_dbg(port, "scaled bandwidth %u/%u, scale %u\n", ubw, dbw, scale);
2266
2267	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2268	offset: port->cap_adap + ADP_USB3_CS_2, length: 1);
2269	if (ret)
2270	return ret;
2271
2272	val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK);
2273	val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT;
2274	val |= ubw;
2275
2276	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2277	offset: port->cap_adap + ADP_USB3_CS_2, length: 1);
2278	}
2279
2280	/**
2281	* usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3
2282	* @port: USB3 adapter port
2283	* @upstream_bw: New upstream bandwidth
2284	* @downstream_bw: New downstream bandwidth
2285	*
2286	* This can be used to set how much bandwidth is allocated for the USB3
2287	* tunneled isochronous traffic. @upstream_bw and @downstream_bw are the
2288	* new values programmed to the USB3 adapter allocation registers. If
2289	* the values are lower than what is currently consumed the allocation
2290	* is set to what is currently consumed instead (consumed bandwidth
2291	* cannot be taken away by CM). The actual new values are returned in
2292	* @upstream_bw and @downstream_bw.
2293	*
2294	* Returns %0 in case of success and negative errno if there was a
2295	* failure.
2296	*/
2297	int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
2298	int *downstream_bw)
2299	{
2300	int ret, consumed_up, consumed_down, allocate_up, allocate_down;
2301
2302	ret = usb4_usb3_port_set_cm_request(port);
2303	if (ret)
2304	return ret;
2305
2306	ret = usb4_usb3_port_read_consumed_bandwidth(port, upstream_bw: &consumed_up,
2307	downstream_bw: &consumed_down);
2308	if (ret)
2309	goto err_request;
2310
2311	/* Don't allow it go lower than what is consumed */
2312	allocate_up = max(*upstream_bw, consumed_up);
2313	allocate_down = max(*downstream_bw, consumed_down);
2314
2315	ret = usb4_usb3_port_write_allocated_bandwidth(port, upstream_bw: allocate_up,
2316	downstream_bw: allocate_down);
2317	if (ret)
2318	goto err_request;
2319
2320	*upstream_bw = allocate_up;
2321	*downstream_bw = allocate_down;
2322
2323	err_request:
2324	usb4_usb3_port_clear_cm_request(port);
2325	return ret;
2326	}
2327
2328	/**
2329	* usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth
2330	* @port: USB3 adapter port
2331	* @upstream_bw: New allocated upstream bandwidth
2332	* @downstream_bw: New allocated downstream bandwidth
2333	*
2334	* Releases USB3 allocated bandwidth down to what is actually consumed.
2335	* The new bandwidth is returned in @upstream_bw and @downstream_bw.
2336	*
2337	* Returns 0% in success and negative errno in case of failure.
2338	*/
2339	int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
2340	int *downstream_bw)
2341	{
2342	int ret, consumed_up, consumed_down;
2343
2344	ret = usb4_usb3_port_set_cm_request(port);
2345	if (ret)
2346	return ret;
2347
2348	ret = usb4_usb3_port_read_consumed_bandwidth(port, upstream_bw: &consumed_up,
2349	downstream_bw: &consumed_down);
2350	if (ret)
2351	goto err_request;
2352
2353	/*
2354	* Always keep 900 Mb/s to make sure xHCI has at least some
2355	* bandwidth available for isochronous traffic.
2356	*/
2357	if (consumed_up < 900)
2358	consumed_up = 900;
2359	if (consumed_down < 900)
2360	consumed_down = 900;
2361
2362	ret = usb4_usb3_port_write_allocated_bandwidth(port, upstream_bw: consumed_up,
2363	downstream_bw: consumed_down);
2364	if (ret)
2365	goto err_request;
2366
2367	*upstream_bw = consumed_up;
2368	*downstream_bw = consumed_down;
2369
2370	err_request:
2371	usb4_usb3_port_clear_cm_request(port);
2372	return ret;
2373	}
2374
2375	static bool is_usb4_dpin(const struct tb_port *port)
2376	{
2377	if (!tb_port_is_dpin(port))
2378	return false;
2379	if (!tb_switch_is_usb4(sw: port->sw))
2380	return false;
2381	return true;
2382	}
2383
2384	/**
2385	* usb4_dp_port_set_cm_id() - Assign CM ID to the DP IN adapter
2386	* @port: DP IN adapter
2387	* @cm_id: CM ID to assign
2388	*
2389	* Sets CM ID for the @port. Returns %0 on success and negative errno
2390	* otherwise. Speficially returns %-EOPNOTSUPP if the @port does not
2391	* support this.
2392	*/
2393	int usb4_dp_port_set_cm_id(struct tb_port *port, int cm_id)
2394	{
2395	u32 val;
2396	int ret;
2397
2398	if (!is_usb4_dpin(port))
2399	return -EOPNOTSUPP;
2400
2401	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2402	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2403	if (ret)
2404	return ret;
2405
2406	val &= ~ADP_DP_CS_2_CM_ID_MASK;
2407	val |= cm_id << ADP_DP_CS_2_CM_ID_SHIFT;
2408
2409	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2410	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2411	}
2412
2413	/**
2414	* usb4_dp_port_bandwidth_mode_supported() - Is the bandwidth allocation mode
2415	* supported
2416	* @port: DP IN adapter to check
2417	*
2418	* Can be called to any DP IN adapter. Returns true if the adapter
2419	* supports USB4 bandwidth allocation mode, false otherwise.
2420	*/
2421	bool usb4_dp_port_bandwidth_mode_supported(struct tb_port *port)
2422	{
2423	int ret;
2424	u32 val;
2425
2426	if (!is_usb4_dpin(port))
2427	return false;
2428
2429	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2430	offset: port->cap_adap + DP_LOCAL_CAP, length: 1);
2431	if (ret)
2432	return false;
2433
2434	return !!(val & DP_COMMON_CAP_BW_MODE);
2435	}
2436
2437	/**
2438	* usb4_dp_port_bandwidth_mode_enabled() - Is the bandwidth allocation mode
2439	* enabled
2440	* @port: DP IN adapter to check
2441	*
2442	* Can be called to any DP IN adapter. Returns true if the bandwidth
2443	* allocation mode has been enabled, false otherwise.
2444	*/
2445	bool usb4_dp_port_bandwidth_mode_enabled(struct tb_port *port)
2446	{
2447	int ret;
2448	u32 val;
2449
2450	if (!is_usb4_dpin(port))
2451	return false;
2452
2453	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2454	offset: port->cap_adap + ADP_DP_CS_8, length: 1);
2455	if (ret)
2456	return false;
2457
2458	return !!(val & ADP_DP_CS_8_DPME);
2459	}
2460
2461	/**
2462	* usb4_dp_port_set_cm_bandwidth_mode_supported() - Set/clear CM support for
2463	* bandwidth allocation mode
2464	* @port: DP IN adapter
2465	* @supported: Does the CM support bandwidth allocation mode
2466	*
2467	* Can be called to any DP IN adapter. Sets or clears the CM support bit
2468	* of the DP IN adapter. Returns %0 in success and negative errno
2469	* otherwise. Specifically returns %-OPNOTSUPP if the passed in adapter
2470	* does not support this.
2471	*/
2472	int usb4_dp_port_set_cm_bandwidth_mode_supported(struct tb_port *port,
2473	bool supported)
2474	{
2475	u32 val;
2476	int ret;
2477
2478	if (!is_usb4_dpin(port))
2479	return -EOPNOTSUPP;
2480
2481	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2482	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2483	if (ret)
2484	return ret;
2485
2486	if (supported)
2487	val |= ADP_DP_CS_2_CMMS;
2488	else
2489	val &= ~ADP_DP_CS_2_CMMS;
2490
2491	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2492	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2493	}
2494
2495	/**
2496	* usb4_dp_port_group_id() - Return Group ID assigned for the adapter
2497	* @port: DP IN adapter
2498	*
2499	* Reads bandwidth allocation Group ID from the DP IN adapter and
2500	* returns it. If the adapter does not support setting Group_ID
2501	* %-EOPNOTSUPP is returned.
2502	*/
2503	int usb4_dp_port_group_id(struct tb_port *port)
2504	{
2505	u32 val;
2506	int ret;
2507
2508	if (!is_usb4_dpin(port))
2509	return -EOPNOTSUPP;
2510
2511	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2512	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2513	if (ret)
2514	return ret;
2515
2516	return (val & ADP_DP_CS_2_GROUP_ID_MASK) >> ADP_DP_CS_2_GROUP_ID_SHIFT;
2517	}
2518
2519	/**
2520	* usb4_dp_port_set_group_id() - Set adapter Group ID
2521	* @port: DP IN adapter
2522	* @group_id: Group ID for the adapter
2523	*
2524	* Sets bandwidth allocation mode Group ID for the DP IN adapter.
2525	* Returns %0 in case of success and negative errno otherwise.
2526	* Specifically returns %-EOPNOTSUPP if the adapter does not support
2527	* this.
2528	*/
2529	int usb4_dp_port_set_group_id(struct tb_port *port, int group_id)
2530	{
2531	u32 val;
2532	int ret;
2533
2534	if (!is_usb4_dpin(port))
2535	return -EOPNOTSUPP;
2536
2537	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2538	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2539	if (ret)
2540	return ret;
2541
2542	val &= ~ADP_DP_CS_2_GROUP_ID_MASK;
2543	val |= group_id << ADP_DP_CS_2_GROUP_ID_SHIFT;
2544
2545	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2546	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2547	}
2548
2549	/**
2550	* usb4_dp_port_nrd() - Read non-reduced rate and lanes
2551	* @port: DP IN adapter
2552	* @rate: Non-reduced rate in Mb/s is placed here
2553	* @lanes: Non-reduced lanes are placed here
2554	*
2555	* Reads the non-reduced rate and lanes from the DP IN adapter. Returns
2556	* %0 in success and negative errno otherwise. Specifically returns
2557	* %-EOPNOTSUPP if the adapter does not support this.
2558	*/
2559	int usb4_dp_port_nrd(struct tb_port *port, int *rate, int *lanes)
2560	{
2561	u32 val, tmp;
2562	int ret;
2563
2564	if (!is_usb4_dpin(port))
2565	return -EOPNOTSUPP;
2566
2567	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2568	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2569	if (ret)
2570	return ret;
2571
2572	tmp = (val & ADP_DP_CS_2_NRD_MLR_MASK) >> ADP_DP_CS_2_NRD_MLR_SHIFT;
2573	switch (tmp) {
2574	case DP_COMMON_CAP_RATE_RBR:
2575	*rate = 1620;
2576	break;
2577	case DP_COMMON_CAP_RATE_HBR:
2578	*rate = 2700;
2579	break;
2580	case DP_COMMON_CAP_RATE_HBR2:
2581	*rate = 5400;
2582	break;
2583	case DP_COMMON_CAP_RATE_HBR3:
2584	*rate = 8100;
2585	break;
2586	}
2587
2588	tmp = val & ADP_DP_CS_2_NRD_MLC_MASK;
2589	switch (tmp) {
2590	case DP_COMMON_CAP_1_LANE:
2591	*lanes = 1;
2592	break;
2593	case DP_COMMON_CAP_2_LANES:
2594	*lanes = 2;
2595	break;
2596	case DP_COMMON_CAP_4_LANES:
2597	*lanes = 4;
2598	break;
2599	}
2600
2601	return 0;
2602	}
2603
2604	/**
2605	* usb4_dp_port_set_nrd() - Set non-reduced rate and lanes
2606	* @port: DP IN adapter
2607	* @rate: Non-reduced rate in Mb/s
2608	* @lanes: Non-reduced lanes
2609	*
2610	* Before the capabilities reduction this function can be used to set
2611	* the non-reduced values for the DP IN adapter. Returns %0 in success
2612	* and negative errno otherwise. If the adapter does not support this
2613	* %-EOPNOTSUPP is returned.
2614	*/
2615	int usb4_dp_port_set_nrd(struct tb_port *port, int rate, int lanes)
2616	{
2617	u32 val;
2618	int ret;
2619
2620	if (!is_usb4_dpin(port))
2621	return -EOPNOTSUPP;
2622
2623	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2624	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2625	if (ret)
2626	return ret;
2627
2628	val &= ~ADP_DP_CS_2_NRD_MLR_MASK;
2629
2630	switch (rate) {
2631	case 1620:
2632	break;
2633	case 2700:
2634	val |= (DP_COMMON_CAP_RATE_HBR << ADP_DP_CS_2_NRD_MLR_SHIFT)
2635	& ADP_DP_CS_2_NRD_MLR_MASK;
2636	break;
2637	case 5400:
2638	val |= (DP_COMMON_CAP_RATE_HBR2 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2639	& ADP_DP_CS_2_NRD_MLR_MASK;
2640	break;
2641	case 8100:
2642	val |= (DP_COMMON_CAP_RATE_HBR3 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2643	& ADP_DP_CS_2_NRD_MLR_MASK;
2644	break;
2645	default:
2646	return -EINVAL;
2647	}
2648
2649	val &= ~ADP_DP_CS_2_NRD_MLC_MASK;
2650
2651	switch (lanes) {
2652	case 1:
2653	break;
2654	case 2:
2655	val |= DP_COMMON_CAP_2_LANES;
2656	break;
2657	case 4:
2658	val |= DP_COMMON_CAP_4_LANES;
2659	break;
2660	default:
2661	return -EINVAL;
2662	}
2663
2664	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2665	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2666	}
2667
2668	/**
2669	* usb4_dp_port_granularity() - Return granularity for the bandwidth values
2670	* @port: DP IN adapter
2671	*
2672	* Reads the programmed granularity from @port. If the DP IN adapter does
2673	* not support bandwidth allocation mode returns %-EOPNOTSUPP and negative
2674	* errno in other error cases.
2675	*/
2676	int usb4_dp_port_granularity(struct tb_port *port)
2677	{
2678	u32 val;
2679	int ret;
2680
2681	if (!is_usb4_dpin(port))
2682	return -EOPNOTSUPP;
2683
2684	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2685	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2686	if (ret)
2687	return ret;
2688
2689	val &= ADP_DP_CS_2_GR_MASK;
2690	val >>= ADP_DP_CS_2_GR_SHIFT;
2691
2692	switch (val) {
2693	case ADP_DP_CS_2_GR_0_25G:
2694	return 250;
2695	case ADP_DP_CS_2_GR_0_5G:
2696	return 500;
2697	case ADP_DP_CS_2_GR_1G:
2698	return 1000;
2699	}
2700
2701	return -EINVAL;
2702	}
2703
2704	/**
2705	* usb4_dp_port_set_granularity() - Set granularity for the bandwidth values
2706	* @port: DP IN adapter
2707	* @granularity: Granularity in Mb/s. Supported values: 1000, 500 and 250.
2708	*
2709	* Sets the granularity used with the estimated, allocated and requested
2710	* bandwidth. Returns %0 in success and negative errno otherwise. If the
2711	* adapter does not support this %-EOPNOTSUPP is returned.
2712	*/
2713	int usb4_dp_port_set_granularity(struct tb_port *port, int granularity)
2714	{
2715	u32 val;
2716	int ret;
2717
2718	if (!is_usb4_dpin(port))
2719	return -EOPNOTSUPP;
2720
2721	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2722	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2723	if (ret)
2724	return ret;
2725
2726	val &= ~ADP_DP_CS_2_GR_MASK;
2727
2728	switch (granularity) {
2729	case 250:
2730	val |= ADP_DP_CS_2_GR_0_25G << ADP_DP_CS_2_GR_SHIFT;
2731	break;
2732	case 500:
2733	val |= ADP_DP_CS_2_GR_0_5G << ADP_DP_CS_2_GR_SHIFT;
2734	break;
2735	case 1000:
2736	val |= ADP_DP_CS_2_GR_1G << ADP_DP_CS_2_GR_SHIFT;
2737	break;
2738	default:
2739	return -EINVAL;
2740	}
2741
2742	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2743	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2744	}
2745
2746	/**
2747	* usb4_dp_port_set_estimated_bandwidth() - Set estimated bandwidth
2748	* @port: DP IN adapter
2749	* @bw: Estimated bandwidth in Mb/s.
2750	*
2751	* Sets the estimated bandwidth to @bw. Set the granularity by calling
2752	* usb4_dp_port_set_granularity() before calling this. The @bw is round
2753	* down to the closest granularity multiplier. Returns %0 in success
2754	* and negative errno otherwise. Specifically returns %-EOPNOTSUPP if
2755	* the adapter does not support this.
2756	*/
2757	int usb4_dp_port_set_estimated_bandwidth(struct tb_port *port, int bw)
2758	{
2759	u32 val, granularity;
2760	int ret;
2761
2762	if (!is_usb4_dpin(port))
2763	return -EOPNOTSUPP;
2764
2765	ret = usb4_dp_port_granularity(port);
2766	if (ret < 0)
2767	return ret;
2768	granularity = ret;
2769
2770	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2771	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2772	if (ret)
2773	return ret;
2774
2775	val &= ~ADP_DP_CS_2_ESTIMATED_BW_MASK;
2776	val |= (bw / granularity) << ADP_DP_CS_2_ESTIMATED_BW_SHIFT;
2777
2778	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2779	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2780	}
2781
2782	/**
2783	* usb4_dp_port_allocated_bandwidth() - Return allocated bandwidth
2784	* @port: DP IN adapter
2785	*
2786	* Reads and returns allocated bandwidth for @port in Mb/s (taking into
2787	* account the programmed granularity). Returns negative errno in case
2788	* of error.
2789	*/
2790	int usb4_dp_port_allocated_bandwidth(struct tb_port *port)
2791	{
2792	u32 val, granularity;
2793	int ret;
2794
2795	if (!is_usb4_dpin(port))
2796	return -EOPNOTSUPP;
2797
2798	ret = usb4_dp_port_granularity(port);
2799	if (ret < 0)
2800	return ret;
2801	granularity = ret;
2802
2803	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2804	offset: port->cap_adap + DP_STATUS, length: 1);
2805	if (ret)
2806	return ret;
2807
2808	val &= DP_STATUS_ALLOCATED_BW_MASK;
2809	val >>= DP_STATUS_ALLOCATED_BW_SHIFT;
2810
2811	return val * granularity;
2812	}
2813
2814	static int __usb4_dp_port_set_cm_ack(struct tb_port *port, bool ack)
2815	{
2816	u32 val;
2817	int ret;
2818
2819	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2820	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2821	if (ret)
2822	return ret;
2823
2824	if (ack)
2825	val |= ADP_DP_CS_2_CA;
2826	else
2827	val &= ~ADP_DP_CS_2_CA;
2828
2829	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2830	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2831	}
2832
2833	static inline int usb4_dp_port_set_cm_ack(struct tb_port *port)
2834	{
2835	return __usb4_dp_port_set_cm_ack(port, ack: true);
2836	}
2837
2838	static int usb4_dp_port_wait_and_clear_cm_ack(struct tb_port *port,
2839	int timeout_msec)
2840	{
2841	ktime_t end;
2842	u32 val;
2843	int ret;
2844
2845	ret = __usb4_dp_port_set_cm_ack(port, ack: false);
2846	if (ret)
2847	return ret;
2848
2849	end = ktime_add_ms(kt: ktime_get(), msec: timeout_msec);
2850	do {
2851	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2852	offset: port->cap_adap + ADP_DP_CS_8, length: 1);
2853	if (ret)
2854	return ret;
2855
2856	if (!(val & ADP_DP_CS_8_DR))
2857	break;
2858
2859	usleep_range(min: 50, max: 100);
2860	} while (ktime_before(cmp1: ktime_get(), cmp2: end));
2861
2862	if (val & ADP_DP_CS_8_DR) {
2863	tb_port_warn(port, "timeout waiting for DPTX request to clear\n");
2864	return -ETIMEDOUT;
2865	}
2866
2867	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2868	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2869	if (ret)
2870	return ret;
2871
2872	val &= ~ADP_DP_CS_2_CA;
2873	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2874	offset: port->cap_adap + ADP_DP_CS_2, length: 1);
2875	}
2876
2877	/**
2878	* usb4_dp_port_allocate_bandwidth() - Set allocated bandwidth
2879	* @port: DP IN adapter
2880	* @bw: New allocated bandwidth in Mb/s
2881	*
2882	* Communicates the new allocated bandwidth with the DPCD (graphics
2883	* driver). Takes into account the programmed granularity. Returns %0 in
2884	* success and negative errno in case of error.
2885	*/
2886	int usb4_dp_port_allocate_bandwidth(struct tb_port *port, int bw)
2887	{
2888	u32 val, granularity;
2889	int ret;
2890
2891	if (!is_usb4_dpin(port))
2892	return -EOPNOTSUPP;
2893
2894	ret = usb4_dp_port_granularity(port);
2895	if (ret < 0)
2896	return ret;
2897	granularity = ret;
2898
2899	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2900	offset: port->cap_adap + DP_STATUS, length: 1);
2901	if (ret)
2902	return ret;
2903
2904	val &= ~DP_STATUS_ALLOCATED_BW_MASK;
2905	val |= (bw / granularity) << DP_STATUS_ALLOCATED_BW_SHIFT;
2906
2907	ret = tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2908	offset: port->cap_adap + DP_STATUS, length: 1);
2909	if (ret)
2910	return ret;
2911
2912	ret = usb4_dp_port_set_cm_ack(port);
2913	if (ret)
2914	return ret;
2915
2916	return usb4_dp_port_wait_and_clear_cm_ack(port, timeout_msec: 500);
2917	}
2918
2919	/**
2920	* usb4_dp_port_requested_bandwidth() - Read requested bandwidth
2921	* @port: DP IN adapter
2922	*
2923	* Reads the DPCD (graphics driver) requested bandwidth and returns it
2924	* in Mb/s. Takes the programmed granularity into account. In case of
2925	* error returns negative errno. Specifically returns %-EOPNOTSUPP if
2926	* the adapter does not support bandwidth allocation mode, and %ENODATA
2927	* if there is no active bandwidth request from the graphics driver.
2928	*/
2929	int usb4_dp_port_requested_bandwidth(struct tb_port *port)
2930	{
2931	u32 val, granularity;
2932	int ret;
2933
2934	if (!is_usb4_dpin(port))
2935	return -EOPNOTSUPP;
2936
2937	ret = usb4_dp_port_granularity(port);
2938	if (ret < 0)
2939	return ret;
2940	granularity = ret;
2941
2942	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2943	offset: port->cap_adap + ADP_DP_CS_8, length: 1);
2944	if (ret)
2945	return ret;
2946
2947	if (!(val & ADP_DP_CS_8_DR))
2948	return -ENODATA;
2949
2950	return (val & ADP_DP_CS_8_REQUESTED_BW_MASK) * granularity;
2951	}
2952
2953	/**
2954	* usb4_pci_port_set_ext_encapsulation() - Enable/disable extended encapsulation
2955	* @port: PCIe adapter
2956	* @enable: Enable/disable extended encapsulation
2957	*
2958	* Enables or disables extended encapsulation used in PCIe tunneling. Caller
2959	* needs to make sure both adapters support this before enabling. Returns %0 on
2960	* success and negative errno otherwise.
2961	*/
2962	int usb4_pci_port_set_ext_encapsulation(struct tb_port *port, bool enable)
2963	{
2964	u32 val;
2965	int ret;
2966
2967	if (!tb_port_is_pcie_up(port) && !tb_port_is_pcie_down(port))
2968	return -EINVAL;
2969
2970	ret = tb_port_read(port, buffer: &val, space: TB_CFG_PORT,
2971	offset: port->cap_adap + ADP_PCIE_CS_1, length: 1);
2972	if (ret)
2973	return ret;
2974
2975	if (enable)
2976	val |= ADP_PCIE_CS_1_EE;
2977	else
2978	val &= ~ADP_PCIE_CS_1_EE;
2979
2980	return tb_port_write(port, buffer: &val, space: TB_CFG_PORT,
2981	offset: port->cap_adap + ADP_PCIE_CS_1, length: 1);
2982	}
2983