| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * UFS Host driver for Synopsys Designware Core |
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| 4 | * |
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| 5 | * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) |
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| 6 | * |
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| 7 | * Authors: Joao Pinto <jpinto@synopsys.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef _UFSHCI_DWC_H |
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| 11 | #define _UFSHCI_DWC_H |
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| 12 | |
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| 13 | /* DWC HC UFSHCI specific Registers */ |
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| 14 | enum dwc_specific_registers { |
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| 15 | DWC_UFS_REG_HCLKDIV = 0xFC, |
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| 16 | }; |
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| 17 | |
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| 18 | /* Clock Divider Values: Hex equivalent of frequency in MHz */ |
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| 19 | enum clk_div_values { |
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| 20 | DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e, |
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| 21 | DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d, |
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| 22 | DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8, |
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| 23 | }; |
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| 24 | |
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| 25 | /* Selector Index */ |
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| 26 | enum selector_index { |
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| 27 | SELIND_LN0_TX = 0x00, |
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| 28 | SELIND_LN1_TX = 0x01, |
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| 29 | SELIND_LN0_RX = 0x04, |
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| 30 | SELIND_LN1_RX = 0x05, |
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| 31 | }; |
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| 32 | |
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| 33 | #endif /* End of Header */ |
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| 34 | |
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