1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Faraday FOTG210 USB OTG controller |
4 | * |
5 | * Copyright (C) 2013 Faraday Technology Corporation |
6 | * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com> |
7 | */ |
8 | |
9 | #include <linux/kernel.h> |
10 | |
11 | #define FOTG210_MAX_NUM_EP 5 /* ep0...ep4 */ |
12 | #define FOTG210_MAX_FIFO_NUM 4 /* fifo0...fifo4 */ |
13 | |
14 | /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */ |
15 | #define FOTG210_GMIR 0xC4 |
16 | #define GMIR_INT_POLARITY 0x8 /*Active High*/ |
17 | #define GMIR_MHC_INT 0x4 |
18 | #define GMIR_MOTG_INT 0x2 |
19 | #define GMIR_MDEV_INT 0x1 |
20 | |
21 | /* Device Main Control Register(0x100) */ |
22 | #define FOTG210_DMCR 0x100 |
23 | #define DMCR_HS_EN (1 << 6) |
24 | #define DMCR_CHIP_EN (1 << 5) |
25 | #define DMCR_SFRST (1 << 4) |
26 | #define DMCR_GOSUSP (1 << 3) |
27 | #define DMCR_GLINT_EN (1 << 2) |
28 | #define DMCR_HALF_SPEED (1 << 1) |
29 | #define DMCR_CAP_RMWAKUP (1 << 0) |
30 | |
31 | /* Device Address Register(0x104) */ |
32 | #define FOTG210_DAR 0x104 |
33 | #define DAR_AFT_CONF (1 << 7) |
34 | |
35 | /* Device Test Register(0x108) */ |
36 | #define FOTG210_DTR 0x108 |
37 | #define DTR_TST_CLRFF (1 << 0) |
38 | |
39 | /* PHY Test Mode Selector register(0x114) */ |
40 | #define FOTG210_PHYTMSR 0x114 |
41 | #define PHYTMSR_TST_PKT (1 << 4) |
42 | #define PHYTMSR_TST_SE0NAK (1 << 3) |
43 | #define PHYTMSR_TST_KSTA (1 << 2) |
44 | #define PHYTMSR_TST_JSTA (1 << 1) |
45 | #define PHYTMSR_UNPLUG (1 << 0) |
46 | |
47 | /* Cx configuration and FIFO Empty Status register(0x120) */ |
48 | #define FOTG210_DCFESR 0x120 |
49 | #define DCFESR_FIFO_EMPTY(fifo) (1 << 8 << (fifo)) |
50 | #define DCFESR_CX_EMP (1 << 5) |
51 | #define DCFESR_CX_CLR (1 << 3) |
52 | #define DCFESR_CX_STL (1 << 2) |
53 | #define DCFESR_TST_PKDONE (1 << 1) |
54 | #define DCFESR_CX_DONE (1 << 0) |
55 | |
56 | /* Device IDLE Counter Register(0x124) */ |
57 | #define FOTG210_DICR 0x124 |
58 | |
59 | /* Device Mask of Interrupt Group Register (0x130) */ |
60 | #define FOTG210_DMIGR 0x130 |
61 | #define DMIGR_MINT_G2 (1 << 2) |
62 | #define DMIGR_MINT_G1 (1 << 1) |
63 | #define DMIGR_MINT_G0 (1 << 0) |
64 | |
65 | /* Device Mask of Interrupt Source Group 0(0x134) */ |
66 | #define FOTG210_DMISGR0 0x134 |
67 | #define DMISGR0_MCX_COMEND (1 << 3) |
68 | #define DMISGR0_MCX_OUT_INT (1 << 2) |
69 | #define DMISGR0_MCX_IN_INT (1 << 1) |
70 | #define DMISGR0_MCX_SETUP_INT (1 << 0) |
71 | |
72 | /* Device Mask of Interrupt Source Group 1 Register(0x138)*/ |
73 | #define FOTG210_DMISGR1 0x138 |
74 | #define DMISGR1_MF3_IN_INT (1 << 19) |
75 | #define DMISGR1_MF2_IN_INT (1 << 18) |
76 | #define DMISGR1_MF1_IN_INT (1 << 17) |
77 | #define DMISGR1_MF0_IN_INT (1 << 16) |
78 | #define DMISGR1_MF_IN_INT(fifo) (1 << (16 + (fifo))) |
79 | #define DMISGR1_MF3_SPK_INT (1 << 7) |
80 | #define DMISGR1_MF3_OUT_INT (1 << 6) |
81 | #define DMISGR1_MF2_SPK_INT (1 << 5) |
82 | #define DMISGR1_MF2_OUT_INT (1 << 4) |
83 | #define DMISGR1_MF1_SPK_INT (1 << 3) |
84 | #define DMISGR1_MF1_OUT_INT (1 << 2) |
85 | #define DMISGR1_MF0_SPK_INT (1 << 1) |
86 | #define DMISGR1_MF0_OUT_INT (1 << 0) |
87 | #define DMISGR1_MF_OUTSPK_INT(fifo) (0x3 << (fifo) * 2) |
88 | |
89 | /* Device Mask of Interrupt Source Group 2 Register (0x13C) */ |
90 | #define FOTG210_DMISGR2 0x13C |
91 | #define DMISGR2_MDMA_ERROR (1 << 8) |
92 | #define DMISGR2_MDMA_CMPLT (1 << 7) |
93 | |
94 | /* Device Interrupt group Register (0x140) */ |
95 | #define FOTG210_DIGR 0x140 |
96 | #define DIGR_INT_G2 (1 << 2) |
97 | #define DIGR_INT_G1 (1 << 1) |
98 | #define DIGR_INT_G0 (1 << 0) |
99 | |
100 | /* Device Interrupt Source Group 0 Register (0x144) */ |
101 | #define FOTG210_DISGR0 0x144 |
102 | #define DISGR0_CX_COMABT_INT (1 << 5) |
103 | #define DISGR0_CX_COMFAIL_INT (1 << 4) |
104 | #define DISGR0_CX_COMEND_INT (1 << 3) |
105 | #define DISGR0_CX_OUT_INT (1 << 2) |
106 | #define DISGR0_CX_IN_INT (1 << 1) |
107 | #define DISGR0_CX_SETUP_INT (1 << 0) |
108 | |
109 | /* Device Interrupt Source Group 1 Register (0x148) */ |
110 | #define FOTG210_DISGR1 0x148 |
111 | #define DISGR1_OUT_INT(fifo) (1 << ((fifo) * 2)) |
112 | #define DISGR1_SPK_INT(fifo) (1 << 1 << ((fifo) * 2)) |
113 | #define DISGR1_IN_INT(fifo) (1 << 16 << (fifo)) |
114 | |
115 | /* Device Interrupt Source Group 2 Register (0x14C) */ |
116 | #define FOTG210_DISGR2 0x14C |
117 | #define DISGR2_DMA_ERROR (1 << 8) |
118 | #define DISGR2_DMA_CMPLT (1 << 7) |
119 | #define DISGR2_RX0BYTE_INT (1 << 6) |
120 | #define DISGR2_TX0BYTE_INT (1 << 5) |
121 | #define DISGR2_ISO_SEQ_ABORT_INT (1 << 4) |
122 | #define DISGR2_ISO_SEQ_ERR_INT (1 << 3) |
123 | #define DISGR2_RESM_INT (1 << 2) |
124 | #define DISGR2_SUSP_INT (1 << 1) |
125 | #define DISGR2_USBRST_INT (1 << 0) |
126 | |
127 | /* Device Receive Zero-Length Data Packet Register (0x150)*/ |
128 | #define FOTG210_RX0BYTE 0x150 |
129 | #define RX0BYTE_EP8 (1 << 7) |
130 | #define RX0BYTE_EP7 (1 << 6) |
131 | #define RX0BYTE_EP6 (1 << 5) |
132 | #define RX0BYTE_EP5 (1 << 4) |
133 | #define RX0BYTE_EP4 (1 << 3) |
134 | #define RX0BYTE_EP3 (1 << 2) |
135 | #define RX0BYTE_EP2 (1 << 1) |
136 | #define RX0BYTE_EP1 (1 << 0) |
137 | |
138 | /* Device Transfer Zero-Length Data Packet Register (0x154)*/ |
139 | #define FOTG210_TX0BYTE 0x154 |
140 | #define TX0BYTE_EP8 (1 << 7) |
141 | #define TX0BYTE_EP7 (1 << 6) |
142 | #define TX0BYTE_EP6 (1 << 5) |
143 | #define TX0BYTE_EP5 (1 << 4) |
144 | #define TX0BYTE_EP4 (1 << 3) |
145 | #define TX0BYTE_EP3 (1 << 2) |
146 | #define TX0BYTE_EP2 (1 << 1) |
147 | #define TX0BYTE_EP1 (1 << 0) |
148 | |
149 | /* Device IN Endpoint x MaxPacketSize Register(0x160+4*(x-1)) */ |
150 | #define FOTG210_INEPMPSR(ep) (0x160 + 4 * ((ep) - 1)) |
151 | #define INOUTEPMPSR_MPS(mps) ((mps) & 0x2FF) |
152 | #define INOUTEPMPSR_STL_EP (1 << 11) |
153 | #define INOUTEPMPSR_RESET_TSEQ (1 << 12) |
154 | |
155 | /* Device OUT Endpoint x MaxPacketSize Register(0x180+4*(x-1)) */ |
156 | #define FOTG210_OUTEPMPSR(ep) (0x180 + 4 * ((ep) - 1)) |
157 | |
158 | /* Device Endpoint 1~4 Map Register (0x1A0) */ |
159 | #define FOTG210_EPMAP 0x1A0 |
160 | #define EPMAP_FIFONO(ep, dir) \ |
161 | ((((ep) - 1) << ((ep) - 1) * 8) << ((dir) ? 0 : 4)) |
162 | #define EPMAP_FIFONOMSK(ep, dir) \ |
163 | ((3 << ((ep) - 1) * 8) << ((dir) ? 0 : 4)) |
164 | |
165 | /* Device FIFO Map Register (0x1A8) */ |
166 | #define FOTG210_FIFOMAP 0x1A8 |
167 | #define FIFOMAP_DIROUT(fifo) (0x0 << 4 << (fifo) * 8) |
168 | #define FIFOMAP_DIRIN(fifo) (0x1 << 4 << (fifo) * 8) |
169 | #define FIFOMAP_BIDIR(fifo) (0x2 << 4 << (fifo) * 8) |
170 | #define FIFOMAP_NA(fifo) (0x3 << 4 << (fifo) * 8) |
171 | #define FIFOMAP_EPNO(ep) ((ep) << ((ep) - 1) * 8) |
172 | #define FIFOMAP_EPNOMSK(ep) (0xF << ((ep) - 1) * 8) |
173 | |
174 | /* Device FIFO Confuguration Register (0x1AC) */ |
175 | #define FOTG210_FIFOCF 0x1AC |
176 | #define FIFOCF_TYPE(type, fifo) ((type) << (fifo) * 8) |
177 | #define FIFOCF_BLK_SIN(fifo) (0x0 << (fifo) * 8 << 2) |
178 | #define FIFOCF_BLK_DUB(fifo) (0x1 << (fifo) * 8 << 2) |
179 | #define FIFOCF_BLK_TRI(fifo) (0x2 << (fifo) * 8 << 2) |
180 | #define FIFOCF_BLKSZ_512(fifo) (0x0 << (fifo) * 8 << 4) |
181 | #define FIFOCF_BLKSZ_1024(fifo) (0x1 << (fifo) * 8 << 4) |
182 | #define FIFOCF_FIFO_EN(fifo) (0x1 << (fifo) * 8 << 5) |
183 | |
184 | /* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */ |
185 | #define FOTG210_FIBCR(fifo) (0x1B0 + (fifo) * 4) |
186 | #define FIBCR_BCFX 0x7FF |
187 | #define FIBCR_FFRST (1 << 12) |
188 | |
189 | /* Device DMA Target FIFO Number Register (0x1C0) */ |
190 | #define FOTG210_DMATFNR 0x1C0 |
191 | #define DMATFNR_ACC_CXF (1 << 4) |
192 | #define DMATFNR_ACC_F3 (1 << 3) |
193 | #define DMATFNR_ACC_F2 (1 << 2) |
194 | #define DMATFNR_ACC_F1 (1 << 1) |
195 | #define DMATFNR_ACC_F0 (1 << 0) |
196 | #define DMATFNR_ACC_FN(fifo) (1 << (fifo)) |
197 | #define DMATFNR_DISDMA 0 |
198 | |
199 | /* Device DMA Controller Parameter setting 1 Register (0x1C8) */ |
200 | #define FOTG210_DMACPSR1 0x1C8 |
201 | #define DMACPSR1_DMA_LEN(len) (((len) & 0xFFFF) << 8) |
202 | #define DMACPSR1_DMA_ABORT (1 << 3) |
203 | #define DMACPSR1_DMA_TYPE(dir_in) (((dir_in) ? 1 : 0) << 1) |
204 | #define DMACPSR1_DMA_START (1 << 0) |
205 | |
206 | /* Device DMA Controller Parameter setting 2 Register (0x1CC) */ |
207 | #define FOTG210_DMACPSR2 0x1CC |
208 | |
209 | /* Device DMA Controller Parameter setting 3 Register (0x1CC) */ |
210 | #define FOTG210_CXPORT 0x1D0 |
211 | |
212 | struct fotg210_request { |
213 | struct usb_request req; |
214 | struct list_head queue; |
215 | }; |
216 | |
217 | struct fotg210_ep { |
218 | struct usb_ep ep; |
219 | struct fotg210_udc *fotg210; |
220 | |
221 | struct list_head queue; |
222 | unsigned stall:1; |
223 | unsigned wedged:1; |
224 | unsigned use_dma:1; |
225 | |
226 | unsigned char epnum; |
227 | unsigned char type; |
228 | unsigned char dir_in; |
229 | unsigned int maxp; |
230 | const struct usb_endpoint_descriptor *desc; |
231 | }; |
232 | |
233 | struct fotg210_udc { |
234 | spinlock_t lock; /* protect the struct */ |
235 | void __iomem *reg; |
236 | |
237 | unsigned long irq_trigger; |
238 | |
239 | struct device *dev; |
240 | struct fotg210 *fotg; |
241 | struct usb_phy *phy; |
242 | struct usb_gadget gadget; |
243 | struct usb_gadget_driver *driver; |
244 | |
245 | struct fotg210_ep *ep[FOTG210_MAX_NUM_EP]; |
246 | |
247 | struct usb_request *ep0_req; /* for internal request */ |
248 | __le16 ep0_data; |
249 | u8 ep0_dir; /* 0/0x80 out/in */ |
250 | |
251 | u8 reenum; /* if re-enumeration */ |
252 | }; |
253 | |
254 | #define gadget_to_fotg210(g) container_of((g), struct fotg210_udc, gadget) |
255 | |