| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
|---|
| 2 | /* |
|---|
| 3 | * drivers/watchdog/at91sam9_wdt.h |
|---|
| 4 | * |
|---|
| 5 | * Copyright (C) 2007 Andrew Victor |
|---|
| 6 | * Copyright (C) 2007 Atmel Corporation. |
|---|
| 7 | * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries |
|---|
| 8 | * |
|---|
| 9 | * Watchdog Timer (WDT) - System peripherals regsters. |
|---|
| 10 | * Based on AT91SAM9261 datasheet revision D. |
|---|
| 11 | * Based on SAM9X60 datasheet. |
|---|
| 12 | * |
|---|
| 13 | */ |
|---|
| 14 | |
|---|
| 15 | #ifndef AT91_WDT_H |
|---|
| 16 | #define AT91_WDT_H |
|---|
| 17 | |
|---|
| 18 | #include <linux/bits.h> |
|---|
| 19 | |
|---|
| 20 | #define AT91_WDT_CR 0x00 /* Watchdog Control Register */ |
|---|
| 21 | #define AT91_WDT_WDRSTT BIT(0) /* Restart */ |
|---|
| 22 | #define AT91_WDT_KEY (0xa5UL << 24) /* KEY Password */ |
|---|
| 23 | |
|---|
| 24 | #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ |
|---|
| 25 | #define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */ |
|---|
| 26 | #define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV) |
|---|
| 27 | #define AT91_SAM9X60_PERIODRST BIT(4) /* Period Reset */ |
|---|
| 28 | #define AT91_SAM9X60_RPTHRST BIT(5) /* Minimum Restart Period */ |
|---|
| 29 | #define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */ |
|---|
| 30 | #define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */ |
|---|
| 31 | #define AT91_WDT_WDRSTEN BIT(13) /* Reset Processor */ |
|---|
| 32 | #define AT91_WDT_WDRPROC BIT(14) /* Timer Restart */ |
|---|
| 33 | #define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */ |
|---|
| 34 | #define AT91_WDT_WDD (0xfffUL << 16) /* Delta Value */ |
|---|
| 35 | #define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD) |
|---|
| 36 | #define AT91_WDT_WDDBGHLT BIT(28) /* Debug Halt */ |
|---|
| 37 | #define AT91_WDT_WDIDLEHLT BIT(29) /* Idle Halt */ |
|---|
| 38 | |
|---|
| 39 | #define AT91_WDT_SR 0x08 /* Watchdog Status Register */ |
|---|
| 40 | #define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */ |
|---|
| 41 | #define AT91_WDT_WDERR BIT(1) /* Watchdog Error */ |
|---|
| 42 | |
|---|
| 43 | /* Watchdog Timer Value Register */ |
|---|
| 44 | #define AT91_SAM9X60_VR 0x08 |
|---|
| 45 | |
|---|
| 46 | /* Watchdog Window Level Register */ |
|---|
| 47 | #define AT91_SAM9X60_WLR 0x0c |
|---|
| 48 | /* Watchdog Period Value */ |
|---|
| 49 | #define AT91_SAM9X60_COUNTER (0xfffUL << 0) |
|---|
| 50 | #define AT91_SAM9X60_SET_COUNTER(x) ((x) & AT91_SAM9X60_COUNTER) |
|---|
| 51 | |
|---|
| 52 | /* Interrupt Enable Register */ |
|---|
| 53 | #define AT91_SAM9X60_IER 0x14 |
|---|
| 54 | /* Period Interrupt Enable */ |
|---|
| 55 | #define AT91_SAM9X60_PERINT BIT(0) |
|---|
| 56 | /* Interrupt Disable Register */ |
|---|
| 57 | #define AT91_SAM9X60_IDR 0x18 |
|---|
| 58 | /* Interrupt Status Register */ |
|---|
| 59 | #define AT91_SAM9X60_ISR 0x1c |
|---|
| 60 | |
|---|
| 61 | #endif |
|---|
| 62 | |
|---|
