| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2007-2017 Cavium, Inc. |
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| 4 | */ |
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| 5 | #include <asm/asm.h> |
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| 6 | #include <asm/regdef.h> |
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| 7 | |
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| 8 | #define CVMSEG_BASE -32768 |
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| 9 | #define CVMSEG_SIZE 6912 |
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| 10 | #define SAVE_REG(r) sd $r, CVMSEG_BASE + CVMSEG_SIZE - ((32 - r) * 8)($0) |
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| 11 | |
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| 12 | NESTED(octeon_wdt_nmi_stage2, 0, sp) |
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| 13 | .set push |
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| 14 | .set noreorder |
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| 15 | .set noat |
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| 16 | /* Clear Dcache so cvmseg works right. */ |
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| 17 | cache 1,0($0) |
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| 18 | /* Use K0 to do a read/modify/write of CVMMEMCTL */ |
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| 19 | dmfc0 k0, $11, 7 |
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| 20 | /* Clear out the size of CVMSEG */ |
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| 21 | dins k0, $0, 0, 6 |
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| 22 | /* Set CVMSEG to its largest value */ |
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| 23 | ori k0, k0, 0x1c0 | 54 |
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| 24 | /* Store the CVMMEMCTL value */ |
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| 25 | dmtc0 k0, $11, 7 |
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| 26 | /* |
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| 27 | * Restore K0 from the debug scratch register, it was saved in |
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| 28 | * the boot-vector code. |
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| 29 | */ |
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| 30 | dmfc0 k0, $31 |
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| 31 | |
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| 32 | /* |
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| 33 | * Save all registers to the top CVMSEG. This shouldn't |
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| 34 | * corrupt any state used by the kernel. Also all registers |
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| 35 | * should have the value right before the NMI. |
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| 36 | */ |
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| 37 | SAVE_REG(0) |
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| 38 | SAVE_REG(1) |
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| 39 | SAVE_REG(2) |
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| 40 | SAVE_REG(3) |
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| 41 | SAVE_REG(4) |
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| 42 | SAVE_REG(5) |
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| 43 | SAVE_REG(6) |
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| 44 | SAVE_REG(7) |
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| 45 | SAVE_REG(8) |
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| 46 | SAVE_REG(9) |
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| 47 | SAVE_REG(10) |
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| 48 | SAVE_REG(11) |
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| 49 | SAVE_REG(12) |
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| 50 | SAVE_REG(13) |
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| 51 | SAVE_REG(14) |
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| 52 | SAVE_REG(15) |
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| 53 | SAVE_REG(16) |
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| 54 | SAVE_REG(17) |
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| 55 | SAVE_REG(18) |
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| 56 | SAVE_REG(19) |
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| 57 | SAVE_REG(20) |
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| 58 | SAVE_REG(21) |
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| 59 | SAVE_REG(22) |
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| 60 | SAVE_REG(23) |
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| 61 | SAVE_REG(24) |
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| 62 | SAVE_REG(25) |
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| 63 | SAVE_REG(26) |
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| 64 | SAVE_REG(27) |
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| 65 | SAVE_REG(28) |
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| 66 | SAVE_REG(29) |
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| 67 | SAVE_REG(30) |
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| 68 | SAVE_REG(31) |
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| 69 | /* Write zero to all CVMSEG locations per Core-15169 */ |
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| 70 | dli a0, CVMSEG_SIZE - (33 * 8) |
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| 71 | 1: sd zero, CVMSEG_BASE(a0) |
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| 72 | daddiu a0, a0, -8 |
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| 73 | bgez a0, 1b |
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| 74 | nop |
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| 75 | /* Set the stack to begin right below the registers */ |
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| 76 | dli sp, CVMSEG_BASE + CVMSEG_SIZE - (32 * 8) |
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| 77 | /* Load the address of the third stage handler */ |
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| 78 | dla $25, octeon_wdt_nmi_stage3 |
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| 79 | /* Call the third stage handler */ |
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| 80 | jal $25 |
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| 81 | /* a0 is the address of the saved registers */ |
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| 82 | move a0, sp |
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| 83 | /* Loop forvever if we get here. */ |
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| 84 | 2: b 2b |
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| 85 | nop |
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| 86 | .set pop |
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| 87 | END(octeon_wdt_nmi_stage2) |
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| 88 | |
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