1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Xilinx Zynq MPSoC Firmware layer |
4 | * |
5 | * Copyright (C) 2014-2021 Xilinx |
6 | * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. |
7 | * |
8 | * Michal Simek <michal.simek@amd.com> |
9 | * Davorin Mista <davorin.mista@aggios.com> |
10 | * Jolly Shah <jollys@xilinx.com> |
11 | * Rajan Vaja <rajanv@xilinx.com> |
12 | */ |
13 | |
14 | #ifndef __FIRMWARE_ZYNQMP_H__ |
15 | #define __FIRMWARE_ZYNQMP_H__ |
16 | #include <linux/types.h> |
17 | |
18 | #include <linux/err.h> |
19 | |
20 | #define ZYNQMP_PM_VERSION_MAJOR 1 |
21 | #define ZYNQMP_PM_VERSION_MINOR 0 |
22 | |
23 | #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \ |
24 | ZYNQMP_PM_VERSION_MINOR) |
25 | |
26 | #define ZYNQMP_TZ_VERSION_MAJOR 1 |
27 | #define ZYNQMP_TZ_VERSION_MINOR 0 |
28 | |
29 | #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \ |
30 | ZYNQMP_TZ_VERSION_MINOR) |
31 | |
32 | /* SMC SIP service Call Function Identifier Prefix */ |
33 | #define PM_SIP_SVC 0xC2000000 |
34 | |
35 | /* PM API versions */ |
36 | #define PM_API_VERSION_1 1 |
37 | #define PM_API_VERSION_2 2 |
38 | |
39 | #define PM_PINCTRL_PARAM_SET_VERSION 2 |
40 | |
41 | #define ZYNQMP_FAMILY_CODE 0x23 |
42 | #define VERSAL_FAMILY_CODE 0x26 |
43 | |
44 | /* When all subfamily of platform need to support */ |
45 | #define ALL_SUB_FAMILY_CODE 0x00 |
46 | #define VERSAL_SUB_FAMILY_CODE 0x01 |
47 | #define VERSALNET_SUB_FAMILY_CODE 0x03 |
48 | |
49 | #define FAMILY_CODE_MASK GENMASK(27, 21) |
50 | #define SUB_FAMILY_CODE_MASK GENMASK(20, 19) |
51 | |
52 | #define API_ID_MASK GENMASK(7, 0) |
53 | #define MODULE_ID_MASK GENMASK(11, 8) |
54 | |
55 | /* ATF only commands */ |
56 | #define TF_A_PM_REGISTER_SGI 0xa04 |
57 | #define PM_GET_TRUSTZONE_VERSION 0xa03 |
58 | #define PM_SET_SUSPEND_MODE 0xa02 |
59 | #define GET_CALLBACK_DATA 0xa01 |
60 | |
61 | /* Number of 32bits values in payload */ |
62 | #define PAYLOAD_ARG_CNT 4U |
63 | |
64 | /* Number of arguments for a callback */ |
65 | #define CB_ARG_CNT 4 |
66 | |
67 | /* Payload size (consists of callback API ID + arguments) */ |
68 | #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1) |
69 | |
70 | #define ZYNQMP_PM_MAX_QOS 100U |
71 | |
72 | #define GSS_NUM_REGS (4) |
73 | |
74 | /* Node capabilities */ |
75 | #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U |
76 | #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U |
77 | #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U |
78 | #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U |
79 | |
80 | /* Loader commands */ |
81 | #define PM_LOAD_PDI 0x701 |
82 | #define PDI_SRC_DDR 0xF |
83 | |
84 | /* |
85 | * Firmware FPGA Manager flags |
86 | * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration |
87 | * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration |
88 | */ |
89 | #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U |
90 | #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) |
91 | |
92 | /* FPGA Status Reg */ |
93 | #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U |
94 | #define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U |
95 | |
96 | /* |
97 | * Node IDs for the Error Events. |
98 | */ |
99 | #define VERSAL_EVENT_ERROR_PMC_ERR1 (0x28100000U) |
100 | #define VERSAL_EVENT_ERROR_PMC_ERR2 (0x28104000U) |
101 | #define VERSAL_EVENT_ERROR_PSM_ERR1 (0x28108000U) |
102 | #define VERSAL_EVENT_ERROR_PSM_ERR2 (0x2810C000U) |
103 | |
104 | #define VERSAL_NET_EVENT_ERROR_PMC_ERR1 (0x28100000U) |
105 | #define VERSAL_NET_EVENT_ERROR_PMC_ERR2 (0x28104000U) |
106 | #define VERSAL_NET_EVENT_ERROR_PMC_ERR3 (0x28108000U) |
107 | #define VERSAL_NET_EVENT_ERROR_PSM_ERR1 (0x2810C000U) |
108 | #define VERSAL_NET_EVENT_ERROR_PSM_ERR2 (0x28110000U) |
109 | #define VERSAL_NET_EVENT_ERROR_PSM_ERR3 (0x28114000U) |
110 | #define VERSAL_NET_EVENT_ERROR_PSM_ERR4 (0x28118000U) |
111 | |
112 | /* ZynqMP SD tap delay tuning */ |
113 | #define SD_ITAPDLY 0xFF180314 |
114 | #define SD_OTAPDLYSEL 0xFF180318 |
115 | |
116 | /** |
117 | * XPM_EVENT_ERROR_MASK_DDRMC_CR: Error event mask for DDRMC MC Correctable ECC Error. |
118 | */ |
119 | #define XPM_EVENT_ERROR_MASK_DDRMC_CR BIT(18) |
120 | |
121 | /** |
122 | * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error. |
123 | */ |
124 | #define XPM_EVENT_ERROR_MASK_DDRMC_NCR BIT(19) |
125 | #define XPM_EVENT_ERROR_MASK_NOC_NCR BIT(13) |
126 | #define XPM_EVENT_ERROR_MASK_NOC_CR BIT(12) |
127 | |
128 | enum pm_module_id { |
129 | PM_MODULE_ID = 0x0, |
130 | XSEM_MODULE_ID = 0x3, |
131 | TF_A_MODULE_ID = 0xa, |
132 | }; |
133 | |
134 | enum pm_api_cb_id { |
135 | PM_INIT_SUSPEND_CB = 30, |
136 | PM_ACKNOWLEDGE_CB = 31, |
137 | PM_NOTIFY_CB = 32, |
138 | }; |
139 | |
140 | enum pm_api_id { |
141 | PM_API_FEATURES = 0, |
142 | PM_GET_API_VERSION = 1, |
143 | PM_REGISTER_NOTIFIER = 5, |
144 | PM_FORCE_POWERDOWN = 8, |
145 | PM_REQUEST_WAKEUP = 10, |
146 | PM_SYSTEM_SHUTDOWN = 12, |
147 | PM_REQUEST_NODE = 13, |
148 | PM_RELEASE_NODE = 14, |
149 | PM_SET_REQUIREMENT = 15, |
150 | PM_RESET_ASSERT = 17, |
151 | PM_RESET_GET_STATUS = 18, |
152 | PM_MMIO_WRITE = 19, |
153 | PM_MMIO_READ = 20, |
154 | PM_PM_INIT_FINALIZE = 21, |
155 | PM_FPGA_LOAD = 22, |
156 | PM_FPGA_GET_STATUS = 23, |
157 | PM_GET_CHIPID = 24, |
158 | PM_SECURE_SHA = 26, |
159 | PM_PINCTRL_REQUEST = 28, |
160 | PM_PINCTRL_RELEASE = 29, |
161 | PM_PINCTRL_SET_FUNCTION = 31, |
162 | PM_PINCTRL_CONFIG_PARAM_GET = 32, |
163 | PM_PINCTRL_CONFIG_PARAM_SET = 33, |
164 | PM_IOCTL = 34, |
165 | PM_QUERY_DATA = 35, |
166 | PM_CLOCK_ENABLE = 36, |
167 | PM_CLOCK_DISABLE = 37, |
168 | PM_CLOCK_GETSTATE = 38, |
169 | PM_CLOCK_SETDIVIDER = 39, |
170 | PM_CLOCK_GETDIVIDER = 40, |
171 | PM_CLOCK_SETPARENT = 43, |
172 | PM_CLOCK_GETPARENT = 44, |
173 | PM_FPGA_READ = 46, |
174 | PM_SECURE_AES = 47, |
175 | PM_EFUSE_ACCESS = 53, |
176 | PM_FEATURE_CHECK = 63, |
177 | }; |
178 | |
179 | /* PMU-FW return status codes */ |
180 | enum pm_ret_status { |
181 | XST_PM_SUCCESS = 0, |
182 | XST_PM_INVALID_VERSION = 4, |
183 | XST_PM_NO_FEATURE = 19, |
184 | XST_PM_INVALID_CRC = 301, |
185 | XST_PM_INTERNAL = 2000, |
186 | XST_PM_CONFLICT = 2001, |
187 | XST_PM_NO_ACCESS = 2002, |
188 | XST_PM_INVALID_NODE = 2003, |
189 | XST_PM_DOUBLE_REQ = 2004, |
190 | XST_PM_ABORT_SUSPEND = 2005, |
191 | XST_PM_MULT_USER = 2008, |
192 | }; |
193 | |
194 | enum pm_ioctl_id { |
195 | IOCTL_GET_RPU_OPER_MODE = 0, |
196 | IOCTL_SET_RPU_OPER_MODE = 1, |
197 | IOCTL_RPU_BOOT_ADDR_CONFIG = 2, |
198 | IOCTL_TCM_COMB_CONFIG = 3, |
199 | IOCTL_SET_TAPDELAY_BYPASS = 4, |
200 | IOCTL_SD_DLL_RESET = 6, |
201 | IOCTL_SET_SD_TAPDELAY = 7, |
202 | IOCTL_SET_PLL_FRAC_MODE = 8, |
203 | IOCTL_GET_PLL_FRAC_MODE = 9, |
204 | IOCTL_SET_PLL_FRAC_DATA = 10, |
205 | IOCTL_GET_PLL_FRAC_DATA = 11, |
206 | IOCTL_WRITE_GGS = 12, |
207 | IOCTL_READ_GGS = 13, |
208 | IOCTL_WRITE_PGGS = 14, |
209 | IOCTL_READ_PGGS = 15, |
210 | /* Set healthy bit value */ |
211 | IOCTL_SET_BOOT_HEALTH_STATUS = 17, |
212 | IOCTL_OSPI_MUX_SELECT = 21, |
213 | /* Register SGI to ATF */ |
214 | IOCTL_REGISTER_SGI = 25, |
215 | /* Runtime feature configuration */ |
216 | IOCTL_SET_FEATURE_CONFIG = 26, |
217 | IOCTL_GET_FEATURE_CONFIG = 27, |
218 | /* Dynamic SD/GEM configuration */ |
219 | IOCTL_SET_SD_CONFIG = 30, |
220 | IOCTL_SET_GEM_CONFIG = 31, |
221 | }; |
222 | |
223 | enum pm_query_id { |
224 | PM_QID_INVALID = 0, |
225 | PM_QID_CLOCK_GET_NAME = 1, |
226 | PM_QID_CLOCK_GET_TOPOLOGY = 2, |
227 | PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3, |
228 | PM_QID_CLOCK_GET_PARENTS = 4, |
229 | PM_QID_CLOCK_GET_ATTRIBUTES = 5, |
230 | PM_QID_PINCTRL_GET_NUM_PINS = 6, |
231 | PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7, |
232 | PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8, |
233 | PM_QID_PINCTRL_GET_FUNCTION_NAME = 9, |
234 | PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10, |
235 | PM_QID_PINCTRL_GET_PIN_GROUPS = 11, |
236 | PM_QID_CLOCK_GET_NUM_CLOCKS = 12, |
237 | PM_QID_CLOCK_GET_MAX_DIVISOR = 13, |
238 | }; |
239 | |
240 | enum rpu_oper_mode { |
241 | PM_RPU_MODE_LOCKSTEP = 0, |
242 | PM_RPU_MODE_SPLIT = 1, |
243 | }; |
244 | |
245 | enum rpu_boot_mem { |
246 | PM_RPU_BOOTMEM_LOVEC = 0, |
247 | PM_RPU_BOOTMEM_HIVEC = 1, |
248 | }; |
249 | |
250 | enum rpu_tcm_comb { |
251 | PM_RPU_TCM_SPLIT = 0, |
252 | PM_RPU_TCM_COMB = 1, |
253 | }; |
254 | |
255 | enum zynqmp_pm_reset_action { |
256 | PM_RESET_ACTION_RELEASE = 0, |
257 | PM_RESET_ACTION_ASSERT = 1, |
258 | PM_RESET_ACTION_PULSE = 2, |
259 | }; |
260 | |
261 | enum zynqmp_pm_reset { |
262 | ZYNQMP_PM_RESET_START = 1000, |
263 | ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START, |
264 | ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001, |
265 | ZYNQMP_PM_RESET_PCIE_CTRL = 1002, |
266 | ZYNQMP_PM_RESET_DP = 1003, |
267 | ZYNQMP_PM_RESET_SWDT_CRF = 1004, |
268 | ZYNQMP_PM_RESET_AFI_FM5 = 1005, |
269 | ZYNQMP_PM_RESET_AFI_FM4 = 1006, |
270 | ZYNQMP_PM_RESET_AFI_FM3 = 1007, |
271 | ZYNQMP_PM_RESET_AFI_FM2 = 1008, |
272 | ZYNQMP_PM_RESET_AFI_FM1 = 1009, |
273 | ZYNQMP_PM_RESET_AFI_FM0 = 1010, |
274 | ZYNQMP_PM_RESET_GDMA = 1011, |
275 | ZYNQMP_PM_RESET_GPU_PP1 = 1012, |
276 | ZYNQMP_PM_RESET_GPU_PP0 = 1013, |
277 | ZYNQMP_PM_RESET_GPU = 1014, |
278 | ZYNQMP_PM_RESET_GT = 1015, |
279 | ZYNQMP_PM_RESET_SATA = 1016, |
280 | ZYNQMP_PM_RESET_ACPU3_PWRON = 1017, |
281 | ZYNQMP_PM_RESET_ACPU2_PWRON = 1018, |
282 | ZYNQMP_PM_RESET_ACPU1_PWRON = 1019, |
283 | ZYNQMP_PM_RESET_ACPU0_PWRON = 1020, |
284 | ZYNQMP_PM_RESET_APU_L2 = 1021, |
285 | ZYNQMP_PM_RESET_ACPU3 = 1022, |
286 | ZYNQMP_PM_RESET_ACPU2 = 1023, |
287 | ZYNQMP_PM_RESET_ACPU1 = 1024, |
288 | ZYNQMP_PM_RESET_ACPU0 = 1025, |
289 | ZYNQMP_PM_RESET_DDR = 1026, |
290 | ZYNQMP_PM_RESET_APM_FPD = 1027, |
291 | ZYNQMP_PM_RESET_SOFT = 1028, |
292 | ZYNQMP_PM_RESET_GEM0 = 1029, |
293 | ZYNQMP_PM_RESET_GEM1 = 1030, |
294 | ZYNQMP_PM_RESET_GEM2 = 1031, |
295 | ZYNQMP_PM_RESET_GEM3 = 1032, |
296 | ZYNQMP_PM_RESET_QSPI = 1033, |
297 | ZYNQMP_PM_RESET_UART0 = 1034, |
298 | ZYNQMP_PM_RESET_UART1 = 1035, |
299 | ZYNQMP_PM_RESET_SPI0 = 1036, |
300 | ZYNQMP_PM_RESET_SPI1 = 1037, |
301 | ZYNQMP_PM_RESET_SDIO0 = 1038, |
302 | ZYNQMP_PM_RESET_SDIO1 = 1039, |
303 | ZYNQMP_PM_RESET_CAN0 = 1040, |
304 | ZYNQMP_PM_RESET_CAN1 = 1041, |
305 | ZYNQMP_PM_RESET_I2C0 = 1042, |
306 | ZYNQMP_PM_RESET_I2C1 = 1043, |
307 | ZYNQMP_PM_RESET_TTC0 = 1044, |
308 | ZYNQMP_PM_RESET_TTC1 = 1045, |
309 | ZYNQMP_PM_RESET_TTC2 = 1046, |
310 | ZYNQMP_PM_RESET_TTC3 = 1047, |
311 | ZYNQMP_PM_RESET_SWDT_CRL = 1048, |
312 | ZYNQMP_PM_RESET_NAND = 1049, |
313 | ZYNQMP_PM_RESET_ADMA = 1050, |
314 | ZYNQMP_PM_RESET_GPIO = 1051, |
315 | ZYNQMP_PM_RESET_IOU_CC = 1052, |
316 | ZYNQMP_PM_RESET_TIMESTAMP = 1053, |
317 | ZYNQMP_PM_RESET_RPU_R50 = 1054, |
318 | ZYNQMP_PM_RESET_RPU_R51 = 1055, |
319 | ZYNQMP_PM_RESET_RPU_AMBA = 1056, |
320 | ZYNQMP_PM_RESET_OCM = 1057, |
321 | ZYNQMP_PM_RESET_RPU_PGE = 1058, |
322 | ZYNQMP_PM_RESET_USB0_CORERESET = 1059, |
323 | ZYNQMP_PM_RESET_USB1_CORERESET = 1060, |
324 | ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061, |
325 | ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062, |
326 | ZYNQMP_PM_RESET_USB0_APB = 1063, |
327 | ZYNQMP_PM_RESET_USB1_APB = 1064, |
328 | ZYNQMP_PM_RESET_IPI = 1065, |
329 | ZYNQMP_PM_RESET_APM_LPD = 1066, |
330 | ZYNQMP_PM_RESET_RTC = 1067, |
331 | ZYNQMP_PM_RESET_SYSMON = 1068, |
332 | ZYNQMP_PM_RESET_AFI_FM6 = 1069, |
333 | ZYNQMP_PM_RESET_LPD_SWDT = 1070, |
334 | ZYNQMP_PM_RESET_FPD = 1071, |
335 | ZYNQMP_PM_RESET_RPU_DBG1 = 1072, |
336 | ZYNQMP_PM_RESET_RPU_DBG0 = 1073, |
337 | ZYNQMP_PM_RESET_DBG_LPD = 1074, |
338 | ZYNQMP_PM_RESET_DBG_FPD = 1075, |
339 | ZYNQMP_PM_RESET_APLL = 1076, |
340 | ZYNQMP_PM_RESET_DPLL = 1077, |
341 | ZYNQMP_PM_RESET_VPLL = 1078, |
342 | ZYNQMP_PM_RESET_IOPLL = 1079, |
343 | ZYNQMP_PM_RESET_RPLL = 1080, |
344 | ZYNQMP_PM_RESET_GPO3_PL_0 = 1081, |
345 | ZYNQMP_PM_RESET_GPO3_PL_1 = 1082, |
346 | ZYNQMP_PM_RESET_GPO3_PL_2 = 1083, |
347 | ZYNQMP_PM_RESET_GPO3_PL_3 = 1084, |
348 | ZYNQMP_PM_RESET_GPO3_PL_4 = 1085, |
349 | ZYNQMP_PM_RESET_GPO3_PL_5 = 1086, |
350 | ZYNQMP_PM_RESET_GPO3_PL_6 = 1087, |
351 | ZYNQMP_PM_RESET_GPO3_PL_7 = 1088, |
352 | ZYNQMP_PM_RESET_GPO3_PL_8 = 1089, |
353 | ZYNQMP_PM_RESET_GPO3_PL_9 = 1090, |
354 | ZYNQMP_PM_RESET_GPO3_PL_10 = 1091, |
355 | ZYNQMP_PM_RESET_GPO3_PL_11 = 1092, |
356 | ZYNQMP_PM_RESET_GPO3_PL_12 = 1093, |
357 | ZYNQMP_PM_RESET_GPO3_PL_13 = 1094, |
358 | ZYNQMP_PM_RESET_GPO3_PL_14 = 1095, |
359 | ZYNQMP_PM_RESET_GPO3_PL_15 = 1096, |
360 | ZYNQMP_PM_RESET_GPO3_PL_16 = 1097, |
361 | ZYNQMP_PM_RESET_GPO3_PL_17 = 1098, |
362 | ZYNQMP_PM_RESET_GPO3_PL_18 = 1099, |
363 | ZYNQMP_PM_RESET_GPO3_PL_19 = 1100, |
364 | ZYNQMP_PM_RESET_GPO3_PL_20 = 1101, |
365 | ZYNQMP_PM_RESET_GPO3_PL_21 = 1102, |
366 | ZYNQMP_PM_RESET_GPO3_PL_22 = 1103, |
367 | ZYNQMP_PM_RESET_GPO3_PL_23 = 1104, |
368 | ZYNQMP_PM_RESET_GPO3_PL_24 = 1105, |
369 | ZYNQMP_PM_RESET_GPO3_PL_25 = 1106, |
370 | ZYNQMP_PM_RESET_GPO3_PL_26 = 1107, |
371 | ZYNQMP_PM_RESET_GPO3_PL_27 = 1108, |
372 | ZYNQMP_PM_RESET_GPO3_PL_28 = 1109, |
373 | ZYNQMP_PM_RESET_GPO3_PL_29 = 1110, |
374 | ZYNQMP_PM_RESET_GPO3_PL_30 = 1111, |
375 | ZYNQMP_PM_RESET_GPO3_PL_31 = 1112, |
376 | ZYNQMP_PM_RESET_RPU_LS = 1113, |
377 | ZYNQMP_PM_RESET_PS_ONLY = 1114, |
378 | ZYNQMP_PM_RESET_PL = 1115, |
379 | ZYNQMP_PM_RESET_PS_PL0 = 1116, |
380 | ZYNQMP_PM_RESET_PS_PL1 = 1117, |
381 | ZYNQMP_PM_RESET_PS_PL2 = 1118, |
382 | ZYNQMP_PM_RESET_PS_PL3 = 1119, |
383 | ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 |
384 | }; |
385 | |
386 | enum zynqmp_pm_suspend_reason { |
387 | SUSPEND_POWER_REQUEST = 201, |
388 | SUSPEND_ALERT = 202, |
389 | SUSPEND_SYSTEM_SHUTDOWN = 203, |
390 | }; |
391 | |
392 | enum zynqmp_pm_request_ack { |
393 | ZYNQMP_PM_REQUEST_ACK_NO = 1, |
394 | ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2, |
395 | ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3, |
396 | }; |
397 | |
398 | enum pm_node_id { |
399 | NODE_SD_0 = 39, |
400 | NODE_SD_1 = 40, |
401 | }; |
402 | |
403 | enum tap_delay_type { |
404 | PM_TAPDELAY_INPUT = 0, |
405 | PM_TAPDELAY_OUTPUT = 1, |
406 | }; |
407 | |
408 | enum dll_reset_type { |
409 | PM_DLL_RESET_ASSERT = 0, |
410 | PM_DLL_RESET_RELEASE = 1, |
411 | PM_DLL_RESET_PULSE = 2, |
412 | }; |
413 | |
414 | enum pm_pinctrl_config_param { |
415 | PM_PINCTRL_CONFIG_SLEW_RATE = 0, |
416 | PM_PINCTRL_CONFIG_BIAS_STATUS = 1, |
417 | PM_PINCTRL_CONFIG_PULL_CTRL = 2, |
418 | PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3, |
419 | PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4, |
420 | PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5, |
421 | PM_PINCTRL_CONFIG_TRI_STATE = 6, |
422 | PM_PINCTRL_CONFIG_MAX = 7, |
423 | }; |
424 | |
425 | enum pm_pinctrl_slew_rate { |
426 | PM_PINCTRL_SLEW_RATE_FAST = 0, |
427 | PM_PINCTRL_SLEW_RATE_SLOW = 1, |
428 | }; |
429 | |
430 | enum pm_pinctrl_bias_status { |
431 | PM_PINCTRL_BIAS_DISABLE = 0, |
432 | PM_PINCTRL_BIAS_ENABLE = 1, |
433 | }; |
434 | |
435 | enum pm_pinctrl_pull_ctrl { |
436 | PM_PINCTRL_BIAS_PULL_DOWN = 0, |
437 | PM_PINCTRL_BIAS_PULL_UP = 1, |
438 | }; |
439 | |
440 | enum pm_pinctrl_schmitt_cmos { |
441 | PM_PINCTRL_INPUT_TYPE_CMOS = 0, |
442 | PM_PINCTRL_INPUT_TYPE_SCHMITT = 1, |
443 | }; |
444 | |
445 | enum pm_pinctrl_drive_strength { |
446 | PM_PINCTRL_DRIVE_STRENGTH_2MA = 0, |
447 | PM_PINCTRL_DRIVE_STRENGTH_4MA = 1, |
448 | PM_PINCTRL_DRIVE_STRENGTH_8MA = 2, |
449 | PM_PINCTRL_DRIVE_STRENGTH_12MA = 3, |
450 | }; |
451 | |
452 | enum pm_pinctrl_tri_state { |
453 | PM_PINCTRL_TRI_STATE_DISABLE = 0, |
454 | PM_PINCTRL_TRI_STATE_ENABLE = 1, |
455 | }; |
456 | |
457 | enum zynqmp_pm_shutdown_type { |
458 | ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0, |
459 | ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1, |
460 | ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2, |
461 | }; |
462 | |
463 | enum zynqmp_pm_shutdown_subtype { |
464 | ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0, |
465 | ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1, |
466 | ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2, |
467 | }; |
468 | |
469 | enum tap_delay_signal_type { |
470 | PM_TAPDELAY_NAND_DQS_IN = 0, |
471 | PM_TAPDELAY_NAND_DQS_OUT = 1, |
472 | PM_TAPDELAY_QSPI = 2, |
473 | PM_TAPDELAY_MAX = 3, |
474 | }; |
475 | |
476 | enum tap_delay_bypass_ctrl { |
477 | PM_TAPDELAY_BYPASS_DISABLE = 0, |
478 | PM_TAPDELAY_BYPASS_ENABLE = 1, |
479 | }; |
480 | |
481 | enum ospi_mux_select_type { |
482 | PM_OSPI_MUX_SEL_DMA = 0, |
483 | PM_OSPI_MUX_SEL_LINEAR = 1, |
484 | }; |
485 | |
486 | enum pm_feature_config_id { |
487 | PM_FEATURE_INVALID = 0, |
488 | PM_FEATURE_OVERTEMP_STATUS = 1, |
489 | PM_FEATURE_OVERTEMP_VALUE = 2, |
490 | PM_FEATURE_EXTWDT_STATUS = 3, |
491 | PM_FEATURE_EXTWDT_VALUE = 4, |
492 | }; |
493 | |
494 | /** |
495 | * enum pm_sd_config_type - PM SD configuration. |
496 | * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE |
497 | * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1 |
498 | * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2 |
499 | * @SD_CONFIG_FIXED: To set fixed config registers |
500 | */ |
501 | enum pm_sd_config_type { |
502 | SD_CONFIG_EMMC_SEL = 1, |
503 | SD_CONFIG_BASECLK = 2, |
504 | SD_CONFIG_8BIT = 3, |
505 | SD_CONFIG_FIXED = 4, |
506 | }; |
507 | |
508 | /** |
509 | * enum pm_gem_config_type - PM GEM configuration. |
510 | * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register |
511 | * @GEM_CONFIG_FIXED: To set fixed config registers |
512 | */ |
513 | enum pm_gem_config_type { |
514 | GEM_CONFIG_SGMII_MODE = 1, |
515 | GEM_CONFIG_FIXED = 2, |
516 | }; |
517 | |
518 | /** |
519 | * struct zynqmp_pm_query_data - PM query data |
520 | * @qid: query ID |
521 | * @arg1: Argument 1 of query data |
522 | * @arg2: Argument 2 of query data |
523 | * @arg3: Argument 3 of query data |
524 | */ |
525 | struct zynqmp_pm_query_data { |
526 | u32 qid; |
527 | u32 arg1; |
528 | u32 arg2; |
529 | u32 arg3; |
530 | }; |
531 | |
532 | int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 *ret_payload, u32 num_args, ...); |
533 | |
534 | #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) |
535 | int zynqmp_pm_get_api_version(u32 *version); |
536 | int zynqmp_pm_get_chipid(u32 *idcode, u32 *version); |
537 | int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily); |
538 | int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out); |
539 | int zynqmp_pm_clock_enable(u32 clock_id); |
540 | int zynqmp_pm_clock_disable(u32 clock_id); |
541 | int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state); |
542 | int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider); |
543 | int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider); |
544 | int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id); |
545 | int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id); |
546 | int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode); |
547 | int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode); |
548 | int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data); |
549 | int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data); |
550 | int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value); |
551 | int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type); |
552 | int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select); |
553 | int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, |
554 | const enum zynqmp_pm_reset_action assert_flag); |
555 | int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status); |
556 | unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode); |
557 | int zynqmp_pm_bootmode_write(u32 ps_mode); |
558 | int zynqmp_pm_init_finalize(void); |
559 | int zynqmp_pm_set_suspend_mode(u32 mode); |
560 | int zynqmp_pm_request_node(const u32 node, const u32 capabilities, |
561 | const u32 qos, const enum zynqmp_pm_request_ack ack); |
562 | int zynqmp_pm_release_node(const u32 node); |
563 | int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, |
564 | const u32 qos, |
565 | const enum zynqmp_pm_request_ack ack); |
566 | int zynqmp_pm_aes_engine(const u64 address, u32 *out); |
567 | int zynqmp_pm_efuse_access(const u64 address, u32 *out); |
568 | int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); |
569 | int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); |
570 | int zynqmp_pm_fpga_get_status(u32 *value); |
571 | int zynqmp_pm_fpga_get_config_status(u32 *value); |
572 | int zynqmp_pm_write_ggs(u32 index, u32 value); |
573 | int zynqmp_pm_read_ggs(u32 index, u32 *value); |
574 | int zynqmp_pm_write_pggs(u32 index, u32 value); |
575 | int zynqmp_pm_read_pggs(u32 index, u32 *value); |
576 | int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value); |
577 | int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); |
578 | int zynqmp_pm_set_boot_health_status(u32 value); |
579 | int zynqmp_pm_pinctrl_request(const u32 pin); |
580 | int zynqmp_pm_pinctrl_release(const u32 pin); |
581 | int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id); |
582 | int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, |
583 | u32 *value); |
584 | int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, |
585 | u32 value); |
586 | int zynqmp_pm_load_pdi(const u32 src, const u64 address); |
587 | int zynqmp_pm_register_notifier(const u32 node, const u32 event, |
588 | const u32 wake, const u32 enable); |
589 | int zynqmp_pm_feature(const u32 api_id); |
590 | int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); |
591 | int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); |
592 | int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); |
593 | int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset); |
594 | int zynqmp_pm_force_pwrdwn(const u32 target, |
595 | const enum zynqmp_pm_request_ack ack); |
596 | int zynqmp_pm_request_wake(const u32 node, |
597 | const bool set_addr, |
598 | const u64 address, |
599 | const enum zynqmp_pm_request_ack ack); |
600 | int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode); |
601 | int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode); |
602 | int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode); |
603 | int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); |
604 | int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, |
605 | u32 value); |
606 | #else |
607 | static inline int zynqmp_pm_get_api_version(u32 *version) |
608 | { |
609 | return -ENODEV; |
610 | } |
611 | |
612 | static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) |
613 | { |
614 | return -ENODEV; |
615 | } |
616 | |
617 | static inline int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily) |
618 | { |
619 | return -ENODEV; |
620 | } |
621 | |
622 | static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, |
623 | u32 *out) |
624 | { |
625 | return -ENODEV; |
626 | } |
627 | |
628 | static inline int zynqmp_pm_clock_enable(u32 clock_id) |
629 | { |
630 | return -ENODEV; |
631 | } |
632 | |
633 | static inline int zynqmp_pm_clock_disable(u32 clock_id) |
634 | { |
635 | return -ENODEV; |
636 | } |
637 | |
638 | static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) |
639 | { |
640 | return -ENODEV; |
641 | } |
642 | |
643 | static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) |
644 | { |
645 | return -ENODEV; |
646 | } |
647 | |
648 | static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) |
649 | { |
650 | return -ENODEV; |
651 | } |
652 | |
653 | static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) |
654 | { |
655 | return -ENODEV; |
656 | } |
657 | |
658 | static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) |
659 | { |
660 | return -ENODEV; |
661 | } |
662 | |
663 | static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) |
664 | { |
665 | return -ENODEV; |
666 | } |
667 | |
668 | static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) |
669 | { |
670 | return -ENODEV; |
671 | } |
672 | |
673 | static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) |
674 | { |
675 | return -ENODEV; |
676 | } |
677 | |
678 | static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) |
679 | { |
680 | return -ENODEV; |
681 | } |
682 | |
683 | static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) |
684 | { |
685 | return -ENODEV; |
686 | } |
687 | |
688 | static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) |
689 | { |
690 | return -ENODEV; |
691 | } |
692 | |
693 | static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select) |
694 | { |
695 | return -ENODEV; |
696 | } |
697 | |
698 | static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, |
699 | const enum zynqmp_pm_reset_action assert_flag) |
700 | { |
701 | return -ENODEV; |
702 | } |
703 | |
704 | static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, |
705 | u32 *status) |
706 | { |
707 | return -ENODEV; |
708 | } |
709 | |
710 | static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode) |
711 | { |
712 | return -ENODEV; |
713 | } |
714 | |
715 | static inline int zynqmp_pm_bootmode_write(u32 ps_mode) |
716 | { |
717 | return -ENODEV; |
718 | } |
719 | |
720 | static inline int zynqmp_pm_init_finalize(void) |
721 | { |
722 | return -ENODEV; |
723 | } |
724 | |
725 | static inline int zynqmp_pm_set_suspend_mode(u32 mode) |
726 | { |
727 | return -ENODEV; |
728 | } |
729 | |
730 | static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities, |
731 | const u32 qos, |
732 | const enum zynqmp_pm_request_ack ack) |
733 | { |
734 | return -ENODEV; |
735 | } |
736 | |
737 | static inline int zynqmp_pm_release_node(const u32 node) |
738 | { |
739 | return -ENODEV; |
740 | } |
741 | |
742 | static inline int zynqmp_pm_set_requirement(const u32 node, |
743 | const u32 capabilities, |
744 | const u32 qos, |
745 | const enum zynqmp_pm_request_ack ack) |
746 | { |
747 | return -ENODEV; |
748 | } |
749 | |
750 | static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) |
751 | { |
752 | return -ENODEV; |
753 | } |
754 | |
755 | static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out) |
756 | { |
757 | return -ENODEV; |
758 | } |
759 | |
760 | static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, |
761 | const u32 flags) |
762 | { |
763 | return -ENODEV; |
764 | } |
765 | |
766 | static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, |
767 | const u32 flags) |
768 | { |
769 | return -ENODEV; |
770 | } |
771 | |
772 | static inline int zynqmp_pm_fpga_get_status(u32 *value) |
773 | { |
774 | return -ENODEV; |
775 | } |
776 | |
777 | static inline int zynqmp_pm_fpga_get_config_status(u32 *value) |
778 | { |
779 | return -ENODEV; |
780 | } |
781 | |
782 | static inline int zynqmp_pm_write_ggs(u32 index, u32 value) |
783 | { |
784 | return -ENODEV; |
785 | } |
786 | |
787 | static inline int zynqmp_pm_read_ggs(u32 index, u32 *value) |
788 | { |
789 | return -ENODEV; |
790 | } |
791 | |
792 | static inline int zynqmp_pm_write_pggs(u32 index, u32 value) |
793 | { |
794 | return -ENODEV; |
795 | } |
796 | |
797 | static inline int zynqmp_pm_read_pggs(u32 index, u32 *value) |
798 | { |
799 | return -ENODEV; |
800 | } |
801 | |
802 | static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value) |
803 | { |
804 | return -ENODEV; |
805 | } |
806 | |
807 | static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) |
808 | { |
809 | return -ENODEV; |
810 | } |
811 | |
812 | static inline int zynqmp_pm_set_boot_health_status(u32 value) |
813 | { |
814 | return -ENODEV; |
815 | } |
816 | |
817 | static inline int zynqmp_pm_pinctrl_request(const u32 pin) |
818 | { |
819 | return -ENODEV; |
820 | } |
821 | |
822 | static inline int zynqmp_pm_pinctrl_release(const u32 pin) |
823 | { |
824 | return -ENODEV; |
825 | } |
826 | |
827 | static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) |
828 | { |
829 | return -ENODEV; |
830 | } |
831 | |
832 | static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id) |
833 | { |
834 | return -ENODEV; |
835 | } |
836 | |
837 | static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, |
838 | u32 *value) |
839 | { |
840 | return -ENODEV; |
841 | } |
842 | |
843 | static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, |
844 | u32 value) |
845 | { |
846 | return -ENODEV; |
847 | } |
848 | |
849 | static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address) |
850 | { |
851 | return -ENODEV; |
852 | } |
853 | |
854 | static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event, |
855 | const u32 wake, const u32 enable) |
856 | { |
857 | return -ENODEV; |
858 | } |
859 | |
860 | static inline int zynqmp_pm_feature(const u32 api_id) |
861 | { |
862 | return -ENODEV; |
863 | } |
864 | |
865 | static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, |
866 | u32 value) |
867 | { |
868 | return -ENODEV; |
869 | } |
870 | |
871 | static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, |
872 | u32 *payload) |
873 | { |
874 | return -ENODEV; |
875 | } |
876 | |
877 | static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset) |
878 | { |
879 | return -ENODEV; |
880 | } |
881 | |
882 | static inline int zynqmp_pm_force_pwrdwn(const u32 target, |
883 | const enum zynqmp_pm_request_ack ack) |
884 | { |
885 | return -ENODEV; |
886 | } |
887 | |
888 | static inline int zynqmp_pm_request_wake(const u32 node, |
889 | const bool set_addr, |
890 | const u64 address, |
891 | const enum zynqmp_pm_request_ack ack) |
892 | { |
893 | return -ENODEV; |
894 | } |
895 | |
896 | static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) |
897 | { |
898 | return -ENODEV; |
899 | } |
900 | |
901 | static inline int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode) |
902 | { |
903 | return -ENODEV; |
904 | } |
905 | |
906 | static inline int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode) |
907 | { |
908 | return -ENODEV; |
909 | } |
910 | |
911 | static inline int zynqmp_pm_set_sd_config(u32 node, |
912 | enum pm_sd_config_type config, |
913 | u32 value) |
914 | { |
915 | return -ENODEV; |
916 | } |
917 | |
918 | static inline int zynqmp_pm_set_gem_config(u32 node, |
919 | enum pm_gem_config_type config, |
920 | u32 value) |
921 | { |
922 | return -ENODEV; |
923 | } |
924 | |
925 | #endif |
926 | |
927 | #endif /* __FIRMWARE_ZYNQMP_H__ */ |
928 | |